Integrated circuit (IC) with corrugated channel structure

Abstract

The invention relates to an integrated circuit (IC) with a corrugated channel structure. An IC device (100) includes one or more corrugated channel structures (106) formed in a top portion (104A) of a semiconductor substrate (102), wherein the corrugated channel structure (106) includes a first sidewall (122), a second sidewall (124), and an upper portion (126). In an example, the corrugated channel structure (106) is provided with a substantially uniform profile of dopant across a horizontal plane from the first sidewall (122) to the second sidewall (124).

Description

Technical Field

[0001] The disclosed embodiments generally relate to the fields of integrated circuits (ICs) and IC manufacturing. More particularly, but not exclusively, the disclosed embodiments relate to IC devices including one or more corrugated channel structures. Background Art

[0002] FinFET is a type of three-dimensional (3D) MOSFET transistor in which the channel contains a non-planar structure similar to a "fin" and includes semiconductor material protruding from the semiconductor substrate. FinFET is considered a leading candidate to replace conventional planar FETs in advanced CMOS technology nodes due to its superior gate control of the channel, resulting in faster switching times, improved immunity to short channel effects, higher current density, and improved I on / I off In manufacturing flows involving line-of-sight beamline implantation techniques, achieving uniform dopant distribution across raised structures such as fins is challenging. Summary of the invention

[0003] A simplified overview is presented below to provide a basic understanding of some examples of the present disclosure. The present invention summary is not an extensive overview of the examples, and is neither intended to identify the key or important elements of the examples nor to describe their scope. In fact, the main purpose of the present invention summary is to present some concepts of the present disclosure in a simplified form as a preface to the more detailed description presented in the subsequent sections below.

[0004] In one example, a method of manufacturing an IC device is disclosed. The method may include, among other things, forming at least one corrugated channel structure in a top portion of a semiconductor substrate including a substrate material of a first conductivity type; implanting a first dose of a dopant in a first implant into a first sidewall of the at least one corrugated channel structure at a first beam line tilt angle relative to a surface normal of the semiconductor substrate; implanting a second dose of the dopant in a second implant into a second sidewall of the at least one corrugated channel structure at a second beam line tilt angle relative to the surface normal; and implanting a third dose of the dopant in a vertical implant into an upper portion of the at least one corrugated channel structure at a substantially 0° tilt angle relative to the surface normal.

[0005] In one example, an IC device is disclosed, which may include, among other things, a semiconductor substrate including a top portion, the semiconductor substrate including a substrate material of a first conductivity type; and at least one corrugated channel structure formed in the top portion of the semiconductor substrate, the at least one corrugated channel structure including a first sidewall, a second sidewall, and an upper portion, the at least one corrugated channel structure having, for example, a substantially uniform distribution curve of dopants across a horizontal plane from the first sidewall to the second sidewall. In some embodiments, the IC device may further include a gate dielectric layer, which is above the at least one corrugated channel structure; and a gate, which is above the gate dielectric layer.

[0006] In one example, a method for manufacturing an IC device is disclosed. The method may include, among other things: forming at least one ripple channel structure in a top portion of a semiconductor substrate including a substrate material of a first conductivity type, the at least one ripple channel structure including an upper portion, a first sidewall, and a second sidewall, wherein the first sidewall and the second sidewall may form a respective vertical profile of an adjacent trench and extend to a respective bottom of the adjacent trench; forming an oxide hard mask over the upper portion of the at least one ripple channel structure and the bottom of the adjacent trench, the oxide hard mask being formed in an opening of a nitride hard mask, the nitride hard mask being formed over the at least one ripple channel structure; removing the nitride hard mask from the first sidewall and the second sidewall of the at least one ripple channel structure; implanting one or more doses of dopants into the first sidewall and the second sidewall using an angled beamline implant process; removing the oxide hard mask from the upper portion and the bottom; and implanting a second dose of the dopant into the upper portion and the bottom using a vertical implant process. In some embodiments, the dopants of the angled beam-line implant process and the vertical implant process may include a dopant species having a second conductivity type opposite to the first conductivity type of the substrate material. In some embodiments, the dopants of the angled beam-line implant process and the vertical implant process may include a dopant species having the first conductivity type. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the figures of the accompanying drawings, embodiments of the present disclosure are illustrated by way of example and not by way of limitation. It should be noted that different references to "one" or "an" embodiment in the present disclosure are not necessarily references to the same embodiment, and such references may mean at least one. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, such feature, structure, or characteristic may be feasible in conjunction with other embodiments, whether or not explicitly described.

[0008] The accompanying drawings are incorporated into and form a part of the specification for the purpose of illustrating one or more example embodiments of the present disclosure. Various advantages and features of the present disclosure will be understood from the following detailed description taken in conjunction with the appended claims and with reference to the accompanying drawings, in which:

[0009] Figures 1A-1G depicts cross-sectional views of an IC device at various stages of formation including a dual hard mask process flow for fabricating a doped damascene channel structure according to an example of the present disclosure;

[0010] Figure 2A-2E depicts cut-away cross-sectional views of an IC device including a folded DEMOS transistor at various stages of formation according to some examples of the present disclosure, wherein beam-line implant doping may be achieved using a dual hard mask process flow;

[0011] Figure 3 depicts a three-dimensional perspective view of an IC device including a resistor including a doped corrugated structure formed according to some examples of the present disclosure;

[0012] Figure 4 is a flow chart of an IC manufacturing method according to some examples of the present disclosure;

[0013] Figure 5 depicting a simulated dopant profile across a corrugated channel structure according to an example; and

[0014] Figure 6 Depicted is a simulated cross-sectional view of a damascene channel structure with an oxide hard mask according to an example. DETAILED DESCRIPTION

[0015] Examples of the present disclosure are described with reference to the accompanying drawings, in which similar reference numerals are generally used to refer to similar elements. The drawings are not drawn to scale, and they are provided only as illustrative examples. Many specific details, relationships, and methods are set forth below to provide an understanding of one or more examples. However, it should be understood that some examples may be practiced without these specific details. In other examples, well-known subsystems, components, structures, and techniques are not shown in detail to avoid confusing the understanding of the examples. Therefore, examples of the present disclosure may be practiced without such specific components.

[0016] In addition, terms such as "coupling" and "connection" and their derivatives may be used in the following specific embodiments, the appended claims, or both. It should be understood that these terms are not necessarily intended to be synonymous with each other. "Coupling" can be used to indicate that two or more elements (which may or may not be in direct physical or electrical contact with each other) cooperate or interact with each other. "Connection" can be used to indicate the establishment of communication between two or more elements coupled to each other, i.e., a communication relationship. In addition, in one or more examples set forth herein, in general, if an element can be programmed to perform or otherwise structurally arranged to perform a certain function, then an element, component, or module can be configured to perform the function.

[0017] Without limitation, examples of IC devices including one or more raised channel structures and their fabrication are described below in the context of a process flow involving line-of-sight implantation techniques (eg, using a beam-line ion implant system).

[0018] It is desirable that the dopant level across the raised channel structure (also referred to herein as a corrugated channel structure or fin) has a uniform distribution so that the electrical performance characteristics and other performance characteristics of the device containing the raised channel structure are better controlled. By way of example, a device with source / drain extension (for example, but not limited to, a drain extended metal oxide semiconductor (DEMOS) field effect transistor (FET) device, a lateral diffusion MOS (LDMOS) device) generally requires a relatively uniform doping level across various portions of the fin (for example, across the top portion, the bottom portion, and between the two sidewalls forming the lateral portion of the fin) to achieve acceptable threshold voltage control and prevent impact ionization in the more heavily doped region that may be caused by hot carrier phenomena. Such devices may be employed, for example, in analog circuit implementations. Beam line implants on fin devices generally cause a higher doping level at the top of the fin relative to the bottom and sidewalls due to the fin bottom and sidewalls being shielded by adjacent fins. The higher doping at the top of the fin is because the top is implanted twice when implanting each side of the fin, thereby doubling the dose, which may hinder obtaining a uniform level of dopant distribution in the fin. In addition, depending on the form factor of the fin, the size design / spacing of the trenches, the angle of incidence of the implants, etc., the bottom surface of the trenches between adjacent fins may also be implanted twice, thereby further deteriorating the dopant profile in the fins and surrounding areas in the device.

[0019] Some implant techniques that do not involve line-of-sight implantation, such as plasma-assisted doping or atomic layer deposition (ALD) doping, can be employed in the manufacturing process to achieve a more uniform dopant distribution in fin-based devices. However, such techniques are generally more expensive, thus increasing manufacturing costs.

[0020] Examples of the present disclosure recognize these and other related deficiencies and provide a manufacturing process that includes a dual hard mask process, wherein two hard masks may be optionally provided for facilitating sequential implantation of portions of the fin in an isolated manner. In an example embodiment, the sidewalls may be implanted first by an angled beam implant process while protecting the top of the fin and the bottom of the trench between the fins, followed by a vertical implant for implanting the top of the fin and the bottom of the trench between adjacent fin processes after removing the protective mask, thereby reducing or avoiding the negative effects of double dose. While such examples provide materials and processes that advantageously allow for integration of beam implant technology in a manufacturing process, no particular result is required unless expressly recited in a particular claim.

[0021] Reference now Figures 1A-1G , in which cross-sectional views of an IC device at various stages of formation according to an example of the present disclosure are depicted, the stages of formation including a dual hard mask process flow for fabricating a doped corrugated channel structure. Depending on the implementation and application, the example IC device 100 may represent any type of active or passive device having one or more elevated single crystal semiconductor structures formed in a top portion of a semiconductor substrate, wherein the elevated structures (or fins) may form a corrugated surface and may be operated as a non-planar three-dimensional (3D) channel with controlled electrical characteristics based on a suitable dopant profile. In some arrangements, the IC device 100 may illustrate active devices, such as but not limited to folded DEMOS FET devices, LDMOS FinFET devices, and devices configured for high voltage power applications (e.g., having an appropriate breakdown voltage (V bd ) and on-resistance (R on ) characteristics), low voltage logic applications, high voltage radio frequency (RF) applications, and the like. In some arrangements, the IC device 100 may illustrate fin-based resistors with varying degrees of temperature dependence, such as a temperature coefficient of resistance (TCR) within a suitable range. Additionally, the IC device 100 may be fabricated as a bulk FinFET, an epitaxial FinFET, a silicon-on-insulator (SOI) FinFET, and the like, depending on the implementation and / or application.

[0022] Specifically refer to Figure 1A, shows an IC device 100 at an early manufacturing stage, wherein one or more fins 106 are formed in a top portion 104A of a semiconductor substrate 102, wherein the semiconductor substrate 102 includes a bottom portion 104B underlying the top portion 104A. In some examples, the substrate 102 may primarily include appropriately doped silicon as a substrate material, although other semiconductor materials such as Ge, SiGe, GaAs, SiC, GaN, other III-V materials, etc. may be used in some implementations, wherein in some arrangements, one or more epitaxial layers or single crystal layers may be formed or disposed as part of the semiconductor substrate 102. In an example implementation, the fins or corrugated channel structures 106 may be separated by corresponding grooves or trenches 107 formed between adjacent corrugated channel structures 106, wherein the trenches 107 may be formed by a reactive ion etching (RIE) process using fluorine radicals and an appropriately patterned mask (in Figure 1A By way of example, the groove 107 may have an average depth of 300 nanometers (nm) to 1200 nm, which corresponds to an average height 199 of the corrugated channel structure 106, wherein the corrugated channel structure 106 may include a body 109 having an upper portion 126, a lower portion 128, a first sidewall 122, and a second sidewall 124. In some arrangements, the first sidewall 122 and the second sidewall 124 may be provided as respective lateral portions of the body 109. In some arrangements, the body 109 of the corrugated channel structure 106 may include a tapered structure, wherein the width of the upper portion 126 may be approximately 40% to 50% of the height 199 of the corrugated channel structure 106. In some arrangements, the width of the lower portion 128 of the body 109 may be approximately 50% to 60% of the height 199 of the corrugated channel structure 106. In a similar manner, the average width of the grooves 107 may be set to be a fraction of the overall height 199 of the corrugated channel structure 106 .

[0023] As part of the front-end process, a pad or gate oxide layer 108 having a thickness of about 8 nm to 15 nm may be formed over the top portion 104A including the corrugated channel structure 106, wherein the oxide layer 108 may be provided to relieve stress between the substrate 102 and the subsequent nitride layer, which stress may otherwise induce dislocations in the substrate material. In some examples, the pad oxide layer 108 may be grown using a dry oxidation process at a temperature in a range from 900° C. to 1200° C. and an oxygen pressure in a range from 20 kPa to 140 kPa. Thereafter, a conformal nitride hard mask layer 130 having a thickness of about 40 nm to 80 nm may be formed over the pad oxide layer 108, as shown in FIG. Figure 1BIt should be understood that, without limitation, the formation of various layers (e.g., pad oxide layer 108 and nitride hard mask layer 130, as well as other dielectric layers, conductive layers, non-conductive layers, etc.) that may be required in the manufacture of example IC devices of the present disclosure may be performed using a variety of techniques, materials, and at different thicknesses depending on the implementation and / or application. Figure 1B , a conformal nitride hard mask layer 130 may be formed to cover the pad oxide layer 108 formed over the upper portion 126, the first sidewall 122 and the second sidewall 124 of the corrugated channel structure 106, and the bottom surface 111 of the trench 107. For the purposes of the present disclosure, in some examples, the conformal nitride hard mask layer 130 may be considered as a first hard mask, which may be selectively removed according to a dual hard mask process to facilitate the formation of a second hard mask, wherein in some examples, the second hard mask may include an oxide hard mask, as will be described below.

[0024] In an example embodiment, an isotropic etching process, such as an RIE process, may be performed to selectively remove the nitride hard mask layer 130 from horizontal layers or surfaces of the IC device 100, such as a horizontal surface of the pad oxide layer 108 above the upper portion 126 of the ripple channel structure 106 and a horizontal surface of the pad oxide layer 108 above the bottom 111 of the trench 107. Therefore, after the selective removal of the nitride hard mask layer 130 is completed, an opening exposing the pad oxide material may be formed above the ripple channel structure 106 and the bottom 111 of the trench 107, thereby leaving only the remaining portion of the nitride hard mask 130 above the pad oxide layer 108 covering the sidewalls 122, 124 of the ripple channel structure 106, as shown in FIG. Figure 1C Subsequently, a non-continuous oxide hard mask layer 132 having a thickness of about 40 nm to 80 nm may be formed as a second hard mask over the exposed portion of the pad oxide layer 108, the exposed portion remaining over the upper portion 126 of the corrugated channel structure 106 and the bottom 111 of the trench 107, as shown in FIG. Figure 1D Although the portion of the oxide hard mask layer 132 in the bottom 111 is Figure 1D 132 for illustrative purposes, but such oxide hard mask portions (in some instances, referred to herein as dielectric barrier structures) are expected to be more curvilinear in nature, such as rounded structures, due to the consumption of substrate material in the bottom portion 111 during the formation of the oxide hard mask 132. In a similar manner, substrate material of the upper portion 126 of the wavy channel structure 106 may also be consumed during the formation of the oxide hard mask 132, wherein the upper portion 126 may have rounded corners. By way of representative example reference Figure 6, which depicts a simulated cross-sectional view of a portion of an IC device 600 including one or more corrugated channel structures 602 having an oxide hard mask portion 614A above an upper portion 606 and an oxide hard mask portion or dielectric barrier structure 614B above a bottom 611 of a trench 607 formed between adjacent corrugated channel structures 602. As can be seen in the depicted simulation, the dielectric barrier structure 614B in the bottom 611 is generally circular. Additionally, the upper portion 606 of the corrugated channel structure 602 includes rounded corners 612A and 612B that taper toward respective sidewalls 622A and 6222B of the corrugated channel structure 602. In contrast, in cases where some baseline processes do not use or require a double hard mask process flow to protect the horizontal surfaces of the upper portion of the fin and the bottom of the trench from being doubly implanted in a beam-line ion implantation process (e.g., plasma-assisted doping or atomic layer deposition (ALD) doping) as described in the present disclosure, the fin structure in the IC device may not exhibit corner rounding or tapering as described herein.

[0025] Return to Figure 1D The oxide mask layer 132 may include one or more silicon dioxide (SiO 2 ) sublayer and may be formed by thermal oxidation of silicon. In some additional and / or alternative arrangements, a chemical vapor deposition (CVD) process may be used to form an oxide mask layer, which may include SiO containing a certain hydrogen content (e.g., 2 wt %-5 wt %). x Material.

[0026] After forming the oxide mask layer 132, the IC device 100 may undergo a selective strip process to remove the remaining nitride hard mask material 130 and possibly some of the pad oxide layer 108 from the sidewalls 122, 124 of the damascene channel structure 106 before implanting the appropriate dopant species using a beam-line implant process in one or more stages. In an example embodiment, hot phosphoric acid (HPO) may be used to remove the remaining nitride hard mask material 130 and possibly some of the pad oxide layer 108. 3 PO 4 ) stripping to remove the material. The beam-line implant process may include implanting one or more dopant species of the appropriate conductivity type, which may be implanted at various dose levels, implant energies, twist / tilt angles, etc., depending on the type of IC device 100 being manufactured, the functionality and characteristics of the different device regions involved, etc. Figure 1E In one arrangement, one or more doses of dopant may be implanted in the first implant 150 at a first beam implant tilt angle φ relative to a surface normal 161 of the semiconductor substrate 102 (eg, relative to a horizontal plane 167 associated therewith). 1(e.g., 4° to 10°) is implanted in one sidewall (e.g., first sidewall 122) of the corrugated channel structure 106. In a similar manner, one or more doses of dopant may be implanted in the second implant 152 at a second beam line implant tilt angle φ relative to the surface normal 161 of the semiconductor substrate 102. 2 (e.g., 4° to 10°) is implanted in another sidewall (e.g., second sidewall 124) of the corrugated channel structure 106, such as Figure 1F In both the angled beam-line implant processes 150, 152, the horizontal surfaces of the corrugated channel structure 106 (e.g., the top surface 163 of the upper portion 126 and the bottom 111 of the trench 107) are at least partially protected from the implant processes 150, 152 (which would otherwise be exposed and doped twice) due to the oxide hard mask layer 132 covering the surface 163, thereby avoiding negative effects that may be caused by double doping as mentioned in the present disclosure.

[0027] After the angled beam implant processes 150, 152 are completed, the oxide hard mask layer 132 may be stripped using a suitable process, such as a dilute hydrofluoric acid (HF) descum process. Thereafter, the IC device 100 may undergo a vertical implant process 154 at a substantially zero tilt angle (e.g., 0°±2°) relative to the surface normal 161 of the semiconductor substrate 102, such as Figure 1G 104A, or the like, for introducing one or more doses of appropriate dopant species into the corrugated channel structure 106 and selected regions of the semiconductor substrate 102 including the top portion 104A, the bottom portion, or both, depending on the IC device implementation. The sidewalls 122 and 124 receive little or no secondary doping from the vertical implant process because the sidewalls 122 and 124 are substantially parallel to the angle of incidence of the implant 154, thereby maintaining the net concentration of the dopant species previously introduced in the angled beamline implants 150, 152. Thereafter, one or more annealing steps (not specifically shown) may be used to activate the dopant species in the remaining portions and regions of the corrugated channel structure 106 and the semiconductor substrate 102. In some examples, without limitation, the annealing process may include a rapid thermal anneal (RTA) process at approximately 1000° C. to 1200° C. for approximately 10 to 15 seconds.

[0028] Steering Figure 4, in which a flow chart of an IC manufacturing method 400 according to some examples of the present disclosure is shown. At block 402, at least one corrugated channel structure may be formed in a top portion of a semiconductor substrate including a substrate material of a first conductivity type (e.g., p-type or n-type), wherein the body of the corrugated channel structure may include an upper portion and a first sidewall and a second sidewall (e.g., disposed as a vertical lateral portion of the body). As described above, the first sidewall and the second sidewall of the corrugated channel structure may form a vertical profile of a corresponding trench formed adjacent to the corrugated channel structure, each trench having a bottom to which the first sidewall and the second sidewall extend. At block 404, a pad oxide layer may be formed over the upper portion and sidewalls of at least one corrugated channel structure and the bottom of an adjacent trench. At block 406, a conformal nitride hard mask having a suitable thickness may be formed over the pad oxide layer, wherein the nitride hard mask may be patterned to create an opening therein, the opening overlying the upper portion of the corrugated channel structure and on the bottom of the adjacent trench, while covering the first sidewall and the second sidewall of the corrugated channel structure. In some examples, the nitride hard mask may include one or more epitaxial mask materials such as silicon nitride, or silicon-doped boron nitride (SiN) having 1 atomic % to 30 atomic % silicon. x In some examples, silicon-doped boron nitride may be used in diborane (B 2 H 6 ), silane (SiH 4 ) and ammonia (NH 3 ) plasma enhanced CVD (PECVD) process, in boron trichloride (BCl 3 ), dichlorosilane (SiH 2 Cl 2 ) and atomic layer deposition (ALD) process under ammonia or metal organic chemical vapor deposition (MOCVD) process, etc.

[0029] At block 408, an oxide hard mask having a suitable thickness may be formed in the openings over the upper portion of the corrugated channel structure and on the bottom of the adjacent trenches. As previously described, in some examples, the oxide hard mask may include SiO formed by thermal oxidation of silicon or by a low pressure CVD (LPCVD) process. 2. At box 410, the remaining nitride hard mask material and pad oxide material may be removed from the first sidewall and the second sidewall of the corrugated channel structure. At box 412, a dopant having a suitable conductivity type may be implanted (e.g., at a first dose) in the first implant at a first beam line tilt angle relative to a surface normal of a semiconductor substrate including the corrugated channel structure. Thereafter, in a second implant, a dopant having a suitable conductivity type may be implanted (e.g., at a second dose) in the second sidewall of the corrugated channel structure at a second beam line tilt angle relative to a surface normal of the semiconductor substrate including the corrugated channel structure (box 414). In some arrangements, one or more doses of dopants may be implanted in the first sidewall and the second sidewall using appropriate ion species and energy, wherein the doses, tilt angles, twist angles, energies, etc. used to implant the two sidewalls may be the same or different.

[0030] Subsequently, the oxide hard mask may be removed, and dopants having the appropriate conductivity type may be implanted (e.g., at a third dose) in a vertical implant into the upper portion of the corrugated channel structure and the bottom of the adjacent trench at a substantially 0° tilt angle relative to a surface normal of the semiconductor substrate including the corrugated channel structure (block 416). Similar to the angled beam line implant used to implant the sidewalls, the vertical implant may involve the appropriate dopant species, energy, and dose level (e.g., a dose level different from or the same as that used in the angled beam line implant).

[0031] Depending on the embodiment, dopant species such as boron, gallium, and indium can be provided as first conductivity type dopants because they provide p-type conductivity in the semiconductor material, while dopant species such as phosphorus, arsenic, and antimony can be provided as second conductivity type dopants (e.g., n-type dopants) with respect to the beam-line and vertical implant processes described above. Other dopant species that are not electrically active but can reduce diffusion of electrically active species can also be implanted according to the principles of the present disclosure. Such species can include, for example, C, N, and F.

[0032] After each implant is completed, a suitable annealing step may be performed to activate the implanted dopant species to achieve substantially uniform doping (e.g., within ±5%) across the body of the channel structure and in the substrate material underlying the adjacent trenches (block 418). As previously described, annealing and dopant activation may be performed using rapid thermal processing at high temperatures, wherein vacancies created at high temperatures promote movement of dopant species (e.g., phosphorus, arsenic, boron, etc.) from interstitial lattice sites to substitutional lattice sites, while amorphization damage from the implant process may be mitigated by recrystallization. After completing the dopant activation and annealing steps, method 400 may continue with the remaining IC manufacturing stages (e.g., formation of gates, contacts, vias, silicidation, metallization, and integration with planar devices, etc., depending on the type and functionality of the device) as applicable.

[0033] Because double dosing of the upper portion 126 of the corrugated channel structure 106 and the bottom 111 of the adjacent trench 107 is substantially prevented, various types of beam-line implant processes may be advantageously deployed in conjunction with a dual hard mask process flow as described herein to provide a more uniform dopant profile in a corrugated channel structure that may be manufactured in a variety of product environments and technology nodes. Figure 5 , depicting a simulated dopant profile across a portion of an IC device 500 including one or more corrugated channel structures 506 according to an example. By way of illustration, the IC device 500 includes a semiconductor substrate 502 having a corrugated top portion 504, the corrugated top portion 504 including corrugated channel structures 506, the corrugated channel structures 506 each having a body 508 having an upper portion 526 and lateral sidewall portions 522 and 524 separated by respective trenches (e.g., trenches 510A, 510B). P-type dopants, such as boron, are implanted using angled beamline implants and vertical implants in the simulated process flow. As shown in FIG. Figure 5 It can be seen that a substantially uniform dopant profile is seen across the surface shape of the corrugated channel structure 506, such as across the width of the body 508 along a horizontal axis (e.g., the X-axis) parallel to the surface of the substrate 502. In addition, a substantially uniform dopant profile is also seen near the bottoms 512A, 512B of the trenches 510A, 510B and the substrate region 514 underlying the corrugated channel structure 506. As used herein, the term "substantially uniform" may be used to refer to an order of magnitude of ±1 / 2, or as Figure 5 This is illustrated in the example of .

[0034] While the principles of the present disclosure are not implicitly limited to any particular electrical device, some representative IC devices will now be described immediately below that include corrugated channel structures that may be doped using one or more beam-line implant processes in conjunction with a dual hard mask process flow according to the examples herein.

[0035] Figure 2A-2E Depicts a cut-away cross-sectional view of an IC device 200 including a folded DEMOS transistor 206 at various stages of formation according to some examples of the present disclosure, where beam-line implant doping may be achieved using a dual hard mask process flow. Figure 2A, DEMOS transistor 206 is formed in and on substrate 202, wherein substrate 202 may include a base layer 254 including a first portion 204A of a suitable semiconductor material 204. In some examples, first portion 204A of semiconductor material 204 may primarily include silicon. In an example embodiment, an epitaxial mask 256 may be formed on or over base layer 254 to expose base layer 254 in selected areas for epitaxial fins or corrugated channel structures 258. By way of example, epitaxial mask 256 may include silicon dioxide, silicon nitride, or silicon-doped boron nitride. Epitaxial fin 258 may be formed by an epitaxial process, which by way of example may be implemented as a vapor phase epitaxial process using silane or disilane. Epitaxial fin 258 may form a top portion of substrate 202 and may include a second portion 204B of semiconductor material 204. In some arrangements, semiconductor material portions 204A and 204B may be formed or configured substantially similar to those described above with reference to Figures 1A-1G The described parts 104B and 104A. Figure 2A-2E , the second portion 204B of the semiconductor material 204 may have the same composition as the first portion 204A of the semiconductor material 204. In alternative versions, the second portion 204B of the semiconductor material 204 may have a different composition than the first portion 204A of the semiconductor material 204. For example, the first portion 204A of the semiconductor material 204 may consist primarily of silicon, and the second portion 204B of the semiconductor material 204 may include silicon with some germanium or silicon with some carbon in order to provide enhanced mobility.

[0036] The semiconductor material 204 may have a first conductivity type, in this example, a p-type. By way of example, the semiconductor material 204 may have an average resistivity of 10 ohm-cm (ohm-centimeter) to 100 ohm-cm. Embodiments of the substrate 202 and the semiconductor material 204 are within the scope of this example.

[0037] The epitaxial mask 256 may then be removed using a suitable dry / wet stripping / etching process. For example, silicon dioxide in the epitaxial mask 256 may be removed by a dilute aqueous solution of HF acid. Silicon nitride and boron nitride in the epitaxial mask 256 may be removed by a plasma etching process using fluorine radicals.

[0038] IC device 200 may include folded DEMOS transistor 206 and other active and / or passive devices (in Figure 2A-2E In the examples described herein, the folded DEMOS transistor 206 will be described as an n-channel transistor. A p-channel version of the folded DEMOS transistor 206 is within the scope of this example and can be formed by appropriate changes in dopant polarity.

[0039] Figure 2B Depicted in has been removed Figure 2A 2. The IC device 200 after applying the epitaxial mask 256 of FIG. 2. In the example arrangement, by way of illustration, the epitaxial fins 258 may have an average height of 400 nm to 1200 nm above the base layer 254. Having an average depth of 400 nm to 1200 nm may advantageously provide a higher current capability for the folded DEMOS transistor 206 as compared to a planar DEMOS transistor, while advantageously enabling the folded DEMOS transistor 206 to be formed using a planar process simultaneously with other components (e.g., planar transistors) in the IC device 200.

[0040] Forming the epitaxial fin 258 may form a corrugated top surface 216 of the semiconductor material 204. The corrugated top surface 216 includes an upper portion 218, a lower portion 220, a first lateral portion 222 extending from the upper portion 218 to the lower portion 220, and a second lateral portion 224 extending from the upper portion 218 to the lower portion 220. The top surface of the epitaxial fin 258 opposite the boundary between the first portion 204A of the semiconductor material 204 and the second portion 204B of the semiconductor material 204 may be configured to provide the upper portion 218. The boundary between the first portion 204A of the semiconductor material 204 and the second portion 204B of the semiconductor material 204 may be configured to provide the lower portion 220, which may be substantially similar to the bottom 111 of the trench 107 described above. Additionally, the sidewalls of the epitaxial fin 258 may provide a first lateral portion 222 and a second lateral portion 224, which may be substantially similar to the sidewalls 122 and 124 described above. Thus, in some arrangements, the size and form factor of the epitaxial fin 258 may be substantially similar to that described above with reference to Figures 1A-1G The size and form factor of the corrugated channel structure 106 are described in detail.

[0041] Although the upper part 218 Figure 2B 258, but may be a convex or concave surface due to non-uniformities in the epitaxial process used to form the epitaxial fins 258. In some arrangements, the first lateral portion 222 and the second lateral portion 224 may be angled at 84° to 88° relative to the upper portion 218 to facilitate subsequent formation of layers between the epitaxial fins 258 (e.g., in trench spaces formed between adjacent epitaxial fins 258).

[0042] refer to Figure 2C, a charge balance region 210 of the folded DEMOS transistor 206 is formed in the semiconductor material 204 of the substrate 202. The charge balance region 210 has a first conductivity type, which is p-type in this example. The charge balance region 210 can be formed by introducing a first conductivity type dopant (e.g., boron in this example) into the semiconductor material 204. In an example embodiment, a proper angled beam implant process and a vertical beam implant process can be used in combination with the above reference Figures 1A-1G The described double hard mask process implants boron into the first lateral portion 222 and the second lateral portion 224 of the corrugated top surface 216 and the upper portion 218 and the lower portion 220. In some examples, the drift region 212 of the folded DEMOS transistor 206 can be formed in the semiconductor material 204, wherein the drift region 212 can have a second conductivity type opposite to the first conductivity type. In this example, the second conductivity type is n-type. The drift region 212 can be formed by using a beam-line implant process in conjunction with the double hard mask process as described above to introduce a second conductivity type dopant (e.g., arsenic or phosphorus in this example) into the semiconductor material 204 along the upper portion 218, the first lateral portion 222, the second lateral portion 224, and the lower portion 220 of the corrugated top surface 216.

[0043] In some examples, the first conductivity type dopant and the second conductivity type dopant may be introduced into the semiconductor material 204 by sequential beam-line implant processes, including a first beam-line ion implant process for the first conductivity type dopant and a second beam-line ion implant process for the second conductivity type dopant, wherein each implant process may be performed in conjunction with a corresponding dual hard mask process. Depending on the implementation, the beam-line ion implant process may be performed in several steps or stages, wherein implanting at different tilt angles may result in a more uniform dopant distribution along the corrugated top surface 216 compared to implanting without tilting. The beam-line ion implant process in conjunction with the disclosed dual hard mask process may provide greater dose control and more uniform dopant distribution than other implant processes and may enable the formation of the charge balance region 210 and the drift region 212 in manufacturing facilities that do not have alternative implant techniques and more expensive implant techniques (e.g., plasma assisted doping or atomic layer deposition (ALD) doping), thereby making the manufacture of advanced IC devices including corrugated channel structures more cost-effective.

[0044] In some examples, the charge balance region 210 may have a 1×10 16 cm -3 to 1×10 18 cm -3The average net concentration of the first conductive type dopant in the drift region 212 may be 65% to 150% of the average net concentration of the first conductive type dopant in the charge balance region 210, which may provide the advantage of reducing the electric field in the drift region 212 during operation of the folded DEMOS transistor 206.

[0045] In the example arrangement, the drift region 212 may extend to a body region 208, or simply body 208, of the folded DEMOS transistor 206 formed in the semiconductor material 204. In a variation of this example, the drift region 212 may be surrounded by the charge balance region 210, such as Figure 2C . In some arrangements, the body region 208 may include a semiconductor material of a first conductivity type, in this example, a p-type. In some arrangements, the body 208 may be formed by introducing a first conductivity type dopant, such as boron, into the semiconductor material 204, followed by heating the semiconductor material 204 to disperse and activate the first conductivity type dopant, thereby forming the body 208. The first conductivity type dopant may be introduced into the semiconductor material 204 by a beam-line ion implantation process in conjunction with the dual hard mask process of the present disclosure. The body 208 may be formed to have a depth (D ) below an upper portion 218 of the corrugated top surface 216. 1 ), which is similar to the depth (D 2 ). In some additional and / or alternative examples, the body 208 may be implemented as part of the semiconductor material 204 without introducing additional dopants, thereby not requiring a double hard mask process. Regardless of how the body 208 may be formed in example embodiments, the body 208 may be arranged to contact the drift region 212 continuously along the upper portion 218, the first lateral portion 222, the second lateral portion 224, and the lower portion 220 of the corrugated top surface 216.

[0046] refer to Figure 2D , a field plate dielectric layer 226 of the folded DEMOS transistor 206 is formed on or above the drift region 212, and extends continuously along the upper portion 218, the first lateral portion 222, the second lateral portion 224, and the lower portion 220 of the corrugated top surface 216. The field plate dielectric layer 226 extends close to the body 208 and may partially overlap the body 208. A gate dielectric layer 228 is formed on or above the body 208, and extends continuously along the upper portion 218, the first lateral portion 222, the second lateral portion 224, and the lower portion 220 of the corrugated top surface 216. Figure 2D As depicted in , the gate dielectric layer 228 may extend to the field plate dielectric layer 226 .

[0047] refer to Figure 2EA gate 230 including a conductive material (eg, polysilicon) is formed on or above the gate dielectric layer 228, wherein the gate 230 may partially overlap the field plate dielectric layer 226. Figure 2E , the gate 230 may extend continuously over the gate dielectric layer 228 along the upper portion 218, the first lateral portion 222, the second lateral portion 224, and the lower portion 220 of the corrugated top surface 216. A gate / field plate spacer 260 is formed over the gate 230, wherein the gate / field plate spacer 260 may include a non-conductive material such as, by way of example, silicon dioxide, silicon nitride, or silicon oxynitride. The gate / field plate spacer 260 may be formed by thermal oxidation of polysilicon in the gate 230, or may be formed by forming one or more dielectric material layers by a CVD process, followed by forming an etch mask and removing the dielectric material layers exposed by the etch mask, leaving the dielectric material layers under the etch mask to provide the gate / field plate spacer 260. In some arrangements, by way of example, the gate / field plate spacer 260 may be up to twice as thick as the field plate dielectric layer 226.

[0048] Continue to refer Figure 2E , a field plate 232 and a drain-tied field plate 262 may be formed on or over the field plate dielectric layer 226, wherein the field plate 232 may be formed adjacent to the gate 230 and may extend partially over the drift region 212 adjacent to the gate 230. In this example, the field plate 232 is electrically isolated from the gate 230 by the gate / field plate isolator 260, as shown in FIG. Figure 2E . The drain-tied field plate 262 is located above the drift region 212 opposite the gate 230. Although the drain-tied field plate 262 is separated from the field plate 232, in some arrangements, the field plate 232 and the drain-tied field plate 262 may be formed simultaneously, for example, by forming a field plate layer (not shown) on the field plate dielectric layer 226, and may be separated by a suitable etching process. In some arrangements, the field plate layer may include polysilicon or other conductive materials. A field plate etch mask may be formed over the field plate layer, covering the area for the field plate 232 and the drain-tied field plate 262. The field plate layer exposed by the field plate etch mask is removed, leaving the field plate etch mask on the field plate dielectric layer 226 to provide the field plate 232 and the drain-tied field plate 262. Additional details regarding the various layers forming the IC device 200 including the folded drain DEMOS transistor 206 may be found in US Pat. No. 10,978,559, issued in the name of Haynie et al., which is incorporated herein by reference for all purposes.

[0049] Figure 3A three-dimensional perspective view of an IC device 300 including a resistor 399 formed as a doped corrugated structure in a semiconductor substrate 397 according to some examples of the present disclosure is depicted. As illustrated, the resistor 399 may include a plurality of corrugated channel structures or fins 302 formed in the semiconductor substrate 397, wherein the fins 302 may be doped with suitable dopants using one or more beam-line implant processes in conjunction with a dual hard mask flow for facilitating uniform dopant concentrations as described above. After implantation and annealing, silicide terminals 304A, 304B may be formed in respective header regions of the resistor 399. Regions 306 of the resistor 399 that are not intended to be silicided may be blocked by a silicide block (SiBLK) layer (not explicitly shown in this figure), which may be patterned to expose contact openings in the resistor header region. After silicidation of the contact openings for forming terminals 304A, 304B, a pre-metal dielectric (PMD) stack (not explicitly shown in this figure) may be formed over IC device 300, for example using known or heretofore unknown processes, materials, and compositions, which PMD stack may include one or more layers and / or liners.

[0050] Although various examples of the present disclosure have been described above, the examples have been presented by way of example only and not by way of limitation. Numerous changes may be made to the disclosed examples according to the disclosure herein without departing from the spirit or scope of the present disclosure. Therefore, the breadth and scope of the present disclosure should not be limited by any of the examples described above. In fact, the scope of the present disclosure should be limited according to the appended claims and their equivalents.

[0051] For example, in the present disclosure and the appended claims, unless otherwise stated and / or specified to the contrary, any one or more of the layers described herein may be formed in any number of suitable ways, such as using spin coating techniques, sputtering techniques (e.g., magnetron and / or ion beam sputtering), (thermal) growth techniques, or deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), PECVD, or atomic layer deposition (ALD), etc. As another example, the silicon nitride may be silicon-rich silicon nitride or oxygen-rich silicon nitride. The silicon nitride may contain some oxygen, but not so much that the dielectric constant of the material is significantly different from that of high purity silicon nitride.

[0052] In addition, in at least some additional or alternative embodiments, the function / action described in the frame may not occur in the order shown in the flow chart. For example, depending on the functionality / action involved, the two frames shown in succession can actually be substantially performed simultaneously or the frames can sometimes be performed in reverse order. In addition, the function of a given frame of a flow chart and / or block diagram can be divided into multiple frames, and / or the function of two or more frames of a flow chart and / or block diagram can be at least partially integrated. In addition, some frames in the flow chart can be optionally omitted. In addition, although some diagrams include arrows on the communication path to show the main direction of communication, it should be understood that communication can occur in the direction opposite to the arrows depicted. Finally, other frames can be added / inserted between the illustrated frames.

[0053] The order or sequence of actions, steps, functions, components or boxes shown in any of the flowcharts and / or block diagrams depicted in the drawings of the present disclosure may be modified, altered, replaced, customized or otherwise rearranged within a particular flowchart or block diagram, including the deletion or omission of a particular action, step, function, component or box. In addition, the actions, steps, functions, components or boxes shown in a particular flowchart may be intermixed or otherwise arranged or rearranged with the actions, steps, functions, components or boxes shown in another flowchart to achieve additional changes, modifications and configurations relative to one or more processes for the purpose of practicing the teachings of the present disclosure. Similarly, although various examples have been described herein, not all features of a particular example are necessarily limited thereto and / or are therefore required.

[0054] At least some portions of the above description may include certain directional terms, such as "upper," "lower," "top," "bottom," "left," "right," "front," "back," "vertical," "horizontal," and the like, which may be used with reference to the orientation of some of the figures described or their illustrative elements. Because components of some examples may be positioned in a number of different orientations, the directional terms are used for illustrative purposes and are in no way limiting. Likewise, references to features referred to as "first," "second," and the like do not indicate any particular order, importance, and the like, and such references may be interchangeable, depending on the context, implementation, and the like. Furthermore, unless specifically noted otherwise, the features of the examples described herein may be combined with one another.

[0055] Although various embodiments have been shown and described in detail, the claims are not limited to any specific embodiment or example. The above specific embodiments should not be considered to imply that any specific component, element, step, action, or function is basic so that it must be included in the scope of the claims. In the case of narrating or describing phrases such as "at least one of A and B" or phrases of similar meaning, such phrases should be understood to mean "only A, only B, or both A and B". Unless explicitly stated, references to singular elements are not intended to mean "one and only one", but "one or more". In a similar manner, depending on the context, phrases such as "a plurality" or "multiple" may mean "one or more" or "at least one". All structural and functional equivalents of the elements of the embodiments described above are expressly incorporated herein by reference, and are intended to be covered by the appended claims.

Claims

1. A method for manufacturing an integrated circuit IC, comprising: forming at least one corrugation channel structure in a top portion of a semiconductor substrate comprising a substrate material of a first conductivity type; implanting a first dose of a dopant into a first sidewall of the at least one corrugated channel structure at a first beam line tilt angle relative to a surface normal of the semiconductor substrate in a first implant; implanting a second dose of the dopant in a second implant into a second sidewall of the at least one corrugated channel structure at a second beam line tilt angle relative to the surface normal; and A third dose of the dopant is implanted in a vertical implant in an upper portion of the at least one corrugated channel structure at a substantially 0° tilt angle relative to the surface normal.

2. The method of claim 1, wherein the at least one corrugated channel structure comprises a plurality of corrugated channel structures separated by corresponding grooves formed between adjacent corrugated channel structures, each groove comprising a bottom portion receiving the vertical implant.

3. The method according to claim 2, further comprising: forming a nitride hard mask over the ripple channel structure before implanting the dopant in the first implant and the second implant and the vertical implant; selectively removing the nitride hard mask from the upper portion of the corresponding ripple channel structure and the bottom of the corresponding trench while the first sidewall and the second sidewall of the corresponding ripple channel structure remain covered by the nitride hard mask; forming an oxide hard mask over the upper portion of the respective corrugated channel structure and the bottom of the respective trench; removing the nitride hard mask from the first sidewall and the second sidewall of the corrugated channel structure and implanting the dopant into the first sidewall and the second sidewall in the first implant and the second implant, respectively; removing the oxide hard mask from the upper portion of the corresponding corrugated channel structure and the bottom of the corresponding trench; and The dopant is implanted in the upper portion and the bottom portion in the vertical implant. 4 . The method of claim 1 , wherein the dopants of the first implant and the second implant and the vertical implant comprise dopant species having a second conductivity type opposite to the first conductivity type of the substrate material. 5 . The method of claim 1 , wherein the dopants of the first implant and the second implant and the vertical implant include a dopant species having the first conductivity type.

6. The method of claim 1, further comprising: forming a gate dielectric layer over the at least one corrugated channel structure; and A gate is formed over the gate dielectric layer.

7. The method of claim 1, wherein at least one of the first dose and the second dose is implanted in the presence of a dielectric barrier structure at a bottom of a trench between the at least one corrugation channel structure and an adjacent corrugation channel structure.

8. An integrated circuit IC, comprising: a semiconductor substrate including a top portion, the semiconductor substrate comprising a substrate material of a first conductivity type; and At least one corrugated channel structure is formed in the top portion of the semiconductor substrate, the at least one corrugated channel structure comprising a first sidewall, a second sidewall, and an upper portion, the at least one corrugated channel structure having a substantially uniform distribution curve of dopants across a horizontal plane from the first sidewall to the second sidewall.

9. The IC of claim 8, further comprising: a gate dielectric layer overlying the at least one corrugated channel structure; and A gate is located above the gate dielectric layer.

10. The IC of claim 8, wherein the upper portion of the at least one corrugated channel structure has rounded corners.

11. The IC of claim 8, wherein the dopant comprises a dopant species having a second conductivity type opposite to the first conductivity type of the substrate material.

12. The IC of claim 8, wherein the dopant comprises a dopant species having the first conductivity type.

13. A method for manufacturing an integrated circuit IC, comprising: forming at least one corrugation channel structure in a top portion of a semiconductor substrate including a substrate material of a first conductivity type, the at least one corrugation channel structure comprising an upper portion, a first sidewall, and a second sidewall, wherein the first sidewall and the second sidewall extend to respective bottoms of adjacent trenches; forming an oxide hard mask over the upper portion of the at least one ripple channel structure and the bottom of the adjacent trench, the oxide hard mask formed in an opening of a nitride hard mask formed over the at least one ripple channel structure; removing the nitride hard mask from the first sidewall and the second sidewall of the at least one ripple channel structure; implanting one or more doses of dopant into the first sidewall and the second sidewall using an angled beamline implant process; removing the oxide hard mask from the upper portion and the bottom portion; and A second dose of the dopant is implanted into the upper portion and the bottom portion in a vertical implant process.

14. The method of claim 13, wherein the dopants of the angled beamline implant process and the vertical implant process include dopant species having a second conductivity type opposite to the first conductivity type of the substrate material.

15. The method of claim 13, wherein the dopants of the angled beamline implant process and the vertical implant process include dopant species having the first conductivity type. 16 . The method of claim 13 , wherein the angled beamline implant process and the vertical implant process are performed for forming a drift region in the top portion of the semiconductor substrate, the drift region extending into the at least one corrugation channel structure.

17. The method of claim 13, wherein the angled beamline implant process and the vertical implant process are performed to form a charge balance region in the top portion of the semiconductor substrate, the charge balance region extending into the at least one corrugated channel structure.

18. The method of claim 13, wherein the angled beamline implant process and the vertical implant process are performed to form a body region in the top portion of the semiconductor substrate, the body region extending into the at least one corrugation channel structure.

19. The method of claim 13, wherein the angled beam-line implant process and the vertical implant process are configured to implant at least one of boron, gallium, indium, phosphorus, arsenic, and antimony.

20. The method of claim 13, further comprising: forming a gate dielectric layer over the at least one corrugated channel structure; and A gate is formed over the gate dielectric layer.

21. The method of claim 13, wherein at least one dose of the dopant is implanted in the presence of a portion of the oxide hard mask operating as a dielectric barrier structure at the bottom of a trench between the at least one corrugation channel structure and an adjacent corrugation channel structure.

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