Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the semiconductor structure comprising a substrate with a PMOS region and an NMOS region, and a discrete fin formed on the substrate; a gate structure located on the substrate and across the fin, the gate structure covering part of the top and part of the sidewall of the fin; a first isolation structure located in the fin between adjacent gate structures to be isolated in the PMOS region; a second isolation structure located in the fin across the side of the gate structure in the NMOS region and arranged in parallel with the gate structure, the bottom of the second isolation structure extending into the fin; a first source-drain doped layer located in the fin on both sides of the gate structure in the PMOS region; and a second source-drain doped layer located in the fin on both sides of the gate structure in the NMOS region. The application reduces the difference in response speed between the PMOS region and the NMOS region after the first isolation structure is formed, thereby improving the performance of the semiconductor structure, and is also conducive to saving the area of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration. Transistors, as one of the basic semiconductor devices, are widely used. Therefore, with the increase of the density and integration of semiconductor devices, the gate size of planar transistors is becoming shorter and shorter, and the control ability of the traditional planar transistor to the channel current is becoming weaker, which causes the short channel effect and increases the leakage current, and finally affects the electrical performance of the semiconductor device.

[0003] In order to better adapt to the reduction of feature size, semiconductor technology gradually begins to transition from planar MOSFET to three-dimensional transistor with higher efficiency, such as fin field effect transistor (FinFET). In the FinFET, the gate can control the ultra-thin body (fin) from at least two sides. Compared with the planar MOSFET, the control ability of the gate to the channel is stronger, and the short channel effect can be well suppressed; and the FinFET has better compatibility with existing integrated circuit manufacturing than other devices.

[0004] In addition, in order to improve the running speed of the chip and improve the performance of the transistor, the prior art introduces a stress layer in the source / drain doped region, introduces compressive stress or tensile stress in the channel region of the transistor, so as to improve the mobility of the carriers in the channel, thereby improving the performance of the transistor. Therefore, at present, the stress layer in the fin field effect transistor is located in the fin on both sides of the gate structure.

[0005] However, with the reduction of the size of the semiconductor device, the distance between adjacent fins is also reduced. In order to prevent bridging between adjacent devices, a double diffusion break (DDB) structure is introduced, and the spacing between two adjacent transistors along the extension direction of the fin is one gate pitch. In order to further compress the chip area, a single diffusion break (SDB) structure is introduced. After introducing the SDB structure, the spacing between two adjacent transistors along the extension direction of the fin is only the width of one gate.

[0006] However, the performance of the semiconductor structure still needs to be improved. SUMMARY

[0007] The problem solved by embodiments of the present application is to provide a semiconductor structure and a forming method thereof to improve the performance of the semiconductor structure.

[0008] To solve the above problems, the embodiment of the present application provides a semiconductor structure, comprising: a substrate, the substrate comprising a PMOS region and an NMOS region, and a separate fin formed on the substrate; a gate structure located on the substrate and crossing the fin, the gate structure covering part of the top and part of the sidewall of the fin; a first isolation structure located in the PMOS region and in the fin between adjacent gate structures to be isolated; a second isolation structure located in the NMOS region, the second isolation structure crossing the fin on the side of the gate structure and arranged side by side with the gate structure, the bottom of the second isolation structure extending into the fin; a first source-drain doping layer located in the fin on both sides of the gate structure in the PMOS region; and a second source-drain doping layer located in the fin on both sides of the gate structure in the NMOS region.

[0009] Correspondingly, the embodiment of the present application also provides a forming method of a semiconductor structure, comprising: providing a substrate, the substrate comprising a PMOS region and an NMOS region, and a separate fin formed on the substrate; forming a gate structure crossing the fin on the substrate, the gate structure covering part of the top and part of the sidewall of the fin; forming a first isolation structure in the fin between adjacent gate structures to be isolated in the PMOS region; after forming the first isolation structure, forming a first source-drain doping layer in the fin on both sides of the gate structure in the PMOS region; forming a second source-drain doping layer in the fin on both sides of the gate structure in the NMOS region; and forming a second isolation structure in the NMOS region at the position of part of the gate structure, the second isolation structure extending into the fin.

[0010] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0011] The semiconductor structure provided by the embodiment of the present application comprises a first isolation structure in the PMOS region and in the fin between the adjacent gate structures to be isolated, a second isolation structure in the NMOS region, the second isolation structure crossing the fin of the side of the gate structure and being arranged side by side with the gate structure, the bottom of the second isolation structure extending into the fin, a first source-drain doping layer in the fin on both sides of the gate structure in the PMOS region, and a second source-drain doping layer in the fin on both sides of the gate structure in the NMOS region. Since the carriers of the PMOS region are holes and the carriers of the NMOS region are electrons, the response speed of the electrons is faster than that of the holes, and the holes are more sensitive to the change of stress, that is, after the loss of the same absolute value of stress, the response speed of the PMOS region decreases more than that of the NMOS region. The first isolation structure is formed in the fin between the adjacent gate structures to be isolated in the PMOS region, which avoids removing the gate structure in the PMOS region and reduces the stress loss of the first source-drain doping layer caused by the formation of the first isolation structure, and accordingly reduces the decrease of the response speed of the PMOS region, thereby reducing the difference between the response speeds of the PMOS region and the NMOS region after the formation of the first isolation structure, and further improving the performance of the semiconductor structure. Moreover, compared with the scheme of forming the first isolation structure in both the PMOS region and the NMOS region, the embodiment of the present application comprises the first isolation structure in the PMOS region and in the fin between the adjacent gate structures to be isolated, the second isolation structure in the NMOS region, the second isolation structure crossing the fin of the side of the gate structure and being arranged side by side with the gate structure, and the bottom of the second isolation structure extending into the fin, that is, the second isolation structure extending into the fin is formed at the position of part of the gate structure in the NMOS region, which is beneficial to saving the area of the semiconductor structure.

[0012] The method for forming the semiconductor structure provided by the embodiment of the present application forms the first isolation structure in the fin between the adjacent gate structures to be isolated in the PMOS region, forms the first source / drain doping layer in the fin on both sides of the gate structure in the PMOS region, forms the second source / drain doping layer in the fin on both sides of the gate structure in the NMOS region, and forms the second isolation structure in the position of the partial gate structure in the NMOS region, which extends into the fin. Since the carrier of the PMOS region is a hole and the carrier of the NMOS region is an electron, the response speed of the electron is faster than that of the hole, and the hole is more sensitive to the change of stress, that is, after the loss of the same absolute value of stress, the response speed of the PMOS region decreases more than that of the NMOS region. The first isolation structure is formed in the fin between the adjacent gate structures to be isolated in the PMOS region, which avoids removing the gate structure in the PMOS region and reduces the stress loss of the first source / drain doping layer caused by the formation of the first isolation structure, and accordingly reduces the decrease range of the response speed of the PMOS region, thereby reducing the difference between the response speeds of the PMOS region and the NMOS region after the formation of the first isolation structure, and further improving the performance of the semiconductor structure. Moreover, compared with the scheme of forming the first isolation structure in the PMOS region and the NMOS region, the first isolation structure is formed in the fin between the adjacent gate structures to be isolated in the PMOS region, and the second isolation structure extending into the fin is formed in the position of the partial gate structure in the NMOS region, that is, the second isolation structure extending into the fin is formed in the position of the partial gate structure in the NMOS region, which is beneficial to saving the area of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figures 1 to 6 is a structure diagram corresponding to each step in a method for forming a semiconductor structure;

[0014] Figure 7 is a structure diagram of an embodiment of the semiconductor structure of the present application;

[0015] Figure 8 is Figure 7 is a local enlarged view at the position B;

[0016] Figures 9 to 27 is a structure diagram corresponding to each step in a method for forming a semiconductor structure of an embodiment of the present application. DETAILED DESCRIPTION

[0017] At present, the performance of the semiconductor structure still needs to be improved. Now, the reason why the performance of the semiconductor structure needs to be improved is analyzed in combination with a method for forming a semiconductor structure.Figures 1 to 6 is a structure diagram corresponding to each step in a method for forming a semiconductor structure.

[0018] Since the semiconductor structure of the NMOS region is similar to that of the PMOS region, for the convenience of showing the structure of the semiconductor, Figures 1 to 6 only the PMOS region is shown.

[0019] Referring to Figure 1 , a substrate 10 is provided, the substrate 10 includes a PMOS region 21 and an NMOS region (not shown), and the substrate 10 is formed with discrete fin portions 11, and the substrate 10 is further formed with gate structures 12 crossing the fin portions, the gate structures 12 cover part of the top and part of the sidewall of the fin portions 11,

[0020] Referring to Figure 2 , in the PMOS region 21 and the NMOS region, a patterned mask structure 13 is formed on the gate structures 12, the mask structure 13 is formed with initial mask openings 14 located above the gate structures 12 to be removed in the PMOS region 21 and above the gate structures 12 to be removed in the NMOS region.

[0021] Referring to Figure 3 , along the initial mask openings 14, the mask structure 13 at the bottom of the initial mask openings 14 is removed, forming mask openings 15, the mask openings 15 expose the top of the gate structures 12 to be removed.

[0022] Referring to Figure 4 , along the mask openings 15, the gate structures 12 and the fin portions 11 at the bottom of the mask openings 15 are removed, forming initial isolation openings 16.

[0023] Referring to Figure 5 , along the initial isolation openings 16, the substrate 10 at the bottom of the initial isolation openings 16 is removed by a partial thickness, forming isolation openings 17; after the isolation openings 17 are formed, the remaining mask structure 13 is removed.

[0024] Referring to Figure 6 , a layer of isolation structure material (not labeled) is filled in the isolation openings 17, and the layer of isolation structure material is also formed on the remaining gate structures 12, wherein the layer of isolation structure material in the isolation openings 17 in the PMOS region 21 and the layer of isolation structure material in the isolation openings 17 in the NMOS region are both isolation structures 18.

[0025] It is found through research that, since the carriers of the PMOS region are holes and the carriers of the NMOS region are electrons, the response speed of the electrons is faster, so the response speed of the NMOS region is faster compared with the response speed of the PMOS region. Therefore, after removing the partial gate structures of the PMOS region 21 and the NMOS region, the response speed of the PMOS region decreases by a greater magnitude than the response speed of the NMOS region, thereby further increasing the difference value of the response speeds of the PMOS region and the NMOS region, and further affecting the performance of the semiconductor structure.

[0026] To solve the above technical problems, the embodiment of the present application provides a semiconductor structure, comprising: a substrate, the substrate comprising a PMOS region and an NMOS region, and discrete fin portions formed on the substrate; a gate structure located on the substrate and crossing the fin portions, the gate structure covering part of the top and part of the sidewall of the fin portions; a first isolation structure located in the PMOS region and in the fin portions between adjacent gate structures to be isolated; a second isolation structure located in the NMOS region, the second isolation structure crossing the fin portions on the side of the gate structure and arranged side by side with the gate structure, and the bottom of the second isolation structure extending into the fin portions; a first source-drain doped layer located in the fin portions on both sides of the gate structure of the PMOS region; and a second source-drain doped layer located in the fin portions on both sides of the gate structure of the NMOS region.

[0027] The semiconductor structure provided by the embodiment of the present application comprises a first isolation structure in the PMOS region and in the fin between the adjacent gate structures to be isolated, a second isolation structure in the NMOS region, the second isolation structure crossing the fin of the side of the gate structure and being arranged side by side with the gate structure, and the bottom of the second isolation structure extending into the fin; a first source-drain doping layer in the fin on both sides of the gate structure of the PMOS region, and a second source-drain doping layer in the fin on both sides of the gate structure of the NMOS region. Since the carrier of the PMOS region is a hole, and the carrier of the NMOS region is an electron, the response speed of the electron is faster than that of the hole, and the hole is more sensitive to the change of stress, that is, after the loss of the same absolute value of stress, the response speed of the PMOS region decreases more than that of the NMOS region. The first isolation structure is formed in the fin between the adjacent gate structures to be isolated in the PMOS region, which avoids removing the gate structure of the PMOS region, reduces the stress loss of the first source-drain doping layer caused by the formation of the first isolation structure, and accordingly reduces the decrease of the response speed of the PMOS region, thereby reducing the difference between the response speeds of the PMOS region and the NMOS region after the formation of the first isolation structure, and further improving the performance of the semiconductor structure. Moreover, compared with the scheme of forming the first isolation structure in the PMOS region and the NMOS region, the embodiment of the present application comprises the first isolation structure in the PMOS region and in the fin between the adjacent gate structures to be isolated, the second isolation structure in the NMOS region, the second isolation structure crossing the fin of the side of the gate structure and being arranged side by side with the gate structure, and the bottom of the second isolation structure extending into the fin, that is, the second isolation structure extending into the fin is formed at the position of the part of the gate structure of the NMOS region, which is beneficial to saving the area of the semiconductor structure.

[0028] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0029] Figure 7 is a structure schematic diagram of an embodiment of the semiconductor structure of the present application;

[0030] Figure 8 is Figure 7 is a local enlarged view at the position B.

[0031] Reference Figures 7 to 8In this embodiment, the semiconductor structure includes: a substrate 100 including a PMOS region 101 and an NMOS region 102, and a discrete fin 110 formed on the substrate 100; a gate structure 120 located on the substrate 100 and across the fin 110, the gate structure 120 covering part of the top and part of the sidewall of the fin 110; a first isolation structure 150 located in the PMOS region 101 and in the fin 110 between adjacent gate structures 120 to be isolated; a second isolation structure 155 located in the NMOS region 102, the second isolation structure 155 across the fin 110 on the side of the gate structure 120 and arranged side by side with the gate structure 120, the bottom of the second isolation structure 155 extending into the fin 110; a first source-drain doped layer 161 located in the fin 110 on both sides of the gate structure 120 in the PMOS region 101; and a second source-drain doped layer 162 located in the fin 110 on both sides of the gate structure 120 in the NMOS region 102.

[0032] The substrate 100 is used to provide a process platform for forming the semiconductor structure.

[0033] In this embodiment, the substrate 100 is used to form a field effect transistor. As an example, the substrate 100 is used to form a fin field effect transistor.

[0034] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide, or other materials, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0035] The fin 110 provides a process basis for forming an active fin.

[0036] In this embodiment, the material of the fin 110 includes silicon. In other embodiments, the material of the fin can also include germanium, silicon germanium, III-V semiconductor material, monocrystalline silicon, or other materials.

[0037] In this embodiment, the semiconductor structure further includes an isolation layer (not shown in the figure) located on the substrate 100 and surrounding the fin 110, the isolation layer covering part of the sidewall of the fin 110.

[0038] The isolation layer is used to achieve isolation between adjacent fins 110 and isolation between the substrate 100 and each semiconductor device. The fin 110 exposed by the isolation layer serves as an active fin.

[0039] Specifically, the isolation layer is a shallow trench isolation (STI) structure. As an example, the material of the isolation layer is silicon oxide. In other embodiments, the material of the isolation layer can also be silicon nitride or silicon oxynitride, or other insulating materials.

[0040] The fin 110 covered by the gate structure 120 is used to provide a conductive channel when the semiconductor device is working.

[0041] Specifically, the effective fin covered by the gate structure 120 is used to provide a conductive channel when the semiconductor device is working.

[0042] In this embodiment, the gate structure 120 is a device gate structure 123.

[0043] Specifically, the device gate structure 123 includes a gate dielectric layer (not shown in the figure) and a gate electrode layer (not shown in the figure) covering the gate dielectric layer.

[0044] The device gate structure 123 is used to form a field effect transistor with the conductive channel and the source / drain doped layer 163.

[0045] The gate dielectric layer is used to isolate the gate electrode layer from the conductive channel.

[0046] The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0047] In this embodiment, the device gate structure 123 is a metal gate structure, and therefore, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. The gate electrode layer includes a work function layer and an electrode layer covering the work function layer, or can only include the work function layer.

[0048] Correspondingly, the gate dielectric layer includes a high-k gate dielectric layer. The material of the high-k gate dielectric layer is a high-k dielectric material, which refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the high-k gate dielectric layer is HfO2.

[0049] In other embodiments, the device gate structure can also be a polysilicon gate structure.

[0050] The first isolation structure 150 is a double diffusion break (DDB) isolation structure, and is located between the adjacent gate structures 120 to be isolated in the PMOS region 101, so as to realize electrical isolation between part of the adjacent gate structures 120 and prevent bridge between adjacent devices.

[0051] Since the carriers of the PMOS region 101 are holes and the carriers of the NMOS region 102 are electrons, the response speed of the NMOS region 102 is faster than that of the PMOS region 101, and the holes are more sensitive to stress changes, that is, the response speed of the PMOS region 101 decreases more than that of the NMOS region 102 after the same absolute stress loss. The first isolation structure 150 is formed in the fin 110 between the adjacent gate structures 120 to be isolated in the PMOS region 101, which avoids removing the gate structures 120 in the PMOS region 101 and reduces the stress loss of the first source / drain doping layer formed subsequently, and accordingly reduces the response speed decrease of the PMOS region 101, thereby reducing the difference between the response speeds of the PMOS region 101 and the NMOS region 102 after the first isolation structure 150 is formed, and further improving the performance of the semiconductor structure.

[0052] The first isolation structure 150 is located in the fin between the adjacent gate structures to be isolated in the PMOS region 101, and is used to realize electrical isolation between part of the adjacent gate structures 120. It can be understood that the top of the first isolation structure 150 is higher than the top of the conductive channel, that is, the top of the first isolation structure 150 is higher than the top of the fin 110, and the bottom of the first isolation structure 150 is lower than the bottom of the fin 110, so that the isolation effect of the first isolation structure 150 is better.

[0053] Since the bottom of the first isolation structure 150 is lower than the bottom of the fin 110, that is, the bottom of the first isolation structure 150 is also lower than the bottom of the gate structure 120.

[0054] Generally, before the first isolation structure 150 is formed, a first recess (not shown in the figure) is first formed in the fin 110 between the adjacent gate structures 120 to be isolated in the PMOS region, and then the first isolation structure 150 is formed in the first recess. In the step of forming the first recess, the range of the first recess bottom being lower than the fin 110 bottom along the normal direction of the top surface of the substrate 100 is 100 angstrom to 1000 angstrom, which is beneficial to ensure that the bottom of the first isolation structure 150 is lower than the bottom of the fin 110.

[0055] In the embodiment, the material of the first isolation structure 150 includes graphene.

[0056] The graphene material can have good insulation performance, so that the first isolation structure 150 can achieve better electrical isolation effect between the adjacent gate structures 120. In other embodiments, the material of the first isolation structure can also include other dielectric materials, such as a material with a relative dielectric constant lower than 3.9.

[0057] The second isolation structure 155 is a single diffusion break (SDB) isolation structure, which is arranged across the fin 110 on the side of the gate structure 120 and parallel to the gate structure 120, and the bottom of the second isolation structure 155 extends into the fin 110, so as to achieve electrical isolation between the adjacent second source / drain doped layers 162 and prevent bridging between adjacent devices.

[0058] Compared with the scheme of forming the first isolation structure in both the PMOS region and the NMOS region, the embodiment of the present application forms the first isolation structure 150 in the fin 110 between the adjacent gate structures 120 to be isolated in the PMOS region 101, and in the NMOS region 102, the second isolation structure 155 is formed at the position of the gate structure 120, and the second isolation structure 155 extends into the fin 110, that is, the second isolation structure 155 extending into the fin 110 is formed at the position of the gate structure 120 in the NMOS region 102, which is beneficial to saving the area of the semiconductor structure.

[0059] Specifically, in the NMOS region 102, the second isolation structure 155 is arranged across the fin 110 on the side of the gate structure 120 and parallel to the gate structure 120, and the bottom of the second isolation structure 155 extends into the fin 110, so as to achieve electrical isolation between the adjacent second source / drain doped layers 162. It can be understood that the bottom of the second isolation structure 155 is lower than the bottom of the fin 110, so that the isolation effect of the second isolation structure 155 is better.

[0060] In the embodiment, the material of the second isolation structure 155 is a dielectric material.

[0061] The first source / drain doped layer 161 is used as a source region and a drain region of a transistor in the PMOS region 101. During device operation, the first source / drain doped layer 161 is used to provide carriers for the PMOS region 101.

[0062] In the embodiment, the first source / drain doped layer 161 is doped with P-type ions, which include B ions, Ga ions or In ions.

[0063] The second source / drain doped layer 162 is used as a source region and a drain region of a transistor in the NMOS region 102. During device operation, the second source / drain doped layer 162 is used to provide carriers for the NMOS region 102.

[0064] As the second isolation structure 155 is arranged across the fin 110 and parallel to the gate structure 120, it can be understood that the second source-drain doped layer 162 is also located on both sides of the second isolation structure 155.

[0065] The second source-drain doped layer 162 and the first source-drain doped layer 161 form a source-drain doped layer 163.

[0066] In this embodiment, the second source-drain doped layer 562 is doped with N-type ions, which include P ions, As ions or Sb ions.

[0067] In this embodiment, the semiconductor structure further comprises an interlayer dielectric layer 170 covering the top of the first source-drain doped layer 161 and the second source-drain doped layer 162, and covering the sidewall of the gate structure 120, the top of the first isolation structure 150 and the sidewall of the second isolation structure 155.

[0068] The interlayer dielectric layer 170 is used to isolate adjacent devices. The interlayer dielectric layer 170 covering the top of the source-drain doped layer 163, the sidewall of the gate structure 120 and the top of the first isolation structure 150 is usually formed before the second isolation structure 155 is formed, so as to facilitate the formation of the second isolation structure 155 at the position of the partial gate structure 120 of the NMOS region 102.

[0069] It should be noted that the material of the interlayer dielectric layer 170 is an insulating material, for example, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. As an example, the material of the interlayer dielectric layer 170 is silicon oxide.

[0070] In this embodiment, the semiconductor structure further comprises a source-drain interconnection layer 165 located in the interlayer dielectric layer 170 on the top of the first source-drain doped layer 161 and the top of the second source-drain doped layer 162, and electrically connected to the first source-drain doped layer 161 and the second source-drain doped layer 162 respectively; and a first air sidewall 171 located between the source-drain interconnection layer 165 and the gate structure 120.

[0071] The source-drain interconnection layer 165 is electrically connected to the top of the first source-drain doped layer 161 and the top of the second source-drain doped layer 162 respectively, and is used to realize the electrical connection between the source-drain doped layer 163 and an external circuit.

[0072] As the dielectric constant of air is smaller than that of dielectric materials, the first air sidewall 171 is beneficial to reduce the parasitic capacitance between the gate structure 120 and the source-drain interconnection layer 165, and improve the performance of the semiconductor structure.

[0073] The first air side wall 171 is located between the gate structure 120 and the source-drain interconnection layer 165, that is, the first air side wall 171 exposes the sidewall of the source-drain interconnection layer 165.

[0074] It should be noted that the thickness of the first air side wall 171 should not be too small or too large. If the thickness of the first air side wall 171 is too small, it is easy to increase the difficulty of forming the first air side wall 171; if the thickness of the first air side wall 171 is too large, it is easy to reduce the effect of the subsequent film layer formed in the first air side wall. Therefore, in the embodiment, the thickness of the first air side wall 171 ranges from 10 angstroms to 30 angstroms.

[0075] In the embodiment, the semiconductor structure further includes: a side wall structure 130 located on the substrate 100 and across the fin 110, the side wall structure 130 is arranged opposite to the sidewall of the gate structure 120; and a second air side wall 172 located between the gate structure 120 and the side wall structure 130.

[0076] The side wall structure 130 is used to protect the sidewall of the gate structure 120, that is, the sidewall of the device gate structure 123.

[0077] The second air side wall 172 is beneficial to further reduce the parasitic capacitance between the gate structure 120 and the source-drain interconnection layer 165, and improve the performance of the semiconductor structure.

[0078] It should be noted that generally, an initial side wall structure (not shown in the figure) is formed first, the initial side wall structure includes a first side wall layer (not shown in the figure) closest to the gate structure 120, after the source-drain interconnection layer 165 is formed, the first side wall layer is removed, the second air side wall 172 is formed, and the remaining initial side wall structure serves as the side wall structure 130. It can be understood that the initial side wall structure is a laminated structure.

[0079] In a specific embodiment, the initial side wall structure includes a first side wall layer closest to the gate structure 120, a second side wall layer (not shown in the figure) covering the first side wall layer, and a third side wall layer (not shown in the figure) covering the second side wall layer.

[0080] In other embodiments, the initial side wall structure can also be a single-layer structure, and correspondingly, the second air side wall and the first air side wall are mutually penetrated.

[0081] It should be noted that the material of the side wall structure 130 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride, silicon carbon nitrogen oxide, silicon oxynitride, boron nitride, boron carbon nitride, and low-k dielectric material. Among them, the low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9.

[0082] As an example, the first sidewall layer is a low-k dielectric material, the material of the second sidewall layer is silicon nitride, and the material of the third sidewall layer is silicon oxide.

[0083] In other embodiments, the first sidewall layer can also be reserved after the source-drain interconnection layer.

[0084] In this embodiment, the semiconductor structure further includes a contact etch stop layer (CESL) 136 located between the source-drain doped layer 163 and the interlayer dielectric layer 170, on top of the first isolation structure 150, and on the sidewall of the gate structure 120.

[0085] The contact etch stop layer 136 is used to improve the stress of the source-drain doped layer 163.

[0086] In addition, the step of forming the source-drain interconnection layer 165 generally includes: forming a third recess (not shown in the figure) in the interlayer dielectric layer 170 on top of the source-drain doped layer 163, the third recess exposing the source-drain doped layer; and forming the source-drain interconnection layer 165 in the third recess.

[0087] In this embodiment, the semiconductor structure further includes a contact etch stop layer (CESL) 136 located between the source-drain doped layer 163 and the interlayer dielectric layer 170, on top of the first isolation structure 150, and on the sidewall of the gate structure 120.

[0088] In this embodiment, the semiconductor structure further includes a contact etch stop layer (CESL) 136 located between the source-drain doped layer 163 and the interlayer dielectric layer 170, on top of the first isolation structure 150, and on the sidewall of the gate structure 120.

[0089] It should be noted that the material of the sealing layer 180 includes a dielectric material. As an example, the material of the sealing layer 180 is silicon nitride.

[0090] Correspondingly, the present application also provides a method for forming a semiconductor structure. Figures 9 to 27 is a structure schematic diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present application.

[0091] Reference Figure 9 , a substrate 500 is provided, the substrate including a PMOS region 501 and an NMOS region 502, and the substrate 500 has a discrete fin 510 formed thereon.

[0092] The substrate 500 is used to provide a process platform for subsequent process procedures.

[0093] In this embodiment, the substrate 500 is used to form a field effect transistor. As an example, the substrate 500 is used to form a fin field effect transistor.

[0094] In this embodiment, the substrate 500 is a silicon substrate. In other embodiments, the substrate can also be a germanium, silicon germanium, silicon carbide, gallium arsenide, or other material, and can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other type of substrate.

[0095] The fin 510 provides a process basis for forming an effective fin later, and occupies a space position for forming a first isolation structure and a second isolation structure later.

[0096] In this embodiment, the material of the fin 510 includes silicon. In other embodiments, the material of the fin can also include germanium, silicon germanium, a group III-V semiconductor material, monocrystalline silicon, or other material.

[0097] In this embodiment, after the substrate 500 is provided, before the gate structure is formed, the forming method further includes: forming an isolation layer (not shown in the figure) surrounding the fin 510 on the substrate 500, the isolation layer covering part of the sidewall of the fin 510.

[0098] The isolation layer is used to achieve isolation between adjacent fins 510, and is used to achieve isolation between the substrate 500 and each semiconductor device formed later. The fin 510 exposed by the isolation layer serves as an effective fin.

[0099] Specifically, the isolation layer is a shallow trench isolation structure. As an example, the material of the isolation layer is silicon oxide. In other embodiments, the material of the isolation layer can also be silicon nitride or silicon oxynitride, or other insulating material.

[0100] Continuing to refer to Figure 9 The gate structure 520 is formed on the substrate 500 to span the fin 510, and covers part of the top and part of the sidewall of the fin 510.

[0101] The fin 510 covered by the gate structure 520 is used to provide a conductive channel when the semiconductor device is working.

[0102] Specifically, the effective fin covered by the gate structure 520 is used to provide a conductive channel when the semiconductor device is working.

[0103] In this embodiment, in the step of forming the gate structure 520 on the substrate 500 to span the fin 510, the gate structure 520 is a pseudo gate structure 521.

[0104] The pseudo gate structure 521 is used to occupy a space position for forming a device gate structure later.

[0105] As an example, the material of the pseudo gate structure 521 can be polysilicon, amorphous silicon, or amorphous carbon, etc.

[0106] Referring to Figure 10 , in combination with referenceFigure 9 In this embodiment, after the gate structure 520 is formed, before the first isolation structure is formed, the forming method further includes: forming a side wall structure 530 on the side wall of the gate structure 520, the side wall structure 530 includes a first side wall layer 531 closest to the gate structure 520.

[0107] wherein, Figure 10 for Figure 9 A local enlarged view of the A region.

[0108] The side wall structure 530 is also used to protect the side wall of the dummy gate structure 521 and the device gate structure formed later.

[0109] The first side wall layer occupies a space position for the second air side wall formed later.

[0110] Specifically, the side wall structure 530 is a laminated structure.

[0111] The side wall structure 530 is a laminated structure, and accordingly, after the first side wall layer 531 closest to the gate structure 520 is removed and the second air side wall is formed, the side wall structure 530 remains between the first air side wall and the second air side wall, so that the lateral width of the first air side wall and the second air side wall is not easily too large, thereby reducing the probability of the film layer formed in the first air side wall or the second air side wall later.

[0112] Here, the lateral width refers to the width in the direction perpendicular to the side wall of the gate structure 520.

[0113] In other embodiments, the side wall structure can also be a single-layer structure, and accordingly, the side wall structure includes only the first side wall layer on the side wall of the gate structure.

[0114] More specifically, the side wall structure 530 includes the first side wall layer 531 closest to the gate structure 520, a second side wall layer (not shown in the figure) covering the first side wall layer 531, and a third side wall layer (not shown in the figure) covering the second side wall layer.

[0115] It should be noted that the material of the side wall structure 530 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride, silicon carbon nitrogen oxide, silicon nitrogen oxide, boron nitride, boron carbon nitride, and low-k dielectric material. The low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9.

[0116] As an example, the material of the first side wall layer 531 is a low-k dielectric material, the material of the second side wall layer is silicon nitride, and the material of the third side wall layer is silicon oxide.

[0117] In this embodiment, the side wall structure 530 is also formed on the top and sidewall of the fin 510 on both sides of the gate structure 520.

[0118] Reference is made to Figures 11 to 15 and in combination with reference to Figures 9 to 10 In the PMOS region 501, the first isolation structure 550 is formed in the fin 510 between the adjacent gate structures 520 to be isolated.

[0119] It should be noted that, in order to clearly show the structure of the semiconductor, Figures 11 to 15 Only the PMOS region is shown.

[0120] The first isolation structure 550 is a double diffusion break isolation structure, and the first isolation structure 550 is located between the adjacent gate structures 520 to be isolated, for realizing the electrical isolation between part of the adjacent gate structures 520, and preventing the bridging between the adjacent devices.

[0121] Since the carriers of the PMOS region 501 are holes, and the carriers of the NMOS region 502 are electrons, the response speed of the NMOS region 502 is faster than that of the PMOS region 501; and the holes are more sensitive to the change of stress, that is, after losing the same absolute value of stress, the response speed of the PMOS region 501 decreases more than that of the NMOS region 502. By forming the first isolation structure 550 in the fin 510 between the adjacent gate structures 520 to be isolated in the PMOS region 501, the gate structure 520 of the PMOS region 501 is avoided to be removed, the stress loss caused by forming the first isolation structure 550 to the first source / drain doping layer formed subsequently is reduced, and the response speed decrease amplitude of the PMOS region 501 is also reduced accordingly, thereby reducing the difference between the response speeds of the PMOS region 501 and the NMOS region 502 after the first isolation structure 550 is formed, and further improving the performance of the semiconductor structure.

[0122] Specifically, the first isolation structure 550 is located in the fin 510 between the adjacent gate structures 520 to be isolated in the PMOS region 501, for realizing the electrical isolation between part of the adjacent gate structures 520. It can be understood that the top of the first isolation structure 550 is higher than the top of the conductive channel, that is, the top of the first isolation structure 550 is higher than the top of the fin 510, and the bottom of the first isolation structure 550 is lower than the bottom of the fin 510, so that the isolation effect of the first isolation structure 550 is better.

[0123] Since the bottom of the first isolation structure 550 is lower than the bottom of the fin 510, that is, the bottom of the first isolation structure 550 is also lower than the bottom of the gate structure 520.

[0124] In the embodiment, the step of forming the first isolation structure 550 comprises: forming a first recess 551 in the fin 510 between the adjacent gate structures 520 to be isolated in the PMOS region 501; and forming the first isolation structure 550 in the first recess 551.

[0125] The first recess 551 is formed in the fin 510 between the adjacent gate structures 520 to be isolated in the PMOS region 501 before the first isolation structure 550 is formed in the first recess 551, which is beneficial to reduce the difficulty of forming the first isolation structure 550.

[0126] In the embodiment, before the first recess 551 is formed, the forming method further comprises: forming a source-drain recess 560 in the fin 510 on both sides of the gate structure 520 in the PMOS region 501; and Figure 11 as shown, the step of forming the first recess 551 comprises: removing the fin 510 at the bottom of the source-drain recess 560 between the adjacent gate structures 520 to be isolated, so as to form the first recess 551. Figures 12 to 13

[0127] The source-drain recess 560 is formed in the fin 510 on both sides of the gate structure 520 in the PMOS region 501 before the fin 510 at the bottom of the source-drain recess 560 between the adjacent gate structures 520 to be isolated is removed, which reduces the thickness of the fin 510 to be removed, and thus reduces the process difficulty.

[0128] Specifically, after the side wall structure 530 is formed, before the first isolation structure 550 is formed, the forming method further comprises: forming a patterned third mask structure 543 on the top and the side wall of the gate structure 520, the third mask structure 543 being a PMOS Si recess (PSR) mask structure, and exposing the top and the side wall of the fin 510 on both sides of the gate structure 520; the step of forming the source-drain recess 560 comprises: removing a part of the thickness of the fin 510 with the third mask structure 543 as a mask, so as to form the source-drain recess 560 in the fin 510 on both sides of the gate structure 520 in the PMOS region 501; and after the source-drain recess 560 is formed, the method further comprises: removing the third mask structure 543.

[0129] It should be noted that the top of the first isolation structure 550 is higher than the top of the fin 510, and the bottom of the first isolation structure 550 is lower than the bottom of the fin 510; and correspondingly, in the process of removing the fin 510 at the bottom of the source-drain recess 560 between the adjacent gate structures 520 to be isolated, a first part of the thickness of the substrate is also removed.

[0130] ​It is also to be noted that, when the range of the first recess 551 bottom being lower than the fin 510 bottom along the normal direction of the substrate 500 top surface is 100 angstrom to 1000 angstrom, it is beneficial to ensure that the first isolation structure 550 bottom is lower than the fin bottom, so as to easily make the isolation effect of the first isolation structure 550 better.

[0131] In the embodiment, the step of forming the first recess 551 includes: forming a first mask structure 541 covering the top of the fin 510 and the gate structure 520, the first mask structure 541 being formed with a first mask opening 5411 above the fin 510 between the adjacent gate structures 520 to be isolated (as shown in FIG. 5B); removing the first mask structure 541 at the bottom of the first mask opening 5411 and part of the thickness of the fin 510 along the first mask opening 5411 to form the first recess 551 (as shown in FIG. 5C); and the forming method further includes: removing the first mask structure 541. Figure 12 Figure 13 In the embodiment, the step of forming the first recess 551 includes: forming a first mask structure 541 covering the top of the fin 510 and the gate structure 520, the first mask structure 541 being formed with a first mask opening 5411 above the fin 510 between the adjacent gate structures 520 to be isolated (as shown in FIG. 5B); removing the first mask structure 541 at the bottom of the first mask opening 5411 and part of the thickness of the fin 510 along the first mask opening 5411 to form the first recess 551 (as shown in FIG. 5C); and the forming method further includes: removing the first mask structure 541.

[0132] In the embodiment, the step of forming the first recess 551 includes: forming a first mask structure 541 covering the top of the fin 510 and the gate structure 520, the first mask structure 541 being formed with a first mask opening 5411 above the fin 510 between the adjacent gate structures 520 to be isolated (as shown in FIG. 5B); removing the first mask structure 541 at the bottom of the first mask opening 5411 and part of the thickness of the fin 510 along the first mask opening 5411 to form the first recess 551 (as shown in FIG. 5C); and the forming method further includes: removing the first mask structure 541.

[0133] It is to be noted that the first mask structure 541 includes a first mask layer 5412 covering the top of the fin 510 and the gate structure 520, a second mask layer 5413 covering the first mask layer 5412, and a third mask layer 5414 covering the second mask layer 5413.

[0134] It is also to be noted that the material of the first mask structure 541 includes an anti-reflective coating material, spin-on carbon (SOC), photoresist, etc. As an example, the material of the first mask layer 5412 includes spin-on carbon and anti-reflective coating material, the material of the second mask layer 5413 includes a reflective coating material, and the material of the third mask layer 5414 includes photoresist.

[0135] In the embodiment, in the step of forming the first isolation structure 550, the first isolation structure 550 is formed under the protection of the first mask structure (as shown in FIG. 5C). Figure 14 ​The first mask structure 541 is removed (as shown) after the first isolation structure 550 is formed. Figure 15 The first mask structure 541 is removed (as shown) after the first isolation structure 550 is formed.

[0136] The first isolation structure 550 is formed under the protection of the first mask structure 541, which is conducive to reducing the probability of the material corresponding to the first isolation structure 550 being formed on other film layers (for example, the side wall structure 530 and the gate structure 520).

[0137] In this embodiment, the process of forming the first isolation structure 550 in the first recess 551 includes a dielectric-on-dielectric (DOD) selective deposition process.

[0138] The first isolation structure 550 is formed in the first recess 551 by using the dielectric-on-dielectric (DOD) selective deposition process, which is conducive to simplifying the process steps of forming the first isolation structure 550 and saving process costs.

[0139] Specifically, after the first recess 551 is formed and before the first isolation structure 550 is formed, the forming method further includes: performing an oxidation treatment on the surface of the first recess 551; and after the oxidation treatment, forming the first isolation structure 550 in the first recess 551.

[0140] The surface of the first recess 551 is oxidized before the first isolation structure 550 is formed, which is conducive to improving the efficiency of forming the first isolation structure 550 by using the dielectric-on-dielectric (DOD) selective deposition process.

[0141] In this embodiment, the material of the first isolation structure 550 includes graphene.

[0142] The graphene material can have good insulation performance, so that the first isolation structure 550 can achieve a better effect of electrically isolating between some adjacent gate structures 520. In other embodiments, the material of the first isolation structure can also include other dielectric materials, for example, a material with a relative dielectric constant lower than 3.9.

[0143] Referring to FIG. 5B, Figure 16 After the first isolation structure 550 is formed, the first source / drain doped layer 561 is formed in the fin portion on both sides of the gate structure 520 in the PMOS region 501.

[0144] The first source / drain doped layer 561 is used as a source region and a drain region of the transistor in the PMOS region 501. During device operation, the first source / drain doped layer 561 is used to provide carriers for the PMOS region 501.

[0145] Specifically, the step of forming the first source-drain doping layer 561 comprises: after forming the first isolation structure 550, forming the first source-drain doping layer 561 in the source-drain recess 560 remaining in the PMOS region 501.

[0146] After forming the first isolation structure 550, the first source-drain doping layer 561 is formed in the source-drain recess 560 remaining in the PMOS region 501, that is, the first source-drain doping layer 561 is not formed when the first isolation structure 550 is formed, thereby further reducing the influence of forming the first isolation structure 550 on the first source-drain doping layer 561.

[0147] It should be noted that the first source-drain doping layer 561 is doped with P-type ions, and the P-type ions include B ions, Ga ions or In ions.

[0148] Reference Figures 17 to 21 After forming the second source-drain doping layer, the structure schematic diagram is shown in FIG. 6B.

[0149] Wherein, Figure 17 After forming the second source-drain doping layer, the structure schematic diagram is shown in FIG. 6B. Figure 16 After forming the second source-drain doping layer, the structure schematic diagram is shown in FIG. 6B. Figure 18 After forming the second source-drain doping layer, the structure schematic diagram is shown in FIG. 6B. Figure 17 The partial enlarged view of the A area is shown in FIG. 6C. Figure 19 The partial enlarged view of the A area is shown in FIG. 6C. Figure 17 After forming the second source-drain doping layer, the structure schematic diagram is shown in FIG. 6B. Figure 20 After forming the second source-drain doping layer, the structure schematic diagram is shown in FIG. 6B. Figure 19 The partial enlarged view of the A area is shown in FIG. 6C. Figure 21 The partial enlarged view of the A area is shown in FIG. 6C. Figure 20 After forming the second source-drain doping layer, the structure schematic diagram is shown in FIG. 6B.

[0150] The second source-drain doping layer 562 is used as the source region and the drain region of the transistor in the NMOS region 502. During device operation, the second source-drain doping layer 562 is used to provide carriers for the NMOS region 502.

[0151] It should be noted that the second source-drain doping layer 562 is doped with N-type ions, and the N-type ions include P ions, As ions or Sb ions.

[0152] In this embodiment, after forming the second source-drain doping layer 562, the second source-drain doping layer 562 and the first source-drain doping layer 561 form a source-drain doping layer 563, and before forming the second isolation structure, the forming method further comprises: as shown in FIG. 6D, forming an interlayer dielectric layer 570 covering the top of the source-drain doping layer 563, and the interlayer dielectric layer 570 also covers the sidewall of the gate structure 520 and the top of the first isolation structure 550. Figure 21 After forming the second source-drain doping layer, the structure schematic diagram is shown in FIG. 6B.

[0153] The interlayer dielectric layer 570 is used to isolate adjacent devices. Moreover, before forming the second isolation structure, the interlayer dielectric layer 570 is formed to cover the top of the source-drain doped layer 563, and the interlayer dielectric layer 570 also covers the sidewall of the gate structure 520 and the top of the first isolation structure 550, which facilitates the subsequent formation of the second isolation structure at the position of the partial gate structure 520 in the NMOS region 502.

[0154] It should be noted that the material of the interlayer dielectric layer 570 is an insulating material, for example, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. As an example, the material of the interlayer dielectric layer 570 is silicon oxide.

[0155] In this embodiment, as shown in FIG. 5B, after forming the second source-drain doped layer 562, the second source-drain doped layer 562 and the first source-drain doped layer 562 constitute the source-drain doped layer 563, and before forming the interlayer dielectric layer 570, the forming method further includes: forming a sacrificial layer 535 on the sidewall of the gate structure 520. Figures 17 to 18

[0156] The sacrificial layer 535 is used to occupy a space position for the subsequent formation of the first air side wall, and is also used as a self-aligned side wall layer in the subsequent process of forming the source-drain interconnection layer.

[0157] Specifically, the process of forming the sacrificial layer 535 includes an atomic layer deposition process.

[0158] The atomic layer deposition process is used to form the sacrificial layer 535, which is advantageous to improve the thickness uniformity of the sacrificial layer 535, thereby improving the thickness uniformity of the subsequently formed first air side wall.

[0159] It should be noted that the material of the sacrificial layer 535 includes one or more of amorphous silicon, amorphous carbon, and silicon nitride. As an example, the material of the sacrificial layer 535 includes amorphous silicon.

[0160] Amorphous silicon is a commonly used material in deposition processes, which has the characteristics of simple process and low cost. At the same time, the amorphous silicon structure is stable and is not easy to deform or produce stress, which greatly reduces the influence on the semiconductor structure. In the subsequent process of removing the sacrificial layer 535, the high etching selectivity between the selected material of the sacrificial layer 535 and the selected material of the interlayer dielectric layer 570 can be used to achieve the purpose of removing the sacrificial layer 535.

[0161] ​It is also to be noted that after the second source-drain doping layer 562 is formed, before the sacrificial layer 535 is formed, a contact etch stop layer (CESL) 536 is formed to cover the top of the source-drain doping layer 563, and the contact etch stop layer 536 also covers the sidewalls and top of the gate structure 520, and the top of the first isolation structure 550.

[0162] The contact etch stop layer 536 is used to improve the stress of the source-drain doping layer 563, and the contact etch stop layer 536 is also used as an initial etch stop position in a subsequent process of forming a source-drain interconnection layer.

[0163] It is to be further noted that the thickness of the sacrificial layer 535 should not be too small or too large. If the thickness of the sacrificial layer 535 is too small, it is easy to increase the difficulty of subsequent removal of the sacrificial layer 535 to form the first air side wall; if the thickness of the sacrificial layer 535 is too large, it is easy to reduce the effect of subsequent film layer formation in the first air side wall. Therefore, in the embodiment, the thickness of the sacrificial layer 535 ranges from 10 angstroms to 30 angstroms.

[0164] Reference is made to Figure 22 in combination with reference to Figure 21 In the NMOS region 502, a second isolation structure 555 is formed at the position of the partial gate structure 520, and the second isolation structure 555 extends into the fin 510 (as shown in Figure 22 .

[0165] It is to be noted that, in order to clearly show the semiconductor structure, Figure 22 only the NMOS region is shown in the semiconductor structure.

[0166] The second isolation structure 555 is a single diffusion break isolation structure, and the second isolation structure 555 is located at the position of the partial gate structure 520, and is used to achieve electrical isolation between the partial adjacent second source-drain doping layers 562, and prevent bridging between adjacent devices.

[0167] Compared with the scheme of forming the first isolation structure in both the PMOS region and the NMOS region, in the embodiment, the first isolation structure 550 is formed in the fin 510 between the adjacent gate structures 520 to be isolated in the PMOS region 501, and the second isolation structure 555 is formed at the position of the partial gate structure 520 in the NMOS region 502, and the second isolation structure 555 extends into the fin 510, that is, the second isolation structure 555 extending into the fin 510 is formed at the position of the partial gate structure 520 in the NMOS region 502, which is beneficial to save the area of the semiconductor structure.

[0168] It can be understood that the second isolation structure 555 is arranged across the fin 510 on the side of the gate structure 520 and is parallel to the gate structure 520, and the second source-drain doped layer 562 is also located on both sides of the second isolation structure 555.

[0169] Specifically, the step of forming the second isolation structure 555 includes: in the NMOS region 502, removing part of the gate structure 520 and part of the fin 510 at the bottom of the gate structure 520, and forming a second recess (not shown in the figure) in the interlayer dielectric layer 570; and forming the second isolation structure 555 in the second recess.

[0170] The second recess is formed in the interlayer dielectric layer 570 first, and then the second isolation structure 555 is formed in the second recess, which is beneficial to reduce the difficulty of forming the second isolation structure 555.

[0171] It should be noted that in the NMOS region 502, the second isolation structure 555 is formed at the position of part of the gate structure 520, and the second isolation structure 555 extends into the fin 510, which is used to realize electrical isolation between adjacent second source-drain doped layers 562. It can be understood that the bottom of the second isolation structure 555 is lower than the bottom of the fin 510, which is easy to make the isolation effect of the second isolation structure 555 better.

[0172] Correspondingly, in the NMOS region 502, in the process of removing part of the gate structure 520 and part of the fin 510 at the bottom of the gate structure 520, the second part of the thickness of the substrate 500 is also removed.

[0173] It should be further noted that the material of the second isolation structure 555 is a dielectric material.

[0174] In this embodiment, after the interlayer dielectric layer 570 is formed and before the second recess is formed, the forming method further includes: removing the dummy gate structure 521, and forming a device gate structure 523 (shown in the figure) at the position of the dummy gate structure 521. Figure 21

[0175] Specifically, the device gate structure 523 includes a gate dielectric layer (not shown in the figure) and a gate electrode layer (not shown in the figure) covering the gate dielectric layer.

[0176] The device gate structure 523 is used to form a field effect transistor with the conductive channel and the source-drain doped layer 563.

[0177] The gate dielectric layer is used to isolate the gate electrode layer and the conductive channel.

[0178] The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. ​

[0179] In this embodiment, the device gate structure 523 is a metal gate structure, and thus the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC. The gate electrode layer includes a work function layer and an electrode layer covering the work function layer, or can only include the work function layer.

[0180] Correspondingly, the gate dielectric layer includes a high-k gate dielectric layer. The material of the high-k gate dielectric layer is a high-k dielectric material, which refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3, etc. As an example, the material of the high-k gate dielectric layer is HfO2.

[0181] In other embodiments, the device gate structure can also be a polysilicon gate structure.

[0182] It should be noted that in the process of removing the dummy gate structure 521, the contact etching stop layer 536 on the top of the dummy gate structure 521 is also removed.

[0183] Correspondingly, in this embodiment, in the step of forming the second recess, the device gate structure 523 at the position where part of the dummy gate structure 521 is removed.

[0184] Reference Figures 23 to 26 In this embodiment, after the second isolation structure 555 is formed, the forming method further includes: forming a source-drain interconnection layer 565 electrically connected to the source-drain doped layer 563 in the interlayer dielectric layer 570 on the top of the source-drain doped layer 563, the source-drain interconnection layer 565 covering the sidewall of the sacrificial layer 535; after the source-drain interconnection layer 565 is formed, the sacrificial layer 535 is removed, and a first air sidewall 571 (as shown in Figures 25 to 26 ) is formed between the source-drain interconnection layer 565 and the gate structure 520.

[0185] Among them, Figure 26 As Figure 25 A local enlarged view of the B region.

[0186] It should be noted that, in order to clearly show the semiconductor structure, Figures 23 to 25 only the NMOS region is shown in the figure.

[0187] The source-drain interconnection layer 565 is electrically connected to the source-drain doped layer 563, and is used to realize the electrical connection between the source-drain doped layer 563 and an external circuit.

[0188] Since the dielectric constant of air is smaller than that of dielectric material, the first air sidewall 571 is beneficial to reduce the parasitic capacitance between the gate structure 520 and the source-drain interconnection layer 565, and improve the performance of the semiconductor structure.

[0189] It can be understood that, since the source-drain interconnection layer 565 is formed, the sacrificial layer 535 is removed, and the first air sidewall 571 is formed between the source-drain interconnection layer 565 and the gate structure 520, that is, after the first air sidewall 571 is formed by removing the sacrificial layer 535, the sidewall of the source-drain interconnection layer 165 is exposed.

[0190] Specifically, the step of forming the source-drain interconnection layer 565 comprises: forming a third recess 566 in the interlayer dielectric layer 570 on top of the source-drain doped layer 563, with the sacrificial layer 535 as a self-aligned sidewall, the third recess 566 exposing the source-drain doped layer 563 (as shown in Figure 23 The source-drain interconnection layer 565 is formed in the third recess 566 (as shown in Figure 24

[0191] Forming the third recess 566 in the interlayer dielectric layer 570 on top of the source-drain doped layer 563 with the sacrificial layer 535 as a self-aligned sidewall is beneficial to reduce the probability of damage to other film layers (such as the device gate structure 523, the sidewall structure 530, etc.) in the process of forming the third recess 566, improve the position accuracy, size accuracy and topography accuracy of the third recess 566, and thus improve the quality of the source-drain interconnection layer 565; moreover, forming the third recess 566 in the interlayer dielectric layer 570 on top of the source-drain doped layer 563 first, and then forming the source-drain interconnection layer 565 in the third recess 566, is beneficial to reduce the difficulty of forming the source-drain interconnection layer 565.

[0192] More specifically, the step of forming the third recess 566 in the interlayer dielectric layer 570 on top of the source-drain doped layer 563 comprises: forming a patterned second mask structure 542 on the device gate structure 523 and the interlayer dielectric layer 570, the second mask structure 542 having a second mask opening 5421 above the source-drain doped layer 563; removing the second mask structure 542, the interlayer dielectric layer 570 and the contact etching stop layer 536 at the bottom of the second mask opening 5421 along the second mask opening 5421 to expose the source-drain doped layer 563, so as to form the third recess 566; and removing the second mask structure 542 after the third recess 566 is formed.

[0193] In this embodiment, the contact etching stop layer 536 is used as an initial stop position to form an initial third recess (not shown in the figure), and then the contact etching stop layer 536 at the bottom of the initial third recess is removed along the initial third recess to form the third recess 566.

[0194] ​In one embodiment, the second mask structure 542 includes a metal hard mask layer 5422. The sacrificial layer 535 is used to reduce the risk of damaging the device gate structure 523 during the removal of the metal hard mask layer 5422.

[0195] It is noted that the third recess 566 is formed in the ILD layer 570 on top of the source / drain doped layer 563 using an anisotropic dry etching process with the sacrificial layer 535 as a self-aligned sidewall. As an example, the etching selectivity ratio of the sacrificial layer 535 to the ILD layer 570 is greater than 8.

[0196] In other embodiments, the contact etch stop layer covering the sidewall of the gate structure is also removed in the step of removing the sacrificial layer to form the first air sidewall between the source / drain interconnect layer and the gate structure.

[0197] In the present embodiment, the process of removing the sacrificial layer 535 includes an anisotropic etching process.

[0198] The anisotropic etching process has anisotropic characteristics, thus has a high etching precision and a good control of the profile, which is beneficial to improve the quality of the first air sidewall 571. As an example, the anisotropic etching process includes an anisotropic dry etching process.

[0199] In particular, the etching selectivity ratio of the sacrificial layer 535 to the ILD layer 570 is greater than 8.

[0200] In the present embodiment, the first sidewall layer 531 is removed after the formation of the source / drain interconnect layer 565 to form the second air sidewall 572 between the gate structure 520 and the remaining sidewall structure 530.

[0201] The second air sidewall 572 is beneficial to further reduce the parasitic capacitance between the gate structure 520 and the source / drain interconnect layer 565 and improve the performance of the semiconductor structure.

[0202] In other embodiments, the sidewall structure can be a single-layer structure, and the sidewall structure only includes the first sidewall layer on the sidewall of the gate structure. Correspondingly, the first sidewall layer is removed after the formation of the source / drain interconnect layer to form the first air sidewall and the second air sidewall which are mutually penetrating. In some other embodiments, the first sidewall layer can also be retained after the formation of the source / drain interconnect layer.

[0203] Reference is made to Figure 27 After the formation of the second air sidewall 572, a sealing layer 580 is formed on top of the first air sidewall 571 and the second air sidewall 572 to seal the first air sidewall 571 and the second air sidewall 572.

[0204] It should be noted that the process of forming the sealing layer 580 on the top of the first air side wall 571 and the second air side wall 572 includes plasma chemical vapor deposition (PCVD), which has poor gap filling performance and is easy to seal the top of the first air side wall 571 and the second air side wall 572. In other embodiments, the process of forming the sealing layer on the top of the first air side wall and the second air side wall can also include other suitable chemical vapor deposition processes.

[0205] It should also be noted that the material of the sealing layer 580 includes a dielectric material. As an example, the material of the sealing layer 580 is silicon nitride.

[0206] It should be noted that the semiconductor structure can be formed by the forming method described in the foregoing embodiments, or can be formed by other forming methods. For the specific description of the semiconductor structure of the present embodiment, reference can be made to the corresponding description in the foregoing embodiments, which will not be described herein again.

[0207] Although the present application has been disclosed as above, the present application is not limited to the above. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized by, Comprising: a substrate including a PMOS region and an NMOS region, the substrate having discrete fins formed thereon; gate structures on the substrate and across the fins, the gate structures covering portions of the top and sidewalls of the fins; first isolation structures in the PMOS region and in the fins between adjacent gate structures to be isolated; second isolation structures in the NMOS region, the second isolation structures across the fins on the sides of the gate structures and arranged side-by-side with the gate structures, the second isolation structures having bottoms extending into the fins; first source / drain doping layers in the fins on both sides of the gate structures in the PMOS region; second source / drain doping layers in the fins on both sides of the gate structures in the NMOS region.

2. The semiconductor structure of claim 1, wherein, The material of the first isolation structures includes graphene.

3. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: an interlayer dielectric layer covering the tops of the first and second source / drain doping layers, the interlayer dielectric layer also covering the sidewalls of the gate structures, the tops of the first isolation structures, and the sidewalls of the second isolation structures.

4. The semiconductor structure of any one of claims 1 to 3, wherein, The gate structures are device gate structures.

5. The semiconductor structure of claim 3, wherein, The semiconductor structure further comprises: source / drain interconnect layers in the interlayer dielectric layer on top of the first and second source / drain doping layers and electrically connected to the first and second source / drain doping layers, respectively; first air spacers between the source / drain interconnect layers and the gate structures.

6. The semiconductor structure of claim 5, wherein, The semiconductor structure further comprises: sidewall structures on the substrate and across the fins, the sidewall structures arranged opposite the sidewalls of the gate structures; second air spacers between the gate structures and the sidewall structures.

7. A method of forming a semiconductor structure, comprising: Comprising: providing a substrate including a PMOS region and an NMOS region, the substrate having discrete fins formed thereon; forming gate structures on the substrate and across the fins, the gate structures covering portions of the top and sidewalls of the fins; forming first isolation structures in the PMOS region and in the fins between adjacent gate structures to be isolated; forming first source / drain doping layers in the fins on both sides of the gate structures in the PMOS region after forming the first isolation structures; forming second source / drain doping layers in the fins on both sides of the gate structures in the NMOS region; forming second isolation structures in the NMOS region and extending into the fins at locations of the gate structures.

8. The method of forming a semiconductor structure of claim 7, wherein, The step of forming the first isolation structures comprises: forming first recesses in the PMOS region and in the fins between adjacent gate structures to be isolated; forming the first isolation structures in the first recesses.

9. The method of forming a semiconductor structure of claim 8, wherein, Before forming the first recesses, the method further comprises: forming source / drain recesses in the fins on both sides of the gate structures in the PMOS region; 10. The method of forming a semiconductor structure according to claim 8 or 9, wherein the step of forming the first recesses comprises removing the fins at the bottoms of the source / drain recesses between adjacent gate structures to be isolated to form the first recesses. The step of forming the first recesses comprises: forming a first mask structure covering the fin and the top of the gate structure, the first mask structure having a first mask opening formed therein, the first mask opening being above the fin between the adjacent gate structures to be isolated; along the first mask opening, removing the first mask structure at the bottom of the first mask opening and a partial thickness of the fin to form a first recess; the forming method further comprises: removing the first mask structure.

11. The method of forming a semiconductor structure of claim 10, wherein, in the step of forming the first isolation structure, the first isolation structure is formed under the protection of the first mask structure; after forming the first isolation structure, the first mask structure is removed.

12. The method of forming a semiconductor structure of claim 9, wherein, the step of forming the first source / drain doping layer comprises: forming the first source / drain doping layer in the source / drain recess remaining in the PMOS region after forming the first isolation structure.

13. The method of forming a semiconductor structure of claim 8, wherein, the process of forming the first isolation structure in the first recess comprises a dielectric selective deposition process on dielectric.

14. The method of forming a semiconductor structure of claim 13, wherein, after forming the first recess and before forming the first isolation structure, the forming method further comprises: performing an oxidation treatment on the surface of the first recess; after the oxidation treatment, the first isolation structure is formed in the first recess.

15. The method of forming a semiconductor structure of claim 7, wherein, after forming the second source / drain doping layer and before forming the second isolation structure, the forming method further comprises: forming an interlayer dielectric layer covering the top of the source / drain doping layer, the interlayer dielectric layer also covering the sidewall of the gate structure and the top of the first isolation structure; the step of forming the second isolation structure comprises: in the NMOS region, removing a portion of the gate structure and the fin at the bottom of the portion of the gate structure to form a second recess in the interlayer dielectric layer; forming a second isolation structure in the second recess.

16. The method of forming a semiconductor structure of claim 15, wherein, in the step of forming the gate structure across the fin on the substrate, the gate structure is a dummy gate structure; after forming the interlayer dielectric layer and before forming the second recess, the forming method further comprises: removing the dummy gate structure to form a device gate structure at the position of the dummy gate structure; in the step of forming the second recess, the device gate structure at the position of the portion of the dummy gate structure is removed.

17. The method of forming a semiconductor structure of claim 7, wherein, after forming the second source / drain doping layer, the second source / drain doping layer and the first source / drain doping layer constitute a source / drain doping layer, and before forming the interlayer dielectric layer, the forming method further comprises: forming a sacrificial layer on the sidewall of the gate structure; after forming the second source / drain doping layer, the second source / drain doping layer and the first source / drain doping layer constitute a source / drain doping layer, and before forming the interlayer dielectric layer, the forming method further comprises: forming a sacrificial layer on the sidewall of the gate structure; after forming the second isolation structure, the forming method further comprises: in the interlayer dielectric layer on the top of the source / drain doping layer, forming a source / drain interconnection layer electrically connected to the source / drain doping layer, the source / drain interconnection layer covering the sidewall of the sacrificial layer; after forming the source / drain interconnection layer, removing the sacrificial layer to form a first air spacer between the source / drain interconnection layer and the gate structure.

18. The method of forming a semiconductor structure of claim 17, wherein, the step of forming the source / drain interconnection layer comprises: forming a third recess in an interlayer dielectric layer on top of the source-drain doped layer, the third recess exposing the source-drain doped layer; forming a source-drain interconnect layer in the third recess.

19. The method of forming a semiconductor structure of claim 17 or 18, wherein, After forming the gate structure and before forming a first isolation structure, the forming method further comprises: forming a sidewall structure on the sidewall of the gate structure, the sidewall structure comprising a first sidewall layer closest to the gate structure; After forming the source-drain interconnect layer, the first sidewall layer is removed, forming a second air sidewall between the gate structure and the remaining sidewall structure.

20. The method of forming a semiconductor structure of claim 17, wherein, The process of forming the sacrificial layer comprises an atomic layer deposition process.

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