Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device; the display panel comprises a plurality of light-emitting control lines, a plurality of reset control lines, a plurality of light-emitting switching lines and a plurality of reset switching lines by making the driving circuit layer, one light-emitting switching line is connected with one light-emitting control line, one reset switching line is connected with one reset control line, wherein, at least one light-emitting switching line is provided with a break; and / or, at least one reset switching line is provided with a break; then the impedance of the light-emitting control line and the reset control line can be small, and the static electricity is dispersed on the multiple parts of the light-emitting switching line; and / or the static electricity is dispersed on the multiple parts of the reset switching line, the accumulation of static electricity is avoided, the risk of static electricity explosion caused by the tip discharge is reduced, and the yield of the display panel is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the display technical field, especially to a display panel and a display device. BACKGROUND

[0002] OLED (Organic Light-Emitting Diode) display devices are widely used due to the advantages of self-luminous, wide color gamut, low power consumption, and flexible display. The OLED display device is driven by a pixel driving circuit. However, during the use of the OLED display device, it is found that the impedance of part of the signal lines is large, which can easily cause large signal delay, and further cause pixel charging shortage or wrong charging, resulting in display defects. In order to reduce the impedance of the signal line, part of the signal lines can be designed in double layers, that is, two parts of the signal line are formed by two film layers to reduce the impedance of the signal line. However, during actual use, it is found that due to the relatively thin edge of the signal line, static electricity is accumulated on the signal line, which can easily cause sharp end discharge between the edge of the signal line and the active layer, and further cause the conduction of the active layer and the signal line, so that the transistor cannot be closed, and bright spots appear on the display panel, resulting in display abnormalities.

[0003] Therefore, the existing display device has the technical problem of display abnormalities caused by sharp end discharge between the edge of the signal line and the active layer. SUMMARY

[0004] The embodiments of the present application provide a display panel and a display device to solve the technical problem of display abnormalities caused by sharp end discharge between the edge of the signal line and the active layer in the existing display device.

[0005] In order to achieve the above-mentioned purpose, according to the first aspect of the present application, a display panel is provided, which comprises:

[0006] a substrate;

[0007] a driving circuit layer arranged on one side of the substrate, the driving circuit layer comprising a plurality of light-emitting control lines, a plurality of reset control lines, a plurality of light-emitting switching lines and a plurality of reset switching lines, one light-emitting switching line being connected with one light-emitting control line, and one reset switching line being connected with one reset control line;

[0008] wherein at least one light-emitting switching line is provided with a break; and / or at least one reset switching line is provided with a break.

[0009] According to the second aspect of the present application, a display device is provided, which comprises the display panel according to any one of the above-mentioned embodiments.

[0010] The display panel and the display device are provided in the embodiments of the present application. The display panel comprises a driving circuit layer, a plurality of light-emitting control lines, a plurality of reset control lines, a plurality of light-emitting switching lines and a plurality of reset switching lines. One light-emitting switching line is connected with one light-emitting control line, and one reset switching line is connected with one reset control line. At least one light-emitting switching line is provided with a breakage. At least one reset switching line is provided with a breakage. The light-emitting control lines and the reset control lines have small impedance, and static electricity is dispersed on a plurality of parts of the light-emitting switching lines and / or the reset switching lines. Accumulation of static electricity is avoided, the risk of static electricity explosion caused by sharp-point discharge is reduced, and the yield of the display panel is improved.

[0011] Other features and advantages of the present application will be illustrated in the following detailed description of the embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0013] In order to more completely understand the present application and its advantages, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.

[0014] Figure 1 The cross-sectional schematic diagram of a comparative display device is provided for the embodiments of the present application.

[0015] Figure 2 The planar schematic diagram of a display panel is provided for the embodiments of the present application.

[0016] Figure 3 The first cross-sectional schematic diagram of a display panel is provided for the embodiments of the present application.

[0017] Figure 4 The second cross-sectional schematic diagram of a display panel is provided for the embodiments of the present application.

[0018] Figure 5 The circuit diagram of a pixel driving circuit of a display panel is provided for the embodiments of the present application.

[0019] Figure 6 The overlay diagram of each film layer of a pixel unit of a display panel is provided for the embodiments of the present application.

[0020] Figure 7 The exploded view of an active layer of a display panel in the embodiments of the present application is provided. Figure 6

[0021] ​Figure 8 is a sectional view of a display panel in Figure 6

[0022] Figure 9 is a sectional view of a display panel in Figure 6

[0023] Figure 10 Figure 6 is a sectional view of a display panel in

[0024] Figure 11 Figure 6 is a sectional view of a display panel in

[0025] Figure 12 is a sectional view of a display panel in Figure 6

[0026] Figure 13 is a sectional view of a display panel in Figure 6

[0027] Figure 14 is a sectional view of a display panel in Figure 6

[0028] Figure 15 is a sectional view of a display panel in Figure 6

[0029] Figure 16 is a sectional view of a display panel in Figure 6

[0030] Figure 17 is a sectional view of a display panel in Figure 6 DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person skilled in the art without creative labor fall within the protection scope of the present application.

[0032] ​​​​​​​​​​In order to illustrate the principle of the technical problem of the embodiments of the present application, the embodiments of the present application provide a contrast display device. It can be understood that the contrast display device cannot be used as prior art of the embodiments of the present application. Specifically, the contrast display device includes a plurality of sub-pixel units, each of which includes a pixel driving circuit and a light emitting device. The pixel driving circuit includes a light emitting control wire and a reset control wire. The light emitting control wire is connected with a light emitting control transistor, and the reset control wire is connected with a reset transistor. In order to reduce the impedance of the light emitting control wire and the reset control wire, the light emitting control wire and the reset control wire are arranged in double layers.

[0033] As shown in Figure 1 The contrast display device includes a substrate 111, a semiconductor film layer 112, a first insulating film layer 113, a first gate film layer 114, a second insulating film layer 115, and a first source-drain film layer 116. The light emitting control wire includes a first light emitting control wire arranged in the first gate film layer 114 and a second light emitting control wire arranged in the first source-drain film layer 116. The reset control wire includes a first reset control wire arranged in the first gate film layer 114 and a second reset control wire arranged in the first source-drain film layer 116. Since the light emitting control wire is a double-layer wire, the first light emitting control wire and the second light emitting control wire are both long wires. Static electricity 117 is easy to accumulate on the light emitting control wire. The second light emitting control wire is arranged in a staggered manner with the first light emitting control wire, and the capacitance between the second light emitting control wire and the semiconductor film layer 112 is large, further increasing the capacitance between the light emitting control wire and the semiconductor film layer 112. The first light emitting control wire is relatively close to the semiconductor film layer 112, and the edge of the first light emitting control wire is relatively thin. The first light emitting control wire is easy to have a sharp end discharge between the semiconductor film layer 112, resulting in static electricity injury, causing the active pattern of the light emitting control wire and the light emitting transistor to be conductive. The light emitting control wire controls the light emitting transistor, which causes the light emitting transistor to be always on, causing the sub-pixel unit to be always on, resulting in a bright spot and display failure. Similarly, the first reset control wire and the second reset control wire are long wires, and static electricity is easy to accumulate on the reset control wire. The first reset control wire is relatively close to the semiconductor film layer 112, and the edge of the first reset control wire is relatively thin. The first reset control wire is easy to have a sharp end discharge between the semiconductor film layer 112, resulting in static electricity injury, causing the active pattern of the reset control wire and the reset transistor to be conductive. The reset control wire controls the reset transistor, which causes the reset transistor to be always on, also causing the sub-pixel unit to display abnormally. Therefore, the existing display device has the technical problem that the sharp end discharge between the edge of the signal line and the active layer causes display abnormality.

[0034] The embodiments of the present application aim at the above technical problem, and provide a display panel and a display device to solve the above technical problem.

[0035] Figure 2 A plan view of a display panel according to an embodiment of the present application. Figure 3 A first cross-sectional view of a display panel according to an embodiment of the present application. Figure 4 A second cross-sectional view of a display panel according to an embodiment of the present application. Figure 5 A circuit diagram of a pixel driving circuit of a display panel according to an embodiment of the present application. Figure 6 A stack diagram of each film layer of a pixel unit of a display panel according to an embodiment of the present application. Figure 7 A stack diagram of each film layer of a pixel unit of a display panel according to an embodiment of the present application. Figure 6 An exploded view of an active layer of a display panel in FIG. Figure 8 An exploded view of an active layer of a display panel in FIG. Figure 6 An exploded view of a first gate layer of a display panel in FIG. Figure 9 An exploded view of a first gate layer of a display panel in FIG. Figure 6 An exploded view of a second gate layer of a display panel in FIG. Figure 10 An exploded view of a second gate layer of a display panel in FIG. Figure 6 An exploded view of a first source-drain layer of a display panel in FIG. Figure 11 An exploded view of a first source-drain layer of a display panel in FIG. Figure 6 An exploded view of a second source-drain layer of a display panel in FIG. Figure 12 An exploded view of a second source-drain layer of a display panel in FIG. Figure 6 An exploded view of a pixel electrode layer of a display panel in FIG. Figure 13 An exploded view of a pixel electrode layer of a display panel in FIG. Figure 6 A stack diagram of an active layer and a first gate layer of a display panel in FIG. Figure 14 A stack diagram of an active layer, a first gate layer and a second gate layer of a display panel in FIG. Figure 6 A stack diagram of an active layer, a first gate layer and a second gate layer of a display panel in FIG. Figure 15 A stack diagram of an active layer, a first gate layer, a second gate layer and a first source-drain layer of a display panel in FIG. Figure 6 A stack diagram of an active layer, a first gate layer, a second gate layer and a first source-drain layer of a display panel in FIG. Figure 16 A stack diagram of an active layer, a first gate layer, a second gate layer, a first source-drain layer and a second source-drain layer of a display panel in FIG. Figure 6 A stack diagram of an active layer, a first gate layer, a second gate layer, a first source-drain layer and a second source-drain layer of a display panel in FIG. Figure 17 A first cross-sectional view of a display panel according to an embodiment of the present application. Figure 6 As shown in FIG.

[0036] As shown in FIG. Figures 2 to 17 The display panel 2 includes a substrate 21 and a driving circuit layer 22, the driving circuit layer 22 is disposed on one side of the substrate 21, the driving circuit layer 22 includes a plurality of light-emitting control lines EM, a plurality of reset control lines Reset-A, a plurality of light-emitting switching lines SL4 and a plurality of reset switching lines SL3, one light-emitting switching line SL4 is connected with one light-emitting control line EM, and one reset switching line SL3 is connected with one reset control line Reset-A.

[0037] Wherein, at least one of the light-emitting adapter wires SL4 is provided with a break 311; and / or at least one of the reset adapter wires SL3 is provided with a break.

[0038] An embodiment of the present application provides a display panel, which includes a driving circuit layer comprising multiple light-emitting control lines, multiple reset control lines, multiple light-emitting adapter lines, and multiple reset adapter lines, wherein a light-emitting adapter line is connected to a light-emitting control line, and a reset adapter line is connected to a reset control line, wherein at least one light-emitting adapter line is provided with a break; and / or at least one reset adapter line is provided with a break; thereby, the impedance of the light-emitting control line and the reset control line can be made small, and static electricity can be dispersed over multiple parts of the light-emitting adapter line; and / or static electricity can be dispersed over multiple parts of the reset adapter line, thereby avoiding static electricity accumulation, reducing the risk of static electricity injury caused by tip discharge, and improving the yield of the display panel.

[0039] Specifically, the light emitting control line EM and the light emitting adapter line SL4 are provided at different layers; the reset adapter line SL3 and the reset control line Reset-A are provided at different layers.

[0040] In some embodiments, as Figures 2 to 17 As shown, the display panel 2 includes a plurality of pixel units 240, each of which includes a plurality of sub-pixel units (e.g., a first sub-pixel unit 240a, a second sub-pixel unit 240b, and a third sub-pixel unit 240c). The light-emitting adapter line SL4 includes a plurality of light-emitting connecting lines EM-L, and a break 311 is provided between two adjacent light-emitting connecting lines EM-L. Each light-emitting connecting line EM-L is provided corresponding to a sub-pixel unit. By providing each light-emitting connecting line corresponding to a sub-pixel unit, each light-emitting connecting line can drive each transistor, so that each sub-pixel unit operates normally. At the same time, the light-emitting adapter line is divided into a plurality of light-emitting connecting lines, which further disperses static electricity, avoids static electricity accumulation, reduces the risk of electrostatic damage caused by tip discharge, and improves the yield of the display panel.

[0041] In some embodiments, as Figures 2 to 17As shown, the display panel 2 includes a plurality of pixel units 240, each of the pixel units 240 includes a plurality of sub-pixel units (for example, a first sub-pixel unit 240a, a second sub-pixel unit 240b, and a third sub-pixel unit 240c), the reset transfer line SL4 includes a plurality of reset connection lines RL, the reset connection lines RL are provided in pairs, and the reset connection lines RL in each pair are separated by the breakage. Each reset connection line RL is provided corresponding to one sub-pixel unit. By providing each reset connection line corresponding to one sub-pixel unit, each reset connection line can drive a transistor, so that each sub-pixel unit works normally. At the same time, the reset transfer line is divided into a plurality of reset connection lines, which further disperses static electricity, avoids static electricity accumulation, reduces the risk of static electricity explosion caused by sharp discharge, and improves the yield of the display panel.

[0042] The above embodiment takes the breakage being arranged between two sub-pixel units as an example for description, but the embodiment of the present application is not limited thereto. The breakage can be arranged in one sub-pixel unit, as long as the breakage avoids the active pattern of each transistor, that is, the projection of the breakage and the active pattern of each transistor on the substrate does not overlap.

[0043] In some embodiments, as shown in FIG. 1, the display panel 2 includes a plurality of pixel units 240, each of the pixel units 240 includes a plurality of sub-pixel units (for example, a first sub-pixel unit 240a, a second sub-pixel unit 240b, and a third sub-pixel unit 240c), the reset transfer line SL4 includes a plurality of reset connection lines RL, the reset connection lines RL are provided in pairs, and the reset connection lines RL in each pair are separated by the breakage. Each reset connection line RL is provided corresponding to one sub-pixel unit. By providing each reset connection line corresponding to one sub-pixel unit, each reset connection line can drive a transistor, so that each sub-pixel unit works normally. At the same time, the reset transfer line is divided into a plurality of reset connection lines, which further disperses static electricity, avoids static electricity accumulation, reduces the risk of static electricity explosion caused by sharp discharge, and improves the yield of the display panel. Figures 2 to 17 As shown, the display panel 2 includes a plurality of pixel units 240, each of the pixel units 240 includes a plurality of sub-pixel units (for example, a first sub-pixel unit 240a, a second sub-pixel unit 240b, and a third sub-pixel unit 240c), the reset transfer line SL4 includes a plurality of reset connection lines RL, the reset connection lines RL are provided in pairs, and the reset connection lines RL in each pair are separated by the breakage. Each reset connection line RL is provided corresponding to one sub-pixel unit. By providing each reset connection line corresponding to one sub-pixel unit, each reset connection line can drive a transistor, so that each sub-pixel unit works normally. At the same time, the reset transfer line is divided into a plurality of reset connection lines, which further disperses static electricity, avoids static electricity accumulation, reduces the risk of static electricity explosion caused by sharp discharge, and improves the yield of the display panel.

[0044] In some embodiments, as shown in FIG. 1, the display panel 2 includes a plurality of pixel units 240, each of the pixel units 240 includes a plurality of sub-pixel units (for example, a first sub-pixel unit 240a, a second sub-pixel unit 240b, and a third sub-pixel unit 240c), the reset transfer line SL4 includes a plurality of reset connection lines RL, the reset connection lines RL are provided in pairs, and the reset connection lines RL in each pair are separated by the breakage. Each reset connection line RL is provided corresponding to one sub-pixel unit. By providing each reset connection line corresponding to one sub-pixel unit, each reset connection line can drive a transistor, so that each sub-pixel unit works normally. At the same time, the reset transfer line is divided into a plurality of reset connection lines, which further disperses static electricity, avoids static electricity accumulation, reduces the risk of static electricity explosion caused by sharp discharge, and improves the yield of the display panel. Figures 2 to 17As shown, the driving circuit layer 22 includes a first gate layer 224 and a first source-drain layer 228. The first gate layer 224 is disposed between the substrate 21 and the first source-drain layer 228. The first gate layer 224 includes the light-emitting connection line EM-L and the reset connection line RL. The first source-drain layer 228 includes the light-emitting control line EM and the reset control line Reset-A. By disposing the light-emitting connection line and the reset connection line in the first gate layer, and disposing the light-emitting control line and the reset control line in the first source-drain layer, with the light-emitting connection line connected to the light-emitting control line and the reset connection line connected to the reset control line, the impedance of the light-emitting control line and the reset control line can be reduced. Furthermore, by disconnecting multiple light-emitting connection lines connected to the same light-emitting control line and multiple reset connection lines connected to the same reset control line, static electricity accumulation can be avoided, reducing the risk of electrostatic damage caused by tip discharge, and improving the yield of the display panel.

[0045] like Figures 2 to 17 As shown, an embodiment of the present application provides a display panel, which includes a plurality of pixel units 240, each of which includes a plurality of sub-pixel units (for example, a first sub-pixel unit 240a, a second sub-pixel unit 240b, and a third sub-pixel unit 240c). The display panel 2 includes a substrate 21 and a driving circuit layer 22. The driving circuit layer 22 is disposed on one side of the substrate 21. The driving circuit layer 22 includes a first gate layer 224 and a first source-drain layer 228. The first gate layer 224 is disposed between the substrate 21 and the first source-drain layer 228. The first gate layer 224 includes a plurality of light-emitting connection lines EM-L and a plurality of reset connection lines RL. The first source-drain layer 228 includes a light-emitting control line EM and a reset control line Reset-A. The light-emitting connection line EM-L is connected to the light-emitting control line EM, and the reset connection line RL is connected to the reset control line Reset-A.

[0046] In two adjacent sub-pixel units (eg, the first sub-pixel unit 240a and the second sub-pixel unit 240b), two adjacent light-emitting connection lines EM-L are disconnected, and / or two adjacent reset connection lines RL are disconnected.

[0047] The display panel provided by the embodiments of the present application can make the impedance of the light-emitting control line and the reset control line smaller, and the static electricity is dispersed on the plurality of light-emitting connection lines; and / or the static electricity is dispersed on the plurality of reset connection lines, thereby avoiding static electricity accumulation, reducing the risk of static electricity explosion caused by sharp discharge, and improving the yield of the display panel.

[0048] Specifically, the edges of the light-emitting connection line and the reset connection line exist ramping.

[0049] Specifically, in the first direction, the adjacent two light-emitting connection lines are disconnected in the adjacent two sub-pixel units, and / or the adjacent two reset connection lines are disconnected in the adjacent two sub-pixel units.

[0050] Specifically, it can be understood that in the pixel driving circuit, each transistor has a gate, a first electrode and a second electrode, but in the actual preparation process, in order to reduce the occupied space of the transistor, some electrodes of the transistor are not separately provided, but the electrodes of each transistor and the signal line are directly connected, for example, in the pixel driving circuit, the first electrode of the driving transistor T1 and the second electrode of the switching transistor T2 are connected to the first node A, and in the preparation of the driving transistor and the switching transistor, the first electrode of the driving transistor and the second electrode of the switching transistor do not need to be separately provided, but the active pattern of the driving transistor and the active pattern of the switching transistor are directly connected together, and the connection position of the active pattern of the driving transistor and the active pattern of the switching transistor can be regarded as the first node A, thereby reducing the electrodes of the transistor and reducing the occupied space of the transistor. In another example, the first electrode of the compensation transistor is connected to the second electrode of the initialization transistor, but in the actual design, the first electrode of the compensation transistor and the second electrode of the initialization transistor do not need to be separately provided, but the active pattern of the compensation transistor and the active pattern of the initialization transistor are directly connected together, and the connection position of the active pattern of the compensation transistor and the active pattern of the initialization transistor can be regarded as the position connected with the Q point, or regarded as the Q point, thereby reducing the electrodes of the transistor and reducing the occupied space of the transistor. Similarly, other structures not marked in the film layer diagram are also designed in the above manner, which can be referred to the above description, and will not be described in detail in the following embodiments.

[0051] Specifically, in the actual manufacturing process, in order to reduce the space occupied by transistors, another approach is to share electrodes for multiple transistors, or to share the same structure for transistor electrodes and signal lines. For example, the gate of a driving transistor is connected to one plate of a storage capacitor. Instead of separately providing the gate of the driving transistor and one plate of the storage capacitor, a single structure can serve as the gate of the driving transistor and one plate of the storage capacitor. Similarly, for other cases where the same structure is used as electrodes and / or signal lines for multiple transistors, please refer to the above description and will not be repeated in the following embodiments.

[0052] Specifically, the display panel includes a plurality of repeating units, and one repeating unit may include a pixel unit, such as the attached pixel unit in the embodiment of the present application. Figure 6 The pixel unit shown is a pixel unit in which the reset connection line is electrically connected to the first electrode of the initialization transistor. A repeating unit may also include two pixel units. The difference between the two pixel units is that the reset connection line in one pixel unit is electrically connected to the first electrode of the initialization transistor, and the first electrode of the initialization transistor is connected to the initialization signal line, thereby reducing the voltage drop of the initialization signal line. The reset connection line in the other pixel unit is electrically connected to the reset signal line, thereby reducing the voltage drop of the reset signal line. For other parts, the two pixel units can be the same. The following embodiment is described as an example of a repeating unit including one pixel unit.

[0053] Specifically, the display panel may include multiple pixel units 240, each pixel unit 240 may include multiple sub-pixel units, the multiple sub-pixel units may include a first sub-pixel unit 240a, a second sub-pixel unit 240b and a third sub-pixel unit 240c, the first sub-pixel unit 240a, the second sub-pixel unit 240b and the third sub-pixel unit 240c all include a pixel driving circuit 220 and a light-emitting device LED, the design of the light-emitting devices of the first sub-pixel unit 240a, the second sub-pixel unit 240b and the third sub-pixel unit 240c may be different, specifically, the light-emitting colors of the light-emitting devices of the first sub-pixel unit 240a, the second sub-pixel unit 240b and the third sub-pixel unit 240c may be different, and / or the areas of the light-emitting devices may be different, and / or the thicknesses of the light-emitting devices may be different.

[0054] Specifically, the luminous colors of the first sub-pixel unit, the second sub-pixel unit and the third sub-pixel unit can be red, green and blue respectively, but the embodiments of the present application are not limited to this. For example, the luminous colors of the first sub-pixel unit, the second sub-pixel unit and the third sub-pixel unit can be red, blue and green respectively, or the luminous colors of the first sub-pixel unit, the second sub-pixel unit and the third sub-pixel unit can be blue, green and red respectively.

[0055] Specifically, in the embodiments of the present application, it should be noted that, except for the differences of the parts specified, the design of all pixel units can refer to the design of the pixel units provided in the embodiments of the present application, and by analogy, the design of all pixel driving circuits can refer to the design of the pixel driving circuits in the embodiments of the present application, for example, the difference between the two pixel driving circuits lies in that the high potential power line of one pixel driving circuit is different from the high potential power line in the other pixel driving circuit, and the other designs of the two pixel driving circuits are the same, therefore, when the design of the pixel driving circuit is described, it can be considered that, except for the difference of the high potential power line, the other designs of the two pixel driving circuits are the same, and by analogy, the difference and the same design of the pixel unit can be determined, which will not be described in detail in the following embodiments.

[0056] Specifically, as shown in Figure 2 , the display panel 2 includes a display area AA and a non-display area NA, and the pixel units are arranged in the display area AA.

[0057] Specifically, as shown in Figure 3 , Figure 4 , the display panel 2 includes a substrate 21, a driving circuit layer 22, a light-emitting functional layer 24, and an encapsulation layer 25.

[0058] Specifically, the driving circuit layer 22 includes a buffer layer 221, an active layer 222, a first gate insulating layer 223, a first gate layer 224, a second gate insulating layer 225, a second gate layer 226, an interlayer insulating layer 227, a first source-drain layer 228, a passivation layer 229, a first planarization layer 231, a second source-drain layer 232, a second planarization layer 233, and a third planarization layer 234, the buffer layer 221 is arranged on one side of the substrate 21, the active layer 222 is arranged on the side of the buffer layer 221 away from the substrate 21, the first gate insulating layer 223 is arranged on the side of the active layer 222 away from the buffer layer 221, the first gate layer 224 is arranged on the side of the first gate insulating layer 223 away from the active layer 222, the second gate insulating layer 225 is arranged on the side of the first gate layer 224 away from the first gate insulating layer 223, the second gate layer 226 is arranged on the side of the second gate insulating layer 225 away from the first gate layer 224, the interlayer insulating layer 227 is arranged on the side of the second gate layer 226 away from the second gate insulating layer 225, the first source-drain layer 228 is arranged on the side of the interlayer insulating layer 227 away from the second gate layer 226, the passivation layer 229 is arranged on the side of the first source-drain layer 228 away from the interlayer insulating layer 227, the first planarization layer 231 is arranged on the side of the passivation layer 229 away from the first source-drain layer 228, the second source-drain layer 232 is arranged on the side of the first planarization layer 231 away from the passivation layer 229, the second planarization layer 233 is arranged on the side of the second source-drain layer 232 away from the first planarization layer 231, and the third planarization layer 234 is arranged on the side of the second planarization layer 233 away from the second source-drain layer 232.

[0059] Specifically, the light-emitting functional layer 24 includes a pixel electrode layer 241, a pixel definition layer 242, a light-emitting material layer 243, and a common electrode layer 244. The pixel definition layer 242 is disposed on a side of the pixel electrode layer 241 away from the driving circuit layer 22. The light-emitting material layer 243 is disposed on a side of the pixel definition layer 242 away from the pixel electrode layer 241. The common electrode layer 244 is disposed on a side of the light-emitting material layer 243 away from the pixel definition layer 242.

[0060] Specifically, the pixel definition layer 242 can include a first pixel definition layer 242a and a second pixel definition layer 242b, but the embodiments of the present application are not limited thereto, and the pixel definition layer can also be a single layer design.

[0061] Specifically, the encapsulation layer 25 includes a first inorganic layer, an organic layer, and a second inorganic layer.

[0062] Specifically, the light-emitting functional layer 24 includes a light-emitting device LED, and the pixel electrode layer 241 in the light-emitting functional layer 24 includes an anode ANO of the light-emitting device LED.

[0063] Specifically, since the display panel is described from the circuit, the film layer structure, and the design of each film layer of the display panel in the embodiments of the present application, there may be some structures that belong to both this structure and another structure. This is because it is limited from different angles. For example, the pixel driving circuit belongs to the driving circuit layer, which is considered from the film layer structure. The pixel driving circuit is formed by the structure in the driving circuit layer. In addition, the pixel unit includes the pixel driving circuit, which is considered from the design of the pixel unit. Each pixel unit needs to be driven by the corresponding pixel driving circuit. It can be understood that the pixel driving circuit belonging to the driving circuit layer and the pixel unit is the same pixel driving circuit. Similarly, other similar limited descriptions can be referred to the above description, and will not be described in detail in the following embodiments.

[0064] In some embodiments, in any two of the sub-pixel units, two adjacent light-emitting connection lines are discontinuously arranged. By discontinuously arranging two adjacent light-emitting connection lines in any two sub-pixel units, static electricity can be dispersed on multiple light-emitting connection lines, thereby reducing the risk of tip discharge between the light-emitting connection line and the active layer, and improving the yield of the display panel.

[0065] Specifically, compared with the comparative display device, the first light-emitting control wire is a long wire, and static electricity can accumulate on the first light-emitting control wire. In addition, there is a ramp on the edge of the first light-emitting control wire, and the thickness of the edge is relatively small, so that the edge of the first light-emitting control wire is prone to sharp discharge between the semiconductor film layer. The embodiments of the present application can disperse static electricity to multiple light-emitting connection lines to release, avoid the problem of static discharge between the light-emitting connection line and the active pattern caused by the accumulation of static electricity, thereby reducing the risk of sharp discharge between the light-emitting connection line and the active layer, and improving the yield of the display panel.

[0066] In some embodiments, within any two of the sub-pixel units, the adjacent two reset connection lines are arranged to be disconnected. By arranging the adjacent two reset connection lines in any two sub-pixel units to be disconnected, static electricity can be dispersed on multiple reset connection lines, thereby reducing the risk of sharp discharge between the reset connection line and the active layer, and improving the yield of the display panel.

[0067] Specifically, compared with the comparative display device, the first reset control wire is a long wire, and static electricity can accumulate on the first reset control wire. In addition, there is a ramp on the edge of the first reset control wire, and the thickness of the edge is relatively small, so that the edge of the first reset control wire is prone to sharp discharge between the semiconductor film layer. The embodiments of the present application can disperse static electricity to multiple reset connection lines to release, avoid the problem of static discharge between the reset connection line and the active pattern caused by the accumulation of static electricity, thereby reducing the risk of sharp discharge between the reset connection line and the active layer, and improving the yield of the display panel.

[0068] In some embodiments, as shown in Figures 6 to 15 In some embodiments, as shown in Figures 6 to 15 In some embodiments, as shown in

[0069] Specifically, compared with the comparative display device, the first light-emitting control line is a long line, and the first reset control line is a long line. Static electricity will accumulate on the first light-emitting control line and the first reset control line. Moreover, since there will be a slope at the edges of the first light-emitting control line and the first reset control line, the thickness of the edge is relatively small, which leads to the fact that tip discharge is easy to occur between the slope of the first light-emitting control line and the first reset control line and the semiconductor film layer. In the embodiment of the present application, by disconnecting two adjacent light-emitting connection lines and two adjacent reset connection lines, static electricity can be dispersed to multiple light-emitting connection lines and multiple reset connection lines for release, thereby avoiding the problem of electrostatic breakdown between the light-emitting connection line and the active pattern caused by static electricity accumulation, and avoiding the problem of electrostatic breakdown between the reset connection line and the active pattern caused by static electricity accumulation, thereby reducing the risk of tip discharge between the light-emitting connection line and the reset connection line and the active layer, and improving the yield of the display panel.

[0070] In some embodiments, as Figures 6 to 16 As shown, the light-emitting control line EM and the light-emitting connection line EM-L are arranged along a first direction X, the projection of the light-emitting connection line EM-L on the substrate 21 overlaps with the projection of the light-emitting control line EM on the substrate 21, and the width H1 of the light-emitting connection line EM-L in the second direction Y is greater than or equal to the width H2 of the light-emitting control line EM in the second direction Y; wherein, in the overlapping area between the light-emitting connection line EM-L and the light-emitting control line EM, the projection of the light-emitting control line EM on the substrate 21 is located within the projection of the light-emitting connection line EM-L on the substrate, and the angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees. By making the projection of the light-emitting connecting line EM-L on the substrate 21 overlap with the projection of the light-emitting control line EM on the substrate 21, the width of the light-emitting connecting line EM-L in the second direction Y is greater than or equal to the width of the light-emitting control line EM in the second direction Y. In the overlapping area between the two, the projection of the light-emitting control line EM on the substrate is located within the projection of the light-emitting connecting line EM-L on the substrate, so that the light-emitting connecting line EM-L can block the light-emitting control line, avoiding the formation of capacitance between the light-emitting control line EM-L and the active pattern, reducing the capacitance between the light-emitting control line and the active pattern, reducing the risk of tip discharge between the light-emitting connecting line and the active layer, and improving the yield of the display panel.

[0071] Specifically, compared to the comparative display device, in which the first and second light-emitting control lines are misaligned, the first and second light-emitting control lines each form coupling capacitances with the active pattern, which can easily lead to tip discharges between the first light-emitting control line and the active pattern, causing electrostatic damage. In the embodiment of the present application, by making the width of the light-emitting connecting line in the second direction greater than or equal to the width of the light-emitting control line in the second direction, the projection of the light-emitting control line on the substrate lies within the projection of the light-emitting connecting line on the substrate in the overlapping region. The light-emitting connecting line can cover the light-emitting control line, thereby reducing or even eliminating the coupling capacitance between the light-emitting control line and the active pattern, thereby reducing the risk of tip discharges between the light-emitting connecting line and the active pattern and improving the yield of the display panel.

[0072] Specifically, in the arrangement area corresponding to the active pattern, the projection of the light-emitting control line on the substrate is located within the projection of the light-emitting connection line on the substrate.

[0073] In some embodiments, as Figures 6 to 16 As shown, the reset control line Reset-Q and the reset connection line RL are arranged along the first direction X, the projection of the reset connection line RL on the substrate 21 overlaps with the projection of the reset control line Reset-Q on the substrate 21, and the width H3 of the reset connection line RL in the second direction Y is greater than or equal to the width H4 of the reset control line Reset-Q in the second direction Y; wherein, in the overlapping area of ​​the reset connection line RL and the reset control line Reset-Q, the projection of the reset control line Reset-Q on the substrate 21 is located within the projection of the reset connection line RL on the substrate 21, and the angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees. By making the projection of the reset connection line RL on the substrate 21 overlap with the projection of the reset control line Reset-Q on the substrate 21, the width of the reset connection line RL in the second direction Y is greater than or equal to the width of the reset control line Reset-Q in the second direction Y. In the overlapping area between the two, the projection of the reset control line Reset-Q on the substrate 21 is located within the projection of the reset connection line RL on the substrate 21, so that the reset connection line RL can block the reset control line Reset-Q, avoiding the formation of capacitance between the reset control line Reset-Q and the active pattern, reducing the capacitance between the light-emitting control line and the active pattern, reducing the risk of tip discharge between the light-emitting connection line and the active layer, and improving the yield of the display panel.

[0074] Specifically, compared with the comparative display device, the first reset control line and the second reset control line are respectively coupled with the active pattern, which causes the first reset control line to be prone to sharp discharge between the first reset control line and the active pattern, and causes electrostatic explosion. In the embodiments of the present application, the width of the reset connection line in the second direction is greater than or equal to the width of the reset control line in the second direction, the projection of the reset control line Reset-Q on the substrate 21 is located in the projection of the reset connection line RL on the substrate 21 in the overlapping area of the two, and the reset connection line can cover the reset control line, so as to reduce or even eliminate the coupling capacitance between the reset control line and the active pattern, thereby reducing the risk of sharp discharge between the reset connection line and the active pattern and improving the yield of the display panel.

[0075] Specifically, in the setting area corresponding to the active pattern, the projection of the reset control line on the substrate is located in the projection of the reset connection line on the substrate.

[0076] Specifically, as shown in Figure 1 , Figure 17 can be seen, the embodiments of the present application can cover the reset control line by the reset connection line in the overlapping area of the light-emitting connection line and the light-emitting control line, cover the reset control line by the reset connection line in the overlapping area of the reset connection line and the reset control line, reduce or even eliminate the coupling capacitance between the light-emitting control line and the active pattern, and reduce or even eliminate the coupling capacitance between the reset control line and the active pattern.

[0077] In some embodiments, as shown in Figures 6 to 16 , the drive circuit layer 22 includes a first via hole 301, the light-emitting control line EM passes through the first via hole 301 and is connected with the light-emitting connection line EM-L, and the light-emitting control line EM is symmetrically arranged about the first via hole 301. By connecting the light-emitting control line with the light-emitting connection line through the first via hole and symmetrically arranging the light-emitting control line about the first via hole, the light-emitting connection line can better shield the light-emitting control line, avoid the light-emitting control line and the active pattern being directly arranged opposite to each other to form a coupling capacitance, reduce the coupling capacitance between the light-emitting control line and the active pattern, reduce the risk of sharp discharge between the light-emitting connection line and the active pattern, and improve the yield of the display panel.

[0078] Specifically, the light-emitting connection line is symmetrically arranged about the first via hole.

[0079] Specifically, compared with the comparative display device, the first light-emitting control line and the second light-emitting control line are symmetrically arranged about the first via hole, which can reduce the risk of sharp discharge between the light-emitting connection line and the active pattern and improve the yield of the display panel.

[0080] Specifically, the first via hole 301 penetrates the interlayer insulating layer 227 and the second gate insulating layer 225.

[0081] In some embodiments, as shown in FIG. 2, the driving circuit layer 22 further comprises a pixel driving circuit 220, an active layer 222, a first source-drain layer 228, and a second via hole 302. Figures 6 to 16 Specifically, the pixel driving circuit 220 comprises a reset transistor T7, the active layer 222 comprises an active pattern T7A of the reset transistor T7, and the first source-drain layer 228 further comprises a reset signal line VI-A.

[0082] Specifically, the second via hole 302 is arranged corresponding to the reset signal line VI-A, the second via hole 302 is arranged corresponding to the active pattern T7A of the reset transistor T7, and the reset signal line VI-A is connected with the active pattern T7A of the reset transistor T7 through the second via hole 302. By arranging the reset signal line in the first source-drain layer, and arranging the second via hole corresponding to the active pattern of the reset transistor and the reset signal line, the part of the reset signal line in the active layer can be removed, so as to avoid occupying the space of the active layer and improve the aperture ratio.

[0083] Specifically, compared with the two parts of the reset signal line formed by the semiconductor film layer and the first source-drain film layer in the comparative display device, the embodiment of the present application considers that the semiconductor film layer has less influence on the impedance of the reset signal line, removes the part of the reset signal line in the active layer, and makes the reset signal line adopt a single-layer design, so as to avoid occupying the space of the active layer and avoid the process complexity leading to the yield reduction. By arranging the second via hole corresponding to the active pattern of the reset transistor and the reset signal line, the reset signal line can be directly connected with the active pattern of the reset transistor through the second via hole, without the need of adding a switching line, so as to reduce the process steps and reduce the occupied space.

[0084] Specifically, the second via hole 302 penetrates the interlayer insulating layer 227, the second gate insulating layer 225, and the first gate insulating layer 223.

[0085] In some embodiments, as shown in FIG. 2, the driving circuit layer 22 further comprises a pixel driving circuit 220, an active layer 222, a first source-drain layer 228, and a third via hole 303. Figures 6 to 16 Specifically, the pixel driving circuit 220 comprises an initialization transistor T4, the active layer 222 comprises an active pattern T4A of the initialization transistor T4, and the first source-drain layer 228 further comprises an initialization signal line VI-Q.

[0086] The third via 303 is provided corresponding to the initialization signal line VI-Q, and the third via 303 is provided corresponding to the active pattern T4A of the initialization transistor T4. The initialization signal line VI-Q passes through the third via 303 and is connected to the active pattern T4A of the initialization transistor T4. By providing the initialization signal line in the first source-drain layer and providing the third via corresponding to the active pattern of the initialization transistor and the initialization signal line, the initialization signal line can be moved from being part of the active layer and the second gate layer to being part of the first source-drain layer, thereby reducing impedance, avoiding occupying space in the active layer, and improving the aperture ratio.

[0087] Specifically, compared to comparative display devices that use a semiconductor film layer and a second gate film layer to form the two parts of the initialization signal line, the embodiments of the present application take into account the relatively large impedance of the semiconductor film layer and the second gate film layer. By forming the initialization signal line using the first source and drain electrode layer, the impedance of the initialization signal line is reduced, allowing the initialization signal line to adopt a single-layer design, avoiding occupying space in the active layer and avoiding process complexity that leads to reduced yield. By aligning the third via with the active pattern of the initialization transistor and the initialization signal line, the initialization signal line can be directly connected to the active pattern of the initialization transistor through the third via, eliminating the need for additional adapter wires, reducing process steps, and reducing occupied space.

[0088] Specifically, the third via hole 303 penetrates the interlayer insulating layer 227 , the second gate insulating layer 225 and the first gate insulating layer 223 .

[0089] Specifically, the impedance of the first source-drain electrode layer is smaller than the impedance of the second gate layer, and the impedance of the first source-drain electrode layer is smaller than the impedance of the active layer.

[0090] In some embodiments, as Figures 6 to 16 As shown, the driving circuit layer 22 further includes data lines Data, and a distance exists between the projection of the light-emitting connection lines EM-L on the substrate 21 and the projection of at least a portion of the data lines Data on the substrate 21. By providing a distance between the projection of the light-emitting connection lines EM-L on the substrate 21 and the projection of at least a portion of the data lines Data on the substrate 21, the light-emitting connection lines EM-L can be disconnected, and the coupling capacitance between each light-emitting control line EM and the data lines Data is reduced, thereby reducing the total capacitance of at least a portion of the data lines. This can prevent crosstalk caused by insufficient pixel charging time or even incorrect charging, thereby improving display uniformity and enhancing display quality.

[0091] Specifically, compared to the comparative display device, in which the first light-emitting control line and the second light-emitting control line both overlap with the data lines, the embodiment of the present application disconnects a plurality of light-emitting connecting lines, retains portions of the light-emitting connecting lines that serve as the gates of the first light-emitting control transistor and the second light-emitting control transistor, and the projections of the light-emitting connecting lines on the substrate do not overlap with at least portions of the data lines, thereby reducing the coupling capacitance between the light-emitting control lines and at least portions of the data lines.

[0092] In some embodiments, as Figures 6 to 16 As shown, the driving circuit layer 22 further includes a data line Data, and a distance exists between the projection of the reset connection line RL on the substrate 21 and the projection of the data line Data on the substrate 21. By providing a distance between the projection of the reset connection line RL on the substrate 21 and the projection of the data line Data on the substrate 21, each reset connection line RL can be disconnected, and the coupling capacitance between each reset control line Reset-A and the data line Data is reduced, thereby reducing the total capacitance of the data line, preventing crosstalk caused by insufficient pixel charging time or even incorrect charging, thereby improving display uniformity and enhancing display quality.

[0093] Specifically, compared to the comparative display device, in which both the first reset control line and the second reset control line overlap with the data line, the embodiment of the present application disconnects multiple reset connection lines, retains the portion of the reset connection line that serves as the gate of the reset transistor, and the projection of the reset connection line on the substrate does not overlap with the data line, thereby reducing the coupling capacitance between the reset control line and at least the data line.

[0094] In some embodiments, as Figures 3 to 16 As shown, the driving circuit layer 22 further includes a first gate layer 224, a first source-drain layer 228, and a second source-drain layer 232. The second source-drain layer 232 is arranged on a side of the first source-drain layer 228 away from the first gate layer 224. The second source-drain layer 232 includes a high potential power line VDD.

[0095] The first gate layer 224 further includes an initialization connection line SL2, and the first source-drain layer further includes an initialization control line Reset-Q. The initialization connection line SL2 includes a first connection portion SL2a and a second connection portion SL2b. The first connection portion SL2a connects the initialization control line Reset-Q and the second connection portion SL2b. A distance exists between the projection of one end of the first connection portion SL2a on the substrate 21 and the projection of one end of the high-potential power line VDD on the substrate 21. By providing a distance between the projection of one end of the first connection portion on the substrate and the projection of one end of the high-potential power line on the substrate, the coupling capacitance between the high-potential power line and the initialization control line can be reduced, thereby improving display uniformity and enhancing display quality.

[0096] Specifically, it can be seen that the initialization control line is connected with one end of the first connection part SL2a through the via hole, and the projection of the other end of the first connection part SL2a on the substrate is spaced apart from the projection of one end of the high potential power line VDD on the substrate.

[0097] In some embodiments, as shown in FIG. 2, the driving circuit layer 22 further includes a first gate layer 224, a second gate layer 226, a first source-drain layer 228, and a second source-drain layer 232. The second gate layer 226 is arranged between the first gate layer 224 and the first source-drain layer 228. The second source-drain layer 232 is arranged on a side of the first source-drain layer 228 away from the second gate layer 226. The second gate layer 226 includes a first high potential power connection line VDD-L1. The first source-drain layer 228 includes a second high potential power connection line VDD-L2. The second source-drain layer 232 includes a high potential power line VDD. Figures 3 to 16

[0098] Specifically, as shown in FIG. 2, the second high potential power connection line VDD-L2 is connected with the first high potential power connection line VDD-L1 and the high potential power line VDD. The driving circuit layer 22 further includes a fourth via hole 304. The second high potential power connection line VDD-L2 is connected with the first high potential power connection line VDD-L1 through the fourth via hole 304. The lower end of the fourth via hole 304 is on the same straight line with the lower end of the second high potential power connection line VDD-L2. By arranging the lower end of the fourth via hole on the same straight line with the lower end of the second high potential power connection line, the fourth via hole can be far away from the active pattern of the driving transistor, so as to avoid the influence of the fourth via hole on the electrical property of the active pattern of the driving transistor, thereby improving the electrical property stability of the driving transistor.

[0099] Specifically, as shown in FIG. 2, the second high potential power connection line VDD-L2 is connected with the first high potential power connection line VDD-L1 and the high potential power line VDD. The driving circuit layer 22 further includes a fourth via hole 304. The second high potential power connection line VDD-L2 is connected with the first high potential power connection line VDD-L1 through the fourth via hole 304. The lower end of the fourth via hole 304 is on the same straight line with the lower end of the second high potential power connection line VDD-L2. By arranging the lower end of the fourth via hole on the same straight line with the lower end of the second high potential power connection line, the fourth via hole can be far away from the active pattern of the driving transistor, so as to avoid the influence of the fourth via hole on the electrical property of the active pattern of the driving transistor, thereby improving the electrical property stability of the driving transistor. Figure 5 ​As shown in the figure, the pixel driving circuit 220 comprises a switch transistor T2, a driving transistor T1, a compensation transistor T3 and an initialization transistor T4, a gate of the switch transistor T2 is connected with a switch control line Scan(n), a first electrode of the switch transistor T2 is connected with the data line Data, and a second electrode of the switch transistor T2 is connected with a first electrode of the driving transistor T1 at a first node A; a gate of the compensation transistor T3 is connected with the switch control line Scan(n), a first electrode of the compensation transistor T3 is connected with a gate of the driving transistor T1 at a second node Q, and a second electrode of the compensation transistor T3 is connected with a second electrode of the driving transistor T1 at a third node B; a gate of the initialization transistor T4 is connected with an initialization control line Reset-Q, a first electrode of the initialization transistor T4 is connected with an initialization signal line VI-Q, and a second electrode of the initialization transistor T4 is connected with the gate of the driving transistor T1 at the second node Q.

[0100] Specifically, as shown in the figure, Figure 5 the pixel driving circuit 220 further comprises:

[0101] a first light emitting control transistor T5, a gate of the first light emitting control transistor T5 is connected with a light emitting control line EM, a first electrode of the first light emitting control transistor T5 is connected with a high potential power supply line VDD, and a second electrode of the first light emitting control transistor T5 is connected with the first electrode of the driving transistor T1 at the first node A;

[0102] a second light emitting control transistor T6, a gate of the second light emitting control transistor T6 is connected with the light emitting control line EM, a first electrode of the second light emitting control transistor T6 is connected with the second electrode of the driving transistor T1 at the third node B;

[0103] a reset transistor T7, a gate of the reset transistor T7 is connected with a reset control line Reset-A, a first electrode of the reset transistor T7 is connected with a reset signal line VI-A, a second electrode of the reset transistor T7 is connected with a second electrode of the second light emitting control transistor T6 at a fourth node C, and the second electrode of the reset transistor T7 is connected with an anode of the light emitting device LED at the fourth node C;

[0104] a storage capacitor Cst, one plate of the storage capacitor Cst is connected with the high potential power supply line VDD, and the other plate of the storage capacitor Cst is connected with the gate of the driving transistor T1 at the second node Q.

[0105] Specifically, as shown in the figure, Figure 5 the cathode of the light emitting device LED is connected with a low potential power supply line VSS.

[0106] Specifically, it can be understood that the display panel includes a plurality of switch control lines, each of which can drive a row of pixel units, the switch control line Scan(n) is the nth switch control line in the plurality of switch control lines, n is greater than or equal to 1, and n is a positive integer. The switch control line Scan(n) can be connected with the gate drive circuit, input signals through the gate drive circuit, or directly input signals through the drive chip. Similarly, the display panel can include a plurality of initialization control lines, a plurality of reset control lines and a plurality of light-emitting control lines. Each initialization control line, each light-emitting control line and each reset control line drive a row of pixel units. The initialization control line, the light-emitting control line and the reset control line can also be connected with the gate drive circuit or input signals through the drive chip. The gate drive circuit connected with the initialization control line, the light-emitting control line and the reset control line can be the same as the gate drive circuit connected with the switch control line, or can be different from the gate drive circuit connected with the switch control line.

[0107] Specifically, it can be understood that, due to the filling of structures in each via hole and the lamination of each film layer, the positions of each via hole cannot be seen. It can be understood that the positions of each via hole can be determined according to the positions of each structure.

[0108] In some embodiments, as shown in Figures 3 to 16 The display panel 2 includes a plurality of arrayed pixel units 240, the pixel units 240 including a first sub-pixel unit 240a, a second sub-pixel unit 240b and a third sub-pixel unit 240c, the first sub-pixel unit 240a including a first light-emitting device 341, the second sub-pixel unit 240b including a second light-emitting device 342, and the third sub-pixel unit 240c including a third light-emitting device 343. The areas of the anodes ANO1 of the first light-emitting device 341, the anodes ANO2 of the second light-emitting device 342 and the anodes ANO3 of the third light-emitting device 343 are different from each other. Since the light-emitting efficiencies of different light-emitting devices are different, by making the areas of the anodes of the first light-emitting device, the second light-emitting device and the third light-emitting device different from each other, the volumes of the light-emitting devices can be set according to the light-emitting efficiencies of the light-emitting devices, so that the light-emitting brightness of each light-emitting device can be consistent, and the display effect is improved.

[0109] Specifically, it can be understood that the light-emitting device LED includes a first light-emitting device, a second light-emitting device and a third light-emitting device, and the anode of the light-emitting device includes the anode of the first light-emitting device, the anode of the second light-emitting device and the anode of the third light-emitting device.

[0110] Specifically, as shown in Figure 3 , Figure 4As shown, the light-emitting material layer 243 includes a first light-emitting material layer 243a, a second light-emitting material layer 243b, and a third light-emitting material layer 243c. The first light-emitting material layer 243a, the second light-emitting material layer 243b, and the third light-emitting material layer 243c emit different colors. Specifically, the pixel electrode layer forms the anode of the light-emitting device, the light-emitting material layer forms the light-emitting material of the light-emitting device, and the common electrode forms the cathode of the light-emitting device.

[0111] Specifically, taking the example that the luminous colors of the first luminescent material layer 243a, the second luminescent material layer 243b and the third luminescent material layer 243c are red, green and blue respectively, since the luminous efficiency of each luminescent material is different, specifically the luminous efficiency of the blue luminescent material is the smallest and the luminous efficiency of the red luminescent material is the largest, the area of ​​the anode of the first light-emitting device can be made smaller than the area of ​​the anode of the second light-emitting device, and the area of ​​the anode of the second light-emitting device is smaller than the area of ​​the anode of the third light-emitting device.

[0112] In some embodiments, as Figures 2 to 16 As shown, in a first direction X, the width of the anode ANO1 of the first light-emitting device 341 is smaller than the width of the anode ANO2 of the second light-emitting device 342; the width of the anode ANO2 of the second light-emitting device 342 is smaller than the width of the anode ANO3 of the third light-emitting device 343. The first direction X is the same as the extension direction of the light-emitting control line. By making the width of the anode of the first light-emitting device smaller than the width of the anode of the second light-emitting device, and the width of the anode of the second light-emitting device smaller than the width of the anode of the third light-emitting device, the volume of the light-emitting devices can be adjusted according to the luminous efficiency of each light-emitting device, so that the luminous brightness of each light-emitting device can be consistent, thereby improving the display effect.

[0113] In some embodiments, as Figures 3 to 6 、 Figure 7As shown, the driving circuit layer 22 further comprises an active layer 222, the display panel 2 comprises a plurality of pixel units 240 arranged in an array, each of the pixel units 240 comprises three pixel driving circuits 220, in each of the pixel driving circuits 220, the active layer 222 comprises an active pattern T1A of a driving transistor T1, an active pattern T2A of a switching transistor T2, a first electrode T2S of the switching transistor T2, an active pattern T3A of a compensation transistor T3, a first electrode T3S of the compensation transistor T3, an active pattern T4A of an initialization transistor T4, a first electrode T4S of the initialization transistor, a second electrode T4D of the initialization transistor, an active pattern T5A of a first light emitting control transistor T5, a first electrode T5S of the first light emitting control transistor T5, an active pattern T6A of a second light emitting control transistor T6, a second electrode T6D of the second light emitting control transistor T6, an active pattern T7A of a reset transistor T7, a first electrode T7S of the reset transistor T7, a second electrode T7D of the reset transistor T7, a first node A and a third node B, the active pattern T1A of the driving transistor T1 is arranged along a first direction X, the active pattern T2A of the switching transistor T2, the active pattern T4A of the first initialization transistor T4, the active pattern T5A of the first light emitting control transistor T5, the active pattern T6A of the second light emitting control transistor T6 and the active pattern T7A of the reset transistor T7 are arranged along a second direction Y, the active pattern T3A of the compensation transistor T3 comprises a portion arranged along the first direction X and a portion arranged along the second direction Y, the active pattern T1A of the driving transistor T1 is connected with the active pattern T2A of the switching transistor T2, the active pattern T3A of the compensation transistor T3, the active pattern T5A of the first light emitting control transistor T5 and the active pattern T6A of the second light emitting control transistor T6, the active pattern T3A of the compensation transistor T3 is connected with the active pattern T4A of the first initialization transistor T4, the active pattern T6A of the second light emitting control transistor T6 is connected with the active pattern T7A of the reset transistor T7, and an angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees.

[0114] Specifically, Figures 6 to 16 is a partial view of two rows of pixel units, therefore, it can be seen that the reset transistor is located below the second light emitting control transistor.

[0115] In some embodiments, as Figures 3 to 6 、 Figure 8As shown, the driving circuit layer 22 further includes a first gate layer 224. In each of the pixel driving circuits 220, the first gate layer 224 includes a gate T1G of the driving transistor T1, a gate T2G of the switching transistor T2, a gate T3G of the compensation transistor T3, a gate T4G of the initialization transistor T4, a gate T5G of the first light-emitting control transistor T5, a gate T6G of the second light-emitting control transistor T6, a gate T7G of the reset transistor T7, a first plate Cst1 of the storage capacitor Cst, a light-emitting connection line EM-L, a switch connection line SL1, an initialization connection line SL2, and a reset connection line RL. The initialization connection line SL2, the switch connection line SL1, the gate T1G of the driving transistor T1, the light-emitting connection line EM-L, and the reset connection line RL are arranged in sequence along the second direction Y.

[0116] Specifically, such as Figure 6 、 Figure 8 As shown, it can be seen that in a row of pixel units, the light-emitting connection line EM-L is disconnected and the reset connection line RL is disconnected.

[0117] Specifically, such as Figure 8 As shown, the gate T2G of the switching transistor T2 is connected to the gate T3G of the compensation transistor T3.

[0118] Specifically, such as Figure 8 As shown, it can be seen that some structures are identified by multiple marks. This is because the electrode and the signal line share this structure, and the signals transmitted on the structure are the same (without considering the voltage drop problem). For example, the gate T5G of the first light-emitting control transistor T5 and the light-emitting connecting line EM-L identify the same structure. This is because the portion of the light-emitting connecting line EM-L corresponding to the active pattern of the first light-emitting control transistor T5 serves as the gate T5G of the first light-emitting control transistor T5. Similarly, the meaning of other structures identified by multiple marks can be determined.

[0119] Specifically, such as Figures 6 to 8 As shown, it can be understood that the gate of each transistor is arranged corresponding to the active pattern of each transistor, for example, the gate T3G of the compensation transistor is arranged corresponding to the active pattern T3A of the compensation transistor T3.

[0120] In some embodiments, as Figures 5 to 8 As shown, the gate T3G of the compensation transistor T3 includes a first gate T3Ga and a second gate T3Gb, and the first gate T3Ga is connected to the second gate T3Gb. By making the gate of the compensation transistor a double-gate design, the gate control capability of the display panel can be improved and the leakage current can be reduced.

[0121] In some embodiments, as Figures 5 to 8As shown, the gate of the initialization transistor T4 includes a third gate T4Ga and a fourth gate T4Gb, and the third gate T4Ga is connected with the fourth gate T4Gb. By designing the gate of the initialization transistor as a double-gate, the gate control capability of the display panel can be improved, and the leakage current can be reduced.

[0122] In some embodiments, as shown in Figures 3 to 6 、 Figure 9 As shown, the driving circuit layer 22 further includes a second gate layer 226. In each of the pixel driving circuits 220, the second gate layer 226 includes a first high-potential power connection line VDD-L1 and a second plate Cst2 of a storage capacitor Cst, and the first high-potential power connection line VDD-L1 is connected with the second plate Cst2 of the storage capacitor Cst.

[0123] Specifically, as shown in Figure 6 、 Figure 9 As shown, the first high-potential power connection line VDD-L1 is connected with the second plate Cst2 of the storage capacitor Cst. The second plate Cst2 of the storage capacitor Cst is provided with a via hole, and the second plate Cst2 of the storage capacitor Cst is arranged in correspondence with the first plate Cst1 of the storage capacitor Cst. The first electrode of the compensation transistor can pass through the via hole to be connected with the gate of the driving transistor.

[0124] Specifically, the second gate layer can further include a repair line. When an abnormality occurs in a sub-pixel unit or a pixel unit, the repair line can be used to disconnect the anode of the light-emitting device corresponding to the sub-pixel unit from the pixel driving circuit, and directly connect the repair line with the anode of the sub-pixel unit to directly drive the sub-pixel unit, thereby avoiding the occurrence of dark spots. When no abnormality occurs in the sub-pixel unit or the pixel unit, the repair line can be left hanging.

[0125] In some embodiments, as shown in Figures 3 to 6 、 Figure 10 As shown, the driving circuit layer 22 further includes a first source-drain layer 228. In each of the pixel driving circuits 220, the first source-drain layer 228 includes an initialization signal line VI-Q, an initialization control line Reset-Q, a switch control line Scan(n), a second high-potential power connection line VDD-L2, a light-emitting control line EM, a reset control line Reset-A, a reset signal line VI-A, a first adapter line KL1, a second adapter line KL2, a third adapter line KL3, and a fourth adapter line KL4. The initialization signal line VI-Q, the initialization control line Reset-Q, the switch control line Scan(n), the first adapter line KL1, the second high-potential power connection line VDD-L2, the light-emitting control line EM, the third adapter line KL3, the reset control line Reset-A, and the reset signal line VI-A are sequentially and spacedly arranged along the second direction Y.

[0126] Specifically, such as Figures 6 to 10 As shown, it can be seen that in a row of pixel units, the initialization signal lines VI-Q are continuous, and the initialization signal lines VI-Q are connected to the first electrode T4S of the initialization transistor T4.

[0127] Specifically, such as Figures 6 to 10 As shown, it can be seen that in a row of pixel units, the initialization control lines Reset-Q are continuous, and the initialization control lines Reset-Q are connected to the initialization connection lines SL2, thereby reducing the impedance of the initialization control lines.

[0128] Specifically, such as Figures 6 to 10 As shown, it can be seen that in a row of pixel units, the switch control line Scan(n) is connected, and the switch control line Scan(n) is connected to the switch connection line SL1.

[0129] Specifically, such as Figures 6 to 10 As shown, it can be seen that in a row of pixel units, the second high potential power connection line VDD-L2 is continuous, and the second high potential power connection line VDD-L2 is connected to the second electrode Cst2 of the storage capacitor Cst, so that the second high potential power connection line VDD-L2 is connected to the first high potential power connection line VDD-L1, reducing the impedance of the high potential power line.

[0130] Specifically, such as Figures 6 to 10 As shown, it can be seen that in a row of pixel units, the light emitting control lines EM are continuous, and the light emitting control lines EM are connected to the light emitting connection lines EM-L, thereby reducing the impedance of the light emitting control lines.

[0131] Specifically, such as Figures 6 to 10 As shown, it can be seen that in a row of pixel units, the reset control line Reset-A is continuous, and the reset control line Reset-A is connected to the reset connection line RL, thereby reducing the impedance of the reset control line.

[0132] Specifically, such as Figures 6 to 10 As shown, it can be seen that in a row of pixel units, the reset signal line VI-A is continuous, and the reset signal line VI-A is connected to the first electrode T7S of the reset transistor T7.

[0133] Specifically, such as Figures 6 to 10 As shown, the first adapter wire KL1 is connected to the first electrode T2S of the switching transistor T2, one end of the second adapter wire KL2 is connected to the first electrode T3S of the compensation transistor T3, the other end of the second adapter wire KL2 is connected to the gate T1G of the driving transistor T1, the third adapter wire KL3 is connected to the first electrode T5S of the first light-emitting control transistor T5, and the fourth adapter wire KL4 is connected to the second electrode T6D of the second light-emitting control transistor T6.

[0134] In some embodiments, as shown in Figures 3 to 6 , Figure 11 The driving circuit layer 22 further comprises a second source-drain layer 232, in each of the pixel units 240, the second source-drain layer 232 comprises three data lines Data, three high potential power lines VDD, one low potential power line VSS, one reset connection line VI-L and three anode connection lines ANO-L, the three data lines Data and the three high potential power lines VDD are arranged alternately along the first direction X, the low potential power line VSS is arranged on the side of the high potential power line VDD away from the data line Data, the reset connection line VI-L is arranged between one data line Data and one high potential power line VDD, each anode connection line ANO-L is arranged between one high potential power line VDD and one data line Data, and the three high potential power lines VDD are connected with the second high potential power connection line VDD-L2.

[0135] Specifically, as shown in Figure 6 , Figure 11 The data line Data, the high potential power line VDD, the low potential power line VSS, the reset connection line VI-L and the anode connection line ANO-L are arranged along the second direction Y.

[0136] Specifically, as shown in Figures 6 to 11 It can be seen that the data line Data is connected with the first adapter line KL1, the high potential power line VDD is connected with the second high potential power connection line VDD-L2, and the high potential power line VDD is connected with the third adapter line KL3, so that the meshing and signal transmission of the high potential power line VDD can be realized, and the impedance of the high potential power line can be reduced. It can be understood that the signals on the first high potential power connection line and the second high potential power connection line are the signals of the high potential power line, and the first high potential power connection line and the second high potential power connection line can be regarded as part of the high potential power line.

[0137] Specifically, as shown in Figures 6 to 11 The anode connection line ANO-L can be connected with the fourth adapter line KL4.

[0138] In some embodiments, as shown in Figures 3 to 6 , Figures 11 to 12 The light-emitting functional layer 24 comprises a pixel electrode layer 241, in each of the pixel units 240, the pixel electrode layer 241 comprises three anodes ANO of the light-emitting devices LED, each anode ANO of the light-emitting device LED is connected with one anode connection line ANO-L, and one anode connection line ANO-L is connected with one fourth adapter line.

[0139] Specifically, the anode of the light emitting device projects on the substrate overlaps with the projection of the high potential power line on the substrate.

[0140] Specifically, as shown in Figure 12 It can be seen that the anode ANO of the light emitting device LED is arranged along the second direction Y, the anodes ANO of the plurality of light emitting devices LED are arranged along the first direction X at intervals, the anode ANO of each light emitting device LED is connected with the anode connection line ANO-L, the anode connection line ANO-L is connected with the fourth switching line KL4, the fourth switching line KL4 is connected with the second electrode T6D of the second light emitting control transistor T6, and the connection of the light emitting device and the second light emitting control transistor is realized.

[0141] In some embodiments, as shown in Figures 3 to 12 The display panel 2 includes a plurality of pixel units 240 arranged in an array, the pixel unit 240 includes a first sub-pixel unit 240a, a second sub-pixel unit 240b and a third sub-pixel unit 240c, the first sub-pixel unit 240a includes a first light emitting device 341, the second sub-pixel unit 240b includes a second light emitting device 342, and the third sub-pixel unit 240c includes a third light emitting device 343, the pixel driving circuit 220 includes a first pixel driving circuit 220a, a second pixel driving circuit 220b and a third pixel driving circuit 220c electrically connected with the anode of the first light emitting device 341, the anode of the second light emitting device 342 and the anode of the third light emitting device 343 respectively, the data line Data includes a first data line Data-R, a second data line Data-G and a third data line Data-B electrically connected with the first pixel driving circuit 220a, the second pixel driving circuit 220b and the third pixel driving circuit 220c respectively, and the high potential power line VDD includes a first high potential power line VDD1, a second high potential power line VDD2 and a third high potential power line VDD3 electrically connected with the first pixel driving circuit 220a, the second pixel driving circuit 220b and the third pixel driving circuit 220c respectively.

[0142] Specifically, the first data line Data-R, the second data line Data-G and the third data line Data-B can correspond to the first sub-pixel unit, the second sub-pixel unit and the third sub-pixel unit respectively. It can be understood that the brightness of different sub-pixel units can be the same or different when the display panel is displayed, so there can be a case of driving different sub-pixel units with different driving voltages. Therefore, the first data line Data-R, the second data line Data-G and the third data line Data-B can input different voltages to make each sub-pixel unit display the corresponding brightness.

[0143] Specifically, the first high potential power line VDD1, the second high potential power line VDD2 and the third high potential power line VDD3 can correspond to the first sub-pixel unit, the second sub-pixel unit and the third sub-pixel unit respectively, and the first high potential power line VDD1, the second high potential power line VDD2 and the third high potential power line VDD3 can be the same or different.

[0144] At the same time, in order to illustrate the relative position of each film layer, Figure 6 、 Figures 13 to 16 To explain, from Figure 13 As can be seen from FIG, the relative positions of the structures in the first gate layer 224 and the structures in the active layer 222; Figure 14 The relative positions of the structures in the active layer 222, the first gate layer 224 and the second gate layer 226 can be seen in FIG; Figure 15 The relative positions of the structures in the active layer 222, the first gate layer 224, the second gate layer 226 and the first source and drain layer 228 can be seen in FIG; Figure 16 The relative positions of the structures in the active layer 222 , the first gate layer 224 , the second gate layer 226 , the first source-drain layer 228 and the second source-drain layer 232 can be seen in FIG.

[0145] Specifically, the first electrode of the transistor in the above embodiment is a source electrode, and the second electrode is a drain electrode; or the first electrode of the transistor in the above embodiment is a drain electrode, and the second electrode is a source electrode.

[0146] Specifically, the material of the active layer includes silicon semiconductor material, specifically low-temperature polysilicon; or the material of the active layer includes oxide semiconductor material, specifically metal oxide semiconductor material, more specifically indium gallium zinc oxide.

[0147] Specifically, the driving transistor, the switching transistor, the compensation transistor, the initialization transistor, the first light emission control transistor, the second light emission control transistor and the reset transistor may be P-type transistors or N-type transistors.

[0148] Specifically, it is understood that due to the differences in the cut portions when splitting each film layer, some film layers may have partial structural defects. It is understood that the structure of each film layer in the display panel can be seen in FIG. Figure 6 And determine the relative position and size in combination with each figure, for example, Figure 11 In the embodiment, the first data line Data-R in the second source-drain layer 232 is partially missing, and the low potential power line VSS is not shown, but it can be understood that it can be seen from FIG. Figure 6 The positions and sizes of the first data line Data-R and the low potential power line VSS are determined in conjunction with other figures.

[0149] Specifically, the above embodiments are described in detail from the aspects of the circuit of the display panel, the film layer structure, the specific design of each film layer, the connection relationship and the relative relationship between each film layer, and the like. It can be understood that the embodiments can be combined without conflict, for example, the light emitting control line and the light emitting connection line are arranged along the first direction, the projection of the light emitting connection line on the substrate overlaps the projection of the light emitting control line on the substrate, and the width of the light emitting connection line in the second direction is greater than or equal to the width of the light emitting control line in the second direction; wherein, in the overlapping area of the light emitting connection line and the light emitting control line, the projection of the light emitting control line on the substrate is located in the projection of the light emitting connection line on the substrate; the reset control line and the reset connection line are arranged along the first direction, the projection of the reset connection line on the substrate overlaps the projection of the reset control line on the substrate, and the width of the reset connection line in the second direction is greater than or equal to the width of the reset control line in the second direction; wherein, in the overlapping area of the reset connection line and the reset control line, the projection of the reset control line on the substrate is located in the projection of the reset connection line on the substrate, and the included angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

[0150] Meanwhile, the display device provided by the embodiments of the present application includes the display panel as described in any of the above embodiments.

[0151] Specifically, the display panel includes an organic light emitting diode display panel.

[0152] In the description of the present application, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0153] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0154] The embodiments, implementation manners and related technical features of the present application can be combined, replaced with each other without conflict.

[0155] The above is only the preferred embodiment of the present application, and does not limit the present application in any form. Any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the technical solution of the present application, still belongs to the scope of the technical solution of the present application.

Claims

1. A display panel, characterized by, The display panel comprises a substrate, a driving circuit layer arranged on one side of the substrate, and a plurality of pixel units arranged on the substrate. The driving circuit layer comprises a plurality of light-emitting control lines, a plurality of reset control lines, a plurality of light-emitting switching lines, and a plurality of reset switching lines. At least one of the light-emitting switching lines is provided with a break; and / or at least one of the reset switching lines is provided with a break. Each of the pixel units comprises a plurality of sub-pixel units. The light-emitting switching lines comprise a plurality of light-emitting connection lines, and the break is arranged between any two adjacent light-emitting connection lines.

2. The display panel of claim 1, wherein, Each of the light-emitting connection lines corresponds to one of the sub-pixel units. The reset switching lines comprise a plurality of reset connection lines, and the break is arranged between any two adjacent reset connection lines.

3. The display panel of claim 1, wherein, Each of the reset connection lines corresponds to one of the sub-pixel units. The light-emitting control lines and the light-emitting connection lines are arranged along a first direction.

4. The display panel of any of claims 1 to 3, wherein, The projection of the light-emitting connection line on the substrate overlaps the projection of the light-emitting control line on the substrate.

5. The display panel according to any one of claims 1 to 3, characterized in that, The width of the light-emitting connection line in a second direction is greater than or equal to the width of the light-emitting control line in the second direction.

6. The display panel of any one of claims 1 to 3, wherein, In the overlapping area of the light-emitting connection line and the light-emitting control line, the projection of the light-emitting control line on the substrate is located within the projection of the light-emitting connection line on the substrate. The angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees. The reset control lines and the reset connection lines are arranged along a first direction. The projection of the reset connection line on the substrate overlaps the projection of the reset control line on the substrate. The width of the reset connection line in a second direction is greater than or equal to the width of the reset control line in the second direction. In the overlapping area of the reset connection line and the reset control line, the projection of the reset control line on the substrate is located within the projection of the reset connection line on the substrate. The angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees. The driving circuit layer comprises a first gate layer and a first source-drain layer. The first gate layer is arranged between the substrate and the first source-drain layer. The first gate layer comprises the light-emitting connection lines and the reset connection lines. The first source-drain layer comprises the light-emitting control lines and the reset control lines. The driving circuit layer comprises a first via. The light-emitting control line is connected with the light-emitting connection line through the first via. The light-emitting control line is symmetrically arranged about the first via. The driving circuit layer further comprises a pixel driving circuit, an active layer, a first source-drain layer, and a second via. The pixel driving circuit comprises a reset transistor. The active layer comprises an active pattern of the reset transistor. The first source-drain layer further comprises a reset signal line. The second via is arranged corresponding to the reset signal line. The second via is arranged corresponding to the active pattern of the reset transistor. The reset signal line is connected with the active pattern of the reset transistor through the second via.

7. The display panel of any of claims 1 to 3, wherein, The driving circuit layer further comprises a pixel driving circuit, an active layer, a first source-drain layer and a third via hole, the pixel driving circuit comprises an initialization transistor, the active layer comprises an active pattern of the initialization transistor, and the first source-drain layer further comprises an initialization signal line; The third via hole is arranged correspondingly to the initialization signal line, the third via hole is arranged correspondingly to the active pattern of the initialization transistor, and the initialization signal line is connected to the active pattern of the initialization transistor through the third via hole.

8. The display panel of any one of claims 1 to 3, wherein, The driving circuit layer further comprises a first gate layer, a first source-drain layer and a second source-drain layer, the second source-drain layer is arranged on a side of the first source-drain layer away from the first gate layer, and the second source-drain layer comprises a high-potential power supply line; The first gate layer further comprises an initialization connection line, the first source-drain layer further comprises an initialization control line, the initialization connection line comprises a first connection part and a second connection part, the first connection part is connected to the initialization control line and the second connection part, and a projection of one end of the first connection part on the substrate is spaced apart from a projection of one end of the high-potential power supply line on the substrate.

9. The display panel of any one of claims 1 to 3, wherein, The driving circuit layer further comprises a first gate layer, a second gate layer, a first source-drain layer and a second source-drain layer, the second gate layer is arranged between the first gate layer and the first source-drain layer, the second source-drain layer is arranged on a side of the first source-drain layer away from the second gate layer, the second gate layer comprises a first high-potential power supply connection line, the first source-drain layer comprises a second high-potential power supply connection line, and the second source-drain layer comprises a high-potential power supply line; The second high-potential power supply connection line is connected to the first high-potential power supply connection line and the high-potential power supply line, the driving circuit layer further comprises a fourth via hole, the second high-potential power supply connection line is connected to the first high-potential power supply connection line through the fourth via hole, and a lower end of the fourth via hole is located on the same straight line as a lower end of the second high-potential power supply connection line.

10. A display device, characterized by comprising: The display panel comprises the display panel as claimed in any one of claims 1 to 9.

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