Light emitting diode and preparation method thereof
By designing the Si-doped buffer layer, nucleation layer and filler layer in the light emitting diode, the doping concentration of the first semiconductor layer is reduced, and the problem of difficulty in reducing the voltage level and high stress at large current is solved, and the luminescence uniformity and crystal quality are improved.
Patent Information
- Application Number
- CN202411848832.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-16
- Publication Date
- 2025-04-29
AI Technical Summary
When the prior art reduces the voltage level under large currents, increasing the Si doping concentration of the first semiconductor layer is not obvious, and excessive doping will lead to large stresses and affect luminescence uniformity.
By designing the buffer layer, nucleation layer and filler layer in the light emitting diode as Si-doped layers and doping partly in the growth direction, the doping concentration of the first semiconductor layer is reduced, thereby reducing the voltage level under large currents, avoiding stress problems, and ensuring luminescence uniformity.
It is achieved that the voltage level under large current is reduced without increasing the Si doping concentration of the first semiconductor layer, the stress problem is avoided, the light emission uniformity is ensured, and the crystal quality is improved.
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Figure CN119907372A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light emitting diode and a method for preparing the same. Background Art
[0002] Light Emitting Diode (LED) is a very influential new product in the optoelectronics industry. It has the characteristics of small size, long service life, rich colors and low energy consumption. It is widely used in lighting, display screens, signal lights, backlight sources, toys and other fields.
[0003] In the related art, a light-emitting diode generally includes a buffer layer, a nucleation layer, a fill layer, a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked in sequence. The first semiconductor layer is a Si-doped layer with a doping concentration of up to 8*10 19 cm -3 .
[0004] Due to the need to reduce the voltage level under high current, the relevant technology will consider further increasing the Si doping concentration in the first semiconductor layer, but the effect is not obvious, and excessive doping will cause great stress and affect the uniformity of light emission. Summary of the invention
[0005] The embodiment of the present disclosure provides a light emitting diode and a method for manufacturing the same, which reduces the voltage level under high current on the basis of reducing the doping concentration of the first semiconductor layer. The technical solution is as follows:
[0006] In one aspect, an embodiment of the present disclosure provides a light emitting diode, the light emitting diode comprising:
[0007] A buffer layer, a nucleation layer, a filling layer, a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked in sequence;
[0008] The nucleation layer is a three-dimensional island structure, and the buffer layer, the nucleation layer, the filling layer and the first semiconductor layer are all Si doped layers, wherein the buffer layer, the nucleation layer and the filling layer are all partially doped layers in the growth direction, and the doping concentration of the first semiconductor layer is 0.6*10 19 cm -3 ~6.4*10 19 cm -3 .
[0009] Optionally, the buffer layer includes an intrinsic buffer sublayer and a doped buffer sublayer, and the doped buffer sublayer is located between the intrinsic buffer sublayer and the nucleation layer.
[0010] Optionally, the doping concentration of the doped buffer sublayer is 1*10 17 cm-3 ~5*10 17 cm -3 .
[0011] Optionally, the nucleation layer includes a first intrinsic nucleation sublayer, a doped nucleation sublayer and a second intrinsic nucleation sublayer sequentially stacked on the buffer layer.
[0012] Optionally, the doping concentration of the doped nucleation sublayer is 2*10 17 cm -3 ~6*10 17 cm -3 .
[0013] Optionally, the leveling layer comprises a superlattice structure consisting of an intrinsic leveling sublayer and a doped leveling sublayer sequentially stacked on the nucleation layer.
[0014] Optionally, the thickness of the intrinsic filling sublayer is 1.5 to 3 times the thickness of the doped filling sublayer.
[0015] Optionally, the filling layer includes a superlattice structure with 3 periods.
[0016] Optionally, from the filling layer to the first semiconductor layer, the doping concentrations of the doped filling sublayers in the three-period superlattice structure are 3*10 17 cm -3 ~6*10 17 cm -3 , 5*10 17 cm -3 ~1*10 18 cm -3 , 4*10 17 cm -3 ~8*10 17 cm -3 .
[0017] On the other hand, an embodiment of the present disclosure provides a method for preparing a light emitting diode, the method comprising:
[0018] Making a buffer layer;
[0019] Making a nucleation layer on the buffer layer, wherein the nucleation layer is a three-dimensional island structure;
[0020] Making a filling layer on the nucleation layer;
[0021] A first semiconductor layer, a light-emitting layer, and a second semiconductor layer are sequentially formed on the filling layer, wherein the buffer layer, the nucleation layer, the filling layer, and the first semiconductor layer are all Si-doped layers, wherein the buffer layer, the nucleation layer, and the filling layer are all partially doped layers in the growth direction, and the doping concentration of the first semiconductor layer is 0.6*10 19 cm -3 ~6.4*10 19 cm -3 .
[0022] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:
[0023] In the light-emitting diode provided by the embodiment of the present disclosure, the buffer layer, the nucleation layer, the fill layer and the first semiconductor layer are all Si-doped layers, that is, in addition to the first semiconductor layer, the buffer layer, the nucleation layer and the fill layer are also changed from intrinsic layers to doped layers, thereby reducing the doping concentration of the first semiconductor layer, which can not only reduce the voltage level under large currents, but also avoid stress problems caused by excessive doping concentration of the first semiconductor layer, thereby ensuring uniform light emission. In addition, the buffer layer, the nucleation layer and the fill layer are all partially doped layers in the growth direction, rather than full-layer doping, thereby ensuring the crystal quality of the buffer layer, the nucleation layer and the fill layer as much as possible. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0025] Figure 1 is a structural schematic diagram of a light emitting diode provided by an embodiment of the present disclosure;
[0026] Figure 2 is a schematic structural diagram of another light emitting diode provided by an embodiment of the present disclosure;
[0027] Figure 3 is a flow chart of a method for preparing a light emitting diode provided by an embodiment of the present disclosure;
[0028] Figure 4 This is a flow chart of another method for preparing a light emitting diode provided in an embodiment of the present disclosure.
[0029] The reference numerals are as follows:
[0030] 100: substrate; 101: buffer layer; 102: nucleation layer; 103: leveling layer; 104: first semiconductor layer; 105: light-emitting layer; 107: electron blocking layer; 106: second semiconductor layer; 111: intrinsic buffer sublayer; 112: doped buffer sublayer; 121: first intrinsic nucleation sublayer; 122: doped nucleation sublayer; 123: second intrinsic nucleation sublayer; 131: intrinsic leveling sublayer; 132: doped leveling sublayer. DETAILED DESCRIPTION
[0031] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.
[0032] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0033] Figure 1 is a schematic diagram of the structure of a light emitting diode provided by an embodiment of the present disclosure. Figure 1 , the light emitting diode comprises:
[0034] A buffer layer 101 , a nucleation layer 102 , a leveling layer 103 , a first semiconductor layer 104 , a light emitting layer 105 and a second semiconductor layer 106 are stacked in sequence.
[0035] The nucleation layer 102 is a three-dimensional island structure, the buffer layer 101, the nucleation layer 102, the filling layer 103 and the first semiconductor layer 103 are all Si doped layers, wherein the buffer layer 101, the nucleation layer 102 and the filling layer 103 are all partially doped layers in the growth direction, and the doping concentration of the first semiconductor layer 104 is 0.6*10 19 cm -3 ~6.4*1019 cm -3 。
[0036] Among them, * is the multiplication sign, indicating multiplication.
[0037] In the light-emitting diode provided by the embodiment of the present disclosure, the buffer layer, the nucleation layer, the planarization layer, and the first semiconductor layer are all Si-doped layers. That is, except for the first semiconductor layer, the buffer layer, the nucleation layer, and the planarization layer also change from the intrinsic layer to the doped layer, thereby reducing the doping concentration of the first semiconductor layer. In this way, it can not only reduce the voltage level under large current, but also avoid the stress problem caused by excessive doping concentration of the first semiconductor layer, ensuring light emission uniformity. In addition, the buffer layer, the nucleation layer, and the planarization layer are all partially thickness-doped layers in the growth direction, rather than the whole layer being doped, so as to ensure the crystal quality of the buffer layer, the nucleation layer, and the planarization layer as much as possible.
[0038] Exemplarily, the doping concentration of the first semiconductor layer 104 is 0.8*10 19 cm -3 。
[0039] Figure 2 is a schematic structural diagram of another light-emitting diode provided by the embodiment of the present disclosure. Refer to Figure 2 , this light-emitting diode further includes: a substrate 100, and a buffer layer 101 is located on the substrate 100.
[0040] In the embodiment of the present disclosure, the substrate 100 may be a sapphire substrate.
[0041] In the embodiment of the present disclosure, the buffer layer 101, the nucleation layer 102, the planarization layer 103, the first semiconductor layer 104, and the second semiconductor layer 106 are all GaN layers.
[0042] In the embodiment of the present disclosure, the light-emitting layer 105 may be a multi-quantum well barrier layer.
[0043] Exemplarily, the light-emitting layer 105 is a superlattice composed of 8 to 15 periods of In x Ga 1-x N(0.2 < x < 0.5) quantum wells / GaN (or AlGaN) quantum barriers.
[0044] Exemplarily, the second semiconductor layer 106 is a Mg-doped GaN layer.
[0045] Optionally, refer to Figure 2 , this light-emitting diode further includes: an electron blocking layer 107, and the electron blocking layer 107 is located between the light-emitting layer 105 and the second semiconductor layer 106.
[0046] In an embodiment of the present disclosure, the electron blocking layer 107 may be an electron blocking Al y Ga 1-y N (0.1 < y < 0.5) layer.
[0047] In an embodiment of the present disclosure, the second semiconductor layer 106 may include a high-temperature P-type GaN layer and a P-type doped GaN contact layer.
[0048] Referring to Figure 2 , in an example of an embodiment of the present disclosure, the buffer layer 101 includes an intrinsic buffer sub-layer 111 and a doped buffer sub-layer 112, and the doped buffer sub-layer 112 is located between the intrinsic buffer sub-layer 111 and the nucleation layer 102.
[0049] In this implementation, the doped portion is located in the second half of the growth of the buffer layer. On the one hand, this ensures that the portion in contact with the sapphire substrate is undoped, thus ensuring the crystal quality. On the other hand, it also increases the Si doping so as to reduce the Si doping concentration in the first semiconductor layer.
[0050] Exemplarily, the doping concentration of the doped buffer sub-layer 112 is 1×10 17 cm -3 ~5×10 17 cm -3 .
[0051] For example, the doping concentration of the doped buffer sub-layer 112 is 3×10 17 cm -3 .
[0052] In this implementation, adopting the above doping concentration makes the Si doping concentration in the buffer layer relatively low, which can ensure the crystal quality of the buffer layer, and this doping concentration can have an effect on reducing the Si doping in the first semiconductor layer.
[0053] Exemplarily, the thickness of the intrinsic buffer sub-layer 111 may be 0.4 to 0.5 times that of the buffer layer 101, for example, half of the buffer layer 101.
[0054] In other examples of an embodiment of the present disclosure, the doped buffer sub-layer in the buffer layer 101 may also be located in the middle or other positions of the buffer layer 101.
[0055] Referring to Figure 2 , in an example of an embodiment of the present disclosure, the nucleation layer 102 includes a first intrinsic nucleation sub-layer 121, a doped nucleation sub-layer 122, and a second intrinsic nucleation sub-layer 123 that are sequentially stacked on the buffer layer 101.
[0056] In this implementation, the doping part is arranged in the middle of the nucleation layer. On the one hand, the doping concentration of the first semiconductor layer can be reduced by increasing the doping of Si in the nucleation layer. On the other hand, arranging the doping part in the middle can ensure the adaptation with the adjacent layers and the three-dimensional structure of the nucleation layer.
[0057] For example, the doping concentration of the doped nucleation sublayer 122 is 2*10 17 cm -3 ~6*10 17 cm -3 .
[0058] For example, the doping concentration of the doped nucleation sublayer 122 is 4*10 17 cm -3 .
[0059] In this implementation, the above-mentioned doping concentration is adopted to make the doping concentration of Si in the nucleation layer lower, which can ensure the crystal quality of the nucleation layer, and the doping concentration can play an effect on reducing the Si doping of the first semiconductor layer.
[0060] Exemplarily, the thickness of the doped nucleation sublayer 122 may be 0.25 to 0.3 times of the nucleation layer 102 , for example, one third of the nucleation layer 102 .
[0061] In other examples of the embodiments of the present disclosure, the doped nucleation sublayer in the nucleation layer 102 may also be located at the bottom surface of the nucleation layer 102 or at other locations.
[0062] See also Figure 2 In an example of the embodiment of the present disclosure, the leveling layer 103 includes a superlattice structure consisting of an intrinsic leveling sublayer 131 and a doped leveling sublayer 132 sequentially stacked on the nucleation layer 102 .
[0063] In this implementation, the filling layer adopts a multi-stage doping method. On the one hand, it can reduce the doping concentration of the first semiconductor layer by increasing the doping of Si in the filling layer. On the other hand, the doping part adopts a multi-stage setting to ensure the crystal quality of the filling layer.
[0064] Exemplarily, the thickness of the intrinsic filling sub-layer 131 is 1.5 to 3 times the thickness of the doped filling sub-layer 132 .
[0065] For example, the thickness of the intrinsic leveling sub-layer 131 is twice the thickness of the doped leveling sub-layer 132 .
[0066] In this implementation, the intrinsic leveling sublayer is designed to be thicker, which is beneficial to improving the crystal quality of the leveling layer.
[0067] Exemplarily, the leveling layer 103 includes a superlattice structure with 3 to 5 periods.
[0068] For example, the filling layer 103 includes a superlattice structure with 3 periods.
[0069] In this implementation, the filling layer uses a three-period superlattice, which can ensure the benefits of multi-stage doping on the one hand, and avoid the growth of the filling layer being too complicated on the other hand.
[0070] In the embodiment of the present disclosure, in a direction from the filling layer 103 to the first semiconductor layer 103 , the doping concentration of Si in the filling layer is first high and then low.
[0071] For example, from the direction of the filling layer 103 to the first semiconductor layer 103, the doping concentration of the doped filling sublayer 132 in the three-period superlattice structure is 3*10 17 cm -3 ~6*10 17 cm -3 , 5*10 17 cm -3 ~1*10 18 cm -3 , 4*10 17 cm -3 ~8*10 17 cm -3 .
[0072] For example, from the direction of the filling layer 103 to the first semiconductor layer 103, the doping concentration of the doped filling sublayer 132 in the three-period superlattice structure is 5*10 17 cm -3 ,8*10 17 cm -3 , 6*10 17 cm -3 .
[0073] In this implementation, the above-mentioned doping concentration is used to make the doping concentration of Si in the filling layer lower, which can ensure the crystal quality of the filling layer, and the doping concentration can have the effect of reducing the Si doping of the first semiconductor layer.
[0074] In other examples of the embodiments of the present disclosure, the leveling layer 103 may not be arranged in a superlattice, for example, only one doped leveling sublayer is arranged in the middle of the leveling layer or in other positions.
[0075] It is worth noting that in the embodiments of the present disclosure, structures may be selectively increased or decreased based on the structure of the above-mentioned light emitting diode, and the present disclosure does not impose any limitation on this.
[0076] Figure 3 FIG. 1 is a flow chart of a method for preparing a light emitting diode provided by an embodiment of the present disclosure. Figure 3 As shown, the preparation method comprises:
[0077] Step 301: making a buffer layer.
[0078] Step 302: fabricating a nucleation layer on the buffer layer, wherein the nucleation layer is a three-dimensional island structure.
[0079] Step 303: making a filling layer on the nucleation layer.
[0080] Step 304: A first semiconductor layer, a light-emitting layer, and a second semiconductor layer are sequentially formed on the fill layer, wherein the buffer layer, the nucleation layer, the fill layer, and the first semiconductor layer are all Si-doped layers, wherein the buffer layer, the nucleation layer, and the fill layer are all partially doped layers in the growth direction, and the doping concentration of the first semiconductor layer is 0.6*10 19 cm -3 ~6.4*10 19 cm -3 .
[0081] In the light-emitting diode provided by the embodiment of the present disclosure, the buffer layer, the nucleation layer, the fill layer and the first semiconductor layer are all Si-doped layers, that is, in addition to the first semiconductor layer, the buffer layer, the nucleation layer and the fill layer are also changed from intrinsic layers to doped layers, thereby reducing the doping concentration of the first semiconductor layer, which can not only reduce the voltage level under large currents, but also avoid stress problems caused by excessive doping concentration of the first semiconductor layer, thereby ensuring uniform light emission. In addition, the buffer layer, the nucleation layer and the fill layer are all partially doped layers in the growth direction, rather than full-layer doping, thereby ensuring the crystal quality of the buffer layer, the nucleation layer and the fill layer as much as possible.
[0082] In the disclosed embodiment, the buffer layer, the nucleation layer, the leveling layer, the first semiconductor layer, the light-emitting layer and the second semiconductor layer are grown in a reaction chamber, which is a reaction chamber of a MOCVD (Metal Organic Chemical Vapor Deposition) device.
[0083] When growing each film layer, the growth substrate is placed in a graphite disk in a MOCVD reaction chamber, and each film layer is formed on the substrate in the graphite disk by introducing MO source and reaction gas into the reaction chamber and controlling the rotation of the graphite disk.
[0084] Figure 4 FIG. 1 is a flow chart of a method for preparing a light emitting diode provided by an embodiment of the present disclosure. Figure 4As shown, the preparation method comprises:
[0085] Step 401: growing a buffer layer on a substrate.
[0086] In the embodiment of the present disclosure, the substrate 100 may be a sapphire substrate.
[0087] Wherein, the buffer layer is a Si doped layer, wherein the buffer layer is a doped layer with a partial thickness in the growth direction.
[0088] See also Figure 2 In an example of the embodiment of the present disclosure, the buffer layer 101 includes an intrinsic buffer sublayer 111 and a doped buffer sublayer 112 , and the doped buffer sublayer 112 is located between the intrinsic buffer sublayer 111 and the nucleation layer 102 .
[0089] In this implementation, the doped part is located in the second half of the buffer layer growth. This method ensures that the part in contact with the sapphire substrate is undoped, thereby ensuring the crystal quality. On the other hand, it also increases Si doping, thereby reducing the doping concentration of Si in the first semiconductor layer.
[0090] In this implementation, in step 401, when growing the buffer layer, the Si source is not introduced when growing the intrinsic buffer sublayer in the first half of the buffer layer, and the Si source is introduced when growing the doped buffer sublayer in the second half of the buffer layer.
[0091] For example, the doping concentration of the doped buffer sublayer 112 is 1*10 17 cm -3 ~5*10 17 cm -3 .
[0092] For example, the doping concentration of the doped buffer sublayer 112 is 3*10 17 cm -3 .
[0093] In this implementation, the above-mentioned doping concentration is adopted to make the doping concentration of Si in the buffer layer lower, so that the crystal quality of the buffer layer can be ensured, and the doping concentration can have the effect of reducing the Si doping of the first semiconductor layer.
[0094] Exemplarily, the thickness of the intrinsic buffer sublayer 111 may be 0.4 to 0.5 times that of the buffer layer 101 , for example, half that of the buffer layer 101 .
[0095] In other examples of the embodiments of the present disclosure, the doped buffer sublayer in the buffer layer 101 may also be located in the middle or other positions of the buffer layer 101 .
[0096] Step 402: forming a nucleation layer on the buffer layer, wherein the nucleation layer is a three-dimensional island structure.
[0097] Wherein, the nucleation layer is a Si doped layer, wherein the nucleation layer is a doped layer with a partial thickness in the growth direction.
[0098] See also Figure 2 In an example of the embodiment of the present disclosure, the nucleation layer 102 includes a first intrinsic nucleation sublayer 121 , a doped nucleation sublayer 122 , and a second intrinsic nucleation sublayer 123 sequentially stacked on the buffer layer 101 .
[0099] In this implementation, the doping part is arranged in the middle of the nucleation layer. On the one hand, the doping concentration of the first semiconductor layer can be reduced by increasing the doping of Si in the nucleation layer. On the other hand, arranging the doping part in the middle can ensure the adaptation with the adjacent layers and the three-dimensional structure of the nucleation layer.
[0100] In this implementation, in step 402, when growing the nucleation layer, the Si source is not introduced when growing the first intrinsic nucleation sublayer in the front section of the nucleation layer, the Si source is introduced when growing the doped nucleation sublayer in the middle section of the nucleation layer, and the Si source is not introduced when growing the second intrinsic nucleation sublayer in the back section of the nucleation layer.
[0101] For example, the doping concentration of the doped nucleation sublayer 122 is 2*10 17 cm -3 ~6*10 17 cm -3 .
[0102] For example, the doping concentration of the doped nucleation sublayer 122 is 4*10 17 cm -3 .
[0103] In this implementation, the above-mentioned doping concentration is adopted to make the doping concentration of Si in the nucleation layer lower, which can ensure the crystal quality of the nucleation layer, and the doping concentration can play an effect on reducing the Si doping of the first semiconductor layer.
[0104] Exemplarily, the thickness of the doped nucleation sublayer 122 may be 0.25 to 0.3 times of the nucleation layer 102 , for example, one third of the nucleation layer 102 .
[0105] In other examples of the embodiments of the present disclosure, the doped nucleation sublayer in the nucleation layer 102 may also be located at the bottom surface of the nucleation layer 102 or at other locations.
[0106] Step 403: growing a filling layer on the nucleation layer.
[0107] Wherein, the filling layer is a Si doped layer, wherein the filling layer is a doped layer with a partial thickness in the growth direction.
[0108] See also Figure 2 In an example of the embodiment of the present disclosure, the leveling layer 103 includes a superlattice structure consisting of an intrinsic leveling sublayer 131 and a doped leveling sublayer 132 sequentially stacked on the nucleation layer 102 .
[0109] In this implementation, the filling layer adopts a multi-stage doping method. On the one hand, it can reduce the doping concentration of the first semiconductor layer by increasing the doping of Si in the filling layer. On the other hand, the doping part adopts a multi-stage setting to ensure the crystal quality of the filling layer.
[0110] In this implementation, in step 403, when growing the filling layer, when growing the intrinsic filling sublayer in the superlattice structure, no Si source is introduced, and when growing the doped filling sublayer in the superlattice structure, a Si source is introduced.
[0111] Exemplarily, the thickness of the intrinsic filling sub-layer 131 is 1.5 to 3 times the thickness of the doped filling sub-layer 132 .
[0112] For example, the thickness of the intrinsic leveling sub-layer 131 is twice the thickness of the doped leveling sub-layer 132 .
[0113] In this implementation, the intrinsic leveling sublayer is designed to be thicker, which is beneficial to improving the crystal quality of the leveling layer.
[0114] Exemplarily, the leveling layer 103 includes a superlattice structure with 3 to 5 periods.
[0115] For example, the filling layer 103 includes a superlattice structure with 3 periods.
[0116] In this implementation, the filling layer uses a three-period superlattice, which can ensure the benefits of multi-stage doping on the one hand, and avoid the growth of the filling layer being too complicated on the other hand.
[0117] In the embodiment of the present disclosure, in a direction from the filling layer 103 to the first semiconductor layer 103 , the doping concentration of Si in the filling layer is first high and then low.
[0118] For example, from the direction of the filling layer 103 to the first semiconductor layer 103, the doping concentration of the doped filling sublayer 132 in the three-period superlattice structure is 3*10 17 cm -3 ~6*10 17 cm -3 , 5*10 17 cm -3 ~1*10 18 cm -3 , 4*10 17 cm -3 ~8*1017 cm -3 。
[0119] For example, in the direction from the filling layer 103 to the first semiconductor layer 103, the doping concentrations of the doped filling sub-layers 132 in the 3-period superlattice structure are successively 5×10 17 cm -3 , 8×10 17 cm -3 , 6×10 17 cm -3 。
[0120] In this implementation manner, the above doping concentrations are adopted to make the doping concentration of Si in the filling layer relatively low, which can ensure the crystal quality of the filling layer, and this doping concentration can have an effect on reducing the Si doping of the first semiconductor layer.
[0121] In other examples of the embodiments of the present disclosure, the filling layer 103 may not adopt the superlattice setting. For example, only one doped filling sub-layer is provided, which is provided in the middle or other positions of the filling layer.
[0122] Step 404: Grow a first semiconductor layer, a light-emitting layer, an electron blocking layer, and a second semiconductor layer on the filling layer in sequence.
[0123] Among them, the first semiconductor layer is a Si-doped layer, and the doping concentration of the first semiconductor layer is 0.6×10 19 cm -3 ~6.4×10 19 cm -3 。
[0124] Exemplarily, the doping concentration of the first semiconductor layer 104 is 0.8×10 19 cm -3 。
[0125] In the embodiments of the present disclosure, the light-emitting layer 105 may be a multi-quantum well barrier layer.
[0126] Exemplarily, the light-emitting layer 105 is a superlattice composed of 8 to 15 periods of In x Ga 1-x N(0.2 < x < 0.5) quantum wells / GaN (or AlGaN) quantum barriers.
[0127] Exemplarily, the second semiconductor layer 106 is a Mg-doped GaN layer.
[0128] In the embodiments of the present disclosure, the electron blocking layer 107 may be an electron blocking Al y Ga 1-y N(0.1 < y < 0.5) layer.
[0129] In the embodiment of the present disclosure, the second semiconductor layer 106 may include a high temperature P-type GaN layer and a P-type doped GaN contact layer.
[0130] By conducting an experimental comparison between the light-emitting diode provided by the embodiment of the present disclosure and the light-emitting diode provided by the related art, the data in the following Table 1 can be obtained:
[0131] Table 1
[0132]
[0133]
[0134] It can be seen from Table 1 that the voltage rise of the light emitting diode provided by the embodiment of the present disclosure is small under high current, thereby reducing power consumption under high current.
[0135] In the disclosed embodiment, the buffer layer, the nucleation layer and the leveling layer are all doped with Si, which can increase the range of current expansion and the electron channel to a certain extent, increase conductivity and reduce voltage drop. However, Si is also an impurity that will affect the overall lattice integrity and thus affect the crystal quality. Therefore, the buffer layer is doped in the latter stage, and the Si doping concentration is the lowest. The nucleation layer and the leveling layer adopt non-whole-segment doping and / or interval doping methods to reduce the impact of the overall Si doping on the deterioration of crystal quality. Since Si adopts a multi-layer doping method to make Si doping more, it has a better and smoother light power current voltage (LIV) curve characteristic, and at the same time, the impact on the overall crystal quality is controllable, thereby ensuring that the voltage rise is small under large current, that is, the characteristic of low voltage under large current, and ultimately reducing the power consumption under large current.
[0136] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.
Claims
1. A light emitting diode, characterized in that: The light emitting diode comprises: A buffer layer (101), a nucleation layer (102), a leveling layer (103), a first semiconductor layer (104), a light-emitting layer (105), and a second semiconductor layer (106) stacked in sequence; The nucleation layer (102) is a three-dimensional island structure, the buffer layer (101), the nucleation layer (102), the filling layer (103) and the first semiconductor layer (103) are all Si doped layers, wherein the buffer layer (101), the nucleation layer (102) and the filling layer (103) are all partially doped layers in the growth direction, and the doping concentration of the first semiconductor layer (104) is 0.6*10 19 cm -3 ~6.4*10 19 cm -3 .
2. The light emitting diode according to claim 1, characterized in that: The buffer layer (101) comprises an intrinsic buffer sublayer (111) and a doped buffer sublayer (112), wherein the doped buffer sublayer (112) is located between the intrinsic buffer sublayer (111) and the nucleation layer (102).
3. The light emitting diode according to claim 2, characterized in that: The doping concentration of the doped buffer sublayer (112) is 1*10 17 cm -3 ~5*10 17 cm -3 .
4. The light emitting diode according to any one of claims 1 to 3, characterized in that: The nucleation layer (102) comprises a first intrinsic nucleation sublayer (121), a doped nucleation sublayer (122) and a second intrinsic nucleation sublayer (123) which are sequentially stacked on the buffer layer (101).
5. The light emitting diode according to claim 4, characterized in that: The doping concentration of the doped nucleation sublayer (122) is 2*10 17 cm -3 ~6*10 17 cm -3 .
6. The light emitting diode according to any one of claims 1 to 3, characterized in that: The leveling layer (103) comprises a superlattice structure consisting of an intrinsic leveling sublayer (131) and a doped leveling sublayer (132) sequentially stacked on the nucleation layer (102).
7. The light emitting diode according to claim 6, characterized in that: The thickness of the intrinsic leveling sublayer (131) is 1.5 to 3 times the thickness of the doped leveling sublayer (132).
8. The light emitting diode according to claim 6, characterized in that: The filling layer (103) includes a superlattice structure with three periods.
9. The light emitting diode according to claim 8, characterized in that: In the direction from the filling layer (103) to the first semiconductor layer (103), the doping concentration of the doped filling sublayer (132) in the three-period superlattice structure is 3*10 17 cm -3 ~6*10 17 cm -3 , 5*10 17 cm -3 ~1*10 18 cm -3 , 4*10 17 cm -3 ~8*10 17 cm -3 .
10. A method for preparing a light emitting diode, characterized in that: The preparation method comprises: Making a buffer layer; Making a nucleation layer on the buffer layer, wherein the nucleation layer is a three-dimensional island structure; Making a filling layer on the nucleation layer; A first semiconductor layer, a light-emitting layer, and a second semiconductor layer are sequentially formed on the filling layer, wherein the buffer layer, the nucleation layer, the filling layer, and the first semiconductor layer are all Si-doped layers, wherein the buffer layer, the nucleation layer, and the filling layer are all partially doped layers in the growth direction, and the doping concentration of the first semiconductor layer is 0.6*10 19 cm -3 ~6.4*10 19 cm -3 .