Miniature light emitting diode chip and construction method thereof

Abstract

The invention relates to the technical field of light emitting diodes, and provides a miniature light emitting diode chip and a construction method thereof. The micro LED table top is arranged on the pixel driving back plate; the first isolation layer is arranged on the micro LED table board; and a second insulating layer disposed on the first insulating layer. According to the invention, the electric leakage rate of the chip can be effectively reduced, the output of aggregated current is reduced, and the product reliability is greatly improved. Moreover, through the N-type annular reflecting electrode with a certain angle, the light emitting efficiency of the micro light emitting diode chip can be effectively improved. In addition, the transparent conductive layer is patterned, so that the absorption of the transparent conductive layer on the emergent light of the side wall of the micro LED table top can be reduced, and the luminous efficiency is improved.

Description

Technical Field

[0001] The present invention generally relates to the field of light emitting diode (LED) technology. In particular, the present invention relates to a micro-light emitting diode (Micro-LED) chip and a method for constructing the same. Background Art

[0002] Micro-LED is an emerging display technology that miniaturizes traditional light-emitting diodes to micrometer-level size and integrates these tiny LED arrays onto a chip to form a high-density display panel. Compared with traditional light-emitting diodes (LEDs), micro-LEDs have the advantages of high brightness, high contrast, high response speed, high efficiency, long life, wide color gamut, and small size, and have been widely used.

[0003] However, traditional micro-LED chips have some deficiencies in structural design and material selection, resulting in high leakage rate and large current accumulation in the chip, which affects the reliability of the product. In addition, there is room for improvement in the luminous efficiency of traditional chip structures. For example, due to the internal structure and material properties of the chip, light will be scattered and absorbed during propagation inside the chip, resulting in a portion of the light being unable to be effectively emitted, thereby reducing the luminous efficiency. Summary of the invention

[0004] In order to at least partially solve the above problems in the prior art, the present invention provides a micro light emitting diode chip, comprising:

[0005] Pixel driver backplane;

[0006] A micro LED mesa is located on the pixel driving backplane, wherein there is a gap between adjacent micro LED mesas, and the bottom of the gap has a groove;

[0007] an insulating layer covering the micro-LED mesa, wherein the insulating layer fills the groove; and

[0008] A transparent conductive layer is located on the insulating layer, and the transparent conductive layer is electrically connected to each of the micro LED mesas.

[0009] In one embodiment of the present invention, the micro light emitting diode chip further comprises:

[0010] A metal conductive layer located between the pixel driving backplane and the micro LED table

[0011] In one embodiment of the present invention, it is provided that the metal conductive layer has at least one interface, and the interface may be an interface formed by metal bonding, or may be an interface formed by multiple metal layers, and the like.

[0012] In one embodiment of the present invention, it is provided that the groove is located in the pixel driving backplane and the metal conductive layer, and the groove corresponds to the gap between adjacent micro LED mesas.

[0013] In one embodiment of the present invention, it is provided that the isolation layer is located in the trench, and a top portion of the isolation layer in the gap is located above the trench.

[0014] In one embodiment of the present invention, it is provided that the insulating layer on the groove has a flat top.

[0015] The transparent conductive layer on the flat top of the insulating layer has a flat surface.

[0016] In one embodiment of the present invention, it is provided that the insulating layer comprises:

[0017] a first insulating layer covering the groove and the surface of the micro-LED mesas and exposing at least a portion of the top of the micro-LED mesas; and

[0018] A second insulating layer is located on the first insulating layer.

[0019] In one embodiment of the present invention, it is provided that the second insulating layer located on the groove has a flat top.

[0020] The planar surface of the transparent conductive layer is located above the planar top of the second insulating layer in the gap.

[0021] In one embodiment of the present invention, the micro light emitting diode chip further comprises:

[0022] A first electrode electrically connected to the pixel driving backplane; and

[0023] A second electrode is arranged on the flat surface of the transparent conductive layer and is electrically connected to the micro LED mesa through the transparent conductive layer.

[0024] The pixel driving backplane is provided with a plurality of metal pillars, wherein the micro LED table is located above the metal pillars, and the first electrode is electrically connected to the pixel driving backplane through the metal pillars.

[0025] In one embodiment of the present invention, it is provided that the material of the metal conductive layer includes one or more of the following: Cr, Al, Ti, Ni, Pt, Au and Sn.

[0026] In one embodiment of the present invention, it is provided that the micro LED table comprises:

[0027] A first epitaxial layer, which is located at a position close to the pixel driving backplane relative to the light emitting layer;

[0028] a light emitting layer disposed between the first epitaxial layer and the second epitaxial layer; and

[0029] The second epitaxial layer is located at a position far away from the pixel driving backplane relative to the light emitting layer, wherein the conductivity type of the first epitaxial layer is different from the conductivity type of the second epitaxial layer.

[0030] In one embodiment of the present invention, it is provided that the first epitaxial layer is of N type and the second epitaxial layer is of P type; or

[0031] The first epitaxial layer is of P type, and the second epitaxial layer is of N type.

[0032] In one embodiment of the present invention, the P-type material is a P-type GaN layer or a P-type Al GaN layer, and the N-type material is an N-type GaN layer or an N-type Al GaN layer;

[0033] The light emitting layer comprises a multi-quantum well layer and an electron blocking layer, wherein the multi-quantum well layer is an InGaN / GaN multi-quantum well layer or an InGaN / AlGaN multi-quantum well layer.

[0034] In one embodiment of the present invention, it is provided that the insulating layer is provided with an opening at a position located on the second epitaxial layer, wherein the transparent conductive layer is electrically connected to the micro LED mesas through the opening.

[0035] In one embodiment of the present invention, it is provided that the material of the first insulating layer includes one or more of the following items: Al2O3, SiO2, SIN.

[0036] In one embodiment of the present invention, it is provided that the material of the second insulating layer includes SiO2.

[0037] In one embodiment of the present invention, it is provided that the transparent conductive layer is a transparent conductive layer pattern.

[0038] In one embodiment of the present invention, it is provided that the material of the transparent conductive layer includes one or more of the following items: oxides of ITO or IN, Sn, Zn, Cd and their composite oxide thin film materials.

[0039] In one embodiment of the present invention, it is stipulated that the polarity of the first electrode is opposite to the polarity of the second electrode; the first electrode is a P-type electrode, and the second electrode is an N-type annular reflective electrode; or the first electrode is an N-type electrode, and the second electrode is a P-type annular reflective electrode; the material of the first electrode is Cr, NI, TI, NI, PT, AU metal film material or its stacked structure; the second electrode includes an electrode stack and an electrode reflective film layer arranged on the surface of the electrode stack, wherein the material of the electrode reflective film layer includes Al or Al alloy, and the material of the electrode stack includes one or more of the following items: Ni, Al, Ti, Ni, Pt and Au.

[0040] In one embodiment of the present invention, the micro light emitting diode chip further comprises:

[0041] a passivation layer covering the insulating layer, the transparent conductive layer, the first electrode and the second electrode, wherein the material of the passivation layer comprises SiO2; and

[0042] A micro lens is arranged on the passivation layer above the micro LED mesa.

[0043] In one embodiment of the present invention, it is provided that the pixel driving backplane is a pixel driving backplane on a silicon substrate, the pixel driving backplane has a pixel driving circuit therein, and the pixel driving circuit controls each micro LED table.

[0044] The present invention also provides a method for constructing a micro light emitting diode chip, comprising the following steps:

[0045] Providing a pixel driving backplane and a micro light emitting diode epitaxial wafer, and bonding the pixel driving backplane and the micro light emitting diode epitaxial wafer together, wherein the micro light emitting diode epitaxial wafer comprises a substrate and a micro light emitting diode epitaxial structure arranged on the substrate;

[0046] removing the substrate, and etching the micro light emitting diode epitaxial structure to form a plurality of micro LED mesas, wherein gaps exist between adjacent micro LED mesas;

[0047] Depositing a first insulating layer on the micro-LED mesa, and depositing a second insulating layer on the first insulating layer, wherein the second insulating layer fills the gap;

[0048] Etching the first insulating layer and the second insulating layer to expose at least a portion of the micro LED mesas, and depositing a transparent conductive layer on the second insulating layer and the exposed surface of the micro LED mesas to electrically connect the plurality of micro LED mesas;

[0049] Arranging a first electrode and a second electrode, wherein the first electrode is electrically connected to the pixel driving backplane, and the second electrode is electrically connected to the micro LED mesa through the transparent conductive layer; and

[0050] A passivation layer is deposited on the second insulating layer, the transparent conductive layer, the first electrode, and the second electrode, and a microlens is constructed on the passivation layer.

[0051] In one embodiment of the present invention, the pixel driving backplane and the micro light emitting diode epitaxial wafer are bonded together including the following steps:

[0052] Depositing a first bonding metal stack on the ohmic contact layer of the micro light emitting diode epitaxial wafer;

[0053] Depositing a second bonding metal stack on the surface of the pixel driving backplane; and

[0054] The first bonding metal stack is bonded to the second bonding metal stack to bond the pixel driving backplane and the micro light emitting diode epitaxial wafer together.

[0055] In one embodiment of the present invention, etching the micro-LED epitaxial structure to form a plurality of micro-LED mesas comprises the following steps:

[0056] Using the top of the integrated circuit copper pillar as an epitaxial etching pixel point, etching the micro light emitting diode epitaxial structure to form a plurality of micro LED mesas; and

[0057] Deep trench etching is performed between the plurality of micro LED mesas to form trenches to separate the plurality of micro LED mesas from each other.

[0058] In one embodiment of the present invention, it is provided that the micro-LED mesas are etched into a regular trapezoidal structure, and the horizontal inclination angle of the side of the regular trapezoidal structure is 65° to 85°.

[0059] In one embodiment of the present invention, it is provided that the process of etching deep trenches between the plurality of micro-LED mesas comprises: photolithography and plasma beam etching inert gas physical etching.

[0060] In one embodiment of the present invention, it is provided that depositing a first insulating layer on the micro-LED mesa comprises:

[0061] The first insulating layer is deposited on the surface of the micro LED mesas and the grooves by atomic layer deposition, and the material of the first insulating layer includes one or more of the following items: Al2O3, SiO2, and SIN.

[0062] In one embodiment of the present invention, it is provided that depositing the second insulating layer on the first insulating layer comprises the following steps:

[0063] Depositing the second insulating layer on the first insulating layer by chemical vapor deposition, wherein the deposition thickness of the second insulating layer is 3-6 um; and

[0064] The surface of the second insulating layer is thinned, wherein the distance between the surface of the second insulating layer after thinning and the surface of the micro LED table is greater than or equal to 0.3 um.

[0065] In one embodiment of the present invention, etching the first isolation layer and the second isolation layer to expose at least a portion of the micro LED mesas includes:

[0066] Plasma enhanced photolithography is performed above the micro LED mesas to etch holes in the first isolation layer and the second isolation layer, so that at least a portion of the surface of the micro LED mesas is exposed.

[0067] In one embodiment of the present invention, it is provided that a transparent conductive layer is deposited on the second insulating layer and the surface of the exposed micro-LED mesas by using a target evaporation or sputtering process.

[0068] In one embodiment of the present invention, it is provided that the transparent conductive layer is patterned to form a transparent conductive layer pattern.

[0069] In one embodiment of the present invention, it is provided that the passivation layer is deposited on the isolation layer, the transparent conductive layer, the first electrode and the second electrode by plasma enhanced chemical vapor deposition.

[0070] In one embodiment of the present invention, it is provided that the material of the passivation layer includes SiO2, and the deposition thickness of the passivation layer is 2.5-3.5 um.

[0071] In one embodiment of the present invention, it is provided that constructing a microlens on the passivation layer comprises the following steps:

[0072] Adjusting the photolithographic topography of the microlenses to form a photolithographic array topography corresponding to the position of the micro-LED mesas; and

[0073] The passivation layer is plasma etched to form the microlens.

[0074] In one embodiment of the present invention, it is provided that a secondary deposition of SiO2 is performed on the surface of the microlens to increase the overall microlens curvature radius, spacer height, lens ball height and lens ball width.

[0075] In one embodiment of the present invention, it is provided that the deposition film thickness of the SiO2 secondary deposition is determined according to the deposition thickness of the passivation layer and the lithography array morphology, wherein the deposition film thickness of the SiO2 secondary deposition is 0.2-1 um.

[0076] The present invention also provides a micro light emitting diode chip, comprising:

[0077] Pixel driver backplane;

[0078] A micro LED mesa located on the pixel driving backplane, wherein the top of each micro LED mesa has an opening; and

[0079] A transparent conductive layer pattern is located on the micro LED mesas, wherein the transparent conductive layer pattern is at least located in the opening and the transparent conductive layer patterns between adjacent micro LED mesas are interconnected, and the transparent conductive layer pattern exposes at least a portion of the surface of each micro LED mesas.

[0080] In one embodiment of the present invention, it is provided that the transparent conductive layer pattern comprises:

[0081] A first region electrically connected to the micro LED mesa through the opening; and

[0082] A series line is extended to electrically connect the plurality of first regions.

[0083] In one embodiment of the present invention, it is provided that the extended series line is integrated with the first area.

[0084] In one embodiment of the present invention, it is provided that the extended series lines form a horizontal and vertical arrangement structure.

[0085] In one embodiment of the present invention, it is provided that the intersection area of ​​the extended series lines is the first area.

[0086] In one embodiment of the present invention, it is provided that the transparent conductive layer pattern is at least located on the micro-LED table.

[0087] In one embodiment of the present invention, it is provided that the width of the extended series line is 0.3 to 1 um.

[0088] In one embodiment of the present invention, the micro light emitting diode chip further comprises:

[0089] A metal conductive layer is located between the pixel driving backplane and the micro LED table.

[0090] In one embodiment of the present invention, it is provided that the metal conductive layer has at least one interface.

[0091] In one embodiment of the present invention, the micro light emitting diode chip further comprises:

[0092] An insulating layer is located between the micro LED table and the transparent conductive layer pattern.

[0093] In one embodiment of the present invention, the insulating layer comprises: a first insulating layer, which covers the surface of the micro-LED mesas and exposes at least a portion of the top of the micro-LED mesas; and

[0094] A second insulating layer is located on the first insulating layer.

[0095] In one embodiment of the present invention, the micro light emitting diode chip further comprises:

[0096] A first electrode electrically connected to the pixel driving backplane; and

[0097] A second electrode is arranged on the flat surface of the transparent conductive layer and is electrically connected to the micro LED mesa through the transparent conductive layer.

[0098] The pixel driving backplane is provided with a plurality of metal pillars, wherein the micro LED table is located above the metal pillars, and the first electrode is electrically connected to the pixel driving backplane through the metal pillars.

[0099] In one embodiment of the present invention, it is provided that the material of the metal conductive layer includes one or more of the following: Cr, Al, Ti, Ni, Pt, Au and Sn.

[0100] In one embodiment of the present invention, it is provided that the micro LED table comprises:

[0101] A first epitaxial layer, which is located at a position close to the pixel driving backplane relative to the light emitting layer;

[0102] a light emitting layer disposed between the first epitaxial layer and the second epitaxial layer; and

[0103] The second epitaxial layer is located at a position far away from the pixel driving backplane relative to the light emitting layer, wherein the conductivity type of the first epitaxial layer is different from the conductivity type of the second epitaxial layer.

[0104] In one embodiment of the present invention, it is provided that the first epitaxial layer is of N type and the second epitaxial layer is of P type; or

[0105] The first epitaxial layer is of P type, and the second epitaxial layer is of N type.

[0106] In one embodiment of the present invention, the P-type material is a P-type GaN layer or a P-type Al GaN layer, and the N-type material is an N-type GaN layer or an N-type Al GaN layer;

[0107] The light emitting layer comprises a multi-quantum well layer and an electron blocking layer, wherein the multi-quantum well layer is an InGaN / GaN multi-quantum well layer or an InGaN / AlGaN multi-quantum well layer.

[0108] In one embodiment of the present invention, it is provided that the insulating layer is provided with an opening at a position located on the second epitaxial layer, wherein the transparent conductive layer is electrically connected to the micro LED mesas through the opening.

[0109] In one embodiment of the present invention, it is provided that the material of the first insulating layer includes one or more of the following items: Al2O3, SiO2, SIN.

[0110] In one embodiment of the present invention, it is provided that the material of the second insulating layer includes SiO2.

[0111] In one embodiment of the present invention, it is provided that the material of the transparent conductive layer pattern includes one or more of the following items: oxides of ITO or IN, Sn, Zn, Cd and composite oxide thin film materials thereof.

[0112] In one embodiment of the present invention, it is stipulated that the polarity of the first electrode is opposite to the polarity of the second electrode; the first electrode is a P-type electrode, and the second electrode is an N-type annular reflective electrode; or the first electrode is an N-type electrode, and the second electrode is a P-type annular reflective electrode; the material of the first electrode is Cr, NI, TI, NI, PT, AU metal film material or its stacked structure; the second electrode includes an electrode stack and an electrode reflective film layer arranged on the surface of the electrode stack, wherein the material of the electrode reflective film layer includes Al or Al alloy, and the material of the electrode stack includes one or more of the following items: Ni, Al, Ti, Ni, Pt and Au.

[0113] In one embodiment of the present invention, the micro light emitting diode chip further comprises:

[0114] a passivation layer covering the insulating layer, the transparent conductive layer, the first electrode and the second electrode, wherein the material of the passivation layer comprises SiO2; and

[0115] A micro lens is arranged on the passivation layer above the micro LED mesa.

[0116] In one embodiment of the present invention, it is provided that the pixel driving backplane is a pixel driving backplane on a silicon substrate, the pixel driving backplane has a pixel driving circuit therein, and the pixel driving circuit controls each micro LED table.

[0117] The present invention also provides a method for constructing a micro light emitting diode chip, comprising the following steps:

[0118] Providing a pixel driving backplane and a micro light emitting diode epitaxial wafer, and bonding the pixel driving backplane and the micro light emitting diode epitaxial wafer together, wherein the micro light emitting diode epitaxial wafer comprises a substrate and a micro light emitting diode epitaxial structure arranged on the substrate;

[0119] removing the substrate, and etching the micro light emitting diode epitaxial structure to form a plurality of micro LED mesas;

[0120] Depositing a first insulating layer on the micro-LED mesa, and depositing a second insulating layer on the first insulating layer;

[0121] Etching the first insulating layer and the second insulating layer to expose at least a portion of the micro LED mesas, and depositing a transparent conductive layer on the second insulating layer and the exposed surface of the micro LED mesas to electrically connect the plurality of micro LED mesas;

[0122] Performing patterning on the transparent conductive layer to form a patterned transparent conductive layer;

[0123] Arranging a first electrode and a second electrode, wherein the first electrode is electrically connected to the pixel driving backplane, and the second electrode is electrically connected to the micro LED mesa through the patterned transparent conductive layer;

[0124] A passivation layer is deposited on the second insulating layer, the patterned transparent conductive layer, the first electrode and the second electrode, and a microlens is constructed on the passivation layer. The present invention has at least the following beneficial effects: The present invention proposes a micro light-emitting diode chip and a construction method thereof, wherein at least a portion of the gaps between a plurality of micro-LED countertops is filled by an insulating layer, so that the transparent conductive layer arranged thereon can form a transparent conductive layer connection surface, and avoid excessive bending of the transparent conductive layer to cause leakage, which can effectively reduce the chip leakage rate, reduce the output of the concentrated current, and greatly improve the product reliability. Moreover, it can effectively improve the luminous efficiency of the micro light-emitting diode chip through an N-type annular reflective electrode with a certain angle. In addition, by patterning the transparent conductive layer, it can reduce the absorption of the light emitted from the side wall of the micro-LED countertop by the transparent conductive layer, thereby improving the luminous efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0125] To further illustrate the advantages and features of various embodiments of the present invention, a more detailed description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings only depict typical embodiments of the present invention and are therefore not to be considered as limiting the scope thereof. In the accompanying drawings, for clarity, identical or corresponding parts will be represented by identical or similar reference numerals.

[0126] Figure 1 A schematic structural diagram of a micro light emitting diode chip in the first embodiment of the present invention is shown.

[0127] Figure 2 A front schematic diagram of a micro light emitting diode chip in the first embodiment of the present invention is shown.

[0128] Figure 3 A schematic flow chart of a method for constructing a micro light emitting diode chip in a first embodiment of the present invention is shown.

[0129] Figure 4 A schematic diagram of a second insulating layer obtained by deposition in the first embodiment of the present invention is shown.

[0130] Figure 5 A schematic diagram of a thinned second insulating layer in the first embodiment of the present invention is shown.

[0131] Figure 6 A schematic structural diagram of a micro light emitting diode chip in a second embodiment of the present invention is shown.

[0132] Figure 7 A front schematic diagram of a micro light emitting diode chip in a second embodiment of the present invention is shown.

[0133] Figure 8 A schematic flow chart of a method for constructing a micro light emitting diode chip in a second embodiment of the present invention is shown.

[0134] Fig. 9 A schematic diagram of a second insulating layer obtained by deposition in the second embodiment of the present invention is shown.

[0135] Fig.10 A schematic diagram of a thinned second insulating layer in the second embodiment of the present invention is shown.

[0136] Fig.11 A schematic diagram of an etched second isolation layer in the second embodiment of the present invention is shown. DETAILED DESCRIPTION

[0137] It should be noted that the components in the figures may be shown exaggeratedly for the sake of illustration and are not necessarily true to scale. In the figures, identical or functionally identical components are provided with the same reference numerals.

[0138] In the present invention, unless otherwise specified, "arranged on...", "arranged above..." and "arranged above..." do not exclude the existence of an intermediate between the two. In addition, "arranged on or above..." merely indicates the relative positional relationship between two components, and in certain cases, such as after reversing the product direction, it can also be converted into "arranged below or below...", and vice versa.

[0139] In the present invention, each embodiment is only intended to illustrate the aspects of the present invention and should not be construed as limiting.

[0140] In the present invention, unless otherwise specified, the quantifiers "a", "an" and "an" do not exclude the presence of a plurality of elements.

[0141] It should also be noted that in the embodiments of the present invention, for the sake of clarity and simplicity, only a portion of the parts or components may be shown, but those of ordinary skill in the art will understand that under the teachings of the present invention, the required parts or components may be added according to the needs of the specific scenario. In addition, unless otherwise specified, the features in different embodiments of the present invention may be combined with each other. For example, a feature in the second embodiment may be used to replace a corresponding or functionally identical or similar feature in the first embodiment, and the resulting embodiment also falls within the disclosure scope or recorded scope of the present application.

[0142] It should also be noted that within the scope of the present invention, the terms "same", "equal", "equal to" and the like do not mean that the values ​​of the two are absolutely equal, but allow a certain reasonable error, that is, the terms also cover "substantially the same", "substantially equal", "substantially equal to". By analogy, in the present invention, the terms "perpendicular to", "parallel to" and the like indicating directions also cover the meanings of "substantially perpendicular to" and "substantially parallel to".

[0143] In addition, the numbering of the steps of the methods of the present invention does not limit the execution order of the method steps. Unless otherwise specified, the method steps can be executed in different orders.

[0144] In a first embodiment of the present invention, a micro-LED chip is provided, wherein the size of each micro-LED chip does not exceed 1 cm, preferably does not exceed 20 μm. The micro-LED structure is formed in the micro-LED chip in an array form, with a resolution of, for example, 720*480, 640*480, 1920*1080, 1280*720, 2K or 4K. The diameter of the micro-LED structure is at the nanometer level, for example, 20 nm to 100 nm.

[0145] The micro-LED chip includes an integrated circuit (IC) backplane and a micro-LED array. The micro-LED array includes a plurality of micro-LEDs. Each micro-LED can form at least a portion of a pixel element on the micro-LED chip.

[0146] In some embodiments, the IC backplane can be electrically connected to each micro-LED in the micro-LED array via a separate metal interconnect. In some embodiments, each micro-LED can be electrically controlled individually by the IC backplane. In some embodiments, the IC backplane can be electrically connected to the electrodes of the micro-LED chip via metal interconnects. In some embodiments, a dielectric layer can be formed in the gaps between the micro-LEDs. In some embodiments, a dielectric layer can also be formed in the gaps between the interconnects.

[0147] In some embodiments, each micro-light emitting diode in the micro-light emitting diode array may include a micron-scale mesa structure. In some embodiments, the micron-scale mesa structure may include a first type epitaxial layer, a light emitting layer, and a second type epitaxial layer from bottom to top. That is, in the three-layer structure, the first type epitaxial layer is closest to the IC backplane; the light emitting layer is located above the first type epitaxial layer and is further away from the IC backplane; the second type epitaxial layer is located above the light emitting layer and is farthest away from the IC backplane. In some embodiments, the light emitting layer is formed by a plurality of stacked quantum well layers, in particular superlattice stacked quantum well layers. Preferably, the superlattice stacked quantum well layer includes a plurality of pairs of quantum well layers stacked with quantum barrier layers. In some embodiments, the first type epitaxial layer is a semiconductor material having a first conductivity type and includes a plurality of semiconductor layers. The main matrix material of the first type epitaxial layer may be, but is not limited to, composed of materials such as Ga, N, As, P, In or Al. In addition, the first type epitaxial layer may include, from top to bottom, but is not limited to, a waveguide layer, a confinement layer, a transition layer, and a window layer; in addition, an ohmic contact layer may be formed below the window layer. In some embodiments, the second epitaxial layer is a semiconductor material having a second conductivity type and includes a plurality of semiconductor layers. The main matrix material of the second epitaxial layer may be, but is not limited to, Ga, N, As, P, In or Al. In addition, the first epitaxial layer may include, from top to bottom, but is not limited to, a confinement layer and a waveguide layer; in addition, in some embodiments, an ohmic contact layer may be formed on the confinement layer.

[0148] In some embodiments, a top conductive layer may be formed on the top surface of the micro-LED array. In some embodiments, the top conductive layer may be shared by all micro-LEDs in the micro-LED array. In some embodiments, the light-emitting layer may include at least one quantum well layer. In some embodiments, the micro-LED array may include a single-layer micro-LED structure. In some embodiments, the micro-LED array may include multiple layers of vertically stacked micro-LED structures.

[0149] In some embodiments, the micro-LED array may include blue micro-LEDs. In some embodiments, the pitch of the micro-LED array, i.e., the minimum center-to-center distance between the micro-LEDs, may be between about 2 microns and about 50 microns. In some embodiments, the number of pixels on the micro-LED chip may be between thousands and millions.

[0150] The present invention will be further described below in conjunction with specific embodiments with reference to the accompanying drawings.

[0151] Figure 1 A schematic structural diagram of a micro light emitting diode chip in the first embodiment of the present invention is shown. Figure 2 FIG. 2 shows a schematic front view of a micro-LED chip in the first embodiment of the present invention. Figure 1 and Figure 2 As shown, the micro light emitting diode chip includes: an integrated circuit (IC) driving backplane 101, a metal conductive layer 102, a micro LED table 103, a first insulating layer 104, a second insulating layer 105, a transparent conductive layer 106, a first electrode 107, a second electrode 108, a passivation layer 109 and a micro lens 110.

[0152] The pixel driving backplane 101 is provided with a plurality of integrated circuit copper pillars 111. The pixel driving backplane 101 is a pixel driving backplane on a silicon substrate, wherein the pixel driving backplane 101 has a pixel driving circuit therein, and the pixel driving circuit controls each micro LED table.

[0153] The metal conductive layer 102 is arranged between the pixel driving backplane 101 and the micro LED mesas 103 to bond the pixel driving backplane 101 and the micro LED mesas 103 together. The pixel driving backplane 101 and the metal bonding layer 102 are provided with grooves at positions corresponding to the gaps between adjacent micro LED mesas 103.

[0154] The metal conductive layer 102 is formed by bonding multiple metal stacks at high temperature and high pressure, and its material can be metal materials such as Cr, Al, Ti, Ni, Pt, Au, Sn, etc. The metal conductive layer 102 has at least one interface, which is an interface formed by metal bonding, or an interface formed by multiple metal layers.

[0155] The micro LED table 103 is located above the integrated circuit copper pillar 111, and the micro LED table 103 includes a first epitaxial layer 1031, a light emitting layer 1032, and a second epitaxial layer 1033, wherein the first epitaxial layer 1031 is located at a position close to the pixel driving backplane 101 relative to the light emitting layer 1032, the light emitting layer 1032 is arranged between the first epitaxial layer 1031 and the second epitaxial layer 1033, and the second epitaxial layer 1033 is located at a position far away from the pixel driving backplane 101 relative to the light emitting layer 1032. The first epitaxial layer 1031 is a P-type GaN layer or a P-type Al GaN layer, and the second epitaxial layer 1033 is an N-type GaN layer or an N-type Al GaN layer. The light emitting layer 1032 includes a multi-quantum well layer and an electron blocking layer, wherein the multi-quantum well layer is an InGaN / GaN multi-quantum well layer or an InGaN / Al GaN multi-quantum well layer. There are gaps between adjacent micro LED tables 103 , so that the multiple micro LED tables 103 are separated from each other to form multiple pixel points of the micro light emitting diode chip.

[0156] The first insulating layer 104 covers the surface of the groove and the micro LED table 103, but at least partially exposes the second epitaxial layer 1033, wherein the material of the first insulating layer 104 includes one or more of the following items: Al2O3, SiO2, SIN, and Al2O3 deposition is preferred, which can effectively reduce the leakage rate of the chip.

[0157] The second insulating layer 105 is arranged on the first insulating layer 104, wherein the second insulating layer 105 fills the groove and forms a gap insulating layer surface above the groove, wherein the gap insulating layer surface is a plane, concave, convex or irregular surface. The material of the second insulating layer 105 includes SiO2.

[0158] The transparent conductive layer 106 is arranged on the surface of the second insulating layer 104 and the second epitaxial layer 1033, wherein the plurality of micro LED mesas 103 are electrically connected through the transparent conductive layer 106. The portion of the transparent conductive layer 106 arranged on the surface of the insulating layer at the gap forms a transparent conductive layer connection surface, wherein the transparent conductive layer connection surface is a plane, a concave surface, a convex surface or an irregular surface.

[0159] The material of the transparent conductive layer includes one or more of the following: oxides of ITO or IN, Sn, Zn, Cd and their composite oxide thin film materials.

[0160] The first electrode 107 is electrically connected to the pixel driving backplane 101 through the integrated circuit copper pillar 111 , and the second electrode 108 is arranged on the transparent conductive layer connection surface and is electrically connected to the micro LED table 103 through the transparent conductive layer 106 .

[0161] The polarity of the first electrode 107 is opposite to that of the second electrode 108, wherein the first electrode 107 is a P-type electrode, and the second electrode 108 is an N-type annular reflective electrode. The N-type annular reflective electrode with a certain angle can effectively improve the luminous efficiency of the micro-LED chip. The material of the first electrode 107 includes one or more of the following items: magnetron sputtering or evaporation can be used, and the film material Cr, NI, TI, NI, PT, AU metal or its laminated structure can be selected. The second electrode 108 includes an electrode stack and an electrode reflective film layer arranged on the surface of the electrode stack, wherein the material of the electrode reflective film layer includes Al or Al alloy, and the material of the electrode stack includes one or more of the following items: Ni, Al, Ti, Ni, Pt and Au.

[0162] The passivation layer 109 is arranged on the first insulating layer 104 , the second insulating layer 105 , the transparent conductive layer 106 , the first electrode 107 and the second electrode 108 . The material of the passivation layer 109 may be SiO 2 .

[0163] The micro lens 110 is formed on the passivation layer 109 and located above the micro LED mesa 103 .

[0164] Figure 3 FIG. 2 is a flow chart showing a method for constructing a micro-LED chip in accordance with a first embodiment of the present invention. Figure 3 As shown, the method comprises the following steps:

[0165] Step 301: provide a pixel driving backplane 101 and a micro-LED epitaxial wafer, and bond the pixel driving backplane 101 and the micro-LED epitaxial wafer together, wherein the micro-LED epitaxial wafer includes a substrate and a micro-LED epitaxial structure arranged on the substrate.

[0166] Step 302: remove the substrate, and etch the micro-LED epitaxial structure to form a plurality of micro-LED mesas 103, wherein there are gaps between adjacent micro-LED mesas 103. Step 303: deposit a first insulating layer 104 on the micro-LED mesas 103, and deposit a second insulating layer 105 on the first insulating layer 104, wherein the second insulating layer 104 fills the gaps.

[0167] Step 304 , etching the first insulating layer 104 and the second insulating layer 105 to expose at least a portion of the micro LED mesas 103 , and depositing a transparent conductive layer 106 on the surface of the second insulating layer 105 and the exposed micro LED mesas 103 to electrically connect the plurality of micro LED mesas 103 .

[0168] Step 305 , arranging a first electrode 107 and a second electrode 108 , wherein the first electrode 107 is electrically connected to the pixel driving backplane 101 , and the second electrode 108 is electrically connected to the micro LED mesa 103 through the transparent conductive layer 106 .

[0169] Step 306 : depositing a passivation layer 109 on the second insulating layer 105 , the transparent conductive layer 106 , the first electrode 107 , and the second electrode 108 , and forming a microlens 110 on the passivation layer 109 .

[0170] The following describes in detail each step of the method.

[0171] In step 301, a pixel driving backplane 101 and a micro-LED epitaxial layer are first provided. The micro-LED epitaxial layer includes a substrate and a micro-LED epitaxial structure arranged on the substrate. The LED epitaxial structure includes a first epitaxial layer 1031, a light-emitting layer 1032 and a second epitaxial layer 1033, wherein the second epitaxial layer 1033 is arranged on the substrate, the light-emitting layer 1032 is arranged on the second epitaxial layer, the first epitaxial layer 1031 is arranged on the light-emitting layer 1032, and an ohmic contact layer is provided on the first epitaxial layer. The ohmic contact layer can be an indium tin oxide (ITO) transparent conductive layer or a transparent conductive layer of other materials. A plurality of integrated circuit (IC) copper pillars 111 are provided on the pixel driving backplane 101.

[0172] Furthermore, the pixel driving backplane 101 and the micro-LED epitaxial layer are bonded together, wherein a first bonding metal stack is deposited on the ohmic contact layer of the micro-LED epitaxial layer by evaporation or other methods, and a second bonding metal stack is deposited on the surface of the pixel driving backplane 101 by evaporation or other methods, and the first bonding metal stack is bonded to the second bonding metal stack by high temperature and high pressure bonding to form a metal conductive layer 102, so as to bond the pixel driving backplane 101 and the micro-LED epitaxial layer together. The material of the bonding metal stack can be metal materials such as Cr, Al, Ti, Ni, Pt, Au, Sn, etc.

[0173] In step 302, the substrate is first removed, wherein the substrate is removed by grinding and thinning, or by laser stripping, and the specific removal method can be adjusted according to the material of the substrate (the material of the substrate can be sapphire, silicon-based, etc.). After removing the substrate, the epitaxial buffer layer structure can be further thinned for subsequent etching.

[0174] Furthermore, the light-emitting diode epitaxial structure is plasma etched to form a plurality of micro LED mesas 103, wherein the etching point above the integrated circuit (IC) copper pillar 111 can be used as an epitaxial etching pixel point, and the light-emitting diode epitaxial structure is plasma etched to form a plurality of micro LED mesas 103, and the etched micro LED mesas 103 are located above the integrated circuit (IC) copper pillar 111, wherein the micro LED mesas 103 are etched into a regular trapezoidal structure by adjusting the photolithography morphology, and the horizontal inclination angle of the side of the regular trapezoidal structure is 65° to 85°, and each micro LED mesas 103 can be used as a pixel point of a micro light-emitting diode array.

[0175] Furthermore, deep groove etching is performed between the plurality of micro LED mesas 103 to separate the plurality of micro LED mesas 103 from each other, so that the pixel driving backplane 101 and the metal conductive layer 102 located between the plurality of micro LED mesas 103 are exposed. The deep groove etching can be performed by etching processes such as photolithography, plasma beam etching (IBE), inert gas physical etching, etc.

[0176] The micro LED table 103 obtained by etching includes a first epitaxial layer 1031, a light-emitting layer 1032 and a second epitaxial layer 1033, wherein the first epitaxial layer 1031 is located at a position close to the pixel driving backplane 101 relative to the light-emitting layer 1032, the light-emitting layer 1032 is arranged between the first epitaxial layer 1031 and the second epitaxial layer 1033, and the second epitaxial layer 1033 is located at a position far away from the pixel driving backplane 101 relative to the light-emitting layer 1032. The first epitaxial layer 1031 is a P-type GaN layer or a P-type Al GaN layer, and the second epitaxial layer 1033 is an N-type GaN layer or an N-type Al GaN layer. The light-emitting layer 1032 includes a multi-quantum well layer and an electron blocking layer, wherein the multi-quantum well layer is an InGaN / GaN multi-quantum well layer or an InGaN / Al GaN multi-quantum well layer.

[0177] In step 303, a first insulating layer 104 is first deposited on the micro LED table 103, wherein the first insulating layer 104 can be covered on the micro LED table 103 and the pixel driving backplane 101 and the metal conductive layer 102 exposed by deep groove etching by atomic layer deposition (ALD). The first insulating layer 104 can be made of Al2O3, SiO2, SIN, preferably ALD deposited Al2O3 thin film.

[0178] Furthermore, a second insulating layer 105 is deposited on the first insulating layer 104 to thicken the film. The second insulating layer 105 has a film thickness of 3-6 um, and the first insulating layer 104 can be made of SiO2, wherein the deposition of the second insulating layer 105 is usually completed by chemical vapor deposition (CVD).

[0179] Figure 4 FIG. 2 shows a schematic diagram of a second insulating layer obtained by deposition in the first embodiment of the present invention. Figure 4 As shown, since the micro LED table 103, the pixel driving backplane 101 and the metal conductive layer 102 are stepped after deep groove etching, the surface of the deposited second isolation layer 105 will be uneven, so it is necessary to use chemical mechanical polishing (CMP) and other processes to thin the surface of the second isolation layer 105. Figure 5 FIG. 2 shows a schematic diagram of a thinned second insulating layer in the first embodiment of the present invention. Figure 5 As shown, the second insulating layer 105 after thinning needs to have a certain thickness reserved, wherein the distance between the surface of the second insulating layer 105 after thinning and the surface of the second epitaxial layer 1033 of the micro LED table 103 is greater than or equal to 0.3um. By setting the first insulating layer 104 and the second insulating layer 105, the output of the concentrated current can be effectively reduced, greatly improving the reliability of the product.

[0180] In step 304, the first insulating layer 104 and the second insulating layer 105 are first etched to expose at least a portion of the micro LED table 103, wherein plasma enhanced (PA) lithography is performed above the micro LED table 103 to etch the first insulating layer 104 and the second insulating layer 105 to form openings, so that at least a portion of the surface of the second epitaxial layer 1033 of the micro LED table 103 is exposed, and a transparent conductive layer 106 is deposited on the exposed surface of the second epitaxial layer 1033 and on the surface of the second insulating layer to electrically connect the plurality of micro LED table tops 103.

[0181] In step 305, a first electrode 107 and a second electrode 108 are arranged, wherein the first electrode 107 is electrically connected to the pixel driving backplane 101, and the second electrode 108 is electrically connected to the micro LED table 103 through the transparent conductive layer 106. The polarity of the second electrode 108 is opposite to that of the first electrode 107, wherein the first electrode 107 is a P-type electrode, and the second electrode 108 is an N-type annular reflective electrode. The first electrode 107 can be connected to the integrated circuit copper pillar 111 reserved on the pixel driving backplane 101, which plays a role in protecting the pad height and facilitating subsequent wiring. The second electrode 108 can be arranged around the micro LED table 104 by magnetron sputtering or evaporation. The electrode film material of the second electrode 108 is preferably Al or Al alloy metal as the side wall reflector, and the electrode stack metal can be Ni, Al, Ti, Ni, Pt, Au and other metal materials.

[0182] In step 306, a passivation layer 109 is deposited on the second insulating layer 105, the transparent conductive layer 106, the first electrode 107 and the second electrode 108, and a microlens (LENS) 110 is constructed on the passivation layer 109. The microlens is constructed on the pixel point located on the microLED table 103, and after the step etching at the microLED table 103 is completed, the deep groove etching around the pixel point is completed, the first insulating layer 104, the second insulating layer 105, the transparent conductive layer 106, the first electrode 107 and the second electrode 108 are prepared, the passivation layer 109 is deposited on the wafer by plasma enhanced chemical vapor deposition (PECVD), and the material of the passivation layer 109 can be SiO2, and the deposition thickness is 2.5-3.5um. Furthermore, by adjusting the photolithographic morphology of the microlens (for example, adjusting the photolithographic resin thickness, exposure energy and hardening temperature) to form a photolithographic array morphology corresponding to the position of the micro LED table 103, the passivation layer 109 is plasma etched to form a hemispherical S IO2 microlens 110 in a lens-like shape. The microlens 110 can improve the light extraction efficiency of the micro light emitting diode chip to a certain extent.

[0183] Furthermore, after the microlens 110 is formed, due to the limitations of the microlens photolithography size and plasma etching process, the curvature radius, spacer height, ball height, and lens ball width of the overall microlens are all relatively small. Therefore, a second SiO2 deposition can be performed on the microlens 110 to increase the microlens curvature radius, spacer height, ball height, and lens ball width. The film thickness of the second SiO2 deposition needs to be determined based on the SiO2 film thickness of the first deposition and the photolithography morphology of the microlens. The usual deposition thickness is 0.2-1um, which can be completed by single or multiple depositions.

[0184] Figure 6 A schematic structural diagram of a micro light emitting diode chip in a second embodiment of the present invention is shown. Figure 7 FIG. 2 shows a schematic front view of a micro-LED chip in the second embodiment of the present invention. Figure 6 and Figure 7 As shown, the micro-LED chip includes: a pixel driving backplane 101, a metal conductive layer 102, a micro-LED table 103, a first insulating layer 104, a second insulating layer 105, a transparent conductive layer 106, a first electrode 107, a second electrode 108, a passivation layer 109 and a microlens 110. Compared with the chip in the first embodiment, most of the structures of this chip are basically the same, and will not be repeated here. The difference between the second embodiment and the first embodiment is that

[0185] The transparent conductive layer 106 is patterned to form a transparent conductive layer pattern to reduce the absorption of the light emitted by the micro LED table 103 by the transparent conductive layer 106. Traditionally, the transparent conductive layer 106 is usually covered on the top of the micro LED table 103. Although the transparent conductive layer 106 has relatively good light transmittance, it also has obvious light absorption, which will cause the side wall of the micro LED table 103 to lose some light efficiency when emitting light. In this embodiment, the transparent conductive layer 106 is patterned to reduce the coverage area of ​​the transparent conductive layer 106, thereby reducing its absorption of the light emitted by the side wall of the micro LED table 103 and increasing the light extraction efficiency.

[0186] Each micro LED table 103 has an opening at the top, and the transparent conductive layer pattern is located on the micro LED table 103, wherein the transparent conductive layer pattern is at least located within the opening and the transparent conductive layer patterns between adjacent micro LED tables 1-3 are interconnected, and the transparent conductive layer pattern exposes at least a portion of the surface of each micro LED table 103.

[0187] Preferably, it can be Figure 7 As shown, after the patterning process, the transparent conductive layer 106 only includes a first region electrically connected to the surface of the second epitaxial layer 1033 of the micro LED table 103 and an extended series line connecting a plurality of the first regions. In some embodiments, the extended series line is integrated with the first region. In some embodiments, the extended series line forms a horizontal and vertical arrangement structure. In some embodiments, the intersection area of ​​the extended series line is the first region. In some embodiments, the transparent conductive layer pattern is at least located on the micro LED table. In some embodiments, the width of the extended series line ranges from 0.3 to 1 um.

[0188] Figure 8 FIG. 2 is a flow chart showing a method for constructing a micro-LED chip in accordance with a second embodiment of the present invention. Figure 8 As shown, the method comprises the following steps:

[0189] Step 801, provide a pixel driving backplane 101 and a micro light emitting diode epitaxial wafer, and bond the pixel driving backplane 101 and the micro light emitting diode epitaxial wafer together, wherein the micro light emitting diode epitaxial wafer includes a substrate and a micro light emitting diode epitaxial structure arranged on the substrate.

[0190] Step 802 : removing the substrate, and etching the micro-LED epitaxial structure to form a plurality of micro-LED mesas 103 .

[0191] Step 803 : depositing a first isolation layer 104 on the micro LED mesas 103 , and depositing a second isolation layer 105 on the first isolation layer 104 .

[0192] Step 804 , etching the first insulating layer 104 and the second insulating layer 105 to expose at least a portion of the micro LED mesas 103 , and depositing a transparent conductive layer 106 on the surface of the second insulating layer 105 and the exposed micro LED mesas 103 to electrically connect the plurality of micro LED mesas 103 .

[0193] Step 805 , performing patterning on the transparent conductive layer 106 to reduce absorption of the light emitted by the micro LED mesa 103 by the transparent conductive layer 106 .

[0194] Step 806 , arranging a first electrode 107 and a second electrode 108 , wherein the first electrode 107 is electrically connected to the pixel driving backplane 101 , and the second electrode 108 is electrically connected to the micro LED mesa 103 through the transparent conductive layer 106 .

[0195] Step 807 : depositing a passivation layer 109 on the second insulating layer 105 , the transparent conductive layer 106 , the first electrode 107 , and the second electrode 108 , and forming a microlens 110 on the passivation layer 109 .

[0196] The following describes in detail each step of the method.

[0197] In step 801, a pixel driving backplane 101 and a micro-LED epitaxial layer are first provided. The micro-LED epitaxial layer includes a substrate and a micro-LED epitaxial structure arranged on the substrate. The LED epitaxial structure includes a first epitaxial layer 1031, a light-emitting layer 1032 and a second epitaxial layer 1033, wherein the second epitaxial layer 1033 is arranged on the substrate, the light-emitting layer 1032 is arranged on the second epitaxial layer, the first epitaxial layer 1031 is arranged on the light-emitting layer 1032, and an ohmic contact layer is provided on the first epitaxial layer. The ohmic contact layer can be an indium tin oxide (ITO) transparent conductive layer or a transparent conductive layer of other materials. A plurality of integrated circuit (IC) copper pillars 111 are provided on the pixel driving backplane 101.

[0198] Furthermore, the pixel driving backplane 101 and the micro-LED epitaxial layer are bonded together, wherein a first bonding metal stack is deposited on the ohmic contact layer of the micro-LED epitaxial layer by evaporation or other methods, and a second bonding metal stack is deposited on the surface of the pixel driving backplane 101 by evaporation or other methods, and the first bonding metal stack is bonded to the second bonding metal stack by high temperature and high pressure bonding to form a metal conductive layer 102, so as to bond the pixel driving backplane 101 and the micro-LED epitaxial layer together. The material of the bonding metal stack can be metal materials such as Cr, Al, Ti, Ni, Pt, Au, Sn, etc.

[0199] In step 802, the substrate is first removed, wherein the substrate is removed by grinding and thinning, or by laser stripping, and the specific removal method can be adjusted according to the material of the substrate (the material of the substrate can be sapphire, silicon-based, etc.). After removing the substrate, the epitaxial buffer layer structure can be further thinned for subsequent etching.

[0200] Further, the light-emitting diode epitaxial structure is plasma etched to form a plurality of micro LED mesas 103, wherein the etching point above the integrated circuit (IC) copper pillar 111 can be used as an epitaxial etching pixel point, and the light-emitting diode epitaxial structure is plasma etched to form a plurality of micro LED mesas 103, and the etched micro LED mesas 103 are located above the integrated circuit (IC) copper pillar 111, wherein the micro LED mesas 103 are etched into a regular trapezoidal structure by adjusting the photolithography morphology, and the horizontal inclination angle of the side of the regular trapezoidal structure is 65° to 85°, and each micro LED mesas 103 can be used as a pixel point of a micro light-emitting diode array.

[0201] Furthermore, deep groove etching is performed between the plurality of micro LED mesas 103 to separate the plurality of micro LED mesas 103 from each other, so that the pixel driving backplane 101 and the metal conductive layer 102 located between the plurality of micro LED mesas 103 are exposed. The deep groove etching can be performed by etching processes such as photolithography, plasma beam etching (IBE), inert gas physical etching, etc.

[0202] The micro LED table 103 obtained by etching includes a first epitaxial layer 1031, a light-emitting layer 1032 and a second epitaxial layer 1033, wherein the first epitaxial layer 1031 is located at a position close to the pixel driving backplane 101 relative to the light-emitting layer 1032, the light-emitting layer 1032 is arranged between the first epitaxial layer 1031 and the second epitaxial layer 1033, and the second epitaxial layer 1033 is located at a position far away from the pixel driving backplane 101 relative to the light-emitting layer 1032. The first epitaxial layer 1031 is a P-type GaN layer or a P-type Al GaN layer, and the second epitaxial layer 1033 is an N-type GaN layer or an N-type Al GaN layer. The light-emitting layer 1032 includes a multi-quantum well layer and an electron blocking layer, wherein the multi-quantum well layer is an InGaN / GaN multi-quantum well layer or an InGaN / Al GaN multi-quantum well layer.

[0203] In step 803, a first insulating layer 104 is first deposited on the micro LED table 103, wherein the first insulating layer 104 can be covered on the micro LED table 103 and the pixel driving backplane 101 and the metal conductive layer 102 exposed by deep groove etching by atomic layer deposition (ALD), and the first insulating layer 104 can be made of Al2O3, SiO2, or SIN.

[0204] Furthermore, a second insulating layer 105 is deposited on the first insulating layer 104 to thicken the film. The second insulating layer 105 has a film thickness of 3-6 um, and the first insulating layer 104 can be made of SiO2, wherein the deposition of the second insulating layer 105 is usually completed by chemical vapor deposition (CVD).

[0205] Fig. 9 FIG. 2 shows a schematic diagram of a second insulating layer obtained by deposition in another embodiment of the present invention. Fig. 9 As shown, since the micro LED table 103, the pixel driving backplane 101 and the metal conductive layer 102 are stepped after deep groove etching, the surface of the deposited second isolation layer 105 will be uneven, so it is necessary to use chemical mechanical polishing (CMP) and other processes to thin the surface of the second isolation layer 105. Fig.10 FIG. 2 shows a schematic diagram of a thinned second insulating layer in another embodiment of the present invention. Fig.10 As shown, the second insulating layer 105 after thinning needs to have a certain thickness reserved, wherein the distance between the surface of the second insulating layer 105 after thinning and the surface of the second epitaxial layer 1033 of the micro LED table 103 is greater than or equal to 0.3um. By setting the first insulating layer 104 and the second insulating layer 105, the output of the concentrated current can be effectively reduced, greatly improving the reliability of the product.

[0206] In step 804 , the first isolation layer 104 and the second isolation layer 105 are firstly etched to expose at least a portion of the micro LED mesas 103 . Fig.11 FIG. 2 shows a schematic diagram of a second insulating layer after etching in the second embodiment of the present invention. Fig.11 As shown, a photoresist can be used to set a photolithography pattern with a certain chamfer in the area for setting the second electrode 108 between the plurality of micro LED mesas 103 to form an inverted trapezoidal structure, and the redundant second insulating layer 105 is removed by plasma etching with an etching thickness of 0.5-1um.

[0207] Further, plasma enhanced (PA) lithography is performed above the micro LED mesas 103 to etch holes in the first insulating layer 104 and the second insulating layer 105, so that at least a portion of the surface of the second epitaxial layer 1033 of the micro LED mesas 103 is exposed, and a transparent conductive layer 106 is deposited on the exposed surface of the second epitaxial layer 1033 and the surface of the second insulating layer by evaporation or sputtering to electrically connect the plurality of micro LED mesas 103. The material of the transparent conductive layer 106 includes: ITO or IN, Sn, Zn, Cd oxides and composite oxide thin film materials.

[0208] In step 805, the transparent conductive layer 106 is patterned to reduce the absorption of the light emitted by the micro LED table 103 by the transparent conductive layer 106. Traditionally, the transparent conductive layer 106 is usually covered on the top of the micro LED table 103. Although the transparent conductive layer 106 has relatively good light transmittance, it also has obvious light absorption, which will cause the side wall of the micro LED table 103 to lose some light efficiency when emitting light. In this embodiment, the transparent conductive layer 106 can be patterned to reduce the coverage area of ​​the transparent conductive layer 106, thereby reducing its absorption of the light emitted by the side wall of the micro LED table 103 and increasing the light extraction efficiency. Preferably, it can be as follows Figure 7 As shown, after the patterning process, the transparent conductive layer 106 only includes an ohmic contact region electrically connected to the surface of the second epitaxial layer 1033 of the micro LED table 103 and an extended series line connecting multiple ohmic contact regions, wherein the width of the extended series line ranges from 0.3 to 1 um.

[0209] In step 806, a first electrode 107 and a second electrode 108 are arranged, wherein the first electrode 107 is electrically connected to the pixel driving backplane 101, and the second electrode 108 is electrically connected to the micro LED table 103 through the transparent conductive layer 106. The polarity of the second electrode 108 is opposite to that of the first electrode 107, wherein the first electrode 107 is a P-type electrode, and the second electrode 108 is an N-type annular reflective electrode. The first electrode 107 can be connected to the integrated circuit copper pillar 111 reserved on the pixel driving backplane 101, which plays a role in protecting the pad height and facilitating subsequent wiring. The second electrode 108 can be arranged around the micro LED table 104 by magnetron sputtering or evaporation. The electrode film material of the second electrode 108 is preferably Al or Al alloy metal as the side wall reflective mirror surface, and the electrode stack metal can be Ni, Al, Ti, Ni, Pt, Au and other metal materials.

[0210] In step 807, a passivation layer 109 is deposited on the second insulating layer 105, the transparent conductive layer 106, the first electrode 107 and the second electrode 108, and a microlens (LENS) 110 is constructed on the passivation layer 109. The microlens is constructed on the pixel point located on the microLED table 103, and after the step etching at the microLED table 103 is completed, the deep groove etching around the pixel point is completed, the first insulating layer 104, the second insulating layer 105, the transparent conductive layer 106, the first electrode 107 and the second electrode 108 are prepared, the passivation layer 109 is deposited on the wafer by plasma enhanced chemical vapor deposition (PECVD), and the material of the passivation layer 109 can be SiO2, and the deposition thickness is 2.5-3.5um. Furthermore, by adjusting the photolithographic morphology of the microlens (for example, adjusting the photolithographic resin thickness, exposure energy and hardening temperature) to form a photolithographic array morphology corresponding to the position of the micro LED table 103, the passivation layer 109 is plasma etched to form a hemispherical S IO2 microlens 110 in a lens-like shape. The microlens 110 can improve the light extraction efficiency of the micro light emitting diode chip to a certain extent.

[0211] Furthermore, after the microlens 110 is formed, due to the limitations of the microlens photolithography size and plasma etching process, the curvature radius, spacer height, ball height, and lens ball width of the overall microlens are all relatively small. Therefore, a second SiO2 deposition can be performed on the microlens 110 to increase the microlens curvature radius, spacer height, ball height, and lens ball width. The film thickness of the second SiO2 deposition needs to be determined based on the SiO2 film thickness of the first deposition and the photolithography morphology of the microlens. The usual deposition thickness is 0.2-1um, which can be completed by single or multiple depositions.

[0212] Although various embodiments of the present invention are described above, it should be understood that they are presented as examples only and not as limitations. It is obvious to those skilled in the relevant art that various combinations, modifications and changes can be made thereto without departing from the spirit and scope of the present invention. Therefore, the breadth and scope of the present invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should only be defined according to the attached claims and their equivalents.

Claims

1. A micro light emitting diode chip, characterized in that: include: Pixel driver backplane; A micro LED table, which is located on the pixel driving backplane, wherein there is a gap between adjacent micro LED tables, and the bottom of the gap has a groove; an insulating layer covering the micro-LED mesa, wherein the insulating layer fills the groove; as well as A transparent conductive layer is located on the insulating layer, and the transparent conductive layer is electrically connected to each of the micro LED mesas.

2. The micro light emitting diode chip according to claim 1, characterized in that: Also includes: A metal conductive layer is located between the pixel driving backplane and the micro LED table.

3. The micro light emitting diode chip according to claim 2, characterized in that: The metal conductive layer has at least one interface.

4. The micro light emitting diode chip according to claim 2, characterized in that: The groove is located in the pixel driving backplane and the metal conductive layer, and the groove corresponds to the gap between adjacent micro LED mesas.

5. The micro light emitting diode chip according to claim 4, characterized in that: The insulating layer is located in the trench, and a top of the insulating layer in the gap is located above the trench.

6. The micro light emitting diode chip according to claim 5, characterized in that: The insulating layer on the groove has a flat top, The transparent conductive layer on the flat top of the insulating layer has a flat surface.

7. The micro light emitting diode chip according to claim 6, characterized in that: The insulating layer comprises: a first insulating layer covering the groove and the surface of the micro-LED mesas and exposing at least a portion of the top of the micro-LED mesas; and A second insulating layer is located on the first insulating layer.

8. The micro light emitting diode chip according to claim 7, characterized in that: The second insulating layer located on the groove has a flat top. The planar surface of the transparent conductive layer is located above the planar top of the second insulating layer in the gap.

9. The micro light emitting diode chip according to claim 6, characterized in that: Also includes: A first electrode electrically connected to the pixel driving backplane; as well as A second electrode is arranged on the flat surface of the transparent conductive layer and is electrically connected to the micro LED mesa through the transparent conductive layer. The pixel driving backplane is provided with a plurality of metal pillars, wherein the micro LED table is located above the metal pillars, and the first electrode is electrically connected to the pixel driving backplane through the metal pillars.

10. The micro light emitting diode chip according to claim 2, characterized in that: The material of the metal conductive layer includes one or more of the following: Cr, Al, Ti, Ni, Pt, Au and Sn.

11. The micro light emitting diode chip according to claim 1, characterized in that: The micro LED table comprises: A first epitaxial layer, which is located at a position close to the pixel driving backplane relative to the light emitting layer; a light emitting layer disposed between the first epitaxial layer and the second epitaxial layer; and The second epitaxial layer is located at a position far away from the pixel driving backplane relative to the light emitting layer, wherein the conductivity type of the first epitaxial layer is different from the conductivity type of the second epitaxial layer.

12. The micro light emitting diode chip according to claim 11, characterized in that: The first epitaxial layer is of N type, and the second epitaxial layer is of P type; or The first epitaxial layer is of P type, and the second epitaxial layer is of N type.

13. The micro light emitting diode chip according to claim 12, characterized in that: The P-type material is a P-type GaN layer or a P-type AlGaN layer, and the N-type material is an N-type GaN layer or an N-type AlGaN layer; The light emitting layer comprises a multi-quantum well layer and an electron blocking layer, wherein the multi-quantum well layer is an InGaN / GaN multi-quantum well layer or an InGaN / AlGaN multi-quantum well layer.

14. The micro light emitting diode chip according to claim 11, characterized in that: The insulating layer is provided with an opening at a position located on the second epitaxial layer, wherein the transparent conductive layer is electrically connected to the micro LED mesa through the opening.

15. The micro light emitting diode chip according to claim 7, characterized in that: The material of the first insulating layer includes one or more of the following: Al2O3, SiO2, and SIN.

16. The micro light emitting diode chip according to claim 7, characterized in that: The material of the second insulating layer includes SiO2.

17. The micro light emitting diode chip according to claim 1, characterized in that: The transparent conductive layer is a transparent conductive layer pattern.

18. The micro light emitting diode chip according to claim 1, characterized in that: The material of the transparent conductive layer includes one or more of the following items: oxides of ITO or IN, Sn, Zn, Cd and their composite oxide thin film materials.

19. The micro light emitting diode chip according to claim 9, characterized in that: The polarity of the first electrode is opposite to that of the second electrode; the first electrode is a P-type electrode, and the second electrode is an N-type annular reflective electrode; or the first electrode is an N-type electrode, and the second electrode is a P-type annular reflective electrode; the material of the first electrode is Cr, NI, TI, NI, PT, AU metal film material or its stacked structure; the second electrode includes an electrode stack and an electrode reflective film layer arranged on the surface of the electrode stack, wherein the material of the electrode reflective film layer includes Al or Al alloy, and the material of the electrode stack includes one or more of the following items: Ni, Al, Ti, Ni, Pt and Au.

20. The micro light emitting diode chip according to claim 9, characterized in that: Also includes: a passivation layer covering the insulating layer, the transparent conductive layer, the first electrode and the second electrode, wherein the material of the passivation layer comprises SiO2; as well as A micro lens is arranged on the passivation layer above the micro LED mesa.

21. The micro light emitting diode chip according to claim 20, characterized in that: The pixel driving backplane is a pixel driving backplane on a silicon substrate, and a pixel driving circuit is provided in the pixel driving backplane, and the pixel driving circuit controls each micro LED table.

22. A method for constructing a micro light emitting diode chip, characterized in that: The following steps are involved: Providing a pixel driving backplane and a micro light emitting diode epitaxial wafer, and bonding the pixel driving backplane and the micro light emitting diode epitaxial wafer together, wherein the micro light emitting diode epitaxial wafer comprises a substrate and a micro light emitting diode epitaxial structure arranged on the substrate; removing the substrate, and etching the micro light emitting diode epitaxial structure to form a plurality of micro LED mesas, wherein gaps exist between adjacent micro LED mesas; Depositing a first insulating layer on the micro-LED mesa, and depositing a second insulating layer on the first insulating layer, wherein the second insulating layer fills the gap; Etching the first insulating layer and the second insulating layer to expose at least a portion of the micro LED mesas, and depositing a transparent conductive layer on the second insulating layer and the exposed surface of the micro LED mesas to electrically connect the plurality of micro LED mesas; Arranging a first electrode and a second electrode, wherein the first electrode is electrically connected to the pixel driving backplane, and the second electrode is electrically connected to the micro LED mesa through the transparent conductive layer; as well as A passivation layer is deposited on the second insulating layer, the transparent conductive layer, the first electrode, and the second electrode, and a microlens is constructed on the passivation layer.

23. The method for constructing a micro light emitting diode chip according to claim 22, characterized in that: The pixel driving backplane and the micro light emitting diode epitaxial wafer are bonded together including the following steps: Depositing a first bonding metal stack on the ohmic contact layer of the micro light emitting diode epitaxial wafer; Depositing a second bonding metal stack on the surface of the pixel driving backplane; and The first bonding metal stack is bonded to the second bonding metal stack to bond the pixel driving backplane and the micro light emitting diode epitaxial wafer together.

24. The method for constructing a micro light emitting diode chip according to claim 22, characterized in that: Etching the micro-LED epitaxial structure to form a plurality of micro-LED mesas comprises the following steps: Using the top of the integrated circuit copper pillar as an epitaxial etching pixel point, etching the micro light emitting diode epitaxial structure to form a plurality of micro LED mesas; as well as Deep trench etching is performed between the plurality of micro LED mesas to form trenches to separate the plurality of micro LED mesas from each other.

25. The method for constructing a micro light emitting diode chip according to claim 24, characterized in that: The micro LED mesa is etched into a regular trapezoidal structure, and the horizontal inclination angle of the side of the regular trapezoidal structure is 65° to 85°.

26. The method for constructing a micro light emitting diode chip according to claim 24, characterized in that: The process of deep trench etching between multiple micro-LED mesas includes: photolithography and plasma beam etching inert gas physical etching.

27. The method for constructing a micro light emitting diode chip according to claim 24, characterized in that: Depositing a first insulating layer on the micro-LED mesa comprises: The first insulating layer is deposited on the surface of the micro LED mesas and the grooves by atomic layer deposition, and the material of the first insulating layer includes one or more of the following: Al2O3, SiO2, and SIN.

28. The method for constructing a micro light emitting diode chip according to claim 22, characterized in that: Depositing a second insulating layer on the first insulating layer comprises the following steps: Depositing the second insulating layer on the first insulating layer by chemical vapor deposition, wherein the deposition thickness of the second insulating layer is 3-6 um; as well as The surface of the second insulating layer is thinned, wherein the distance between the surface of the second insulating layer after thinning and the surface of the micro LED table is greater than or equal to 0.3 um.

29. The method for constructing a micro light emitting diode chip according to claim 22, characterized in that: Etching the first isolation layer and the second isolation layer to expose at least a portion of the micro LED mesa comprises: Plasma enhanced photolithography is performed above the micro LED mesas to etch holes in the first isolation layer and the second isolation layer, so that at least a portion of the surface of the micro LED mesas is exposed.

30. The method for constructing a micro light emitting diode chip according to claim 24, characterized in that: A transparent conductive layer is deposited on the second insulating layer and the exposed surface of the micro-LED mesas by using a target evaporation or sputtering process.

31. The method for constructing a micro light emitting diode chip according to claim 30, characterized in that: The transparent conductive layer is patterned to form a transparent conductive layer pattern.

32. The method for constructing a micro light emitting diode chip according to claim 22, characterized in that: The passivation layer is deposited on the isolation layer, the transparent conductive layer, the first electrode and the second electrode by plasma enhanced chemical vapor deposition.

33. The method for constructing a micro light emitting diode chip according to claim 32, characterized in that: The material of the passivation layer includes SiO2, and the deposition thickness of the passivation layer is 2.5-3.5um.

34. The method for constructing a micro light emitting diode chip according to claim 33, characterized in that: Constructing a microlens on the passivation layer comprises the following steps: Adjusting the photolithographic topography of the microlenses to form a photolithographic array topography corresponding to the position of the micro-LED mesas; and The passivation layer is plasma etched to form the microlens.

35. The method for constructing a micro light emitting diode chip according to claim 34, characterized in that: A secondary SiO2 deposition is performed on the surface of the microlens to increase the overall microlens curvature radius, spacer height, lens ball height and lens ball width.

36. The method for constructing a micro light emitting diode chip according to claim 35, characterized in that: The thickness of the deposited film of the secondary deposition of SiO2 is determined according to the thickness of the deposited passivation layer and the morphology of the photolithography array, wherein the thickness of the deposited film of the secondary deposition of SiO2 is 0.2-1 um.

37. A micro light emitting diode chip, characterized in that: include: Pixel driver backplane; A micro LED mesa, which is located on the pixel driving backplane, wherein the top of each micro LED mesa has an opening; as well as A transparent conductive layer pattern is located on the micro LED mesas, wherein the transparent conductive layer pattern is at least located in the opening and the transparent conductive layer patterns between adjacent micro LED mesas are interconnected, and the transparent conductive layer pattern exposes at least a portion of the surface of each micro LED mesas.

38. The micro light emitting diode chip according to claim 37, characterized in that: The transparent conductive layer pattern comprises: A first region electrically connected to the micro LED mesa through the opening; and A series line is extended to electrically connect the plurality of first regions.

39. The micro light emitting diode chip according to claim 38, characterized in that: The extended series line is integral with the first region.

40. The micro light emitting diode chip according to claim 38, characterized in that: The extended series lines form a horizontal and vertical arrangement structure.

41. The micro light emitting diode chip according to claim 40, characterized in that: The intersection area of ​​the extended series lines is the first area.

42. The micro light emitting diode chip according to claim 37, characterized in that: The transparent conductive layer pattern is at least located on the micro LED table.

43. The micro light emitting diode chip according to claim 38, characterized in that: The width of the extended series line is 0.3 to 1 um.

44. The micro light emitting diode chip according to claim 37, characterized in that: Also includes: A metal conductive layer is located between the pixel driving backplane and the micro LED table.

45. The micro light emitting diode chip according to claim 44, characterized in that: The metal conductive layer has at least one interface.

46. ​​The micro light emitting diode chip according to claim 37, characterized in that: Also includes: An insulating layer is located between the micro LED table and the transparent conductive layer pattern.

47. The micro light emitting diode chip according to claim 46, characterized in that: The insulating layer includes: a first insulating layer, which covers the surface of the micro LED mesa and exposes at least a portion of the top of the micro LED mesa; and A second insulating layer is located on the first insulating layer.

48. The micro light emitting diode chip according to claim 37, characterized in that: Also includes: A first electrode electrically connected to the pixel driving backplane; as well as A second electrode is arranged on the flat surface of the transparent conductive layer and is electrically connected to the micro LED mesa through the transparent conductive layer. The pixel driving backplane is provided with a plurality of metal pillars, wherein the micro LED table is located above the metal pillars, and the first electrode is electrically connected to the pixel driving backplane through the metal pillars.

49. The micro light emitting diode chip according to claim 44, characterized in that: The material of the metal conductive layer includes one or more of the following: Cr, Al, Ti, Ni, Pt, Au and Sn.

50. The micro light emitting diode chip according to claim 37, characterized in that: The micro LED table comprises: A first epitaxial layer, which is located at a position close to the pixel driving backplane relative to the light emitting layer; a light emitting layer disposed between the first epitaxial layer and the second epitaxial layer; and The second epitaxial layer is located at a position far away from the pixel driving backplane relative to the light emitting layer, wherein the conductivity type of the first epitaxial layer is different from the conductivity type of the second epitaxial layer.

51. The micro light emitting diode chip according to claim 50, characterized in that: The first epitaxial layer is of N type, and the second epitaxial layer is of P type; or The first epitaxial layer is of P type, and the second epitaxial layer is of N type.

52. The micro light emitting diode chip according to claim 51, characterized in that: The P-type material is a P-type GaN layer or a P-type AlGaN layer, and the N-type material is an N-type GaN layer or an N-type AlGaN layer; The light emitting layer comprises a multi-quantum well layer and an electron blocking layer, wherein the multi-quantum well layer is an InGaN / GaN multi-quantum well layer or an InGaN / AlGaN multi-quantum well layer.

53. The micro light emitting diode chip according to claim 50, characterized in that: The insulating layer is provided with an opening at a position located on the second epitaxial layer, wherein the transparent conductive layer is electrically connected to the micro LED mesa through the opening.

54. The micro light emitting diode chip according to claim 47, characterized in that: The material of the first insulating layer includes one or more of the following: Al2O3, SiO2, and SIN.

55. The micro light emitting diode chip according to claim 47, characterized in that: The material of the second insulating layer includes SiO2.

56. The micro light emitting diode chip according to claim 37, characterized in that: The material of the transparent conductive layer pattern includes one or more of the following items: oxides of ITO or IN, Sn, Zn, Cd and their composite oxide thin film materials.

57. The micro light emitting diode chip according to claim 48, characterized in that: The polarity of the first electrode is opposite to that of the second electrode; the first electrode is a P-type electrode, and the second electrode is an N-type annular reflective electrode; or the first electrode is an N-type electrode, and the second electrode is a P-type annular reflective electrode; the material of the first electrode is Cr, NI, TI, NI, PT, AU metal film material or its stacked structure; the second electrode includes an electrode stack and an electrode reflective film layer arranged on the surface of the electrode stack, wherein the material of the electrode reflective film layer includes Al or Al alloy, and the material of the electrode stack includes one or more of the following items: Ni, Al, Ti, Ni, Pt and Au.

58. The micro light emitting diode chip according to claim 48, characterized in that: Also includes: a passivation layer covering the insulating layer, the transparent conductive layer, the first electrode and the second electrode, wherein the material of the passivation layer comprises SiO2; as well as A micro lens is arranged on the passivation layer above the micro LED mesa.

59. The micro light emitting diode chip according to claim 37, characterized in that: The pixel driving backplane is a pixel driving backplane on a silicon substrate, and a pixel driving circuit is provided in the pixel driving backplane, and the pixel driving circuit controls each micro LED table.

60. A method for constructing a micro light emitting diode chip, characterized in that: The following steps are involved: Providing a pixel driving backplane and a micro light emitting diode epitaxial wafer, and bonding the pixel driving backplane and the micro light emitting diode epitaxial wafer together, wherein the micro light emitting diode epitaxial wafer comprises a substrate and a micro light emitting diode epitaxial structure arranged on the substrate; removing the substrate, and etching the micro light emitting diode epitaxial structure to form a plurality of micro LED mesas; Depositing a first insulating layer on the micro-LED mesa, and depositing a second insulating layer on the first insulating layer; Etching the first insulating layer and the second insulating layer to expose at least a portion of the micro LED mesas, and depositing a transparent conductive layer on the second insulating layer and the exposed surface of the micro LED mesas to electrically connect the plurality of micro LED mesas; Performing patterning on the transparent conductive layer to form a patterned transparent conductive layer; Arranging a first electrode and a second electrode, wherein the first electrode is electrically connected to the pixel driving backplane, and the second electrode is electrically connected to the micro LED mesa through the patterned transparent conductive layer; A passivation layer is deposited on the second insulating layer, the patterned transparent conductive layer, the first electrode and the second electrode, and a microlens is constructed on the passivation layer.

Images