Light-emitting diode and light-emitting diode preparation method

Abstract

The invention provides a light emitting diode and a light emitting diode preparation method. The light emitting diode comprises an epitaxial structure, a first electrode, a second electrode, a reflecting layer, a first electrode bonding pad and a second electrode bonding pad, the epitaxial structure comprises a first semiconductor layer, an active layer and a second semiconductor layer which are stacked in sequence, the first semiconductor layer, the active layer and the second semiconductor layer form a step structure, the first electrode is located on the step surface of the step structure, the second electrode is located on the surface of the second semiconductor layer, and the reflecting layer covers the step structure, the first electrode and the second electrode; the reflecting layer is provided with a first through hole and a second through hole, the first electrode bonding pad is connected with the first electrode through the first through hole, and the second electrode bonding pad is connected with the second electrode through the second through hole; the projection of the first through hole on the bottom surface of the first semiconductor layer is located at the edge of the projection of the first electrode bonding pad on the bottom surface of the first semiconductor layer, and the bottom surface of the first semiconductor layer is a surface far away from the active layer.

Description

Technical Field

[0001] The present disclosure relates to the field of light-emitting devices, and in particular to a light-emitting diode and a method for preparing the light-emitting diode. Background Art

[0002] Light-emitting diodes can cover the wavelength range from ultraviolet to infrared. At present, the low-resolution display market is still dominated by liquid crystal displays (LCD), and micro light-emitting diodes (Micro LED) are gradually gaining attention in the low-resolution display market due to their own advantages.

[0003] The micro light emitting diode provided by the related technology generally includes an epitaxial structure, an electrode, a reflective layer, a pad, and the like.

[0004] However, in the micro light emitting diode provided by the related art, since the pad size is small and the flatness of the pad cannot be guaranteed, the pad is prone to low yield in the subsequent welding process. Summary of the invention

[0005] The embodiments of the present disclosure provide a light emitting diode and a method for manufacturing a light emitting diode, which can improve the soldering yield of the solder pad. The technical solution is as follows:

[0006] In one aspect, a light emitting diode is provided, the light emitting diode comprising: an epitaxial structure, a first electrode, a second electrode, a reflective layer, a first electrode pad, and a second electrode pad;

[0007] The epitaxial structure comprises a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence, wherein the first semiconductor layer, the active layer, and the second semiconductor layer form a step structure, the first electrode is located on a step surface of the step structure, the second electrode is located on a surface of the second semiconductor layer, and the reflective layer covers the step structure and the first electrode and the second electrode;

[0008] The reflective layer has a first through hole and a second through hole, the first electrode pad is connected to the first electrode through the first through hole, and the second electrode pad is connected to the second electrode through the second through hole;

[0009] The projection of the first through hole on the bottom surface of the first semiconductor layer is located at an edge of the projection of the first electrode pad on the bottom surface of the first semiconductor layer, and the bottom surface of the first semiconductor layer is a side away from the active layer.

[0010] Optionally, the projection of the first electrode pad on the bottom surface of the first semiconductor layer is a first rectangle, and the projection of the first through hole on the bottom surface of the first semiconductor layer is located at a corner of the first rectangle.

[0011] Optionally, the bottom surface of the first semiconductor layer is a second rectangle, and a projection of a step surface of the step structure on the bottom surface of the first semiconductor layer is located at a corner of the second rectangle.

[0012] Optionally, the light-emitting diode further includes: a first retaining wall structure and a second retaining wall structure, the first retaining wall structure is located on the surface of the first electrode pad and arranged along the edge of the first electrode pad, and the second retaining wall structure is located on the surface of the second electrode pad and arranged along the edge of the second electrode pad.

[0013] Optionally, the first retaining wall structure and the second retaining wall structure are silicon oxide structures.

[0014] Optionally, both the first retaining wall structure and the second retaining wall structure are annular step retaining wall structures, and the step surfaces of the step retaining wall structures face the center of the ring.

[0015] Optionally, both the first retaining wall structure and the second retaining wall structure are three-step retaining wall structures, and the height of each step structure in the three-step retaining wall structure is 0.2-0.4 microns.

[0016] In another aspect, a method for preparing a light emitting diode is provided, the method comprising:

[0017] forming a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence, wherein the second semiconductor layer, the active layer, and the first semiconductor layer constitute an epitaxial structure;

[0018] Performing a patterning process on the epitaxial structure to form a step structure;

[0019] Manufacturing a first electrode and a second electrode, wherein the first electrode is located on a step surface of the step structure, and the second electrode is located on a surface of the second semiconductor layer;

[0020] Manufacturing a reflective layer, wherein the reflective layer covers the step structure and the first electrode and the second electrode, and the reflective layer has a first through hole and a second through hole;

[0021] A first electrode pad and a second electrode pad are manufactured, wherein the first electrode pad is connected to the first electrode through the first through hole, and the second electrode pad is connected to the second electrode through the second through hole; a projection of the first through hole on the bottom surface of the first semiconductor layer is located at an edge of a projection of the first electrode pad on the bottom surface of the first semiconductor layer, and the bottom surface of the first semiconductor layer is a side away from the active layer.

[0022] Optionally, the method further comprises:

[0023] Forming an insulating film layer on the first electrode pad and the second electrode pad;

[0024] The insulating film layer is patterned to obtain a first retaining wall structure and a second retaining wall structure, wherein the first retaining wall structure is located on the surface of the first electrode pad and arranged along the edge of the first electrode pad, and the second retaining wall structure is located on the surface of the second electrode pad and arranged along the edge of the second electrode pad.

[0025] Optionally, the patterning of the insulating film layer includes:

[0026] The insulating film layer is subjected to multiple patterning processes to form the first retaining wall structure and the second retaining wall structure in a step structure shape.

[0027] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:

[0028] In the embodiment of the present disclosure, the first through hole connecting the first electrode pad and the first electrode is moved from the center of the first electrode pad to the edge of the first electrode pad. In this way, during welding, even if the welding material (conductive particles) partially sinks into the depression of the first electrode pad caused by the first through hole, since the depression is located at the edge, it will not affect the welding of the first electrode pad. In addition, this arrangement makes the middle part of the surface of the first electrode pad smoother, and a large area of ​​flat surface is located in the center of the solder joint, which improves the welding yield, improves the conductivity after welding, and optimizes the light-emitting effect of the light-emitting diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 It is a structural schematic diagram of a light emitting diode provided by the related technology;

[0031] Figure 2 It is a top view of a part of the structure of a light emitting diode provided by the related technology;

[0032] Figure 3 is a structural schematic diagram of a light emitting diode provided by an embodiment of the present disclosure;

[0033] Figure 4 is a top view of a partial structure of a light emitting diode provided by an embodiment of the present disclosure;

[0034] Figure 5 is a structural schematic diagram of a light emitting diode provided by an embodiment of the present disclosure;

[0035] Figure 6 is a top view of a partial structure of a light emitting diode provided by an embodiment of the present disclosure;

[0036] Figure 7 is a top view of a partial structure of a light emitting diode provided by an embodiment of the present disclosure;

[0037] Figure 8 is a flow chart of a method for preparing a light emitting diode provided by an embodiment of the present disclosure;

[0038] Fig. 9 This is a flow chart of another method for preparing a light emitting diode provided in an embodiment of the present disclosure.

[0039] The reference numerals are as follows:

[0040] 10: electrode structure; 100: substrate; 101: first semiconductor layer; 102: active layer; 103: second semiconductor layer; 104: bonding layer; 105: first electrode; 106: second electrode; 107: reflective layer; 108: first electrode pad; 109: second electrode pad; 110: passivation layer; 111: first through hole; 112: second through hole; 120: step surface of step structure; 1000: epitaxial structure; 201: first retaining wall structure; 202: second retaining wall structure. DETAILED DESCRIPTION

[0041] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0042] Figure 1 A schematic diagram of the structure of a light emitting diode provided for related technology. Figure 1 The light emitting diode comprises: a substrate 100 , an epitaxial structure 1000 , a bonding layer 104 , a reflective layer 107 , a passivation layer 110 and an electrode structure 10 .

[0043] The epitaxial structure 1000 includes a first semiconductor layer 101 , an active layer 102 , and a second semiconductor layer 103 . The electrode structure 10 includes a first electrode 105 , a second electrode 106 , a first electrode pad 108 , and a second electrode pad 109 .

[0044] The substrate 100 is bonded to the epitaxial structure 1000 via a bonding layer 104 , the reflective layer 107 covers the surface of the epitaxial structure 1000 , the electrode structure 10 penetrates the reflective layer 107 and is connected to the epitaxial structure 1000 , and the passivation layer 110 covers the surface of the reflective layer 107 .

[0045] The reflective layer 107 has a first through hole 111 and a second through hole 112 , the first electrode pad 108 is connected to the first electrode 105 through the first through hole 111 , and the second electrode pad 109 is connected to the second electrode 106 through the second through hole 112 .

[0046] Figure 2 This is a top view of a part of the structure of a light emitting diode provided by the related art, see Figure 2 Since the depth of the first through hole 111 is relatively deep, a depression A appears in the middle of the surface of the first electrode pad 108, and since the depression A is located at the center of the pad surface, during subsequent welding, the welding material (conductive particles) is easily sunk into the depression A, and the subsequent pad welding yield is reduced, and the conductivity is poor after welding, thereby affecting the light emission of the light-emitting diode.

[0047] An embodiment of the present disclosure provides a light emitting diode, which includes: an epitaxial structure, a first electrode, a second electrode, a reflective layer, a first electrode pad, and a second electrode pad.

[0048] The epitaxial structure includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence, wherein the first semiconductor layer, the active layer, and the second semiconductor layer form a step structure, the first electrode is located on the step surface of the step structure, the second electrode is located on the surface of the second semiconductor layer, and the reflective layer covers the step structure and the first electrode and the second electrode.

[0049] The reflective layer 107 has a first through hole 111 and a second through hole 112, the first electrode pad 108 is connected to the first electrode 105 through the first through hole 111, and the second electrode pad 109 is connected to the second electrode 106 through the second through hole 112;

[0050] The projection of the first through hole 111 on the bottom surface of the first semiconductor layer 101 is located at the edge of the projection of the first electrode pad 108 on the bottom surface of the first semiconductor layer 101 . The bottom surface of the first semiconductor layer 101 is the side away from the active layer 102 .

[0051] The side of the first semiconductor layer 101 away from the active layer 102 refers to the other side opposite to the side of the first semiconductor layer 101 close to the active layer 102 .

[0052] In the embodiment of the present disclosure, the first through hole connecting the first electrode pad and the first electrode is moved from the center of the first electrode pad to the edge of the first electrode pad. In this way, during welding, even if the welding material (conductive particles) partially sinks into the depression of the first electrode pad caused by the first through hole, since the depression is located at the edge, it will not affect the welding of the first electrode pad. In addition, this arrangement makes the middle part of the surface of the first electrode pad smoother, and a large area of ​​flat surface is located in the center of the solder joint, which improves the welding yield, improves the conductivity after welding, and optimizes the light-emitting effect of the light-emitting diode.

[0053] Among them, the welding material is in a fluid state during the welding process, so it is easy to sink into the depression.

[0054] Optionally, the second through hole connecting the second electrode pad and the second electrode can also be moved from the center of the second electrode pad to the edge of the second electrode pad. That is, the projection of the second through hole on the bottom surface of the first semiconductor layer is located at the edge of the projection of the second electrode pad on the bottom surface of the first semiconductor layer.

[0055] Although the smaller depth of the second through hole has less impact on the surface flatness of the second electrode pad, this improvement can also optimize the subsequent welding yield of the second electrode pad to a certain extent.

[0056] In addition, the subsequent further improvements on the design of the position of the first through hole are also applicable to the second through hole, so they are not described in detail.

[0057] Figure 3 A schematic diagram of the structure of a light emitting diode provided by an embodiment of the present disclosure. Figure 3 The light emitting diode comprises: a substrate 100 , an epitaxial structure 1000 , a bonding layer 104 , a reflective layer 107 and an electrode structure 10 .

[0058] The substrate 100 is bonded to the epitaxial structure 1000 via a bonding layer 104 , and the electrode structure 10 penetrates the reflective layer 107 and is connected to the epitaxial structure 1000 .

[0059] In the embodiment of the present disclosure, the epitaxial structure 1000 includes a first semiconductor layer 101, an active layer 102 and a second semiconductor layer 103 stacked in sequence, and the first semiconductor layer 101, the active layer 102 and the second semiconductor layer 103 form a step structure; the first electrode 105 is located on the step surface 120 of the step structure, the second electrode 106 is located on the surface of the second semiconductor layer 103, and the reflective layer 107 covers the step structure as well as the first electrode 105 and the second electrode 106.

[0060] The reflective layer 107 has a first through hole 111 and a second through hole 112 . The first electrode pad 108 is connected to the first electrode 105 through the first through hole 111 , and the second electrode pad 109 is connected to the second electrode 106 through the second through hole 112 .

[0061] It should be noted that the depression on the surface of the first electrode pad caused by the first through hole is a microstructure and is not shown in the drawings. However, it has been verified through experiments that it does affect the welding effect.

[0062] Figure 4 is a top view of a part of the structure of a light emitting diode provided by an embodiment of the present disclosure. Figure 3 and Figure 4 It can be seen that the projection of the first electrode pad 108 on the bottom surface of the first semiconductor layer 101 is a first rectangle, and the projection of the first through hole 111 on the bottom surface of the first semiconductor layer 101 is located at a corner of the first rectangle.

[0063] In the embodiment of the present disclosure, the first through hole 111 is disposed at a corner of the first electrode pad 108 , so that the influence of the depression on the surface of the first electrode pad caused by the first through hole on the welding yield can be minimized.

[0064] exist Figure 4 In the illustrated implementation, the projection of the first through hole 111 on the bottom surface of the first semiconductor layer 101 is located at a corner of the first rectangle away from the second electrode pad 109 .

[0065] In other implementations, the projection of the first through hole 111 on the bottom surface of the first semiconductor layer 101 may also be located at the center of one side of the first rectangle.

[0066] In other embodiments, the projection of the first electrode pad 108 on the bottom surface of the first semiconductor layer 101 may also be other shapes, such as a circle, other polygons, etc.

[0067] like Figure 4As shown, the bottom surface of the first semiconductor layer 101 is a second rectangle, and the projection of the step surface 120 of the step structure on the bottom surface of the first semiconductor layer 101 is located at a corner of the second rectangle.

[0068] In this implementation, the step structure is opened at a corner of the first semiconductor layer 101, and the area occupied by the step structure is small, so that the overall light-emitting area of ​​the light-emitting diode is larger.

[0069] exist Figure 4 In the structure shown, the step structure is in the shape of a notch, and the side wall of the step structure is in an arc shape.

[0070] exist Figure 4 In the structure shown, the projection of the first through hole 111 is a circle, and the circular through hole and the arc are concentrically arranged.

[0071] In other implementations, the sidewall of the step structure and / or the first through hole 111 may also be in other shapes.

[0072] In other embodiments, the step structure may also have a larger area, which is not limited in the embodiments of the present disclosure.

[0073] Figure 5 A schematic diagram of the structure of a light emitting diode provided by an embodiment of the present disclosure. Figure 5 , the light emitting diode and Figure 3 The difference between the light emitting diode shown is that the light emitting diode further includes: a first retaining wall structure 201 and a second retaining wall structure 202 , wherein the first retaining wall structure 201 is located on the surface of the first electrode pad 108 , and the second retaining wall structure 202 is located on the surface of the second electrode pad 109 .

[0074] Figure 6 FIG. 1 is a top view of a part of the structure of a light emitting diode provided by an embodiment of the present disclosure. Figure 6 It can be seen that the first retaining wall structure 201 is arranged along the edge of the first electrode pad 108 , and the second retaining wall structure 202 is arranged along the edge of the second electrode pad 109 .

[0075] In this implementation, by arranging a retaining wall structure at the edge of the pad surface, the easily flowing welding material can be restricted to the middle of the pad surface during the welding process and will not flow outside the pad, thereby ensuring the welding quality and avoiding the adverse effects caused by overflow of the welding material.

[0076] In a possible implementation of the present disclosure, the first retaining wall structure 201 and the second retaining wall structure 202 are silicon oxide structures.

[0077] Exemplarily, the first retaining wall structure 201 and the second retaining wall structure 202 are silicon dioxide structures.

[0078] In this implementation, silicon oxide is used to make the retaining wall structure, which is easy to manufacture and can be attached to the surface of the pad, and can also block the welding material.

[0079] In other implementations, the first retaining wall structure 201 and the second retaining wall structure 202 may also be structures made of other materials, which is not limited.

[0080] See again Figure 5 The first retaining wall structure 201 and the second retaining wall structure 202 are both annular step retaining wall structures, and the step surfaces of the step retaining wall structures face the center of the ring.

[0081] In this implementation, the step structure can better block the welding material and ensure that the welding material is located at the center of the welding surface.

[0082] See again Figure 5 The first retaining wall structure 201 and the second retaining wall structure 202 are both three-step retaining wall structures, and the height of each step structure in the three-step retaining wall structure is 0.2 to 0.4 microns.

[0083] In this implementation, the above-mentioned height can meet the demand for the amount of welding materials, while not being too high to affect the overall thickness of the light-emitting diode.

[0084] Exemplarily, the height of each step structure in the three-step step retaining wall structure is 0.3 micrometers.

[0085] In the embodiment of the present disclosure, the width of the first retaining wall structure 201 and the second retaining wall structure 202 may be 4 to 6 micrometers, for example, 5 micrometers.

[0086] In other implementations, the first retaining wall structure 201 and the second retaining wall structure 202 may also be non-step structures, which is not limited to this.

[0087] Figure 7 is a top view of a part of the structure of a light emitting diode provided by an embodiment of the present disclosure. Figure 7 It can be seen that Figure 6 In comparison, the first retaining wall structure 201 is arranged along the edge of the first electrode pad 108 , but excludes the area corresponding to the first through hole 111 , thereby further ensuring the flatness of the welding area.

[0088] That is, in Figure 6In the structure shown, the projection of the first through hole 111 on the bottom surface of the first semiconductor layer 101 is located within the projection of the first retaining wall structure 201 on the bottom surface of the first semiconductor layer 101 .

[0089] And in Figure 7 In the structure shown, the projection of the first through hole 111 on the bottom surface of the first semiconductor layer 101 is outside the projection of the first retaining wall structure 201 on the bottom surface of the first semiconductor layer 101. This method can exclude the recess A from the first retaining wall structure 201, further preventing the welding material from sinking into the recess A.

[0090] like Figure 6 As shown, the first retaining wall structure 201 is a rectangular ring; Figure 7 As shown, the first retaining wall structure 201 is a rectangular ring with an arc-shaped notch at one corner, and the arc-shaped notch is opposite to the first through hole 111 .

[0091] In the embodiment of the present disclosure, the substrate 100 may be any one of a sapphire substrate, a Si substrate, a SiC substrate, etc., and the present disclosure does not limit the material of the substrate.

[0092] Exemplarily, the substrate 100 is a sapphire substrate.

[0093] In the embodiment of the present disclosure, the first semiconductor layer 101 may be an N-type semiconductor layer, and the second semiconductor layer 103 may be a P-type semiconductor layer.

[0094] For example, the first semiconductor layer 101 may include a stacked N-type AlGaInP current spreading layer and an N-type AlInP carrier confinement layer, and the second semiconductor layer 103 may include a stacked P-type AlInP carrier confinement layer and a P-type GaP window layer.

[0095] The thickness of the P-type GaP window layer is 2.8-3.2 μm, for example, 3 μm.

[0096] In another example, the first semiconductor layer 101 may be a P-type semiconductor layer, and the second semiconductor layer 103 may be an N-type semiconductor layer.

[0097] In the embodiment of the present disclosure, the active layer 102 may be a multi-quantum well layer. For example, the multi-quantum well layer may include a plurality of periodically alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0098] Optionally, a corrosion stop layer may be provided between the bonding layer 104 and the first semiconductor layer 101 , and the corrosion stop layer may be a solidified phosphoric acid mixture.

[0099] In the embodiment of the present disclosure, the material of the bonding layer 104 may be any one of photoresist, benzocyclobutene, and silica gel.

[0100] Exemplarily, the material of the bonding layer 104 is silica gel.

[0101] In the embodiment of the present disclosure, the first semiconductor layer 101 , the active layer 102 , and the second semiconductor layer 103 stacked in sequence form a step structure, and the reflective layer 107 covers the step structure.

[0102] In the embodiment of the present disclosure, the reflective layer 107 is a distributed Bragg reflector (DBR) layer.

[0103] In the embodiment of the present disclosure, both the first electrode 105 and the second electrode 106 may include AuGe or AuBe electrodes.

[0104] In the embodiment of the present disclosure, the first electrode pad 108 and the second electrode pad 109 may each include a Cr layer, an Al layer, a Ti layer, a Ni layer, and an Au alloy layer stacked in sequence.

[0105] In one example, the thickness of the Cr layer is 80-120 nm, the thickness of the Al layer is 2500-3500 nm, the thickness of the Ti layer is 450-550 nm, the thickness of the Ni layer is 1800-2200 nm, and the thickness of the Au alloy layer is 18000-22000 nm.

[0106] Exemplarily, the thickness of the Cr layer is 100 nm, the thickness of the Al layer is 3000 nm, the thickness of the Ti layer is 500 nm, the thickness of the Ni layer is 2000 nm, and the thickness of the Au alloy layer is 20000 nm.

[0107] In one example, the first electrode 105 is an N-electrode, and the first electrode pad 108 is an N-electrode pad; the second electrode 106 is a P-electrode, and the second electrode pad 109 is a P-electrode pad.

[0108] In another example, the first electrode 105 is a P-electrode, and the first electrode pad 108 is a P-electrode pad; the second electrode 106 is an N-electrode, and the second electrode pad 109 is an N-electrode pad.

[0109] Optionally, the light emitting diode may further include a passivation layer 110 , wherein the passivation layer 110 covers the sidewalls of the epitaxial structure 1000 and the reflective layer 107 .

[0110] like Figure 3 As shown, in one example, the thickness of the passivation layer can be lower than the thickness of the pad. The lower the thickness of the passivation layer, the thinner the thickness of the passivation layer at the side is, thereby miniaturizing the light emitting diode. In other examples, the thickness of the passivation layer is the same as the thickness of the pad.

[0111] In the embodiment of the present disclosure, the passivation layer 110 may be a film layer formed of materials such as a SiO 2 layer and an Al 2 O 3 layer.

[0112] For example, the passivation layer 110 is a SiO 2 layer.

[0113] It is worth noting that in the embodiments of the present disclosure, structures may be selectively increased or decreased based on the structure of the above-mentioned light emitting diode, and the present disclosure does not impose any limitation on this.

[0114] Figure 8 A flow chart of a method for preparing a light emitting diode provided in an embodiment of the present disclosure. Figure 8 The method steps include:

[0115] S11, forming a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence, wherein the second semiconductor layer, the active layer, and the first semiconductor layer constitute an epitaxial structure.

[0116] S12, performing graphic processing on the epitaxial structure to form a step structure.

[0117] S13, manufacturing a first electrode and a second electrode, wherein the first electrode is located on a step surface of the step structure, and the second electrode is located on a surface of the second semiconductor layer.

[0118] S14, manufacturing a reflective layer, wherein the reflective layer covers the step structure and the first electrode and the second electrode, and the reflective layer has a first through hole and a second through hole.

[0119] S15. Make a first electrode pad and a second electrode pad, the first electrode pad is connected to the first electrode through the first through hole, and the second electrode pad is connected to the second electrode through the second through hole; the projection of the first through hole on the bottom surface of the first semiconductor layer is located at the edge of the projection of the first electrode pad on the bottom surface of the first semiconductor layer, and the bottom surface of the first semiconductor layer is the side away from the active layer.

[0120] In the embodiment of the present disclosure, the first through hole connecting the first electrode pad and the first electrode is moved from the center of the first electrode pad to the edge of the first electrode pad. In this way, during welding, even if the welding material (conductive particles) partially sinks into the depression of the first electrode pad caused by the first through hole, since the depression is located at the edge, it will not affect the welding of the first electrode pad. In addition, this arrangement makes the middle part of the surface of the first electrode pad smoother, and a large area of ​​flat surface is located in the center of the solder joint, which improves the welding yield, improves the conductivity after welding, and optimizes the light-emitting effect of the light-emitting diode.

[0121] Fig. 9Another light emitting diode manufacturing method provided by the present disclosure is a flow chart. Fig. 9 The method steps include:

[0122] S21. Bond the epitaxial structure to the substrate via a bonding layer.

[0123] In one example, step S21 includes:

[0124] Step 1: fabricating a first semiconductor layer, an active layer and a second semiconductor layer stacked in sequence on a surface of a first temporary substrate, that is, fabricating an epitaxial structure.

[0125] Wherein, the first temporary substrate is a gallium arsenide substrate.

[0126] In one example, step 1 includes:

[0127] The first step is to make the first semiconductor layer.

[0128] In the embodiment of the present disclosure, the first semiconductor layer includes an N-type AlGaInP current spreading layer and an N-type AlInP carrier confinement layer stacked in sequence.

[0129] Exemplarily, a Metal Organic Chemical Vapor Deposition (MOCVD) device is used to sequentially form an N-type AlGaInP current spreading layer and an N-type AlInP carrier confinement layer on the surface of the first temporary substrate.

[0130] In the disclosed embodiment, the growth of the semiconductor layer can be realized by using Veeco K465i or C4 or RB MOCVD equipment or AIXTRON metal organic compound chemical vapor deposition equipment. High purity H2 (hydrogen) or high purity N2 (nitrogen) or a mixture of high purity H2 and high purity N2 is used as a carrier gas, high purity NH3 is used as an N source, trimethyl gallium (TMGa) and triethyl gallium (TEGa) are used as gallium sources, trimethyl indium (TMIn) is used as an indium source, silane (SiH4) is used as an N-type dopant, trimethyl aluminum (TMAl) is used as an aluminum source, and bis(cyclopentadienyl) magnesium (CP2Mg) is used as a P-type dopant.

[0131] Optionally, an etching stop layer may be formed between the first temporary substrate and the first semiconductor layer, and the etching medium layer is a solidified phosphoric acid mixture.

[0132] The second step is to make the active layer.

[0133] In the embodiment of the present disclosure, the active layer is a multi-quantum well layer, including a plurality of periodically alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0134] Exemplarily, a plurality of AlGaInP quantum well layers and AlGaInP quantum barrier layers are alternately grown on the surface of the first semiconductor layer using MOCVD equipment.

[0135] The third step is to make the second semiconductor layer.

[0136] In the embodiment of the present disclosure, the second semiconductor layer includes a P-type AlInP carrier confinement layer and a P-type GaP window layer.

[0137] Exemplarily, a P-type AlInP carrier confinement layer and a P-type GaP window layer are sequentially fabricated on the surface of the active layer using MOCVD equipment.

[0138] Step 2: bonding a second temporary substrate to the surface of the second semiconductor layer.

[0139] The second temporary substrate may be any one of substrates such as a sapphire substrate and a Si substrate.

[0140] In the embodiment of the present disclosure, the second temporary substrate and the second semiconductor layer can be bonded by any one of photoresist, benzocyclobutene, and silica gel.

[0141] The bonding temperature is 280-320° C. For example, the bonding temperature is 300° C.

[0142] In the embodiment of the present disclosure, if the bonding temperature is too high, the semiconductor layer will be damaged, and if the bonding temperature is too low, it will be detrimental to the bonding effect. Using the above temperature for bonding can ensure a good bonding effect without damaging the semiconductor layer.

[0143] Step 3: removing the first temporary substrate.

[0144] Step 4: forming a bonding layer on the surface of the substrate.

[0145] In the embodiment of the present disclosure, the substrate may be any one of a sapphire substrate, a Si substrate and the like, for example, a sapphire substrate.

[0146] In the disclosed embodiment, the material of the bonding layer is any one of photoresist, benzocyclobutene, and silica gel.

[0147] Step 5: bonding the substrate and the first semiconductor layer via the bonding layer.

[0148] The bonding temperature is 280-320° C. For example, the bonding temperature is 300° C.

[0149] Step 6: removing the second temporary substrate.

[0150] In the embodiment of the present disclosure, when removing the second temporary substrate, a solution may be used for treatment, and the adhesive material used for bonding on the surface is removed while the second temporary substrate is removed.

[0151] S22, performing patterning on the first semiconductor layer, the active layer and the second semiconductor layer to form a step structure.

[0152] In one example, step S22 includes:

[0153] The second semiconductor layer, the active layer and the first semiconductor layer stacked in sequence are patterned by using an etching technology to expose the first semiconductor layer to form a step structure.

[0154] In the embodiment of the present disclosure, the step surface of the step structure is located in the first semiconductor layer.

[0155] In the embodiment of the present disclosure, the second semiconductor layer, the active layer, and the first semiconductor layer stacked in sequence are patterned by using an etching technology to expose the first semiconductor layer to form a step structure, which may include:

[0156] In the first step, a layer of photoresist is coated on the surface of the second semiconductor layer.

[0157] The second step is to use a mask to block and expose the photoresist.

[0158] The third step is to develop the exposed photoresist to form a photoresist mask.

[0159] In the fourth step, the second semiconductor layer, the active layer and the first semiconductor layer are etched based on the photoresist mask to form a step structure and an etching groove (ISO).

[0160] Step 5: Use a stripping solution to remove the photoresist.

[0161] S23, manufacturing a first electrode and a second electrode, wherein the first electrode is located on the step surface, and the second electrode is located on the surface of the second semiconductor layer.

[0162] In one example, step S23 includes:

[0163] By adopting electron beam evaporation technology or magnetron sputtering technology, a first electrode is formed on the step surface of the first semiconductor layer, and a second electrode is formed on the surface of the second semiconductor layer.

[0164] S24, manufacturing a reflective layer, wherein the reflective layer covers the step structure and the first electrode and the second electrode, and the reflective layer has a first through hole and a second through hole.

[0165] In one example, step S24 includes:

[0166] A DBR layer is fabricated on the second semiconductor layer and the surface of the step structure by using a plasma enhanced chemical vapor deposition (PECVD) technique or an atomic layer deposition (ALD) technique to form a reflective layer; the reflective layer is patterned to form a first through hole and a second through hole.

[0167] S25 , manufacturing a first electrode pad and a second electrode pad, wherein the first electrode pad is connected to the first electrode through the first through hole, and the second electrode pad is connected to the second electrode through the second through hole.

[0168] The projection of the first through hole on the bottom surface of the first semiconductor layer is located at the edge of the projection of the first electrode pad on the bottom surface of the first semiconductor layer, and the bottom surface of the first semiconductor layer is the side away from the active layer.

[0169] Exemplarily, the projection of the first electrode pad on the bottom surface of the first semiconductor layer is a first rectangle, and the projection of the first through hole on the bottom surface of the first semiconductor layer is located at a corner of the first rectangle.

[0170] In the embodiment of the present disclosure, the first through hole is disposed at a corner of the first electrode pad, so that the influence of the depression on the surface of the first electrode pad caused by the first through hole on the welding yield can be minimized.

[0171] exist Figure 4 In the illustrated implementation, the projection of the first through hole on the bottom surface of the first semiconductor layer is located at a corner of the first rectangle away from the second electrode pad.

[0172] In other implementations, the projection of the first through hole on the bottom surface of the first semiconductor layer may also be located at the center of one side of the first rectangle.

[0173] In other embodiments, the projection of the first electrode pad on the bottom surface of the first semiconductor layer may also be other shapes, such as a circle, other polygons, etc.

[0174] like Figure 4 As shown, the bottom surface of the first semiconductor layer is a second rectangle, and the projection of the step surface of the step structure on the bottom surface of the first semiconductor layer is located at a corner of the second rectangle.

[0175] In this implementation, the step structure is opened at a corner of the first semiconductor layer, and the area occupied by the step structure is small, so that the overall light-emitting area of ​​the light-emitting diode is larger.

[0176] exist Figure 4 In the structure shown, the step structure is in the shape of a notch, and the side wall of the step structure is in an arc shape.

[0177] exist Figure 4 In the structure shown, the projection of the first through hole is a circle, and the circular through hole and the arc are concentrically arranged.

[0178] In other implementations, the sidewall of the step structure and / or the first through hole may also be in other shapes.

[0179] In other embodiments, the step structure may also have a larger area, which is not limited in the embodiments of the present disclosure.

[0180] In one example, step S25 includes:

[0181] In the first step, the metal stack is deposited.

[0182] The metal stack is connected to the first electrode through the first through hole, and is connected to the second electrode through the second through hole.

[0183] In the embodiment of the present disclosure, the metal stack includes a Cr layer, an Al layer, a Ti layer, a Ni layer, and an Au alloy layer stacked in sequence.

[0184] In one example, the thickness of the Cr layer is 80-120 nm, the thickness of the Al layer is 2500-3500 nm, the thickness of the Ti layer is 450-550 nm, the thickness of the Ni layer is 1800-2200 nm, and the thickness of the Au alloy layer is 18000-22000 nm.

[0185] Exemplarily, the thickness of the Cr layer is 100 nm, the thickness of the Al layer is 3000 nm, the thickness of the Ti layer is 500 nm, the thickness of the Ni layer is 2000 nm, and the thickness of the Au alloy layer is 20000 nm.

[0186] The second step is to form a photoresist mask layer on the metal stack.

[0187] The third step is to pattern the metal stack under the protection of the photoresist mask layer to obtain the first electrode pad and the second electrode pad.

[0188] Exemplarily, the metal stack may be patterned by dry etching, for example, using etching gas Cl2+BCl3. In the above etching process, the temperature is room temperature, the pressure is 4 mTorr, and the etching rate is 100 angstroms / second.

[0189] The photoresist mask layer may be a positive photoresist mask layer.

[0190] The fourth step is to remove the photoresist mask layer.

[0191] In the embodiment of the present disclosure, the first electrode and the first electrode pad form a first electrode structure, and the second electrode and the second electrode pad form a second electrode structure.

[0192] S26. Make a first retaining wall structure and a second retaining wall structure, wherein the first retaining wall structure is located on the surface of the first electrode pad and arranged along the edge of the first electrode pad, and the second retaining wall structure is located on the surface of the second electrode pad and arranged along the edge of the second electrode pad.

[0193] In this implementation, by arranging a retaining wall structure at the edge of the pad surface, the easily flowing welding material can be restricted to the middle of the pad surface during the welding process and will not flow outside the pad, thereby ensuring the welding quality and avoiding the adverse effects caused by overflow of the welding material.

[0194] In a possible implementation of the present disclosure, the first retaining wall structure 201 and the second retaining wall structure 202 are silicon oxide structures.

[0195] Exemplarily, the first retaining wall structure 201 and the second retaining wall structure 202 are silicon dioxide structures.

[0196] In this implementation, silicon oxide is used to make the retaining wall structure, which is easy to manufacture and can be attached to the surface of the pad, and can also block the welding material.

[0197] In other implementations, the first retaining wall structure 201 and the second retaining wall structure 202 may also be structures made of other materials, which is not limited.

[0198] See again Figure 5 The first retaining wall structure 201 and the second retaining wall structure 202 are both annular step retaining wall structures, and the step surfaces of the step retaining wall structures face the center of the ring.

[0199] In this implementation, the step structure can better block the welding material and ensure that the welding material is located at the center of the welding surface.

[0200] See again Figure 5 The first retaining wall structure 201 and the second retaining wall structure 202 are both three-step retaining wall structures, and the height of each step structure in the three-step retaining wall structure is 0.2 to 0.4 microns.

[0201] In this implementation, the above-mentioned height can meet the demand for the amount of welding materials, while not being too high to affect the overall thickness of the light-emitting diode.

[0202] Exemplarily, the height of each step structure in the three-step step retaining wall structure is 0.3 micrometers.

[0203] In the embodiment of the present disclosure, the width of the first retaining wall structure 201 and the second retaining wall structure 202 may be 4 to 6 micrometers, for example, 5 micrometers.

[0204] In other implementations, the first retaining wall structure 201 and the second retaining wall structure 202 may also be non-step structures, which is not limited to this.

[0205] Exemplarily, step S26 may include:

[0206] Forming an insulating film layer on the first electrode pad and the second electrode pad;

[0207] The insulating film layer is patterned to obtain a first retaining wall structure and a second retaining wall structure.

[0208] The step of patterning the insulating film layer includes:

[0209] The insulating film layer is subjected to multiple patterning processes to form the first retaining wall structure and the second retaining wall structure in a step structure shape.

[0210] S27, manufacturing a passivation layer, wherein the passivation layer covers the sidewalls of the epitaxial structure and the reflective layer.

[0211] In one example, step S26 includes:

[0212] A SiO2 layer is fabricated on the surface of the step structure by using a plasma enhanced chemical vapor deposition (PECVD) technique or an atomic layer deposition (ALD) technique; the SiO2 layer is patterned to obtain a passivation layer.

[0213] In the embodiment of the present disclosure, the passivation layer may also be a transparent insulating material such as Al2O3, and the present disclosure does not limit the material of the passivation layer.

[0214] Optionally, after the above steps, the method may further include: thinning the substrate, wherein the thickness of the substrate after thinning is 400-600 microns, for example, 500 microns. After thinning, subsequent processes of the light emitting diode are performed to obtain a light emitting diode chip.

[0215] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A light emitting diode, characterized in that: The light emitting diode comprises: an epitaxial structure (1000), a first electrode (105), a second electrode (106), a reflective layer (107), a first electrode pad (108) and a second electrode pad (109); The epitaxial structure (1000) comprises a first semiconductor layer (101), an active layer (102) and a second semiconductor layer (103) which are stacked in sequence, the first semiconductor layer (101), the active layer (102) and the second semiconductor layer (103) forming a step structure, the first electrode (105) being located on a step surface (120) of the step structure, the second electrode (106) being located on a surface of the second semiconductor layer (103), and the reflective layer (107) covering the step structure and the first electrode (105) and the second electrode (106); The reflective layer (107) has a first through hole (111) and a second through hole (112); the first electrode pad (108) is connected to the first electrode (105) through the first through hole (111); and the second electrode pad (109) is connected to the second electrode (106) through the second through hole (112); The projection of the first through hole (111) on the bottom surface of the first semiconductor layer (101) is located at the edge of the projection of the first electrode pad (108) on the bottom surface of the first semiconductor layer (101), and the bottom surface of the first semiconductor layer (101) is the side away from the active layer (102).

2. The light emitting diode according to claim 1, characterized in that: The projection of the first electrode pad (108) on the bottom surface of the first semiconductor layer (101) is a first rectangle, and the projection of the first through hole (111) on the bottom surface of the first semiconductor layer (101) is located at a corner of the first rectangle.

3. The light emitting diode according to claim 1, characterized in that: The bottom surface of the first semiconductor layer (101) is a second rectangle, and the projection of the step surface (120) of the step structure on the bottom surface of the first semiconductor layer (101) is located at a corner of the second rectangle.

4. The light emitting diode according to any one of claims 1 to 3, characterized in that: The light-emitting diode further comprises: a first retaining wall structure (201) and a second retaining wall structure (202), wherein the first retaining wall structure (201) is located on the surface of the first electrode pad (108) and arranged along the edge of the first electrode pad (108), and the second retaining wall structure (202) is located on the surface of the second electrode pad (109) and arranged along the edge of the second electrode pad (109).

5. The light emitting diode according to claim 4, characterized in that: The first retaining wall structure (201) and the second retaining wall structure (202) are silicon oxide structures.

6. The light emitting diode according to claim 4, characterized in that: The first retaining wall structure (201) and the second retaining wall structure (202) are both annular step retaining wall structures, and the step surfaces of the step retaining wall structures face the center of the ring.

7. The light emitting diode according to claim 6, characterized in that: The first retaining wall structure (201) and the second retaining wall structure (202) are both three-step retaining wall structures, and the height of each step structure in the three-step retaining wall structure is 0.2 to 0.4 micrometers.

8. A method for preparing a light emitting diode, characterized in that: The method comprises: forming a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence, wherein the second semiconductor layer, the active layer, and the first semiconductor layer constitute an epitaxial structure; Performing a patterning process on the epitaxial structure to form a step structure; Manufacturing a first electrode and a second electrode, wherein the first electrode is located on a step surface of the step structure, and the second electrode is located on a surface of the second semiconductor layer; Manufacturing a reflective layer, wherein the reflective layer covers the step structure and the first electrode and the second electrode, and the reflective layer has a first through hole and a second through hole; A first electrode pad and a second electrode pad are manufactured, wherein the first electrode pad is connected to the first electrode through the first through hole, and the second electrode pad is connected to the second electrode through the second through hole; a projection of the first through hole on the bottom surface of the first semiconductor layer is located at an edge of a projection of the first electrode pad on the bottom surface of the first semiconductor layer, and the bottom surface of the first semiconductor layer is a side away from the active layer.

9. The method for preparing a light emitting diode according to claim 8, characterized in that: The method further comprises: Forming an insulating film layer on the first electrode pad and the second electrode pad; The insulating film layer is patterned to obtain a first retaining wall structure and a second retaining wall structure, wherein the first retaining wall structure is located on the surface of the first electrode pad and arranged along the edge of the first electrode pad, and the second retaining wall structure is located on the surface of the second electrode pad and arranged along the edge of the second electrode pad.

10. The method for preparing a light emitting diode according to claim 9, characterized in that: The step of patterning the insulating film layer comprises: The insulating film layer is subjected to multiple patterning processes to form the first retaining wall structure and the second retaining wall structure in a step structure shape.

Images