Display device

Abstract

A display device is provided. The display device includes a first sub-display area and a second sub-display area adjacent to each other and a main display area around the first sub-display area and the second sub-display area, a plurality of pixel electrodes in the main display area and spaced apart from each other, a plurality of first sub-pixel electrodes in the first sub-display area and spaced apart from each other, and a plurality of second sub-pixel electrodes in the second sub-display area and spaced apart from each other, a plurality of first replica pixel electrodes in the first sub-display area and connected to the plurality of first sub-pixel electrodes through a plurality of first bridge electrodes, a plurality of planarization patterns in the second sub-display area, a plurality of second sub-pixel electrodes and a plurality of second replica pixel electrodes in the second sub-display area and overlapping the plurality of planarization patterns; and a plurality of second bridge electrodes overlapping the plurality of second sub-pixel electrodes or the plurality of second replica pixel electrodes.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0144552 filed in the Korean Intellectual Property Office on October 26, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] With the development of the information society, the demand for display devices for displaying images has increased in various forms. For example, display devices are being applied to various electronic devices, such as smart phones, digital cameras, notebook computers, navigation devices, and smart televisions (TVs). The display device can be a flat panel display device, such as a liquid crystal display (LCD) device, a field emission display (FED) device, and an organic light emitting display device. Among these flat panel display devices, a light emitting display device can display an image without a backlight unit that provides light to the display panel by including a light emitting element that allows the pixels of the display panel to emit light by themselves.

[0005] The display device may include pixels emitting light, scan lines, data lines, and power lines for driving the pixels, a scan driving unit outputting scan signals to the scan lines, and a display driving unit outputting data voltages to the data lines. Summary of the invention

[0006] Aspects and features of embodiments of the present disclosure provide a display device including a bridge pattern arranged between adjacent display areas.

[0007] Aspects and features of embodiments of the present disclosure also provide a display device including pixels having different structures and capable of obtaining flatness of pixel electrodes for light emitting elements included in the pixels connected by a bridge pattern.

[0008] However, the aspects and features of the embodiments of the present disclosure are not limited to the aspects and features described herein. By referring to the detailed description of the present disclosure given below, the above and other aspects and features of the embodiments of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs.

[0009] According to one or more embodiments of the present disclosure, a display device includes a first sub-display area and a second sub-display area adjacent to each other and a main display area around the first sub-display area and the second sub-display area, a plurality of pixel electrodes in the main display area and spaced apart from each other, a plurality of first sub-pixel electrodes in the first sub-display area and spaced apart from each other, a plurality of first replica pixel electrodes in the first sub-display area and connected to the plurality of first sub-pixel electrodes through a plurality of first bridging electrodes, a plurality of planarizing patterns in the second sub-display area, a plurality of second sub-pixel electrodes and a plurality of second replica pixel electrodes in the second sub-display area and overlapping with the plurality of planarizing patterns, and a plurality of second bridging electrodes overlapping with the plurality of second sub-pixel electrodes or the plurality of second replica pixel electrodes.

[0010] The first sub-pixel electrode, the first replica pixel electrode, and the first bridge electrode may be integrated together in the first sub-display area.

[0011] The second bridge electrode may overlap with a different planarization pattern.

[0012] Each of the plurality of second bridge electrodes may be in direct contact with one of the plurality of planarization patterns.

[0013] In a plan view, the planarization pattern may have a larger area than both the second sub-pixel electrode and the second replica pixel electrode.

[0014] The planarization pattern may include a first planarization pattern and a second planarization pattern directly on the first planarization pattern; and the second planarization pattern may cover an outer surface of the first planarization pattern.

[0015] The display device may also include a plurality of first bridging patterns, a plurality of second bridging patterns, and a plurality of contact patterns, wherein the plurality of first bridging patterns extend in one direction in the second sub-display area, the plurality of second bridging patterns extend in one direction in the first sub-display area, and the plurality of contact patterns overlap the plurality of first bridging patterns and the plurality of second bridging patterns near a boundary between the first sub-display area and the second sub-display area.

[0016] The display device may also include a plurality of first sub-pixel circuits and a plurality of second sub-pixel circuits in the first sub-display area, wherein the plurality of first sub-pixel electrodes may overlap with the plurality of first sub-pixel circuits, and at least some of the plurality of first replica pixel electrodes may overlap with the plurality of second sub-pixel circuits.

[0017] Each of the plurality of second bridge patterns may be electrically connected to one of the plurality of second sub-pixel circuits.

[0018] Each of the plurality of first bridge patterns may be connected to one of the plurality of planarization patterns.

[0019] Each of some of the plurality of second bridge patterns may overlap with the first sub-pixel electrode but may not be connected to the first sub-pixel electrode.

[0020] The display device may also include a first insulating layer in the main display area and the first sub-display area and including an organic insulating material, and an interlayer insulating layer on the first insulating layer in the main display area and the first and second sub-display areas, wherein the first insulating layer does not overlap with the plurality of planarization patterns, the plurality of second sub-pixel electrodes, and the plurality of second replica pixel electrodes.

[0021] In the second sub display area, the interlayer insulating layer may overlap the plurality of planarization patterns, the plurality of second sub-pixel electrodes, and the plurality of second replica pixel electrodes.

[0022] The interlayer insulating layer may overlap the plurality of contact patterns.

[0023] The display device may also include a first pixel defining film in the main display area and the first sub-display area and having multiple openings overlapping with multiple pixel electrodes, multiple first sub-pixel electrodes and multiple first replica pixel electrodes, and a second pixel defining film in the second sub-display area and covering edges of multiple second sub-pixel electrodes and edges of multiple second replica pixel electrodes.

[0024] According to one or more embodiments of the present disclosure, a display device includes a substrate having a first sub-display area and a second sub-display area adjacent to each other and a main display area around the first sub-display area and the second sub-display area, a semiconductor layer including a plurality of active layers in the main display area and the first sub-display area and a plurality of first bridging patterns in the second sub-display area on the substrate, a first insulating layer on the semiconductor layer, a first conductive layer including a plurality of first connecting electrodes in the first sub-display area and a plurality of first planarization patterns in the second sub-display area on the first insulating layer, a second insulating layer on the first conductive layer and not in the second sub-display area, a plurality of second connecting electrodes in the first sub-display area on the second insulating layer, A second conductive layer including a plurality of second planarizing patterns on the plurality of first planarizing patterns in the second sub-display area, an interlayer insulating layer on the second conductive layer, a plurality of second bridging patterns on the interlayer insulating layer in the first sub-display area, a plurality of bridging electrodes on the plurality of second planarizing patterns in the second sub-display area, a third insulating layer on the interlayer insulating layer and the plurality of second bridging patterns in the main display area and the first sub-display area, a plurality of pixel electrodes on the third insulating layer in the main display area, a plurality of first sub-pixel electrodes and a plurality of first replica pixel electrodes on the third insulating layer in the first sub-display area, and a plurality of second sub-pixel electrodes and a plurality of second replica pixel electrodes on the plurality of bridging electrodes in the second sub-display area.

[0025] The bridge electrode may include first portions on different second planarization patterns and a second portion connecting the first portions, and the second sub-pixel electrode and the second duplicate pixel electrode may be on different first portions of the bridge electrode, respectively.

[0026] A width of the second planarization pattern may be greater than a width of the second sub-pixel electrode and a width of the second replica pixel electrode.

[0027] The first connection electrode and the second connection electrode may be electrically connected to the first sub-pixel electrode, and the first replica pixel electrode may be integrated with the first sub-pixel electrode.

[0028] The semiconductor layer may include a first semiconductor layer including a first active layer, and a second semiconductor layer including a second active layer and located between the first semiconductor layer and the first insulating layer and including a plurality of first bridge patterns.

[0029] According to the foregoing and other embodiments of the present disclosure, the display device can ensure the transmittance of the sub-display region where the optical device is located, and can ensure the flatness for the pixel electrode even if the organic insulating layer is not provided.

[0030] It should be noted that the effects, aspects, and features of the embodiments of the present disclosure are not limited to the above-mentioned effects, aspects, and features, and other effects, aspects, and features of the embodiments of the present disclosure will be apparent from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0032] Figure 1 is a perspective view of a display device according to one or more embodiments of the present disclosure;

[0033] Figure 2 yes Figure 1 A plan view of a display device;

[0034] Figure 3 is along Figure 2 A cross-sectional view taken along line AA';

[0035] Figure 4 is a plan view of a display panel according to one or more embodiments of the present disclosure;

[0036] Figure 5 is a circuit diagram of a sub-pixel according to one or more embodiments of the present disclosure;

[0037] Figure 6 It is shown Figure 1 A plan view of an arrangement of pixels in a main display area and a sub-display area of ​​a display device;

[0038] Figure 7 It is shown that the Figure 6 a plan view of an arrangement of pixel electrodes in sub-pixels in a main display area;

[0039] Figure 8 It is shown that the Figure 6 a plan view of an arrangement of pixel electrodes in sub-pixels in a sub-display area;

[0040] Fig. 9 It is shown Figure 1 A cross-sectional view of a main display area of ​​a display device;

[0041] Fig.10 and Fig.11 It is shown Figure 1 A cross-sectional view of a sub-display area of ​​a display device;

[0042] Figures 12 to 19 It is shown that the arrangement Figure 1 A plan view of multiple layers in a sub-display area of ​​a display device; and

[0043] Fig. 20 is a cross-sectional view illustrating a sub display region of a display device according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0044] Hereinafter, the present disclosure will now be described more fully with reference to the accompanying drawings showing embodiments of the present disclosure. However, the present disclosure may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0045] It will also be understood that when a layer is referred to as being 'on' another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like reference numerals refer to like components throughout the specification.

[0046] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present disclosure, the first element discussed below can be referred to as the second element. Similarly, the second element can also be referred to as the first element.

[0047] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0048] Figure 1 is a perspective view of a display device according to one or more embodiments of the present disclosure.

[0049] Reference Figure 1 The display device 10 is a device for displaying videos and / or still images, and can be used as a display screen for portable electronic devices (such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, e-book readers, portable multimedia players (PMPs), navigation devices, or ultra mobile PCs (UMPCs)) and various other products (such as televisions, notebook computers, monitors, billboards, and / or Internet of Things (IoT) devices).

[0050] In one or more embodiments, the display device 10 may be a light-emitting display device, such as an organic light-emitting display device including an organic light-emitting diode (OLED), a quantum dot light-emitting display device including a quantum dot emission layer, an inorganic light-emitting display device including an inorganic semiconductor, or an ultra-small light-emitting display device using a micro or nano light-emitting diode (micro-LED or nano-LED). Hereinafter, the display device 10 will be described as, for example, an organic light-emitting display device.

[0051] In one or more embodiments, the display device 10 may be formed to be flat. For example, the display device 10 may be formed to be substantially flat in a plane defined by the first direction DR1 and the second direction DR2, and may have a suitable thickness (e.g., a predetermined thickness or height) in the third direction DR3. In one or more embodiments, the display device 10 may be at least partially curved, for example, in an edge region. In addition, the display device 10 may be formed to be curved or flexible, such as bendable, foldable, and / or rollable.

[0052] In one or more embodiments, based on the image display surface of the display device 10, the first direction DR1 may be a length direction, a column direction, or a longitudinal direction, the second direction DR2 may be a direction crossing the first direction DR1, for example, a width direction, a row direction, or a horizontal direction, and the third direction DR3 may be a thickness or height direction of the display device 10.

[0053] The display device 10 may include a display panel 100 , a driving unit 200 , and a circuit board 300 .

[0054] The display panel 100 may have a main area MA including a display area DA displaying an image, and a sub area SBA positioned on one side of the main area MA.

[0055] The main area MA may include a display area DA and a non-display area NA around the display area DA along an edge or periphery of the display area DA (e.g., surrounding the display area DA). The display area DA may be located in the middle of the main area MA and may occupy most of the main area MA. The non-display area NA may be located at an edge of the main area MA and may be adjacent to the sub-area SBA.

[0056] The display area DA may be a region where pixels ( Figure 4 In one or more embodiments, a sensing pattern (e.g., a touch electrode) may be provided in the display area DA for detecting an input (such as a touch input), and the display area DA may include a sensing area for detecting a touch input via the sensing pattern.

[0057] In one or more embodiments, the display area DA may have long sides in the first direction DR1 and short sides in the second direction DR2, and may be formed as a plane having a substantially rectangular shape. Corners where the long sides and short sides of the display area DA intersect may be rounded or formed as right angles. The shape of the display area DA may vary. Alternatively, the display area DA may be formed in a non-rectangular polygonal shape, a circular shape, and / or an elliptical shape.

[0058] The display area DA may include a main display area MDA and a sub display area SDA. The sub display area SDA, which is an area where components for adding various functions to the display device 10 are arranged, may correspond to a component area.

[0059] The non-display area NA may be positioned immediately around the display area DA. The non-display area NA may surround the display area DA. An embedded circuit may be arranged in the non-display area NA. For example, an embedded circuit including a scan driving circuit may be positioned in the non-display area NA positioned on one side (e.g., the left side or the right side) or both sides of the display area DA.

[0060] The sub-region SBA may be positioned on one side of the main region MA. For example, the sub-region SBA may be a region protruding from one side of the main region MA in the first direction DR1. For example, the sub-region SBA may protrude from the bottom of the main region MA in the first direction DR1. In one or more embodiments, the sub-region SBA may have a narrower width than the main region MA. For example, the sub-region SBA may have a smaller width than the main region MA in the second direction DR2.

[0061] Wiring and pads may be arranged in the sub-area SBA. For example, wiring and pads connected to the pixels PX and / or embedded circuits positioned in the main area MA and wiring and pads connected to the driving unit 200 and / or circuit board 300 positioned in the sub-area SBA may be arranged in the sub-area SBA. The term "connect" or "connection" may cover both electrical connection and / or physical connection.

[0062] In one or more embodiments, the driving unit 200 (eg, a display driving circuit) may be mounted in the sub-area SBA. The circuit board 300 may be disposed on a portion of the sub-area SBA.

[0063] The driving unit 200 may include a data driving circuit for operating the pixel PX. In one or more embodiments, the driving unit 200 may be formed as an integrated circuit (IC) chip and may be arranged in the sub-area SBA. In one or more embodiments, the driving unit 200 may be arranged on the circuit board 300 in the sub-area SBA, or on another circuit board connected to the display panel 100 through the circuit board 300.

[0064] The circuit board 300 may be arranged on a portion of the sub-area SBA. For example, the circuit board 300 may be bonded to a pad positioned on a portion (e.g., a bottom edge) of the sub-area SBA, and may supply or transmit a power voltage and a driving signal to the display panel 100. For example, the circuit board 300 may supply input image data (e.g., digital image data), a driving signal including a timing signal, and a driving voltage to the display panel 100. The circuit board 300 may be a flexible printed circuit board (FPCB), a rigid printed circuit board (PCB), or a flexible film such as a chip on film (COF), but the present disclosure is not limited thereto.

[0065] Figure 2 yes Figure 1 A plan view of a display device. Figure 3 is along Figure 2 A cross-sectional view taken along line AA'.

[0066] Figure 1 The display device 10 is shown in an unfolded, non-bent state, and Figure 2 and Figure 3 The display device 10 is shown in a bent state in the sub-area SBA. Figure 1 A sub-area SBA is shown which develops parallel to the main area MA, and Figure 2 and Figure 3 A portion of the sub-area SBA is shown in a bent state.

[0067] Reference Figure 2 and Figure 3, the display panel 100 may include a substrate 110 including a main area MA and a sub-area SBA, and a circuit layer 120, a light emitting element layer 130, an encapsulation layer 140, a touch sensing layer TSU, and a color filter layer CFL sequentially arranged on the substrate 110. The circuit layer 120 may be positioned in both the main area MA and the sub-area SBA on the substrate 110. The light emitting element layer 130 and the encapsulation layer 140 may be arranged on portions of the substrate 110 and the circuit layer 120. For example, the light emitting element layer 130 and the encapsulation layer 140 may be positioned in the main area MA.

[0068] In one or more embodiments, the display device 10 may further include additional components disposed on the display panel 100. For example, the display device 10 may further include at least one of a polarizing layer and a protective layer (e.g., a window) disposed on the encapsulation layer 140. The polarizing layer and / or the protective layer may be integrated with the display panel 100, or may be produced separately from the display panel 100 and then attached to the display panel 100 via an adhesive layer.

[0069] The substrate 110 may include an insulating material such as a polymer resin. For example, the substrate 110 may be formed of polyimide or another insulating material. The substrate 110 may be a flexible substrate that is bendable, foldable, and / or rollable. Alternatively, the substrate 110 may include an insulating material such as glass.

[0070] The circuit layer 120 may include pixel circuits and wiring. For example, the circuit layer 120 may include circuit elements (e.g., pixel transistors and / or capacitors) constituting the pixel circuits of the pixels PX and wiring connected to the pixels PX. In one or more embodiments, the circuit layer 120 may also include circuit elements constituting embedded circuits (such as scan drive circuits) and wiring connected to the embedded circuits.

[0071] The light emitting element layer 130 may include a light emitting element arranged in a light emitting region of the pixel PX. For example, each of the pixels PX may include at least one light emitting element and a pixel circuit connected to the light emitting element. Each of the pixels PX may be positioned in a pixel region including a light emitting region in which the light emitting element is arranged and a pixel circuit region in which the pixel circuit is arranged. The light emitting region and the pixel circuit region of each of the pixels PX may overlap each other, but the present disclosure is not limited thereto.

[0072] The circuit layer 120 and the light emitting element layer 130 have been described as separate layers, but the present disclosure is not limited thereto. Alternatively, the circuit layer 120 and the light emitting element layer 130 may be integrated together.

[0073] The encapsulation layer 140 covers the light emitting element layer 130 and may extend to the non-display area NA to contact the circuit layer 120. In one or more embodiments, the encapsulation layer 140 may have a multilayer structure including at least two overlapping inorganic encapsulation films and at least one organic encapsulation film interposed therebetween.

[0074] The touch sensing layer TSU may be disposed on the encapsulation layer 140. The touch sensing layer TSU may include a plurality of touch electrodes for detecting a user's touch in a capacitive manner and touch lines connecting the touch electrodes to the touch driving unit 400. For example, the touch sensing layer TSU may sense the user's touch using a mutual capacitance method or a self capacitance method.

[0075] In one or more embodiments, the touch sensing layer TSU may be disposed on a separate substrate disposed on the display panel 100. In the present embodiment, the separate substrate may be a base member encapsulating the display panel 100.

[0076] The touch electrodes of the touch sensing layer TSU may be arranged in a touch sensor area overlapping the display area DA. The touch wires of the touch sensing layer TSU may be arranged in a touch peripheral area overlapping the non-display area NA.

[0077] In one or more embodiments, the display device 10 may further include an optical device 500. The optical device 500 may be arranged in the sub display area SDA. The optical device 500 may emit or receive infrared light, ultraviolet light, and / or visible light. For example, the optical device 500 may be an optical sensor capable of sensing light incident on the display device 10, such as a proximity sensor, an ambient light sensor, a camera sensor, and / or an image sensor.

[0078] The color filter layer CFL may be arranged on the touch sensing layer TSU. The color filter layer CFL may include a plurality of color filters corresponding to their respective light emitting regions. Each of the color filters may selectively transmit light of a specific wavelength, and may block or absorb light of other wavelengths. The color filter layer CFL may absorb some of the light entering from outside the display device 10, thereby reducing reflected light caused by external light. Therefore, the color filter layer CFL can prevent or reduce color distortion caused by reflection of external light.

[0079] When the color filter layer CFL is directly disposed on the touch sensing layer TSU, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display panel 100 can be relatively thin.

[0080] In one or more embodiments, the display panel 100 may be bent in the bending area BA. The bending area BA may be part of the sub area SBA and may be spaced apart from the main area MA.

[0081] The substrate 110 and the circuit layer 120 may be bent in the bending area BA corresponding to a portion of the sub-area SBA. Accordingly, the size of the bezel area that can be perceived by the user as the non-display area NA can be reduced or minimized.

[0082] Figure 4 is a plan view of a display panel according to one or more embodiments of the present disclosure. Figure 4 The display panel 100 is shown in an unfolded, unbent state.

[0083] Reference Figure 4 , the display panel 100 may include a main area MA and a sub-area SBA. The main area MA may include a display area DA and a non-display area NA, and the sub-area SBA may include a dam area BNKA, a driving circuit mounting area ICA, and a pad area PA.

[0084] The display area DA may be an area where pixels PX are arranged. The pixels PX and wirings (or portions of wirings) connected to the pixels PX may be arranged in the display area DA.

[0085] The pixel PX may be provided on the circuit layer 120 (eg, referring to Figure 3 ) and the light emitting element layer 130 (for example, see Figure 3 ). For example, the pixel PX may include a pixel circuit ( Figure 5 The “pixel circuit PXC”) and the light emitting elements ( Figure 5 “Light-emitting element EL”).

[0086] Each of the pixels PX may include at least two sub-pixels SPX (eg, referring to Figure 5 For example, the pixel PX may include a first color sub-pixel SPX1 emitting a first color light (eg, red light), a second color sub-pixel SPX2 emitting a second color light (eg, green light), and a third color sub-pixel SPX3 emitting a third color light (eg, blue light).

[0087] At least one first color sub-pixel SPX1, at least one second color sub-pixel SPX2, and at least one third color sub-pixel SPX3 adjacent to each other may form a unit pixel PX (may be referred to as pixel PX for short). For example, one first color sub-pixel SPX1, two second color sub-pixels SPX2, and one third color sub-pixel SPX3 adjacent to each other may form a unit pixel PX. Each unit pixel PX may emit light of various colors (including white light) due to the mixing of light beams emitted from its sub-pixels (first color sub-pixel SPX1, second color sub-pixel SPX2, and third color sub-pixel SPX3). In one or more embodiments, the first color sub-pixel SPX1 and the third color sub-pixel SPX3 may be arranged alternately along the first direction DR1 and / or the second direction DR2, and the second color sub-pixel SPX2 may be arranged continuously and / or sequentially along the first direction DR1. The type, shape, and / or layout of the sub-pixels (first color sub-pixel SPX1, second color sub-pixel SPX2, and third color sub-pixel SPX3) may vary. Additionally, the type, number, ratio, and / or layout of the sub-pixels (the first color sub-pixel SPX1 , the second color sub-pixel SPX2 , and the third color sub-pixel SPX3 ) forming each unit pixel PX may also vary.

[0088] The encapsulation layer 140 (eg, see Figure 3 ) may be disposed on the pixel PX. For example, the encapsulation layer 140 may be provided at least in the display area DA to cover the pixel PX, and a portion of the encapsulation layer 140 may extend into the non-display area NA.

[0089] The wiring may be provided in the circuit layer 120 and may be located in both the display area DA and the non-display area NA. In addition, the wiring may also be located in the sub-area SBA. For example, the wiring may extend from the sub-area SBA through the non-display area NA to the display area DA.

[0090] The non-display area NA may be positioned around the display area DA. For example, the non-display area NA may be an edge area of ​​the main area MA positioned on the periphery of the display area DA.

[0091] The non-display area NA may include a dam area DAMA spaced apart from the display area DA, a first non-display area NA1 disposed between the display area DA and the dam area DAMA, and a second non-display area NA2 disposed on the periphery of the dam area DAMA. The dam area DAMA may be an area where a dam is disposed around the display area DA (e.g., surrounding the display area DA). The second non-display area NA2 may include an inorganic encapsulation area IEA (also referred to as a bonding area) where an inorganic encapsulation layer (e.g., an inorganic encapsulation film) of the encapsulation layer 140 is bonded together.

[0092] The sub-region SBA may include a dam region BNKA, a driving circuit mounting region ICA, and a pad region PA sequentially arranged on one side of the main region MA. Wiring (or portions of wiring), dams, and pads PD may be arranged in the sub-region SBA. At least some of the wirings may extend into the main region MA and may be connected to the pixels PX.

[0093] The dam area BNKA may be an area where a dam including at least one organic layer is arranged. In one or more embodiments, the dam area BNKA may include a bending area BA. For example, the dam area BNKA may include a bending area BA spaced apart from the main area MA and a first edge area BEA1 and a second edge area BEA2 positioned on both sides of the bending area BA in the first direction DR1. The dam may be provided in the bending area BA and its surrounding areas (e.g., the first edge area BEA1 and the second edge area BEA2 of the dam area BNKA) to cover the wiring passing through the bending area BA. The display panel 100 may be bent in the bending area BA so that a portion of the sub-area SBA may be positioned on the rear side of the main area MA.

[0094] The driving circuit mounting area ICA may be an area where the driving unit 200 is arranged. Pads for connecting at least some wirings to the driving unit 200 may be arranged in the driving circuit mounting area ICA. For example, input pads for connecting the driving unit 200 to specific pads (e.g., data input pads) of the pad area PA and output pads for connecting the driving unit 200 to the pixels PX may be arranged in the driving circuit mounting area ICA.

[0095] In one or more embodiments, the driving unit 200 may not be disposed on the display panel 100. In this case, the display panel 100 may not include the driving circuit mounting area ICA, and only wiring may be disposed between the dam area BNKA and the pad area PA.

[0096] The pad area PA may be a region where a pad for connecting the display panel 100 and / or the driving unit 200 to the circuit board 300 (eg, referring to Figure 3 ) of the pad area PA. The circuit board 300 may be arranged in the pad area PA or bonded on the pad area PA.

[0097] The pads PD including power pads and signal pads connected to the pixels PX, the driving unit 200, and / or the embedded circuits may be arranged in the pad area PA. The power voltage for driving the pixels PX, the driving unit 200, and / or the embedded circuits may be supplied to the power pads. The driving signals and / or image data for driving the pixels PX, the driving unit 200, and / or the embedded circuits may be provided to the signal pads (e.g., in the pads PD). The type, position, layout, and / or number of the pads PD may vary.

[0098] Figure 5 is a circuit diagram of a sub-pixel according to one or more embodiments of the present disclosure.

[0099] Reference Figure 1 , Figure 4 and Figure 5 , the pixel circuit (also referred to as a pixel driving unit) PXC of the pixel PX of the display device 10 may include a first transistor T1 to a seventh transistor T7. The scan line SL connected to the pixel PX may include a first scan line SL1, a second scan line SL2, a third scan line SL3, and a fourth scan line SL4, and the power line PL connected to the pixel PX may include a first pixel power line VDL, a second pixel power line VSL, a first initialization power line VIL, and a second initialization power line VAIL. In addition, the pixel circuit PXC may also be connected to the emission control line ECL.

[0100] The sub-pixel SPX may include a light emitting unit EMU including at least one light emitting element EL and a pixel circuit PXC connected to the light emitting unit EMU.

[0101] The light emitting element EL may be connected between the second pixel power line VSL to which the second pixel power voltage ELVSS is applied and the pixel circuit PXC. In one or more embodiments, the second pixel power voltage ELVSS may be a low-voltage pixel driving voltage (e.g., a low-level pixel driving voltage). The light emitting element EL, which is the light source of the pixel PX, may receive a driving current supplied from the pixel circuit PXC and may emit light.

[0102] The light emitting element EL may be an organic light emitting diode (OLED), but the present disclosure is not limited thereto. Alternatively, the light emitting element EL may be an inorganic light emitting element, a quantum dot light emitting element, or another type of light emitting element.

[0103] The pixel circuit PXC may control the driving current supplied to the light emitting element EL, and thereby may control the emission timing and brightness of the light emitting element EL. The pixel circuit PXC may include one or more pixel transistors T and a capacitor Cst. In one or more embodiments, the pixel circuit PXC may include a plurality of pixel transistors T, and the plurality of pixel transistors T may include a first transistor T1 to a seventh transistor T7.

[0104] The first transistor T1 may include a gate electrode connected to the first node N1, a first electrode electrically connected to the first pixel power line VDL through a fifth transistor T5, and a second electrode electrically connected to the light emitting unit EMU through a sixth transistor T6. One of the first electrode and the second electrode of the first transistor T1 may be a source electrode, and the other electrode may be a drain electrode. The first transistor T1 may control a source-drain current (hereinafter referred to as a driving current) flowing between the first electrode and the second electrode of the first transistor T1 based on a voltage applied to the gate electrode of the first transistor T1 (e.g., a voltage of the first node N1 corresponding to a voltage of a data signal). For example, the first transistor T1 may be a driving transistor of the sub-pixel SPX.

[0105] The second transistor T2 may include a gate electrode connected to the first scan line SL1, a first electrode connected to the data line DL, and a second electrode connected to the first electrode of the first transistor T1. The second transistor T2 may be turned on by a first scan signal supplied from the first scan line SL1 to electrically connect the first electrode of the first transistor T1 and the data line DL. When the second transistor T2 is turned on, a voltage of a data signal supplied from the data line DL may be applied to the first electrode of the first transistor T1.

[0106] The third transistor T3 may include a gate electrode connected to the second scan line SL2, a first electrode connected to the second electrode of the first transistor T1, and a second electrode connected to the gate electrode of the first transistor T1 (e.g., connected to the first node N1). The third transistor T3 may be turned on by a second scan signal supplied from the second scan line SL2 to electrically connect the gate electrode and the second electrode of the first transistor T1. When the third transistor T3 is turned on, the first transistor T1 may operate as a diode (e.g., the first transistor T1 may be connected in a diode manner).

[0107] The fourth transistor T4 may include a gate electrode connected to the third scan line SL3, a first electrode connected to the gate electrode of the first transistor T1 (e.g., connected to the first node N1), and a second electrode connected to the first initialization power line VIL. The fourth transistor T4 may be turned on by the third scan signal supplied from the third scan line SL3, thereby electrically connecting the gate electrode of the first transistor T1 and the first initialization power line VIL. When the fourth transistor T4 is turned on, the first initialization voltage VINT (e.g., gate initialization voltage) of the first initialization power line VIL may be applied to the gate electrode of the first transistor T1.

[0108] The fifth transistor T5 may include a gate electrode connected to an emission control line ECL, a first electrode connected to a first pixel power line VDL, and a second electrode connected to a first electrode of the first transistor T1. The fifth transistor T5 may be turned on by an emission control signal supplied from the emission control line ECL, thereby electrically connecting the first electrode of the first transistor T1 and the first pixel power line VDL to which the first pixel power voltage ELVDD is applied. When the fifth transistor T5 is turned on, the first pixel power voltage ELVDD may be applied to the first electrode of the first transistor T1. In one or more embodiments, the first pixel power voltage ELVDD may be a high-level pixel driving voltage.

[0109] The sixth transistor T6 may include a gate electrode connected to an emission control line ECL, a first electrode connected to the second electrode of the first transistor T1, and a second electrode connected to the light emitting element EL. The sixth transistor T6 may be turned on by an emission control signal supplied from the emission control line ECL, thereby electrically connecting the first transistor T1 and the light emitting element EL. When both the fifth transistor T5 and the sixth transistor T6 are turned on, a driving current corresponding to a gate electrode voltage of the first transistor T1 may flow to the light emitting element EL.

[0110] The seventh transistor T7 may include a gate electrode connected to the fourth scan line SL4, a first electrode connected to the anode electrode of the light emitting element EL, and a second electrode connected to the second initialization power line VAIL. The seventh transistor T7 may be turned on by a fourth scan signal supplied from the fourth scan line SL4, thereby electrically connecting the anode electrode of the light emitting element EL and the second initialization power line VAIL. The fourth scan signal may be the same as or different from the first scan signal. When the seventh transistor T7 is turned on, a second initialization voltage VAINT (e.g., an anode electrode initialization voltage) from the second initialization power line VAIL may be applied to the anode electrode of the light emitting element EL.

[0111] The capacitor Cst may be connected between the gate electrode (eg, first node N1) of the first transistor T1 and the first pixel power line VDL. The capacitor Cst may be charged to a voltage corresponding to a data signal voltage applied to the gate electrode (eg, first node N1) of the first transistor T1.

[0112] The active layer (e.g., semiconductor pattern including the channel region) of the pixel transistor T (e.g., the first transistor T1 to the seventh transistor T7) may include one of polysilicon, amorphous silicon, and an oxide semiconductor. In one or more embodiments, some of the plurality of pixel transistors T may be formed as transistors of one conductivity type, and other pixel transistors T may be formed as transistors of different conductivity types. In addition, some of the plurality of pixel transistors T may include different types of semiconductor materials.

[0113] For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be formed as P-type transistors (e.g., P-type metal oxide semiconductor field effect transistors (MOSFETs)) having an active layer formed of polysilicon, and the third transistor T3 and the fourth transistor T4 may be formed as N-type transistors (e.g., N-type MOSFETs) having an active layer formed of an oxide semiconductor. In one embodiment, transistors having an active layer formed of polysilicon and transistors having an active layer formed of an oxide semiconductor may be arranged in different layers within the circuit layer 120.

[0114] Figure 6 It is shown Figure 1 A plan view of the arrangement of pixels in a main display area and a sub-display area of ​​a display device. Figure 6 An array of pixels (main display pixels MDX and sub display pixels SDX) in the sub display area SDA and the main display area MDA within the display area DA of the display device 10 is shown.

[0115] Reference Figure 6 , the display area DA of the display device 10 may include a main display area MDA and a sub-display area SDA. As mentioned previously, the sub-display area SDA may be formed on the substrate 110 (eg, referring to Figure 3 ) below which components are arranged. A plurality of main display pixels MDX may be arranged in the main display area MDA, and a plurality of sub-display pixels SDX may be arranged in the sub-display area SDA. Each of the main display pixel MDX and the sub-display pixel SDX may include one or more light-emitting areas EA, and one or more light-emitting elements ( Fig. 9 and Fig.10 A “light emitting element EL”) may be arranged in each of the light emitting areas EA to emit light.

[0116] In the main display area MDA, a plurality of light emitting elements EL emitting light and a pixel circuit PXC (for example, refer to Figure 5 ). The main display area MDA may be an area where the light emitting elements EL and the pixel circuits PXC are arranged in a predetermined pattern. Each of the light emitting elements EL may form a light emitting area EA, and a plurality of light emitting areas EA may together form a single main display pixel MDX. For example, in the main display area MDA, four light emitting areas EA may together form a single main display pixel MDX, and each of the light emitting areas EA may correspond to a sub-pixel SPX (for example, referring to Figure 5 ) pixel circuit PXC. Figure 4As shown in FIG. 1 , one main display pixel MDX may include four sub-pixels (first color sub-pixel SPX1, second color sub-pixel SPX2, and third color sub-pixel SPX3) and four emission areas EA corresponding to the four sub-pixels (first color sub-pixel SPX1, second color sub-pixel SPX2, and third color sub-pixel SPX3). The four emission areas EA may together form a single main display pixel MDX to represent a white level.

[0117] The light emitting elements EL emitting light may also be arranged in the sub-display area SDA to form a light emitting area EA, and a plurality of light emitting areas EA may together form a single sub-display pixel SDX. However, unlike the main display area MDA, for the sub-display pixel 100 (for example, referring to FIG. 1 ), the light emitting elements EL emitting light may also be arranged in the sub-display area SDA to form a light emitting area EA, and a plurality of light emitting areas EA may together form a single sub-display pixel SDX. Figure 3 ) on the back side of the substrate 110 (eg, the optical device 500 (eg, see Figure 3 )) The sub-display area SDA of the overlapping area may have a structure considering the transmittance of light. Specifically, the sub-display area SDA of the display area DA may include a first sub-display area SDA1 in which the light emitting area EA and the pixel circuit PXC are arranged, and a second sub-display area SDA2 in which the light emitting area EA is formed but the pixel circuit PXC is not arranged. In this article, the pixel circuit PXC arranged in the sub-display area SDA may refer to Figure 8 Sub-pixel circuits SPC1 and SPC2 shown in .

[0118] The first sub display area SDA1 may be arranged around the second sub display area SDA2. In one or more embodiments, the second sub display area SDA2 may be arranged in the middle of the sub display area SDA, and the first sub display area SDA1 may surround the second sub display area SDA2. However, the present disclosure is not limited thereto. Alternatively, the first sub display area SDA1 may be arranged on at least one side of the second sub display area SDA2.

[0119] A pixel circuit PXC for emitting light by the light emitting element EL arranged in the sub display area SDA may be provided in the first sub display area SDA1. In contrast, a pixel circuit PXC may not be arranged in the second sub display area SDA2.

[0120] Pixel circuits PXC electrically connected to the light emitting elements EL arranged in the sub-display area SDA may be arranged in the first sub-display area SDA1. Some of the pixel circuits PXC arranged in the first sub-display area SDA1 may be electrically connected to the light emitting elements EL arranged in the first sub-display area SDA1, and other pixel circuits PXC may be connected to the light emitting elements EL arranged in the second sub-display area SDA2. The second sub-display area SDA2 overlapping the optical device 500 of the display panel 100 may have high light transmittance due to the absence of the pixel circuits PXC therein. The second sub-display area SDA2 may emit light due to the presence of the light emitting area EA therein, and may have high light transmittance allowing the optical device 500 arranged on the rear side of the display panel 100 to receive light.

[0121] In the sub-display area SDA, unlike the main display area MDA, the light emitting element EL and the pixel circuit PXC may not necessarily correspond to each other one by one. For example, in the main display area MDA, a single pixel circuit PXC may be electrically connected to a single light emitting element EL. In the main display area MDA, each pixel circuit PXC may correspond to a pixel defining film ( Fig. 9 In contrast, the pixel circuits PXC arranged in the first sub-display area SDA1 may be electrically connected to the light emitting elements EL arranged in the first sub-display area SDA1 and the second sub-display area SDA2. Accordingly, each pixel circuit PXC arranged in the first sub-display area SDA1 may correspond to the light emitting elements EL or light emitting components formed in the first pixel defining film 131 (see FIG. 1 ). Fig. 9 ) in multiple openings.

[0122] Each sub-display pixel SDX formed by a plurality of light-emitting areas EA in the sub-display area SDA may have a layout different from that of the main display pixel MDX. For example, each of the main display pixels MDX may include four light-emitting areas EA, and each of the sub-display pixels SDX may include six light-emitting areas EA. The four light-emitting areas EA of each of the main display pixels MDX correspond to their corresponding pixel circuits PXC, and each of the main display pixels MDX may include four pixel circuits PXC. In contrast, the six light-emitting areas EA of each of the sub-display pixels SDX may form three pairs corresponding to their corresponding pixel circuits PXC in pairs. That is, each of the sub-display pixels SDX may include six light-emitting areas EA that are enabled to emit light by three pixel circuits PXC. Accordingly, the sub-display area SDA may exhibit brightness and resolution different from those of the main display area MDA.

[0123] Hereinafter, the arrangement and configuration of pixels (main display pixels MDX and sub display pixels SDX) in the main display area MDA and the sub display area SDA of the display device 10 will be described.

[0124] Figure 7 is shown included in the arrangement Figure 6 A plan view of the arrangement of pixel electrodes in sub-pixels in a main display area. Figure 8 is shown included in the arrangement Figure 6 A plan view of the arrangement of pixel electrodes in sub-pixels in a sub-display area.

[0125] Figure 7 The arrangement of pixel electrodes (first pixel electrode AE1 , second pixel electrode AE2 , and third pixel electrode AE3 ) and pixel circuits (first pixel circuit PXC1 , second pixel circuit PXC2 , and third pixel circuit PXC3 ) of four main display pixels MDX is shown. Figure 8 The arrangement of subpixel electrodes (for example, subpixel electrodes SAE1, SAE2 and SAE3 of the first subdisplay pixel SDX1 and subpixel electrodes SAE4, SAE5 and SAE6 of the second subdisplay pixel SDX2) and subpixel circuits (first subpixel circuit SPC1 and second subpixel circuit SPC2) of the first subdisplay pixel SDX1 in the first subdisplay area SDA1 and the second subdisplay pixel SDX2 in the second subdisplay area SDA2 are shown.

[0126] Reference Figure 7 , the display device 10 (for example, referring to Figure 1 ) may include a plurality of pixel electrodes (a first pixel electrode AE1, a second pixel electrode AE2, and a third pixel electrode AE3) arranged in the main display area MDA. The pixel electrodes (the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3) may be anode electrodes of light-emitting elements EL that emit light of different colors. For example, the first pixel electrode AE1 may be an anode electrode of a light-emitting element EL that emits a first color light and may be arranged in a first light-emitting area, the second pixel electrode AE2 may be an anode electrode of a light-emitting element EL that emits a second color light and may be arranged in a second light-emitting area, and the third pixel electrode AE3 may be an anode electrode of a light-emitting element EL that emits a third color light and may be arranged in a third light-emitting area. In one or more embodiments, the first light-emitting area may emit red light, the second light-emitting area may emit green light, and the third light-emitting area may emit blue light. However, the present disclosure is not limited thereto. Multiple light-emitting areas EA (for example, refer to Figure 6 ) may be formed on the light emitting element layer 130 (for example, see Fig. 9 ) of the first pixel defining film 131 (for example, refer to Fig. 9 ) in the opening limit.

[0127] The pixel electrodes (the first pixel electrode AE1, the second pixel electrode AE2 and the third pixel electrode AE3) may be arranged, for example, Ways, such as diamond Way. is a registered trademark of Samsung Display Co., Ltd. of South Korea. For example, the first pixel electrode AE1 and the third pixel electrode AE3 can be arranged in a first direction DR1 (for example, referring to Figure 1 ) and a second direction DR2 (eg, referring to Figure 1 ) are alternately arranged and spaced apart from each other. The second pixel electrodes AE2 may be spaced apart from each other in the first direction DR1 and the second direction DR2, and may be spaced apart from the first pixel electrode AE1 and the third pixel electrode AE3 in an oblique direction.

[0128] The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be included in their corresponding sub-pixels SPX (eg, referring to Figure 5 ) and may belong to their corresponding main display pixels MDX. For example, each main display pixel MDX may include a first sub-pixel SPX1 (eg, referring to Figure 4 ), two second sub-pixels SPX2 (for example, refer to Figure 4 ) and a third sub-pixel SPX3 (eg, referring to Figure 4 ), and may also include a first pixel electrode AE1, two second pixel electrodes AE2 and one third pixel electrode AE3.

[0129] The pixel circuits (first pixel circuit PXC1, second pixel circuit PXC2, and third pixel circuit PXC3) arranged in the main display area MDA may correspond one-to-one to the pixel electrodes (first pixel electrode AE1, second pixel electrode AE2, and third pixel electrode AE3). For example, the first pixel circuit PXC1 may correspond to and may be electrically connected to their corresponding first pixel electrode AE1, the second pixel circuit PXC2 may correspond to and may be electrically connected to their corresponding second pixel electrode AE2, and the third pixel circuit PXC3 may correspond to and may be electrically connected to their corresponding third pixel electrode AE3. The main display pixel MDX including four pixel electrodes (first pixel electrode AE1, second pixel electrode AE2, and third pixel electrode AE3) may include four pixel circuits (first pixel circuit PXC1, second pixel circuit PXC2, and third pixel circuit PXC3).

[0130] Reference Figure 8 The display device 10 may include a sub-display area SDA (eg, referring to Figure 6) in the first sub-display area SDA1 and the second sub-display area SDA2. The sub-pixel electrode SAE and the replica pixel electrode CPE may be anode electrodes of the light emitting element EL. That is, as in the main display area MDA, the light emitting element EL may be arranged in the first sub-display area SDA1 and the second sub-display area SDA2 to emit light.

[0131] The sub-display pixels SDX in the sub-display area SDA of the display device 10 (for example, see Figure 6 ) may be configured differently from the configuration of the main display pixel MDX in the main display area MDA. For example, each sub-display pixel SDX may have a sub-pixel electrode SAE and a replica pixel electrode CPE electrically connected to each other via a bridge electrode BAE. The sub-pixel electrode SAE and the replica pixel electrode CPE connected via the bridge electrode BAE may be anode electrodes of light-emitting elements EL emitting light of the same color.

[0132] For example, the first subpixel electrode SAE1 and the first replica pixel electrode CPE1 arranged in the first sub display area SDA1 may be electrically connected to each other via the first bridge electrode BAE1 and may form a light emitting element EL emitting first color light. The light emitting area EA where the first subpixel electrode SAE1 and the first replica pixel electrode CPE1 are arranged may emit light of the same color.

[0133] Similarly, the second sub-pixel electrode SAE2 and the second replica pixel electrode CPE2 arranged in the first sub-display area SDA1 may be electrically connected to each other through the second bridging electrode BAE2, and the third sub-pixel electrode SAE3 and the third replica pixel electrode CPE3 arranged in the first sub-display area SDA1 may be electrically connected to each other through the third bridging electrode BAE3. The second sub-pixel electrode SAE2 and the second replica pixel electrode CPE2 may form a light-emitting element EL that emits the second color light, and the third sub-pixel electrode SAE3 and the third replica pixel electrode CPE3 may form a light-emitting element EL that emits the third color light. The light-emitting area EA where the second sub-pixel electrode SAE2 and the second replica pixel electrode CPE2 are arranged may emit light of the same color, and the light-emitting area EA where the third sub-pixel electrode SAE3 and the third replica pixel electrode CPE3 are arranged may emit light of the same color.

[0134] The fourth subpixel electrode SAE4 and the fourth replica pixel electrode CPE4 arranged in the second sub display area SDA2 may be electrically connected to each other through the fourth bridging electrode BAE4. The fifth subpixel electrode SAE5 and the fifth replica pixel electrode CPE5 arranged in the second sub display area SDA2 may be electrically connected to each other through the fifth bridging electrode BAE5, and the sixth subpixel electrode SAE6 and the sixth replica pixel electrode CPE6 arranged in the second sub display area SDA2 may be electrically connected to each other through the sixth bridging electrode BAE6.

[0135] The fourth subpixel electrode SAE4 and the fourth replica pixel electrode CPE4 form a light emitting element EL that emits a first color light, the fifth subpixel electrode SAE5 and the fifth replica pixel electrode CPE5 can form a light emitting element EL that emits a second color light, and the sixth subpixel electrode SAE6 and the sixth replica pixel electrode CPE6 can form a light emitting element EL that emits a third color light.

[0136] The pixel electrode AE ​​of the main display area MDA (for example, refer to Fig. 9 ), the sub-pixel electrode SAE and the replica pixel electrode CPE may be arranged as follows, for example Patterns, such as diamonds Pattern. For example, the first subpixel electrode SAE1 and the third subpixel electrode SAE3 may be spaced apart from each other in the second direction DR2, and the third replica pixel electrode CPE3 and the first replica pixel electrode CPE1 may be spaced apart from the first subpixel electrode SAE1 and the third subpixel electrode SAE3, respectively, in the first direction DR1. The fourth subpixel electrode SAE4 and the sixth subpixel electrode SAE6 may be spaced apart from each other in the second direction DR2, and the sixth replica pixel electrode CPE6 and the fourth replica pixel electrode CPE4 may be spaced apart from the fourth subpixel electrode SAE4 and the sixth subpixel electrode SAE6, respectively, in the first direction DR1. The second subpixel electrode SAE2 and the second replica pixel electrode CPE2 may be spaced apart from each other obliquely with the first subpixel electrode SAE1 interposed therebetween. The fifth subpixel electrode SAE5 and the fifth replica pixel electrode CPE5 may be spaced apart from each other obliquely with the fourth replica pixel electrode CPE4 interposed therebetween. The bridging electrode BAE may be arranged to connect their corresponding pairs of sub-pixel electrodes SAE and replica pixel electrodes CPE without passing through another bridging electrode BAE and other sub-pixel electrodes SAE and replica pixel electrodes CPE.

[0137] The first sub-display pixel SDX1 arranged in the first sub-display area SDA1 may include six emission areas EA or six pixel electrodes including the first sub-pixel electrode SAE1, the second sub-pixel electrode SAE2, and the third sub-pixel electrode SAE3 and the first replica pixel electrode CPE1, the second replica pixel electrode CPE2, and the third replica pixel electrode CPE3. The second sub-display pixel SDX2 arranged in the second sub-display area SDA2 may include six emission areas EA or six pixel electrodes including the fourth sub-pixel electrode SAE4, the fifth sub-pixel electrode SAE5, and the sixth sub-pixel electrode SAE6 and the fourth replica pixel electrode CPE4, the fifth replica pixel electrode CPE5, and the sixth replica pixel electrode CPE6. Unlike each of the main display pixels MDX in the main display area MDA, each of the sub-display pixels SDX in the sub-display area SDA may have a relatively large number of emission areas EA emitting light of the same color. However, the number or density of light-emitting areas EA per unit area may be greater in the main display pixel MDX than in the sub-display pixel SDX (for example, the number or density of light-emitting areas EA per unit area may be greater in the main display area MDA than in the sub-display area SDA). In addition, the number of light-emitting elements EL emitting the first color light and the third color light may be greater in the sub-display pixel SDX than in the main display pixel MDX, but the number of light-emitting elements EL emitting the second color light may be the same in both the sub-display pixel SDX and the main display pixel MDX. Accordingly, the display device 10 may have a higher resolution in the main display area MDA than in the sub-display area SDA. Considering the light transmittance of the optical device 500 arranged below the sub-display area SDA, the sub-display area SDA may have a lower resolution than the main display area MDA.

[0138] In one or more embodiments, a first sub-pixel circuit SPC1 electrically connected to the first sub-display pixel SDX1 and a second sub-pixel circuit SPC2 electrically connected to the second sub-display pixel SDX2 may be arranged in the first sub-display area SDA1. On the other hand, no pixel circuit may be arranged in the second sub-display area SDA2, but a sub-pixel electrode SAE, a replica pixel electrode CPE, and a bridging electrode BAE and a bridging pattern electrically connecting the sub-pixel electrode SAE, the replica pixel electrode CPE, and the bridging electrode BAE to the second sub-pixel circuit SPC2 may be arranged.

[0139] As will be described later, the sub-pixel electrode SAE, the replica pixel electrode CPE, and the bridging electrode BAE may be arranged in the sub-display area SDA of the display device 10, and may be distinguished from each other based on their positions and connection structures. For example, the first sub-pixel electrode SAE1, the second sub-pixel electrode SAE2, and the third sub-pixel electrode SAE3 arranged in the first sub-display area SDA1 may be connected to the first replica pixel electrode CPE1, the second replica pixel electrode CPE2, and the third replica pixel electrode CPE3 through the first bridging electrode BAE1, the second bridging electrode BAE2, and the third bridging electrode BAE3 positioned in the same layer (e.g., at). The sub-pixel electrode SAE, the replica pixel electrode CPE, and the bridging electrode BAE arranged in the first sub-display area SDA1 may be referred to as a first-type sub-pixel electrode SAE#1, a first-type replica pixel electrode CPE#1, and a first-type bridging electrode BAE#1, respectively.

[0140] In contrast, the fourth subpixel electrode SAE4, the fifth subpixel electrode SAE5 and the sixth subpixel electrode SAE6 arranged in the second sub display area SDA2 may be connected to the fourth replica pixel electrode CPE4, the fifth replica pixel electrode CPE5 and the sixth replica pixel electrode CPE6 through the fourth bridging electrode BAE4, the fifth bridging electrode BAE5 and the sixth bridging electrode BAE6 positioned in different layers. The subpixel electrode SAE, the replica pixel electrode CPE and the bridging electrode BAE arranged in the second sub display area SDA2 may be referred to as the second type subpixel electrode SAE#2, the second type replica pixel electrode CPE#2 and the second type bridging electrode BAE#2, respectively.

[0141] The first sub-pixel circuit SPC1 may be electrically connected to a sub-pixel electrode SAE arranged in the first sub-display pixel SDX1, that is, a first-type sub-pixel electrode SAE#1. Each of the first sub-pixel circuits SPC1 may be electrically connected to one of the first sub-pixel electrode SAE1, the second sub-pixel electrode SAE2, and the third sub-pixel electrode SAE3. The first-type replica pixel electrode CPE#1 arranged in the first sub-display pixel SDX1 may be electrically connected to the first-type sub-pixel electrode SAE#1 through the first-type bridging electrode BAE#1, and a plurality of light emitting elements EL including electrically connected pairs of sub-pixel electrodes SAE and replica pixel electrodes CPE may emit light at the same time (e.g., may emit light synchronously). The sub-pixel electrodes SAE arranged in the first sub-display pixel SDX1 may overlap with their corresponding first sub-pixel circuits SPC1.

[0142] The second sub-pixel circuit SPC2 may be electrically connected to a sub-pixel electrode SAE arranged in the second sub-display pixel SDX2, that is, a second-type sub-pixel electrode SAE#2. The second sub-pixel circuit SPC2 may be electrically connected to a fourth sub-pixel electrode SAE4, a fifth sub-pixel electrode SAE5, and a sixth sub-pixel electrode SAE6. The second-type replica pixel electrode CPE#2 arranged in the second sub-display pixel SDX2 may be electrically connected to the second-type sub-pixel electrode SAE#2 through a second-type bridging electrode BAE#2, and a plurality of light-emitting elements EL including electrically connected pairs of sub-pixel electrodes SAE and replica pixel electrodes CPE may emit light simultaneously (may emit light synchronously). The connection pattern connecting the sub-pixel electrodes SAE of the second sub-pixel circuit SPC2 and the second sub-display pixel SDX2 may be arranged in the sub-display area SDA. At least some of the replica pixel electrodes CPE arranged in the first sub-display pixel SDX1 may be arranged to overlap with the second sub-pixel circuit SPC2. The other replica pixel electrodes CPE arranged in the first sub display pixel SDX1 may be arranged in a region where the sub pixel circuits (the first sub pixel circuit SPC1 and the second sub pixel circuit SPC2 ) are not arranged.

[0143] In one or more embodiments, the first type sub-pixel electrode SAE#1, the first type replica pixel electrode CPE#1, and the first type bridging electrode BAE#1 arranged in the first sub-display area SDA1 may be arranged in the same layer (e.g., at) to form an integrated pattern. For example, the first bridging electrode BAE1, the second bridging electrode BAE2, and the third bridging electrode BAE3, which are the bridging electrodes BAE arranged in the first sub-display area SDA1, may be bridging portions that are integrated with the first sub-pixel electrode SAE1, the second sub-pixel electrode SAE2, and the third sub-pixel electrode SAE3, respectively, and are integrated with the first replica pixel electrode CPE1, the second replica pixel electrode CPE2, and the third replica pixel electrode CPE3, respectively. On the contrary, the second type sub-pixel electrode SAE#2 and the second type replica pixel electrode CPE#2 arranged in the second sub-display area SDA2 may be arranged in the same layer (for example, at), but the second type bridging electrode BAE#2 also arranged in the second sub-display area SDA2 may be arranged in a layer different from the second type sub-pixel electrode SAE#2 and the second type replica pixel electrode CPE#2. For example, the fourth bridging electrode BAE4, the fifth bridging electrode BAE5 and the sixth bridging electrode BAE6 arranged in the second sub-display area SDA2 as the bridging electrode BAE may be connecting electrodes arranged in a layer different from the fourth sub-pixel electrode SAE4, the fifth sub-pixel electrode SAE5 and the sixth sub-pixel electrode SAE6 and the fourth replica pixel electrode CPE4, the fifth replica pixel electrode CPE5 and the sixth replica pixel electrode CPE6, and may electrically connect the fourth sub-pixel electrode SAE4, the fifth sub-pixel electrode SAE5 and the sixth sub-pixel electrode SAE6 with the fourth replica pixel electrode CPE4, the fifth replica pixel electrode CPE5 and the sixth replica pixel electrode CPE6.

[0144] The first type sub-pixel electrode SAE#1 arranged in the first sub-display area SDA1 may be arranged to overlap with the first sub-pixel circuit SPC1, and may be integrated with the first type replica pixel electrode CPE#1 through a first type bridging electrode BAE#1 arranged in the same layer as the first type sub-pixel electrode SAE#1. The second type sub-pixel electrode SAE#2 arranged in the second sub-display area SDA2 may be electrically connected to the second sub-pixel circuit SPC2, but may be arranged not to overlap with the second sub-pixel circuit SPC2. The second type sub-pixel electrode SAE#2 arranged in the second sub-display area SDA2 may be electrically connected to the second type replica pixel electrode CPE#2 through a second type bridging electrode BAE#2 arranged in a layer different from the second type sub-pixel electrode SAE#2, and may be electrically connected to the second sub-pixel circuit SPC2 through a bridging pattern arranged thereunder. This will be described later with reference to other drawings.

[0145] Considering the transmittance of light, the sub-pixel circuits (first sub-pixel circuit SPC1 and second sub-pixel circuit SPC2) may be arranged only in the first sub-display area SDA1. Since the number of sub-pixel circuits (first sub-pixel circuit SPC1 and second sub-pixel circuit SPC2) per unit area is less in the first sub-display area SDA1 than in the main display area MDA, the sub-pixel electrode SAE and the replica pixel electrode CPE may be paired in the sub-display pixels (first sub-display pixel SDX1 and second sub-display pixel SDX2) arranged in the sub-display area SDA, thereby forming a plurality of emission areas EA.

[0146] Fig. 9 It is shown Figure 1 A cross-sectional view of a main display area of ​​a display device.

[0147] Fig. 9 is a schematic cross-sectional view showing two light emitting elements EL and a first pixel circuit PXC1 and a second pixel circuit PXC2 in the main display area MDA. Specifically, Fig. 9 A cross section intersecting portions of the first pixel circuit PXC1 and the second pixel circuit PXC2 adjacent to each other is depicted.

[0148] Reference Fig. 9 , the display panel 100 (for example, see Figure 1 ) may include a substrate 110, a circuit layer 120, a light emitting element layer 130, and an encapsulation layer 140 disposed on the substrate 110. The circuit layer 120, the light emitting element layer 130, and the encapsulation layer 140 may be disposed on the substrate 110 in a thickness direction (eg, a third direction DR3 (eg, reference direction DR4)). Figure 1 )) are arranged or stacked sequentially.

[0149] The substrate 110 may be formed of a bendable, foldable and / or rollable flexible material. The substrate 110 may be formed of an insulating material such as a polymer resin. For example, the substrate 110 may be formed of polyimide.

[0150] The circuit layer 120 may include a pixel circuit PXC (eg, referring to Figure 5 ) and wiring. For example, the circuit layer 120 may include a circuit layer 120 that forms each main display pixel MDX (eg, referring to Figure 6 ) of the pixel circuit PXC (eg, the pixel transistor T and the capacitor Cst) and wiring (eg, such as Figure 5 The power lines PL, scan lines SL, emission control lines ECL and data lines DL shown in FIG.

[0151] Fig. 91 and 2. The first thin film transistor (TFT) TFT1 (also referred to as the first pixel transistor), the second TFT TFT2 (also referred to as the second pixel transistor), and the capacitor Cst included in the pixel circuit PXC of each main display pixel MDX among the elements provided in the circuit layer 120 are shown. The first TFT TFT1 may be a representative first type transistor (e.g., a P-type transistor) including a first semiconductor material (e.g., polysilicon) among the pixel transistors T. For example, the first TFT TFT1 may correspond to Figure 5 one of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7. Fig. 9 A first type transistor (eg, a first connection electrode CNE1 and / or a second connection electrode CNE2) is depicted. Figure 5 The sixth transistor T6 of the pixel transistor T is used as the first TFT TFT1. The second TFT TFT2 may be a representative second type transistor (eg, an N-type transistor) including a second semiconductor material (eg, an oxide semiconductor) among the pixel transistors T. For example, the second TFT TFT2 may correspond to Figure 5 One of the third transistor T3 and the fourth transistor T4.

[0152] The circuit layer 120 may include a semiconductor layer, a conductive layer, and an insulating film disposed between and / or around a conductive layer and a semiconductor layer for forming circuit elements and wirings. For example, the circuit layer 120 may include a blocking layer 121, a lower conductive layer BCDL (also referred to as a bottom conductive layer BCDL in this article), a buffer layer 122, a first semiconductor layer SCL1 (e.g., a polycrystalline silicon semiconductor layer), a first insulating layer 123 (e.g., a first gate insulating film), a first conductive layer CDL1 (e.g., a first gate conductive layer), a second insulating layer 124 (e.g., a second gate insulating film), a second conductive layer CDL2 (e.g., a second gate conductive layer), a third insulating layer 125 (e.g., a first interlayer insulating film), a second semiconductor layer SCL2 (e.g., an oxide semiconductor layer), a fourth insulating layer 126 (e.g., a third gate insulating film), a third conductive layer CDL3 (e.g., a third gate conductive layer), a fifth insulating layer 127 (e.g., a second interlayer insulating film), a fourth conductive layer CDL4 (e.g., a first source and drain conductive layer), and a sixth insulating layer 128 (e.g., a first through-hole layer or a first planarization film). In one or more embodiments, the circuit layer 120 may further include a fifth conductive layer CDL5 (eg, a second source-drain conductive layer), an interlayer insulating layer ILD, and a seventh insulating layer 129 (eg, a second via layer or a second planarization film) sequentially arranged on the sixth insulating layer 128 .

[0153] The barrier layer 121 may be disposed on the substrate 110. The barrier layer 121 may protect the elements disposed in the circuit layer 120 and the light emitting element layer 130 from moisture penetrating through the permeable substrate 110. The barrier layer 121 may include at least one inorganic film including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, and / or another inorganic insulating material). The material of the barrier layer 121 may vary.

[0154] The lower conductive layer BCDL may be disposed on the barrier layer 121. The lower conductive layer BCDL may include a lower metal layer BML and / or at least one wiring (or a portion of at least one wiring) overlapping an active layer (eg, the first active layer ACT1 and / or the second active layer ACT2) of at least one of the pixel transistors T. Fig. 9 , the lower metal layer BML is shown to be arranged to overlap with the first active layer ACT1 of the first TFT TFT1 and the first capacitor electrode CAE1 and the second capacitor electrode CAE2 of the capacitor Cst, but the present disclosure is not limited thereto. For example, the lower metal layer BML may be patterned into a suitable size and / or shape and may be arranged on the entire pixel circuit PXC or on a portion of the pixel circuit PXC. For example, the lower metal layer BML may be arranged only on the portion overlapping with the first active layer ACT1 of the first TFT TFT1 and the first capacitor electrode CAE1 and the second capacitor electrode CAE2 of the capacitor Cst. Figure 5 In one or more embodiments, the lower metal layer BML may be used as a light shielding pattern and / or a back gate electrode of the pixel transistor T.

[0155] The buffer layer 122 may be disposed on the lower conductive layer BCDL and may cover the lower conductive layer BCDL. The buffer layer 122 may include at least one inorganic film including an inorganic insulating material.

[0156] The first TFT TFT1, the second TFT TFT2, and the capacitor Cst may be arranged on one surface of the substrate 110 having the buffer layer 122. The first TFT TFT1 may include a first active layer ACT1 and a first gate electrode G1. The second TFT TFT2 may include a second active layer ACT2 and a second gate electrode G2. In one or more embodiments, the second TFT TFT2 may include a back gate electrode BG. The capacitor Cst may include a first capacitor electrode CAE1 and a second capacitor electrode CAE2.

[0157] The first semiconductor layer SCL1 may be disposed on the buffer layer 122. The first semiconductor layer SCL1 may include a first active layer ACT1 of the first TFT TFT1. For example, the first semiconductor layer SCL1 may include a first active layer ACT1 of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and / or the seventh transistor T7.

[0158] The first active layer ACT1 is provided on the buffer layer 122 and may include a first semiconductor material (e.g., polysilicon). The first active layer ACT1 may include a first channel region CH1, a first source region S1, and a first drain region D1. The first channel region CH1 may overlap with the first gate electrode G1 in the third direction DR3. The first source region S1 may be arranged on one side of the first channel region CH1, and the first drain region D1 may be arranged on the other side of the first channel region CH1. The first source region S1 and the first drain region D1 may be regions formed by doping ions or impurities into a semiconductor to impart conductivity for forming the first active layer ACT1. In one or more embodiments, the first source region S1 may be a source electrode of the first TFT TFT1. In one or more embodiments, the first TFT TFT1 may include a separate source electrode connected to the first source region S1. In one or more embodiments, the first drain region D1 may be a drain electrode of the first TFT TFT1. In one or more embodiments, the first TFT TFT1 may include a separate drain electrode connected to the first drain region D1.

[0159] The first insulating layer 123 may be disposed on the first semiconductor layer SCL1 and the buffer layer 122. The first insulating layer 123 may cover the first semiconductor layer SCL1 and the buffer layer 122.

[0160] The first conductive layer CDL1 may be arranged on the first insulating layer 123. The first conductive layer CDL1 may include a first gate electrode G1 of the first TFT TFT1. The first gate electrode G1 may be arranged to overlap a portion of the first active layer ACT1 (e.g., the first channel region CH1). In one or more embodiments, the first conductive layer CDL1 may further include a wiring (or a portion of a wiring), a conductive pattern (e.g., a bridge pattern), and / or a capacitor electrode. For example, the first conductive layer CDL1 may further include a first capacitor electrode CAE1 of a capacitor Cst.

[0161] In one or more embodiments, the first capacitor electrode CAE1 may be integrally formed with at least the first gate electrode G1 of the first TFT TFT1. For example, the first capacitor electrode CAE1 of each of the capacitors Cst may be integrally formed with the first gate electrode G1 of the first TFT TFT1. Figure 5 For example, the first capacitor electrode CAE1 of each of the capacitors Cst and the gate electrode of the first transistor T1 may be formed as a single conductive pattern, and the second capacitor electrode CAE2 of the corresponding capacitor Cst may be arranged to overlap the conductive pattern.

[0162] The second insulating layer 124 may be disposed on the first conductive layer CDL1 and the first insulating layer 123. The second insulating layer 124 may cover the first conductive layer CDL1 and the first insulating layer 123.

[0163] The second conductive layer CDL2 may be arranged on the second insulating layer 124. The second conductive layer CDL2 may include an electrode of the capacitor Cst (e.g., a second capacitor electrode CAE2). In one or more embodiments, the second conductive layer CDL2 may further include an electrode, a wiring (or a portion of a wiring) and / or a conductive pattern (e.g., a bridge pattern). For example, the second conductive layer CDL2 may further include a back gate electrode BG connected to a second gate electrode G2 of the second TFT TFT2.

[0164] The third insulating layer 125 may be disposed on the second conductive layer CDL2 and the second insulating layer 124. The third insulating layer 125 may cover the second conductive layer CDL2 and the second insulating layer 124.

[0165] The second semiconductor layer SCL2 may be disposed on the third insulating layer 125. The second semiconductor layer SCL2 may include a second active layer ACT2 of the second TFT TFT2. For example, the second semiconductor layer SCL2 may include Figure 5 The second active layer ACT2 of the third transistor T3 and the fourth transistor T4.

[0166] The second active layer ACT2 may be provided in the second semiconductor layer SCL2 and may include a second semiconductor material (eg, an oxide semiconductor). For example, the second active layer ACT2 may include indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO) and / or indium gallium tin oxide (IGTO).

[0167] The second active layer ACT2 may include a second channel region CH2, a second source region S2, and a second drain region D2. The second channel region CH2 may overlap with the second gate electrode G2 in the third direction DR3. The second source region S2 may be arranged on one side of the second channel region CH2, and the second drain region D2 may be arranged on the other side of the second channel region CH2. The second source region S2 and the second drain region D2 may be regions with conductivity in which ions or impurities are doped in a semiconductor to form the second active layer ACT2. In one or more embodiments, the second source region S2 may be a source electrode of the second TFT TFT2. In one or more embodiments, the second TFT TFT2 may include a separate source electrode connected to the second source region S2. In one or more embodiments, the second drain region D2 may be a drain electrode of the second TFTTFT2. In one or more embodiments, the second TFT TFT2 may include a separate drain electrode connected to the second drain region D2.

[0168] The fourth insulating layer 126 may be disposed on the second semiconductor layer SCL2 and the third insulating layer 125. The fourth insulating layer 126 may cover the second semiconductor layer SCL2 and the third insulating layer 125.

[0169] In one or more embodiments, the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, and the fourth insulating layer 126 may be an inorganic insulating film having an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, and / or another inorganic insulating material), and may have a single-layer or multi-layer structure. At least two of the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, and the fourth insulating layer 126 may include the same material or different materials. The materials of the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, and the fourth insulating layer 126 may vary.

[0170] The third conductive layer CDL3 may be disposed on the fourth insulating layer 126. The third conductive layer CDL3 may include a second gate electrode G2 of the second TFT TFT2. The second gate electrode G2 may be disposed to overlap a portion of the second active layer ACT2 (e.g., the second channel region CH2). In one or more embodiments, the third conductive layer CDL3 may further include a wiring (or a portion of a wiring), a conductive pattern (e.g., a bridge pattern), and / or a capacitor electrode.

[0171] In one or more embodiments, the electrodes, conductive patterns and / or wiring provided in each of the bottom conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2 and the third conductive layer CDL3 may include a conductive material such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), another metal, at least one of their alloys, or another conductive material, and may have a single-layer or multi-layer structure. For example, the electrodes, conductive patterns and / or wiring provided in the bottom conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2 and the third conductive layer CDL3 may include Mo or another metal material. At least two of the conductive layers among the bottom conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2 and the third conductive layer CDL3 may include the same material or different materials. The materials of the bottom conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2 and the third conductive layer CDL3 are not limited and may vary.

[0172] The fifth insulating layer 127 may be disposed on the third conductive layer CDL3 and the fourth insulating layer 126. The fifth insulating layer 127 may cover the third conductive layer CDL3 and the fourth insulating layer 126.

[0173] The fourth conductive layer CDL4 may be disposed on the fifth insulating layer 127. The fourth conductive layer CDL4 may include a first connection electrode CNE1 (or a drain electrode of the first TFT TFT1), a first conductive pattern BE1 (or a source electrode of the second TFT TFT2), and a second conductive pattern BE2 (or a drain electrode of the second TFT TFT2). The first connection electrode CNE1 provided in the fourth conductive layer CDL4 may be connected to the first drain region D1 of the first active layer ACT1 through a first contact hole CT1 penetrating the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127. The first conductive pattern BE1 provided in the fourth conductive layer CDL4 may be connected to the second source region S2 of the second active layer ACT2 through a second contact hole CT2 penetrating the fourth insulating layer 126 and the fifth insulating layer 127. The second conductive pattern BE2 may be connected to the second drain region D2 of the second active layer ACT2 through a third contact hole CT3 penetrating the fourth insulating layer 126 and the fifth insulating layer 127. In one or more embodiments, the fourth conductive layer CDL4 may further include wiring (or portions of wiring) and / or conductive patterns (e.g., bridge patterns). For example, the fourth conductive layer CDL4 may include some of the power lines PL provided within or outside the display area DA (e.g., the first pixel power line VDL and / or the second pixel power line VSL).

[0174] The sixth insulating layer 128 may be on the fourth conductive layer CDL4 and the fifth insulating layer 127. The sixth insulating layer 128 may cover the fourth conductive layer CDL4 and the fifth insulating layer 127.

[0175] The fifth conductive layer CDL5 may be arranged on the sixth insulating layer 128. The fifth conductive layer CDL5 may include a second connection electrode CNE2. The second connection electrode CNE2 provided in the fifth conductive layer CDL5 may be connected to the first connection electrode CNE1 through a fourth contact hole CT4 (or a first through hole) penetrating the sixth insulating layer 128. In one or more embodiments, the fifth conductive layer CDL5 may further include a wiring (or a portion of a wiring) and / or a conductive pattern (e.g., a bridge pattern). For example, the fifth conductive layer CDL5 may include some of the power lines PL provided in and / or outside the display area DA (e.g., a first pixel power line VDL and / or a second pixel power line VSL).

[0176] In one or more embodiments, the electrodes, conductive patterns and / or wiring provided in each of the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may include a conductive material (e.g., Mo, Al, Cr, Au, Ti, Ni, Nd, Cu or another metal, an alloy thereof or another conductive material) and may have a single-layer or multi-layer structure. For example, the electrodes, conductive patterns and / or wiring provided in each of the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may be formed with a three-layer structure of titanium / aluminum / titanium (Ti / Al / Ti). The fourth conductive layer CDL4 and the fifth conductive layer CDL5 may include the same material or different materials. The materials of the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may vary.

[0177] The interlayer insulating layer ILD may be disposed on the fifth conductive layer CDL5 and the sixth insulating layer 128. The interlayer insulating layer ILD may cover the fifth conductive layer CDL5 and the sixth insulating layer 128. The interlayer insulating layer ILD may cover a plurality of patterns disposed in the sub-display area SDA, which will be discussed later. The interlayer insulating layer ILD may include an inorganic insulating material and may cover a lower layer disposed in the sub-display area SDA instead of the sixth insulating layer 128 and the seventh insulating layer 129, which are not provided in the sub-display area SDA.

[0178] The seventh insulating layer 129 may be disposed on the interlayer insulating layer ILD. The seventh insulating layer 129 may cover the interlayer insulating layer ILD.

[0179] In one or more embodiments, the sixth insulating layer 128 and the seventh insulating layer 129 may be an organic insulating film including an organic insulating material (e.g., an acryl resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, and / or another organic insulating material), and may have a single-layer or multi-layer structure. The sixth insulating layer 128 and the seventh insulating layer 129 may include the same material or different materials. The materials of the sixth insulating layer 128 and the seventh insulating layer 129 may vary.

[0180] The light emitting element layer 130 may include a pixel PX (eg, Figure 4 ) of the light emitting area EA and the light emitting element EL positioned in the light emitting area EA. In one or more embodiments, the light emitting element layer 130 may further include a spacer SPC disposed on a portion of the first pixel defining film 131.

[0181] The light emitting element EL may include pixel electrodes (first pixel electrode AE1, second pixel electrode AE2, and third pixel electrode AE3) (e.g., anode electrodes) connected to the pixel transistor T (e.g., first TFT TFT1) included in the main display pixel MDX through the first connection electrode CNE1 and / or the second connection electrode CNE2, and may also include a light emitting layer EML and a common electrode CE (e.g., cathode electrode) sequentially arranged on the pixel electrodes (first pixel electrode AE1, second pixel electrode AE2, and third pixel electrode AE3). In one or more embodiments, the light emitting element EL may also include a first intermediate layer (e.g., a hole layer including a hole transport layer) arranged between the pixel electrodes (first pixel electrode AE1, second pixel electrode AE2, and third pixel electrode AE3) and the light emitting layer EML, and a second intermediate layer (e.g., an electron layer including an electron transport layer) arranged between the light emitting layer EML and the common electrode CE.

[0182] The pixel electrodes (first pixel electrode AE1, second pixel electrode AE2, and third pixel electrode AE3) of the light emitting element EL may include a conductive material and may be arranged on the circuit layer 120. For example, the pixel electrodes (first pixel electrode AE1, second pixel electrode AE2, and third pixel electrode AE3) may be arranged to correspond to their respective light emitting areas EA on the seventh insulating layer 129. The pixel electrode AE ​​may be connected to the second connection electrode CNE2 through a fifth contact hole CT5 (or a second through hole) penetrating the seventh insulating layer 129 and the interlayer insulating layer ILD.

[0183] In one or more embodiments, the pixel electrodes (the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3) may include a metal material having a high reflectivity. For example, the pixel electrodes (the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3) may have a single-layer structure of Mo, Ti, Cu, and / or Al, and / or indium tin oxide (ITO), zinc oxide (ZnO), indium oxide (In 2 O 3 ) and silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), Au and / or Ni multilayer structures (e.g., ITO / Mg, ITO / MgF 2 , ITO / Ag and / or ITO / Ag / ITO).

[0184] The light-emitting layer EML of the light-emitting element EL may include a high molecular weight material or a low molecular weight material. In one or more embodiments, the light-emitting layer EML may be arranged on each of the pixel electrodes (the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3) of each main display pixel MDX, and may emit light of a color corresponding to the light-emitting area EA. In one or more embodiments, the light-emitting layer EML may be a common layer shared by light-emitting areas EA of different colors, and may be connected to the sub-pixel SPX (e.g., reference 1 to FIG. 1 ) intended to be displayed by each main display pixel MDX. Figure 5 ) may be arranged in the emission area EA of the corresponding sub-pixel SPX.

[0185] The common electrode CE of the light emitting element EL may include a conductive material and may be connected to the second pixel power line VSL. In one or more embodiments, the common electrode CE may be a common layer formed throughout the entire display area DA, thereby covering the light emitting layer EML and the first pixel defining film 131. The common electrode CE may be arranged across the entire main display area MDA and the sub-display area SDA. In one or more embodiments, the common electrode CE may be formed of a transparent conductive oxide (TCO) such as ITO or IZO, or a semi-transmissive metal material such as Mg, Ag, or an alloy of Mg and Ag, through which light can be transmitted. If the common electrode CE is formed of a semi-transmissive metal material, an improvement in luminous efficiency due to the microcavity effect can be expected.

[0186] The first pixel defining film 131 may have an opening corresponding to the light emitting area EA and may be around the light emitting area EA (e.g., may surround the light emitting area EA). For example, the first pixel defining film 131 may be formed to cover the edges of the pixel electrodes (the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3) of the light emitting element EL, and may include a remaining opening exposing the pixel electrodes (the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3). The area where the exposed pixel electrodes (the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3) overlap with the light emitting layer EML (or their surrounding areas) may be defined as the light emitting area EA of each main display pixel MDX.

[0187] In one or more embodiments, the first pixel defining film 131 may include at least one organic film including an organic insulating material. For example, the first pixel defining film 131 may include acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, benzocyclobutene (BCB) and / or another organic insulating material.

[0188] The spacer SPC may be positioned on a portion of the first pixel defining film 131. The spacer SPC may include at least one organic film including an organic insulating material. The spacer SPC may include the same material as the first pixel defining film 131 or a different material. In one or more embodiments, the first pixel defining film 131 and the spacer SPC may be sequentially formed by separate mask processes. In one or more embodiments, the first pixel defining film 131 and the spacer SPC may be formed synchronously (e.g., simultaneously) using a halftone mask, in which case the first pixel defining film 131 and the spacer SPC can be regarded as a single integrated insulating film. The organic insulating material forming the spacer SPC is not particularly limited and may vary.

[0189] The encapsulation layer 140 may be disposed in the main area MA (eg, see Figure 1 ) on the light emitting element layer 130 in the display area DA and the non-display area NA. For example, the encapsulation layer 140 may be arranged in the display area DA and the non-display area NA to cover the light emitting element layer 130. The encapsulation layer 140 may prevent oxygen or moisture from penetrating into the light emitting element layer 130, and may mitigate electrical or physical effects on the circuit layer 120 and the light emitting element layer 130.

[0190] In one or more embodiments, the encapsulation layer 140 may include a first inorganic encapsulation film 141, an organic encapsulation film 142, and a second inorganic encapsulation film 143 sequentially disposed on the light emitting element layer 130. The first inorganic encapsulation film 141 and the second inorganic encapsulation film 143 may include an inorganic material, and the organic encapsulation film 142 may include an organic material.

[0191] Fig.10 and Fig.11 It is shown Figure 1 A cross-sectional view of a sub-display area of ​​a display device. Fig.10 and Fig.11 The cross section of the light emitting element EL arranged in the first sub-display area SDA1 and the second sub-display area SDA2 and the electrical connection structure between the first sub-pixel circuit SPC1 and the second sub-pixel circuit SPC2 and the light emitting element EL are shown. Specifically, Fig.10 shows a cross-sectional structure of a region where the first sub-pixel electrode SAE1 and the first replica pixel electrode CPE1 are arranged, and Fig.11 The structure of a region where the fourth sub-pixel electrode SAE4 and the fourth replica pixel electrode CPE4 are arranged is shown.

[0192] Reference Fig.10 and Fig.11 , the display device 10 (for example, referring to Figure 1) may include a first sub-pixel circuit SPC1 and a second sub-pixel circuit SPC2 arranged in the first sub-display area SDA1. The first sub-pixel circuit SPC1 and the second sub-pixel circuit SPC2 may include devices or elements formed by wiring and patterns in a first conductive layer CDL1, a second conductive layer CDL2, a third conductive layer CDL3, a fourth conductive layer CDL4, and a fifth conductive layer CDL5 arranged on the substrate 110 and a first semiconductor layer SCL1 and a second semiconductor layer SCL2. The first sub-pixel circuit SPC1 and the second sub-pixel circuit SPC2 may have the same Fig. 9 The first pixel circuit PXC1 and the second pixel circuit PXC2 are described to have the same configuration and connection structure, and therefore, a detailed description of the configuration and connection structure of the first sub-pixel circuit SPC1 and the second sub-pixel circuit SPC2 will be omitted.

[0193] The first sub-pixel circuit SPC1 arranged in the first sub-display area SDA1 may be electrically connected to the first sub-pixel electrode SAE1. The first connection electrode CNE1 of the first sub-pixel circuit SPC1 is connected to the second connection electrode CNE2 of the first sub-pixel circuit SPC1 arranged on the sixth insulating layer 128, and the second connection electrode CNE2 may be connected to the first sub-pixel electrode SAE1 arranged on the seventh insulating layer 129. The first sub-pixel electrode SAE1 is arranged to overlap and connect with the first sub-pixel circuit SPC1, thereby serving as an anode electrode of the light emitting element EL. The first sub-pixel electrode SAE1 may overlap with the opening of the first pixel defining film 131, and may form the light emitting element EL together with the light emitting layer EML arranged in the opening of the first pixel defining film 131 and the common electrode CE arranged on the light emitting layer EML.

[0194] The first replica pixel electrode CPE1 arranged in the first sub-display area SDA1 may be electrically connected to the first sub-pixel electrode SAE1. In one or more embodiments, the first replica pixel electrode CPE1 may be integrated with the first sub-pixel electrode SAE1 through a first bridging electrode BAE1 arranged in the same layer as (e.g., at) the first replica pixel electrode CPE1. The first replica pixel electrode CPE1 and the first bridging electrode BAE1 may be directly arranged on the seventh insulating layer 129. The first replica pixel electrode CPE1 may be arranged to overlap with the second sub-pixel circuit SPC2, but may be electrically connected to the first sub-pixel circuit SPC1 through the first sub-pixel electrode SAE1. The first replica pixel electrode CPE1 may overlap with the opening of the first pixel defining film 131, and may form a light emitting element EL together with the light emitting layer EML arranged in the opening of the first pixel defining film 131 and the common electrode CE arranged on the light emitting layer EML. An electrical signal for emitting light by the light emitting element EL may be synchronously (e.g., simultaneously) applied to both the first sub-pixel electrode SAE1 and the first replica pixel electrode CPE1, and a plurality of light emitting elements EL including the first sub-pixel electrode SAE1 and the first replica pixel electrode CPE1 may simultaneously emit light (e.g., may synchronously emit light). The light emitting layer EML disposed on the first sub-pixel electrode SAE1 and the light emitting layer EML disposed on the first replica pixel electrode CPE1 may both emit light of the same color.

[0195] The second sub-pixel circuit SPC2 arranged in the first sub-display area SDA1 may be electrically connected to the fourth sub-pixel electrode SAE4, the fifth sub-pixel electrode SAE5, or the sixth sub-pixel electrode SAE6 arranged in the second sub-display area SDA2. The pixel circuit PXC may not be arranged in the second sub-display area SDA2, and a plurality of patterns and electrodes capable of transmitting an electrical signal from the second sub-pixel circuit SPC2 may be included in the second sub-display area SDA2.

[0196] The display device 10 may include a sub-display area SDA (eg, Figure 6) in a plurality of bridge patterns (first bridge pattern BRE1 and second bridge pattern BRE2), contact pattern CTE (first contact pattern CTE1 and second contact pattern CTE2), and planarization pattern PTE (first planarization pattern PTE1 and second planarization pattern PTE2). The bridge pattern (first bridge pattern BRE1 and second bridge pattern BRE2), contact pattern CTE, and planarization pattern PTE may be arranged in at least some of the first semiconductor layer SCL1 and second semiconductor layer SCL2 and the first conductive layer CDL1, second conductive layer CDL2, third conductive layer CDL3, fourth conductive layer CDL4, and fifth conductive layer CDL5 forming the pixel circuit PXC or the first sub-pixel circuit SPC1 and second sub-pixel circuit SPC2. The bridge pattern (first bridge pattern BRE1 and second bridge pattern BRE2), contact pattern CTE, and planarization pattern PTE may transfer an emission signal applied from the second sub-pixel circuit SPC2 to the fourth sub-pixel electrode SAE4 arranged in the second sub-display area SDA2.

[0197] For example, the bridge pattern (the first bridge pattern BRE1 and the second bridge pattern BRE2) may include a first bridge pattern BRE1 disposed on the third insulating layer 125 and a second bridge pattern BRE2 disposed on the interlayer insulating layer ILD. The first bridge pattern BRE1 may be disposed in the same layer as (e.g., at) the second semiconductor layer SCL2, but positioned in the second sub-display area SDA2, and the second bridge pattern BRE2 may be disposed across the first sub-display area SDA1 and the second sub-display area SDA2. The second bridge pattern BRE2 may be electrically connected to the first bridge pattern BRE1 through the contact pattern CTE, and the first bridge pattern BRE1 may be electrically connected to the first bridge pattern BRE1 through the planarization pattern PTE and the bridge electrode BAE (e.g., refer to Figure 8 ) is electrically connected to the sub-pixel electrode SAE (for example, refer to Figure 8). The emission signal applied from the second sub-pixel circuit SPC2 may be transferred to the second bridge pattern BRE2 through the third connection electrode CNE3 and the fourth connection electrode CNE4, and may also be transferred to the fourth sub-pixel electrode SAE4 arranged in the second sub-display area SDA2 through the contact pattern CTE, the first bridge pattern BRE1, the planarization pattern PTE, and the fourth bridge electrode BAE4. For example, in the second sub-pixel circuit SPC2, the fourth conductive layer CDL4 may further include a third connection electrode CNE3 arranged in the first sub-display area SDA1. The third connection electrode CNE3 may be connected to the first drain region D1 of the first active layer ACT1 through a contact hole penetrating the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127. In the second sub-pixel circuit SPC2, the fifth conductive layer CDL5 may further include a fourth connection electrode CNE4 arranged in the first sub-display area SDA1. The fourth link electrode CNE4 provided in the fifth conductive layer CDL5 may be connected to the third link electrode CNE3 through a sixth contact hole CT6 penetrating the sixth insulating layer 128 .

[0198] The contact pattern CTE may be arranged on the fifth insulating layer 127, and may include a first contact pattern CTE1 included in the fourth conductive layer CDL4 and a second contact pattern CTE2 arranged on the first contact pattern CTE1 and included in the fifth conductive layer CDL5. The first contact pattern CTE1 and the second contact pattern CTE2 may be arranged to overlap each other and may be formed in substantially the same pattern. For example, the second contact pattern CTE2 may be formed to cover an outer surface (e.g., an outer peripheral surface) of the first contact pattern CTE1.

[0199] A plurality of contact patterns CTE may be positioned near a boundary between the first sub-display area SDA1 and the second sub-display area SDA2. As will be described later, some of the contact patterns CTE may be arranged in the first sub-display area SDA1, while other contact patterns CTE may be arranged in the second sub-display area SDA2. The contact pattern CTE may be used as an electrode connecting the first bridge pattern BRE1 and the second bridge pattern BRE2. The first bridge pattern BRE1 may extend from the contact pattern CTE to a fourth sub-pixel electrode SAE4 arranged in the second sub-display area SDA2. The second bridge pattern BRE2 may extend from the contact pattern CTE to a fourth connection electrode CNE4 of a second sub-pixel circuit SPC2 arranged in the first sub-display area SDA1. The number and arrangement of the bridge patterns (the first bridge pattern BRE1 and the second bridge pattern BRE2) and the contact pattern CTE in the sub-display area SDA may be designed to correspond to the number and arrangement of the fourth sub-pixel electrode SAE4 in the second sub-display area SDA2.

[0200] The planarization pattern PTE may be arranged on the fifth insulating layer 127 and may include a first planarization pattern PTE1 included in the fourth conductive layer CDL4 and a second planarization pattern PTE2 arranged on the first planarization pattern PTE1 and included in the fifth conductive layer CDL5. Both the first planarization pattern PTE1 and the second planarization pattern PTE2 may be arranged in the same layer (e.g., at) as the first contact pattern CTE1 and the second contact pattern CTE2, respectively. Additionally, the cross-sectional arrangement of the first planarization pattern PTE1 and the second planarization pattern PTE2 may be similar to the cross-sectional arrangement of the first contact pattern CTE1 and the second contact pattern CTE2. For example, the first planarization pattern PTE1 and the second planarization pattern PTE2 may be arranged to overlap each other and may be formed into substantially the same pattern. The second planarization pattern PTE2 may be formed to cover the outer surface (e.g., the peripheral surface) of the first planarization pattern PTE1.

[0201] A plurality of planarization patterns PTE may be arranged in the second sub-display area SDA2 to be aligned with the sub-pixel electrode SAE or the replica pixel electrode CPE (eg, referring to Figure 8 ). The first planarization pattern PTE1 and the second planarization pattern PTE2 may overlap each other in pairs and may also overlap with the sub-pixel electrode SAE or the replica pixel electrode CPE. The first planarization pattern PTE1 and the second planarization pattern PTE2 may form an area in the second sub display area SDA2 where the sub-pixel electrode SAE or the replica pixel electrode CPE can be formed to be flat.

[0202] The sixth insulating layer 128 and the seventh insulating layer 129 including an organic insulating material may not be arranged in the entire second sub-display area SDA2 to enhance the light transmittance of the second sub-display area SDA2. The sixth insulating layer 128 and the seventh insulating layer 129 may be arranged in the entire main display area MDA and the entire first sub-display area SDA1, but not completely arranged in the second sub-display area SDA2. The sixth insulating layer 128 and the seventh insulating layer 129 may be arranged only near the boundary between the first sub-display area SDA1 and the second sub-display area SDA2. The sixth insulating layer 128 and the seventh insulating layer 129 may not be arranged at least in the portion of the second sub-display area SDA2 where the light emitting element EL is arranged or the portion where the sub-pixel electrode SAE and the replica pixel electrode CPE are arranged. Since the sixth insulating layer 128 and the seventh insulating layer 129 including an organic insulating material and thus being thick are almost absent, the second sub-display area SDA2 may have a higher light transmittance, and as a result, the amount of light incident on the component or optical device 500 arranged in the second sub-display area SDA2 may be increased.

[0203] The display device 10 may include a plurality of planarization patterns PTE arranged in the second sub-display area SDA2, and the sub-pixel electrode SAE and the replica pixel electrode CPE may be arranged on the planarization pattern PTE. For example, in the light emitting element EL arranged in the second sub-display area SDA2, the sub-pixel electrode SAE and the replica pixel electrode CPE used as the anode electrode may be arranged on the planarization pattern PTE. A planarization layer formed of an organic insulating material may not be arranged in the second sub-display area SDA2, but the flatness of the anode electrode of the light emitting element EL can be ensured due to the presence of the planarization pattern PTE.

[0204] The planarization pattern PTE overlapping the sub-pixel electrode SAE arranged in the second sub-display area SDA2 may be connected to the corresponding sub-pixel electrode SAE and the first bridge pattern BRE1. The planarization pattern PTE may ensure flatness while also serving as a connection electrode for transmitting an emission signal applied through a bridge pattern (a first bridge pattern BRE1 and a second bridge pattern BRE2) to the sub-pixel electrode SAE. In contrast, the planarization pattern PTE overlapping the replica pixel electrode CPE arranged in the second sub-display area SDA2 may not be connected to the first bridge pattern BRE1. The planarization pattern PTE overlapping the replica pixel electrode CPE may also not be connected to the replica pixel electrode CPE, but the present disclosure is not limited thereto. In one or more embodiments, the planarization pattern PTE overlapping the replica pixel electrode CPE may be connected to the replica pixel electrode CPE.

[0205] The interlayer insulating layer ILD may be arranged across the main display area MDA and the sub display area SDA. In the main display area MDA and the first sub display area SDA1, the interlayer insulating layer ILD may be arranged on the sixth insulating layer 128 and the fifth conductive layer CDL5, thereby covering the sixth insulating layer 128 and the fifth conductive layer CDL5. In contrast, in the second sub display area SDA2, the interlayer insulating layer ILD may be arranged on the contact pattern CTE, the planarization pattern PTE, and the fifth insulating layer 127, thereby covering the contact pattern CTE, the planarization pattern PTE, and the fifth insulating layer 127. In the main display area MDA and the first sub display area SDA1, the seventh insulating layer 129 including an organic insulating material may be arranged under the anode electrode of the light emitting element EL, thereby serving as a through-hole layer, but in the second sub display area SDA2, the interlayer insulating layer ILD including an inorganic insulating material may be arranged under the anode electrode of the light emitting element EL, thereby also serving as a through-hole layer.

[0206] The bridging electrodes BAE (specifically, the fourth bridging electrode BAE4, the fifth bridging electrode BAE5, and the sixth bridging electrode BAE6) arranged in the second sub-display area SDA2 may be arranged on the interlayer insulating layer ILD in the second sub-display area SDA2. The fourth bridging electrode BAE4, the fifth bridging electrode BAE5, and the sixth bridging electrode BAE6 may include the same material as the second bridging pattern BRE2, and may be arranged in substantially the same layer as the second bridging pattern BRE2 (for example, at). Similar to the way in which the second bridging pattern BRE2 is positioned on the interlayer insulating layer ILD in the first sub-display area SDA1, the fourth bridging electrode BAE4, the fifth bridging electrode BAE5, and the sixth bridging electrode BAE6 may be positioned on the interlayer insulating layer ILD on the planarization pattern PTE in the second sub-display area SDA2.

[0207] The fourth bridging electrode BAE4, the fifth bridging electrode BAE5 and the sixth bridging electrode BAE6 may include a first portion overlapping the planarization pattern PTE and a second portion connected to a different first portion. Although the first bridging electrode BAE1, the second bridging electrode BAE2 and the third bridging electrode BAE3 have a structure that is integrated with their corresponding sub-pixel electrodes SAE and the replica pixel electrode CPE, the fourth bridging electrode BAE4, the fifth bridging electrode BAE5 and the sixth bridging electrode BAE6 may be arranged in a layer different from their corresponding sub-pixel electrodes SAE and the replica pixel electrode CPE, and may include a portion overlapping with their corresponding sub-pixel electrodes SAE and the replica pixel electrode CPE. For example, the first bridging electrode BAE1, the second bridging electrode BAE2 and the third bridging electrode BAE3 may be integrated with the first sub-pixel electrode SAE1, the second sub-pixel electrode SAE2 and the third sub-pixel electrode SAE3 and the first replica pixel electrode CPE1, the second replica pixel electrode CPE2 and the third replica pixel electrode CPE3 in the first sub-display area SDA1, respectively. In the second sub display area SDA2, the fourth bridging electrode BAE4, the fifth bridging electrode BAE5, and the sixth bridging electrode BAE6 may include a first portion overlapping with the fourth sub pixel electrode SAE4, the fifth sub pixel electrode SAE5, and the sixth sub pixel electrode SAE6 and overlapping with the fourth replica pixel electrode CPE4, the fifth replica pixel electrode CPE5, and the sixth replica pixel electrode CPE6, and a second portion connected to the first portion. The bridging electrode BAE arranged in the first sub display area SDA1 and the second sub display area SDA2 may electrically connect the sub pixel electrode SAE and the replica pixel electrode CPE, but may be arranged in different layers and have different structures.

[0208] The portions of the fourth bridging electrode BAE4, the fifth bridging electrode BAE5, and the sixth bridging electrode BAE6 that overlap with the fourth sub-pixel electrode SAE4, the fifth sub-pixel electrode SAE5, and the sixth sub-pixel electrode SAE6 may be connected to the planarization pattern PTE arranged thereunder. For example, the first portion of the fourth bridging electrode BAE4 that overlaps with the fourth sub-pixel electrode SAE4 may be connected to the planarization pattern PTE through the ninth contact hole CT9 that penetrates the interlayer insulating layer ILD. The planarization pattern PTE that overlaps with and is connected to the fourth sub-pixel electrode SAE4 may be electrically connected to the second sub-pixel circuit SPC2 through the first bridging pattern BRE1. On the other hand, the fourth bridging electrode BAE4 may not be connected to the planarization pattern PTE that overlaps with the fourth replica pixel electrode CPE4. The planarization pattern PTE that overlaps with the fourth replica pixel electrode CPE4 and is not connected to the first bridging pattern BRE1 may not receive an emission signal from the second sub-pixel circuit SPC2. Accordingly, even if the fourth bridging electrode BAE4 is not connected to the planarization pattern PTE overlapping the replica pixel electrode CPE, the fourth bridging electrode BAE4 can still receive the transmission signal by connecting to other parts of the first bridging pattern BRE1, but the present disclosure is not limited to this. Alternatively, the fourth bridging electrode BAE4, the fifth bridging electrode BAE5 and the sixth bridging electrode BAE6 arranged in the second sub-display area SDA2 may be connected to the planarization pattern PTE arranged under the replica pixel electrode CPE.

[0209] The fourth subpixel electrode SAE4, the fifth subpixel electrode SAE5, and the sixth subpixel electrode SAE6 may be arranged on the fourth bridging electrode BAE4, the fifth bridging electrode BAE5, and the sixth bridging electrode BAE6, respectively, and the fourth replica pixel electrode CPE4, the fifth replica pixel electrode CPE5, and the sixth replica pixel electrode CPE6 may also be arranged on the fourth bridging electrode BAE4, the fifth bridging electrode BAE5, and the sixth bridging electrode BAE6, respectively. The fourth subpixel electrode SAE4, the fifth subpixel electrode SAE5, and the sixth subpixel electrode SAE6 and the fourth replica pixel electrode CPE4, the fifth replica pixel electrode CPE5, and the sixth replica pixel electrode CPE6 may be arranged to overlap with the planarization pattern PTE, and may have a flat surface regardless of a step formed by a layer arranged thereunder. The fourth subpixel electrode SAE4, the fifth subpixel electrode SAE5 and the sixth subpixel electrode SAE6 and the fourth, fifth and sixth replica pixel electrodes CPE4, CPE5 and CPE6 may play the same role as the subpixel electrode SAE and the replica pixel electrode CPE arranged in the first sub display area SDA1.

[0210] For example, the fourth subpixel electrode SAE4, the fifth subpixel electrode SAE5 and the sixth subpixel electrode SAE6 and the fourth replica pixel electrode CPE4, the fifth replica pixel electrode CPE5 and the sixth replica pixel electrode CPE6 may be used as anode electrodes of the light emitting element EL arranged in the second sub display area SDA2, and may be electrically connected to each other through the fourth bridging electrode BAE4, the fifth bridging electrode BAE5 and the sixth bridging electrode BAE6. The light emitting element EL including one of the fourth subpixel electrode SAE4, the fifth subpixel electrode SAE5 and the sixth subpixel electrode SAE6 and the light emitting element EL including a corresponding one of the fourth replica pixel electrode CPE4, the fifth replica pixel electrode CPE5 and the sixth replica pixel electrode CPE6 electrically connected to the fourth subpixel electrode SAE4, the fifth subpixel electrode SAE5 and the sixth subpixel electrode SAE6 may emit light at the same time (e.g., may emit light synchronously).

[0211] The second pixel defining film 132 may be arranged in the second sub-display area SDA2. The second pixel defining film 132 may be formed of the same material as the first pixel defining film 131, and may be arranged in substantially the same layer as the first pixel defining film 131. However, considering the light transmittance of the second sub-display area SDA2, the second pixel defining film 132 may be arranged in a reduced or extremely small area. For example, the second pixel defining film 132 may be arranged in the second sub-display area SDA2 to cover the edges of the fourth sub-pixel electrode SAE4, the fifth sub-pixel electrode SAE5, and the sixth sub-pixel electrode SAE6 and the edges of the fourth replica pixel electrode CPE4, the fifth replica pixel electrode CPE5, and the sixth replica pixel electrode CPE6. In one or more embodiments, the second pixel defining film 132 may overlap with the ninth contact hole CT9 penetrating the interlayer insulating layer ILD at the edges of the fourth sub-pixel electrode SAE4, the fifth sub-pixel electrode SAE5, and the sixth sub-pixel electrode SAE6. Portions of the fourth subpixel electrode SAE4, the fifth subpixel electrode SAE5, and the sixth subpixel electrode SAE6 not covered by the second pixel defining film 132 may have a flat surface, and the light emitting layer EML disposed on the flat surface may form a flat surface regardless of the step caused by the ninth contact hole CT9.

[0212] The common electrode CE may be arranged across the main display area MDA and the sub display area SDA. In the second sub display area SDA2, the common electrode CE may be arranged on the second pixel defining film 132 and the light emitting layer EML.

[0213] The second sub-pixel circuit SPC2 arranged in the first sub-display area SDA1 may be electrically connected to the fourth sub-pixel electrode SAE4. The third connection electrode CNE3 of the second sub-pixel circuit SPC2 is connected to the fourth connection electrode CNE4 arranged on the sixth insulating layer 128 through the sixth contact hole CT6, and the fourth connection electrode CNE4 may be connected to the second bridge pattern BRE2 arranged on the interlayer insulating layer ILD via the eighth contact hole CT8. The second bridge pattern BRE2 may be electrically connected to the sub-pixel electrodes SAE (e.g., the fourth sub-pixel electrode SAE4, the fifth sub-pixel electrode SAE5, and the sixth sub-pixel electrode SAE6) arranged in the second sub-display area SDA2 through the contact pattern CTE, the first bridge pattern BRE1, and the planarization pattern PTE. Fig.11 The structure in which the second sub-pixel circuit SPC2 is electrically connected to the fourth sub-pixel electrode SAE4 is shown. The fourth sub-pixel electrode SAE4, the fifth sub-pixel electrode SAE5, and the sixth sub-pixel electrode SAE6 arranged in the second sub-display area SDA2 may not overlap with their corresponding second sub-pixel circuit SPC2 but may be electrically connected to their corresponding second sub-pixel circuit SPC2 through a bridge pattern (a first bridge pattern BRE1 and a second bridge pattern BRE2), and may be used as an anode electrode of the light emitting element EL arranged in the second sub-display area SDA2.

[0214] The fourth replica pixel electrode CPE4 arranged in the second sub-display area SDA2 may be electrically connected to the fourth sub-pixel electrode SAE4. As mentioned above, the fourth replica pixel electrode CPE4 may be electrically connected to the fourth sub-pixel electrode SAE4 through the fourth bridging electrode BAE4 arranged thereunder. The fourth bridging electrode BAE4 is arranged on the interlayer insulating layer ILD, and the fourth sub-pixel electrode SAE4 and the fourth replica pixel electrode CPE4 may be directly arranged on the fourth bridging electrode BAE4. The fourth replica pixel electrode CPE4 may be arranged not to overlap with the second sub-pixel circuit SPC2, but may be electrically connected to the second sub-pixel circuit SPC2 through the fourth sub-pixel electrode SAE4.

[0215] The fourth replica pixel electrode CPE4 may overlap the opening of the second pixel defining film 132, and form a light emitting element EL together with the light emitting layer EML disposed in the opening of the second pixel defining film 132 and the common electrode CE on the light emitting layer EML. An electrical signal for emitting light by the light emitting element EL may be synchronously (e.g., simultaneously) applied to both the fourth sub-pixel electrode SAE4 and the fourth replica pixel electrode CPE4, and a plurality of light emitting elements EL including the fourth sub-pixel electrode SAE4 and the fourth replica pixel electrode CPE4 may emit light simultaneously. The light emitting layer EML disposed on the fourth sub-pixel electrode SAE4 and the light emitting layer EML disposed on the fourth replica pixel electrode CPE4 may emit light of the same color.

[0216] Figures 12 to 19 It is shown that the arrangement Figure 1 A plan view of multiple layers in a sub-display area of ​​a display device. Figures 12 to 19 The sub-display area SDA (for example, referring to Figure 6 ) in the layer (particularly, the second semiconductor layer SCL2 (for example, refer to Fig.10 ) and a planar layout of several layers arranged on the second semiconductor layer SCL2). A description of a planar structure of layers arranged in the sub display area SDA will be presented hereinafter.

[0217] Reference Fig.12 In the first sub display area SDA1, the first sub pixel circuit SPC1 and the second sub pixel circuit SPC2 may be arranged, and in the second sub display area SDA2, a plurality of first bridge patterns BRE1 in the second semiconductor layer SCL2 may be arranged.

[0218] The first sub-pixel circuit SPC1 may be electrically connected to a sub-pixel electrode SAE (eg, referring to Figure 8 ), and the second sub-pixel circuit SPC2 may be a pixel circuit electrically connected to the sub-pixel electrode SAE arranged in the second sub-display area SDA2. The structures of the first sub-pixel circuit SPC1 and the second sub-pixel circuit SPC2 have been referred to above. Fig.10 and Fig.11 description, and therefore, a detailed description thereof will be omitted.

[0219] The first bridge patterns BRE1 may be spaced apart from each other and may have an elongated shape in one direction. The first bridge pattern BRE1 may extend from near a boundary between the first sub display area SDA1 and the second sub display area SDA2 to the second sub display area SDA2. For example, a first end of the first bridge pattern BRE1 may be connected to the first contact pattern CTE1 (for example, referring to Fig.11 ) may overlap and be connected to the first contact pattern CTE1, and a second end of the first bridge pattern BRE1 may extend to the sub-pixel electrode SAE disposed in the second sub display area SDA2. Fig.12 The arrangement of the first bridge pattern BRE1 is shown. The display device 10 (for example, referring to Figure 1 ) may vary. For example, the arrangement, configuration and number of the first bridge pattern BRE1 may vary depending on the arrangement, configuration and number of the second sub-pixel circuits SPC2 arranged in the first sub-display area SDA1 and the arrangement, configuration and number of the sub-pixel electrodes SAE in the second sub-display area SDA2.

[0220] Reference Fig.13 , the first connection electrode CNE1 of the first sub-pixel circuit SPC1 and the third connection electrode CNE3 of the second sub-pixel circuit SPC2 may be arranged in the first sub-display area SDA1. A plurality of first planarization patterns PTE1 may be arranged in the second sub-display area SDA2, and a plurality of first contact patterns CTE1 may be arranged near a boundary between the first sub-display area SDA1 and the second sub-display area SDA2. Fig.13 The fourth conductive layer CDL4 (eg, referring to Fig.10 ) is an arrangement of the first link electrode CNE1, the third link electrode CNE3, the first contact pattern CTE1 and the first planarization pattern PTE1.

[0221] The first link electrode CNE1 and the third link electrode CNE3 may be electrically connected to the first thin film transistor TFT1 (eg, referring to FIG. 1 ) of the first sub-pixel circuit SPC1, respectively. Fig.10 ) and the first thin film transistor TFT1 of the second sub-pixel circuit SPC2 (for example, refer to Fig.10 As previously mentioned, the first and third connection electrodes CNE1 and CNE3 may contact the first semiconductor layer SCL1 (eg, referring to Fig.10 ) of the first active layer ACT1 (for example, refer to Fig.10 ).

[0222] The first contact pattern CTE1 may be arranged to overlap with the first bridge pattern BRE1. The first contact pattern CTE1 may be arranged to correspond to and contact the first bridge pattern BRE1. The first contact pattern CTE1 may be arranged to overlap with an end portion of the first bridge pattern BRE1 positioned near a boundary between two different sub display areas (i.e., a boundary between the first sub display area SDA1 and the second sub display area SDA2).

[0223] The first planarization patterns PTE1 may be arranged in the second sub display area SDA2. The first planarization patterns PTE1 may be spaced apart from each other, and the arrangement of the first planarization patterns PTE1 may correspond to the sub-pixel electrode SAE and the replica pixel electrode CPE (eg, referring to Figure 8 ). Some of the first planarization patterns PTE1 may be arranged to overlap the sub-pixel electrode SAE, and other first planarization patterns PTE1 may be arranged to overlap the replica pixel electrode CPE. The first planarization pattern PTE1 overlapping the sub-pixel electrode SAE may be arranged to overlap and contact the first bridge pattern BRE1. For example, the first planarization pattern PTE1 may contact the first bridge pattern BRE1 through the seventh contact hole CT7.

[0224] Reference Fig.14, the sixth insulating layer 128 may be arranged in the first sub display area SDA1. The sixth insulating layer 128 may be arranged at the boundary between the first sub display area SDA1 and the second sub display area SDA2 so as not to overlap with the first contact pattern CTE1. As mentioned above, the sixth insulating layer 128 may include an organic insulating material, and considering the light transmittance of the second sub display area SDA2, the sixth insulating layer 128 may not be arranged in the second sub display area SDA2. In one or more embodiments, the sixth insulating layer 128 may be arranged in the entire main display area MDA (for example, refer to Figure 1 )middle.

[0225] The sixth insulating layer 128 may include a plurality of fourth contact holes CT4 and a plurality of sixth contact holes CT6 penetrating the sixth insulating layer 128. The fourth contact holes CT4 may be formed to correspond to the first connection electrode CNE1, and the sixth contact holes CT6 may be formed to correspond to the third connection electrode CNE3.

[0226] Reference Fig.15 , the second connection electrode CNE2 of the first sub-pixel circuit SPC1 and the fourth connection electrode CNE4 of the second sub-pixel circuit SPC2 may be arranged in the first sub-display area SDA1. A plurality of second planarization patterns PTE2 may be arranged in the second sub-display area SDA2, and a plurality of second contact patterns CTE2 may be arranged near a boundary between the first sub-display area SDA1 and the second sub-display area SDA2. Fig.15 The fifth conductive layer CDL5 (eg, referring to Fig.10 ) of the second connection electrode CNE2, the fourth connection electrode CNE4, the second contact pattern CTE2 and the second planarization pattern PTE2.

[0227] The second connection electrode CNE2 and the fourth connection electrode CNE4 may be arranged to overlap the first connection electrode CNE1 and the third connection electrode CNE3, respectively. The second connection electrode CNE2 may contact the first connection electrode CNE1 through a fourth contact hole CT4 formed in the sixth insulating layer 128, and the fourth connection electrode CNE4 may contact the third connection electrode CNE3 through a sixth contact hole CT6 formed in the sixth insulating layer 128.

[0228] The second contact pattern CTE2 and the second planarization pattern PTE2 may be arranged to correspond to the first contact pattern CTE1 and the first planarization pattern PTE1, respectively. The second contact pattern CTE2 may be formed to have a larger plane area than the first contact pattern CTE1, and thus cover the outer surface (e.g., the outer peripheral surface) of the first contact pattern CTE1. The second planarization pattern PTE2 may be formed to have a larger plane area than the first planarization pattern PTE1, and thus cover the outer surface (e.g., the outer peripheral surface) of the first planarization pattern PTE1. The first contact pattern CTE1 and the second contact pattern CTE2 may be paired to serve as a connection between the first bridge pattern BRE1 and the second bridge pattern BRE2 (e.g., refer to Fig.11 ) electrode. Also, the first planarization pattern PTE1 and the second planarization pattern PTE2 may be paired to serve as a connection between the first bridge pattern BRE1 and the bridge electrode BAE (eg, referring to Figure 8 ) electrode. Additionally, the planarization pattern PTE (eg, referring to Fig.11 ) may be paired to planarize the area where the sub-pixel electrode SAE and the replica pixel electrode CPE of the second sub-display area SDA2 are arranged.

[0229] Reference Fig.16 , the interlayer insulating layer ILD may be arranged across the first sub display area SDA1 and the second sub display area SDA2. The interlayer insulating layer ILD may be used as an inorganic via layer in the second sub display area SDA2 where no organic insulating material is arranged. In one or more embodiments, the interlayer insulating layer ILD may also be arranged in the main display area MDA.

[0230] In the first sub display area SDA1, the interlayer insulating layer ILD may include a fifth contact hole CT5 formed to overlap the second connection electrode CNE2 and an eighth contact hole CT8 formed to overlap the fourth connection electrode CNE4. In the second sub display area SDA2, the interlayer insulating layer ILD may include a ninth contact hole CT9 formed to overlap some of the second planarization pattern PTE2.

[0231] Reference Fig.17 , a plurality of second bridge patterns BRE2 may be arranged in the first sub display area SDA1. A plurality of bridge electrodes BAE (ie, a fourth bridge electrode BAE4, a fifth bridge electrode BAE5, and a sixth bridge electrode BAE6) may be arranged in the second sub display area SDA2.

[0232] The second bridge patterns BRE2 may be spaced apart from each other and may have an elongated shape in one direction. The second bridge pattern BRE2 may extend from the vicinity of a boundary between the first sub display area SDA1 and the second sub display area SDA2 toward the first sub display area SDA1. A first end of the second bridge pattern BRE2 may overlap and be connected to the second contact pattern CTE2, and a second end of the second bridge pattern BRE2 may extend up to the fourth connection electrode CNE4 of the first sub display area SDA1. Fig.17 Some of the second bridge patterns BRE2 may extend to the fourth connection electrode CNE4 of the second sub-pixel circuit SPC2 and may be connected to the fourth connection electrode CNE4 through the eighth contact hole CT8. Other second bridge patterns BRE2 may be connected to the fourth connection electrode CNE4 of the second sub-pixel circuit SPC2. Fig.17 The fourth connection electrode CNE4 of the other second sub-pixel circuit SPC2 not shown in the figure. However, the second bridge pattern BRE2 may be arranged not to overlap with the fifth contact hole CT5 formed to overlap with the first sub-pixel circuit SPC1. The second bridge pattern BRE2 extending in one direction may be arranged to bypass the fifth contact hole CT5, and the sub-pixel electrode SAE may be connected to the second connection electrode CNE2 through the fifth contact hole CT5. The second sub-pixel circuit SPC2 may be electrically connected to the second bridge pattern BRE2, the contact pattern CTE (for example, refer to Fig.11 The second bridge pattern BRE2, the contact pattern CTE, the first bridge pattern BRE1, and the planarization pattern PTE may be used as a path for transferring an emission signal applied from the second sub-pixel circuit SPC2.

[0233] Fig.17 The arrangement of the second bridge pattern BRE2 is shown. The arrangement and layout of the second bridge pattern BRE2 in the display device 10 can be modified variably. For example, the arrangement, layout and number of the second bridge pattern BRE2 can be changed according to the arrangement, layout and number of the second sub-pixel circuits SPC2 arranged in the first sub-display area SDA1 and the arrangement, layout and number of the sub-pixel electrodes SAE arranged in the second sub-display area SDA2.

[0234] Each of the fourth bridging electrode BAE4, the fifth bridging electrode BAE5, and the sixth bridging electrode BAE6 may be arranged to overlap with two different planarization patterns PTE. The fourth bridging electrode BAE4, the fifth bridging electrode BAE5, and the sixth bridging electrode BAE6 may include a first portion arranged to overlap with the planarization pattern PTE and a second portion connecting the first portion. The first portion or the second portion of the fourth bridging electrode BAE4, the fifth bridging electrode BAE5, and the sixth bridging electrode BAE6 may be connected to the planarization pattern PTE through a ninth contact hole CT9.

[0235] In one or more embodiments, the plurality of second bridge patterns BRE2 and the fourth, fifth, and sixth bridge electrodes BAE4, BAE5, and BAE6 arranged in the second sub display area SDA2 may include TCO such as ITO or IZO.

[0236] Reference Fig.18 , like the sixth insulating layer 128, the seventh insulating layer 129 may be arranged in the first sub display area SDA1 and also partially in the second sub display area SDA2. The seventh insulating layer 129 may be arranged to cover the contact pattern CTE near the boundary between the first sub display area SDA1 and the second sub display area SDA2. However, the seventh insulating layer 129 may not overlap the bridging electrode BAE and the planarization pattern PTE arranged in the second sub display area SDA2. The seventh insulating layer 129 may include a fifth contact hole CT5 formed to penetrate the seventh insulating layer 129.

[0237] Reference Fig.19 , the first sub-pixel electrode SAE1, the second sub-pixel electrode SAE2 and the third sub-pixel electrode SAE3, the first replica pixel electrode CPE1, the second replica pixel electrode CPE2 and the third replica pixel electrode CPE3, and the first bridge electrode BAE1, the second bridge electrode BAE2 and the third bridge electrode BAE3 may be arranged in the first sub-display area SDA1. The fourth sub-pixel electrode SAE4, the fifth sub-pixel electrode SAE5 and the sixth sub-pixel electrode SAE6 and the fourth replica pixel electrode CPE4, the fifth replica pixel electrode CPE5 and the sixth replica pixel electrode CPE6 may be arranged in the second sub-display area SDA2. The first subpixel electrode SAE1, the second subpixel electrode SAE2 and the third subpixel electrode SAE3, the first replica pixel electrode CPE1, the second replica pixel electrode CPE2 and the third replica pixel electrode CPE3 and the first bridging electrode BAE1, the second bridging electrode BAE2 and the third bridging electrode BAE3 of the first sub display area SDA1 may be arranged on the seventh insulating layer 129, and the fourth subpixel electrode SAE4, the fifth subpixel electrode SAE5 and the sixth subpixel electrode SAE6 and the fourth replica pixel electrode CPE4, the fifth replica pixel electrode CPE5 and the sixth replica pixel electrode CPE6 of the second sub display area SDA2 may be arranged on the fourth bridging electrode BAE4, the fifth bridging electrode BAE5 and the sixth bridging electrode BAE6.

[0238] The sub-pixel electrode SAE, the replica pixel electrode CPE, and the bridging electrode BAE in the first sub-display area SDA1 may be integrated together to form a single electrode. For example, the first sub-pixel electrode SAE1, the first bridging electrode BAE1, and the first replica pixel electrode CPE1 may be integrated together to form a single electrode. The first sub-pixel electrode SAE1 may be arranged to overlap with the first sub-pixel circuit SPC1, and may be connected to the second connection electrode CNE2 through the fifth contact hole CT5. The first replica pixel electrode CPE1 may be integrated with the first bridging electrode BAE1 and the first sub-pixel electrode SAE1, and may be electrically connected to the second connection electrode CNE2. The same emission signal may be applied to the paired sub-pixel electrodes SAE and the replica pixel electrode CPE arranged in the first sub-display area SDA1.

[0239] The sub-pixel electrode SAE and the replica pixel electrode CPE in the second sub-display area SDA2 may be arranged on the bridging electrode BAE. For example, the fourth sub-pixel electrode SAE4 and the fourth replica pixel electrode CPE4 may be arranged on the first portion of the fourth bridging electrode BAE4 arranged on the planarization pattern PTE, and may directly contact the first portion of the fourth bridging electrode BAE4. The fourth bridging electrode BAE4 may be electrically connected to their corresponding second sub-pixel circuits SPC2 through the planarization pattern PTE, the bridging pattern (the first bridging pattern BRE1 and the second bridging pattern BRE2) and the contact pattern CTE. The fourth sub-pixel electrode SAE4 and the fourth replica pixel electrode CPE4 may be electrically connected to their corresponding second sub-pixel circuits SPC2 through the fourth bridging electrode BAE4. The same emission signal may be applied to the paired sub-pixel electrodes SAE and the replica pixel electrodes CPE arranged in the second sub-display area SDA2.

[0240] In one or more embodiments, the planarization pattern PTE arranged in the second sub display area SDA2 may have an area larger than the first portion of the bridging electrode BAE, the sub-pixel electrode SAE, and the replica pixel electrode CPE arranged thereon. For example, in one or more embodiments, the planarization pattern PTE may have an area larger than the first portion of the fourth replica pixel electrode CPE4 and the fourth bridging electrode BAE4 with which they overlap. Therefore, the top surfaces of the fourth sub-pixel electrode SAE4, the fourth replica pixel electrode CPE4, and the fourth bridging electrode BAE4 arranged on the planarization pattern PTE may be formed to be flat. Even if an organic insulating material for planarization is not arranged in the second sub display area SDA2, the display device 10 can ensure that the light emitting element EL (for example, refer to Fig.11 ) of the anode electrode of the pixel electrode. Accordingly, the light emitting layer EML (for example, referring to Fig.11) can be formed on a flat surface, thereby preventing degradation caused by steps.

[0241] In addition, patterns (such as the first bridge pattern BRE1, the contact pattern CTE, and the planarization pattern PTE) for connecting the second sub-pixel circuit SPC2 and the sub-pixel electrode SAE arranged in the second sub-display area SDA2 can be formed in the same layer (for example, at) as the semiconductor layer or the conductive layer for implementing the pixel circuits in the main display area MDA and the first sub-display area SDA1. As a result, an advantage of not adding the number of masks during the manufacture of the display device 10 can be provided.

[0242] Furthermore, in one or more embodiments, Fig.10 and Fig.11 As shown in , the first pixel defining film 131 and the second pixel defining film 132, the light emitting layer EML and the common electrode CE may be arranged on the sub-pixel electrode SAE and the replica pixel electrode CPE. As mentioned earlier, the first pixel defining film 131 may be arranged in the entire main display area MDA and the entire first sub-display area SDA1, but an opening exposing a portion of the sub-pixel electrode SAE and a portion of the replica pixel electrode CPE may be formed in the first pixel defining film 131. Additionally, as mentioned earlier, the second pixel defining film 132 may be arranged in the second sub-display area SDA2 to cover only the edges of the sub-pixel electrode SAE and the replica pixel electrode CPE.

[0243] Fig. 20 is a cross-sectional view illustrating a sub display region of a display device according to one or more embodiments of the present disclosure.

[0244] Reference Fig. 20 , the display device 10 (for example, referring to Figure 1 ) may include a plurality of openings formed to correspond to the planarization pattern PTE in the second sub-display area SDA2. The bridging electrodes (the fourth bridging electrode BAE4, the fifth bridging electrode BAE5, and the sixth bridging electrode BAE6 (eg, refer to Figure 8 )) may be disposed on the interlayer insulating layer ILD and may be directly positioned on the planarization pattern PTE through the opening. Fig. 20 Examples and Fig.11 The embodiment of FIG. 1 is different in that the bridging electrodes (the fourth bridging electrode BAE4, the fifth bridging electrode BAE5, and the sixth bridging electrode BAE6) in the second sub display area SDA2 contact the planarization pattern PTE with a larger area through the openings rather than through the contact holes.

[0245] The display device 10 can ensure the flatness of the sub-pixel electrode SAE and the replica pixel electrode CPE used as the anode electrode by arranging the planarization pattern PTE in the second sub-display area SDA2. In one or more embodiments, if the flat area of ​​the planarization pattern PTE is large enough, an opening can be formed in the interlayer insulating layer ILD to ensure flatness while synchronously (e.g., simultaneously) increasing the contact area between the bridging electrode BAE and the planarization pattern PTE. The opening of the interlayer insulating layer ILD can be larger than the opening of the second pixel defining film 132, and the second pixel defining film 132 can cover the stepped portion of the sub-pixel electrode SAE and the replica pixel electrode CPE due to the opening of the interlayer insulating layer ILD. Accordingly, at least the portion of the sub-pixel electrode SAE and the replica pixel electrode CPE exposed by the opening of the second pixel defining film 132 can have a flat surface, and the light-emitting layer EML arranged on the exposed portion of the sub-pixel electrode SAE and the replica pixel electrode CPE can be formed on the flat surface.

[0246] At the end of the detailed description, it will be appreciated by those skilled in the art that many changes and modifications can be made to the embodiments without departing substantially from the principles, spirit and scope of the present disclosure. Therefore, the embodiments of the present disclosure are used only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A display device, comprising: A first sub-display area and a second sub-display area adjacent to each other and a main display area around the first sub-display area and the second sub-display area; a plurality of pixel electrodes, the plurality of pixel electrodes being spaced apart from each other in the main display area; a plurality of first sub-pixel electrodes, the plurality of first sub-pixel electrodes being in the first sub-display region and spaced apart from each other; a plurality of first duplicate pixel electrodes, the plurality of first duplicate pixel electrodes being in the first sub-display area and connected to the plurality of first sub-pixel electrodes through a plurality of first bridging electrodes; a plurality of planarization patterns, wherein the plurality of planarization patterns are in the second sub-display area; a plurality of second sub-pixel electrodes and a plurality of second replica pixel electrodes, the plurality of second sub-pixel electrodes and the plurality of second replica pixel electrodes being in the second sub-display region and overlapping the plurality of planarization patterns; as well as A plurality of second bridging electrodes are provided, and the plurality of second bridging electrodes overlap with the plurality of second sub-pixel electrodes or the plurality of second replica pixel electrodes.

2. The display device according to claim 1, wherein: The first sub-pixel electrode, the first replica pixel electrode and the first bridge electrode are integrated together in the first sub-display area.

3. The display device according to claim 1, wherein: The second bridge electrode overlaps with a different planarization pattern.

4. The display device according to claim 3, wherein: Each of the plurality of second bridge electrodes is in direct contact with one of the plurality of planarization patterns.

5. The display device according to claim 1, wherein: In a plan view, the planarization pattern has a larger area than both the second sub-pixel electrode and the second replica pixel electrode.

6. The display device according to claim 1, wherein: The planarization pattern includes a first planarization pattern and a second planarization pattern directly located on the first planarization pattern, and The second planarization pattern covers an outer surface of the first planarization pattern.

7. The display device according to claim 1, further comprising: a plurality of first bridge patterns extending in one direction in the second sub-display area; a plurality of second bridge patterns, the plurality of second bridge patterns extending in the first sub-display area in the one direction; as well as A plurality of contact patterns overlap the plurality of first bridge patterns and the plurality of second bridge patterns near a boundary between the first sub display area and the second sub display area.

8. The display device according to claim 7, further comprising: a plurality of first sub-pixel circuits and a plurality of second sub-pixel circuits, wherein the plurality of first sub-pixel circuits and the plurality of second sub-pixel circuits are in the first sub-display area, wherein the plurality of first sub-pixel electrodes overlap with the plurality of first sub-pixel circuits, and At least some of the plurality of first replica pixel electrodes overlap with a plurality of the second sub-pixel circuits.

9. The display device according to claim 8, wherein: Each of the plurality of second bridge patterns is electrically connected to one of the plurality of second sub-pixel circuits.

10. The display device according to claim 7, wherein: Each of the plurality of first bridge patterns is connected to one of the plurality of planarization patterns.

11. The display device according to claim 7, wherein: Each of some of the plurality of second bridge patterns overlaps the first sub-pixel electrode but is not connected to the first sub-pixel electrode.

12. The display device according to claim 7, further comprising: a first insulating layer, the first insulating layer being in the main display area and the first sub-display area and comprising an organic insulating material; as well as an interlayer insulating layer, the interlayer insulating layer being on the first insulating layer in the main display area and the first sub-display area and the second sub-display area, The first insulating layer does not overlap with the plurality of planarization patterns, the plurality of second sub-pixel electrodes, and the plurality of second replica pixel electrodes.

13. The display device according to claim 12, wherein: In the second sub display area, the interlayer insulating layer overlaps the plurality of planarization patterns, the plurality of second sub-pixel electrodes, and the plurality of second replica pixel electrodes.

14. The display device according to claim 12, wherein: The interlayer insulating layer overlaps the plurality of contact patterns.

15. The display device according to claim 1, further comprising: a first pixel defining film, the first pixel defining film being in the main display area and the first sub-display area and having a plurality of openings overlapping the plurality of pixel electrodes, the plurality of first sub-pixel electrodes, and the plurality of first replica pixel electrodes; as well as A second pixel defining film is in the second sub-display region and covers edges of the plurality of second sub-pixel electrodes and edges of the plurality of second replica pixel electrodes.

16. A display device, comprising: a substrate having a first sub-display area and a second sub-display area adjacent to each other and a main display area around the first sub-display area and the second sub-display area; a semiconductor layer including, on the substrate, a plurality of active layers in the main display area and the first sub-display area and a plurality of first bridge patterns in the second sub-display area; a first insulating layer, the first insulating layer being on the semiconductor layer; a first conductive layer including a plurality of first connection electrodes in the first sub-display area and a plurality of first planarization patterns in the second sub-display area on the first insulating layer; a second insulating layer, the second insulating layer being on the first conductive layer and not in the second sub-display area; a second conductive layer including a plurality of second connecting electrodes on the second insulating layer in the first sub-display area and a plurality of second planarization patterns on the plurality of first planarization patterns in the second sub-display area; an interlayer insulating layer, the interlayer insulating layer being on the second conductive layer; a plurality of second bridge patterns and a plurality of bridge electrodes, wherein the plurality of second bridge patterns are on the interlayer insulating layer in the first sub-display area, and the plurality of bridge electrodes are on the plurality of second planarization patterns in the second sub-display area; a third insulating layer, the third insulating layer being on the interlayer insulating layer and the plurality of second bridge patterns in the main display area and the first sub-display area; A plurality of pixel electrodes, wherein the plurality of pixel electrodes are on the third insulating layer in the main display area; a plurality of first sub-pixel electrodes and a plurality of first replica pixel electrodes, the plurality of first sub-pixel electrodes and the plurality of first replica pixel electrodes being on the third insulating layer in the first sub-display area; as well as A plurality of second sub-pixel electrodes and a plurality of second replica pixel electrodes are provided on the plurality of bridge electrodes in the second sub-display area.

17. The display device according to claim 16, wherein: The bridge electrode includes a first portion on different second planarization patterns and a second portion connecting the first portions, and The second sub-pixel electrode and the second duplicate pixel electrode are respectively on different first portions of the bridge electrode.

18. The display device according to claim 16, wherein: A width of the second planarization pattern is greater than a width of the second sub-pixel electrode and a width of the second replica pixel electrode.

19. The display device according to claim 16, wherein: The first connecting electrode and the second connecting electrode are electrically connected to the first sub-pixel electrode, and The first replica pixel electrode is integrated with the first sub-pixel electrode.

20. The display device according to claim 16, wherein: The semiconductor layer includes a first semiconductor layer and a second semiconductor layer, the first semiconductor layer includes a first active layer, the second semiconductor layer includes a second active layer and is located between the first semiconductor layer and the first insulating layer, and includes the plurality of first bridge patterns.

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