Display screen and display device

Abstract

The embodiment of the invention provides a display screen and a display device, and relates to the technical field of display. The display screen comprises a display area and a non-display area at least partially surrounding the display area, and the non-display area comprises a bonding area located on one side of the display area; the display screen comprises a pixel array located in a display area and bonding pins located in a bonding area, the colors of odd-numbered rows of pixels in any column of pixels of the pixel array are the same, the colors of the odd-numbered rows of pixels are connected to one data line, the colors of even-numbered rows of pixels in any column of pixels are the same, and the colors of the even-numbered rows of pixels are connected to the other data line. Pixels with the same color in multiple columns of pixels of the pixel array are connected to at least one bonding pin through multiple data lines, and each bonding pin in the at least one bonding pin is used for outputting pixel signals with the same color. The technical scheme is beneficial to reducing the overall power consumption of the device where the display screen is located.

Description

Technical Field

[0001] The present application relates to the field of display technology, and more specifically, to a display screen and a display device. Background Art

[0002] As an indispensable component of modern electronic devices, the power consumption of display screens is receiving increasing attention. Reducing the power consumption of display screens not only helps to extend the service life of the equipment and reduce energy consumption, but also effectively reduces the need for heat dissipation and improves the user experience. In the current era of advocating green environmental protection, energy conservation and emission reduction, the importance of reducing the power consumption of display screens is self-evident, and it has become an important technical direction to promote the sustainable development of the electronics industry.

[0003] In view of this, how to reduce the power consumption of display screens is a technical issue that needs to be continuously studied in the display field. Summary of the invention

[0004] Embodiments of the present application provide a display screen and a display device that can have lower power consumption.

[0005] In a first aspect, a display screen is provided, comprising: a display area and a non-display area at least partially surrounding the display area, the non-display area comprising a bonding area located on one side of the display area; the display screen comprises a pixel array located in the display area and bonding pins located in the bonding area, wherein the odd-numbered rows of pixels in any column of pixels in the pixel array have the same color, the odd-numbered rows of pixels are connected to one data line, and the even-numbered rows of pixels in any column of pixels have the same color, the even-numbered rows of pixels are connected to another data line; pixels with the same color in multiple columns of pixels in the pixel array are connected to at least one bonding pin via multiple data lines, and each of the at least one bonding pin is used to output pixel signals of the same color.

[0006] Through the technical solution of the embodiment of the present application, in a display screen with a DDL architecture, the same bonding pin of the bonding area used to provide data signals is used to transmit pixel signals of the same color without generating conversion of pixel signals of different colors, which is beneficial to reducing the power consumption of the data driver chip connected to the bonding pin, thereby helping to further reduce the overall power consumption of the device in which the display screen is located.

[0007] In some possible embodiments, the display screen also includes: multiple switching tubes and a multi-way selection circuit, located in the non-display area between the display area and the bonding area; each data line connected to the pixel array is correspondingly connected to a switching tube, the switching tube is connected between the data line and the bonding pin, and the switching tube is used to receive a control signal from the multi-way selection circuit to control the data signal timing of multiple pixels connected to the data line.

[0008] In the technical solution of this embodiment, the data signal timing of the pixels in the pixel array is controlled by a multiplexer circuit (MUX), so the data driver chip connected to the bonding pin only needs to continuously provide the pixel data signal without adding additional timing control. The MUX can be used to ensure the accurate display of each pixel in the display screen and the display effect of the display screen. In addition, the data driver chip can also simplify the related timing control, which is conducive to further reducing the power consumption and cost of the data driver chip.

[0009] In some possible implementations, a plurality of switch tubes connected to the same bonding pin in the bonding area are used to respectively receive a plurality of different control signals, so that the opening times of the plurality of switch tubes connected to the same bonding pin are staggered.

[0010] The technical solution of this implementation is beneficial to the timing design of data signals transmitted through the bonding pins, thereby ensuring the normal picture display of the display screen.

[0011] In some possible implementations, the sum of the unit effective pulse widths of the plurality of control signals is less than or equal to 2 unit times, where the unit time is the time during which a row of pixels is turned on.

[0012] In some possible implementations, in the plurality of control signals, there is a preset time interval between adjacent unit effective pulses.

[0013] In some possible implementations, the preset time interval is greater than or equal to a maximum value of a rise time and a fall time of a data signal transmitted by the bonding pin.

[0014] In the above-mentioned several implementation modes, by designing the pulse waveform parameters of the control signal output by the MUX, the control effect of the MUX control signal can be further guaranteed, so as to improve the display effect of the display screen.

[0015] In some possible implementations, each of the multiple control signals is used to control multiple switch tubes connected to different bonding pins in the bonding area, so that the opening time of the multiple switch tubes connected to different bonding pins is the same.

[0016] Through the technical solution of this implementation, multiple pixels in the pixel array are driven in parallel by control signals, which is beneficial to improving the refresh rate of the display screen while ensuring normal image display of the display screen.

[0017] In some possible embodiments, a pixel array includes a plurality of pixel groups, each pixel group includes four columns of pixels, the first column of pixels and the third column of pixels in the four columns of pixels include blue pixels and red pixels arranged alternately, the red pixels and the blue pixels in the first column of pixels and the third column of pixels have different odd and even orders, and the second column of pixels and the fourth column of pixels include green pixels; the odd-numbered rows of red pixels in the first column of pixels and the even-numbered rows of red pixels in the third column of pixels are connected to a first bonding pin in a bonding area, and the first bonding pin is used to output a red data signal; the even-numbered rows of blue pixels in the first column of pixels and the odd-numbered rows of blue pixels in the third column of pixels are connected to a second bonding pin in the bonding area, and the second bonding pin is used to output a blue data signal; the odd-numbered rows of green pixels in the second column of pixels and the even-numbered rows of green pixels in the fourth column of pixels are connected to a third bonding pin in the bonding area, and the third bonding pin is used to output a first green data signal; the even-numbered rows of green pixels in the second column of pixels and the odd-numbered rows of green pixels in the fourth column of pixels are connected to a fourth bonding pin in the bonding area, and the fourth bonding pin is used to output a second green data signal.

[0018] In this embodiment, the distribution of red pixels, blue pixels and green pixels in the pixel array can be relatively uniform, which is beneficial to improving the display performance of the display screen.

[0019] In some possible embodiments, in four columns of pixels, the four data lines connected to the odd-numbered rows of pixels are respectively connected to four first switch tubes, which are used to receive a first control signal to control the switching state of the first switch tubes; the multiple data lines connected to the even-numbered rows of pixels are connected to multiple second switch tubes, which are used to receive a second control signal to control the switching state of the second switch tubes; wherein the opening time of the first switch tubes and the second switch tubes are staggered.

[0020] In the above technical solution, the number of output pins of the data driver chip and the number of bonding pins in the bonding area can be the same as the number of pixel columns in the pixel array, and two MUX control signals can be used to realize the data input of each pixel in the pixel array, and control the display screen to display a reliable picture. The number of MUX control signals in this technical solution is small, which is conducive to simplifying the control and implementation of the MUX circuit.

[0021] In some possible embodiments, two adjacent rows of pixels in a pixel array are used to respectively receive a first row drive signal and a second row drive signal, a unit effective pulse in the first row drive signal is located between two adjacent unit effective pulses in the first control signal, and a unit effective pulse in the second row drive signal is located between two adjacent unit effective pulses in the second control signal.

[0022] In some possible embodiments, multiple columns of pixels in at least two pixel groups are connected to a first bonding pin, a second bonding pin, a third bonding pin, and a fourth bonding pin; the switching tubes on the four data lines connected to the odd-numbered rows of pixels in each pixel group are used to receive a control signal, and the switching tubes on the four data lines connected to the even-numbered rows of pixels in each pixel group are used to receive another control signal, and different pixel groups receive different control signals.

[0023] In the technical solution provided in this embodiment, multiple pixel groups can be connected to four bonding pins in common, which is beneficial to reducing the number of bonding pins in the bonding area and the number of pins of the data driver chip, thereby reducing the power consumption of the data driver chip.

[0024] In some possible embodiments, eight columns of pixels in two pixel groups are connected to a first bonding pin, a second bonding pin, a third bonding pin and a fourth bonding pin; in the eight columns of pixels, four data lines connected to the odd-numbered rows of pixels in the first four columns of pixels are respectively connected to four first switch tubes, which are used to receive a first control signal to control the switching state of the first switch tubes; four data lines connected to the odd-numbered rows of pixels in the last four columns of pixels are respectively connected to four second switch tubes, which are used to receive a second control signal to control the switching state of the second switch tubes; four data lines connected to the even-numbered rows of pixels in the first four columns of pixels are respectively connected to four third switch tubes, which are used to receive a third control signal to control the switching state of the third switch tubes; four data lines connected to the even-numbered rows of pixels in the last four columns of pixels are respectively connected to four fourth switch tubes, which are used to receive a fourth control signal to control the switching state of the fourth switch tube; wherein, the opening times of the first switch tube, the second switch tube, the third switch tube and the fourth switch tube are staggered with each other.

[0025] In the technical solution provided in this embodiment, the display screen can be controlled to display a stable picture through four bonding pins and four MUX control signals. In this technical solution, the number of pins of the data driver chip and the number of bonding pins in the bonding area can be reduced, that is, reduced to half the number of columns of the pixel array, which is conducive to further reducing the power consumption of the data driver chip, thereby reducing the overall power consumption of the display screen. In addition, the four MUX control signals can also ensure the charging effect of each pixel in the pixel array, thereby ensuring the display effect of the display screen.

[0026] In some possible embodiments, two adjacent rows of pixels in a pixel array are used to receive a first row drive signal and a second row drive signal, respectively, and unit effective pulses of the first control signal, the second control signal, the third control signal, and the fourth control signal are adjacent in sequence in the time domain; the unit effective pulse in the first row drive signal is located between two adjacent unit effective pulses in the first control signal, and the unit effective pulse in the second row drive signal is located between two adjacent unit effective pulses in the third control signal.

[0027] In a second aspect, a display device is provided, comprising: a data driving chip, and a display screen provided by the first aspect or any possible implementation manner of the first aspect, wherein the data driving chip is located in a bonding area of ​​the display screen.

[0028] In some possible implementations, the pins of the data driver chip are connected correspondingly to the bonding pins in the bonding area, and the data driver chip is configured to output multiple data signals of a column of pixels in the pixel array through multiple pins respectively, and one pin is used to output data signals of the same color. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of a display screen provided in an embodiment of the present application.

[0030] Figure 2 This is a schematic diagram of pixel distribution in a display screen provided in an embodiment of the present application.

[0031] Figure 3 yes Figure 2 A timing diagram of each signal in the illustrated embodiment.

[0032] Figure 4 This is a schematic diagram of a display screen provided in an embodiment of the present application.

[0033] Figure 5 is another schematic diagram of the display screen provided in an embodiment of the present application.

[0034] Figure 6 yes Figure 5 A timing diagram of each signal in the illustrated embodiment.

[0035] Figure 7 is another schematic diagram of the display screen provided in an embodiment of the present application.

[0036] Figure 8 yes Figure 7 A timing diagram of each signal in the illustrated embodiment.

[0037] Fig. 9 It is a schematic structural block diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0039] The present application relates to a display screen, which can be applied to a variety of fields and scenarios. As an example, the display screen can be applied to 3C electronic products of computers, communications and consumer electronics, including but not limited to televisions, mobile phones, computers, laptops, tablets, personal digital assistants (PDAs), car computers, wearable devices, gaming devices, photographing equipment, etc. The present application does not limit the specific type of electronic device in which the display screen is located.

[0040] In addition, the display screen involved in the present application may be a liquid crystal display (LCD) or an organic light-emitting diode (OLED) display screen, a low-temperature polycrystalline silicon (LTPS) OLED display screen, an oxide OLED display screen, a micro OLED display screen, etc. The present application does not limit the specific type of the display screen.

[0041] Figure 1 A schematic diagram of a display screen provided in an embodiment of the present application is shown.

[0042] like Figure 1 As shown, the display screen 100 includes: a pixel array 110, a scan driving circuit 120 and a data driving circuit 130. The pixel array 110 includes a plurality of pixels 111, and the plurality of pixels 111 can be arranged into N rows and M columns according to actual needs to form a display area of ​​the display screen 100 and present display effects of different pictures.

[0043] For an OLED display screen, each pixel 111 may include an independent light-emitting unit and a pixel circuit for controlling the light-emitting unit. The light-emitting unit may include organic light-emitting materials of three colors: red, green, and blue. The light-emitting materials are driven by current to emit light to form color pixels. The pixel circuit may include electrical components such as a switch tube and a capacitor. The state of the switch tube is controlled by a control signal, so that the light-emitting unit can be effectively driven.

[0044] For other types of display screens, each has its own light-emitting principle, but no matter which display screen is used, each pixel 111 thereof has a pixel circuit to control the light emission of each pixel 111. The scanning drive circuit 120 and the data drive circuit 130 can be connected to each pixel 111 in the pixel array 110, so as to provide a control signal to the pixel circuit of each pixel. Specifically, for N rows and M columns of pixels 111, the scanning drive circuit 120 can be connected to the N rows of pixels 111 to control the turning on and off of the N rows of pixels 111. The data drive circuit 130 can be connected to the M columns of pixels 111 to provide display data to the M columns of pixels.

[0045] Alternatively, if Figure 1 As shown, the display screen 100 may further include a timing control circuit 140, which may also be referred to as a timing controller (Timer Control Register, TCON), which may be connected to the scan drive circuit 120 and / or the data drive circuit 130. The timing control circuit 140 may receive a display control signal, and control the working timing of the scan drive circuit 120 and / or the data drive circuit 130 according to the display control signal, and may control the display data of the data drive circuit 130, wherein the display control signal includes but is not limited to: a power signal, an image signal, a mode control signal, and the like.

[0046] In some implementations of the embodiments of the present application, the data driver circuit 130 may be a source driver or a source driver chip (Source Driver IC), which may also be referred to as a data driver chip. The data driver circuit 130 is used to provide data signals or source drive signals to the pixels in the pixel array 110, thereby controlling the luminous brightness of the pixels. Optionally, the data driver circuit 130 may be separately provided from the display panel 101 where the pixel array 110 is located. The display panel 101 may have different structures according to different types of display screens 100, but generally speaking, the substrate of the display panel is a transparent substrate such as glass or plastic, and the pixel circuit of the pixel array 110 may be formed on the substrate through a semiconductor process, and then the light-emitting unit of the pixel array 110 may be formed in combination with other components, thereby forming the main part of the display screen 100, the display panel 101. The specific structure of the display panel 101 may refer to the specific description of the relevant technology, and will not be described in detail here.

[0047] In some implementations of the embodiments of the present application, the scan driver circuit 120 may be a gate driver or a gate driver chip (Gate Driver IC), which may also be referred to as a scan driver chip. The scan driver circuit 120 may be used to provide a gate drive signal or a row drive signal to the pixels in the pixel array 110, thereby controlling the opening of each row of pixels. Optionally, the scan driver circuit 120 may be set independently of the display panel 101. Alternatively, as Figure 1 As shown, the scan driving circuit 120 can also be integrated into the display panel 101. The scan driving circuit 120 can be called a GOA circuit. The GOA circuit can be prepared on a transparent substrate synchronously with the pixel circuit of the pixel array 110, thereby simplifying the manufacturing process of the display screen 100.

[0048] Figure 2 A schematic diagram showing pixel distribution in a display screen provided in an embodiment of the present application is shown.

[0049] like Figure 2 As shown, the embodiment of the present application may adopt a dual data link (DDL) technology, and a column of pixels in the display screen is correspondingly connected to two data lines (Data Line), which may be referred to as DA lines. Among the two DA lines, one DA line is connected to the odd-numbered rows of pixels in a column of pixels, and the other DA line is connected to the even-numbered rows of pixels in a column of pixels. In the embodiment of the present application, the two DA lines connected to the i-th column of pixels may be written as DAi and DAi', and the data signals transmitted on the two DA lines connected to the i-th column of pixels may be written as DTi and DTi'. Through the DDL technology, each pixel can have a relatively sufficient charging time, ensuring that the display screen can reduce the power consumption of the chip used to provide data signals in the display screen while achieving high frame rate display.

[0050] Optionally, in Figure 2 In the illustrated four columns of pixels, the first and third columns of pixels are provided with alternately arranged red pixels and blue pixels, and the second and fourth columns of pixels are provided with green pixels. In the first and third columns of pixels, the parity order of red pixels and blue pixels is different.

[0051] In the four columns of pixels, the two DA lines of each column of pixels are connected to two switch tubes respectively, and each DA line is connected to an integrated circuit (IC) chip through the switch tube. The IC can be the above Figure 1 The data driving circuit 130 of the embodiment shown is also called a data driving chip. Figure 2In the example shown, the four DA lines of the first two columns of pixels are connected to the same output pin of the IC for receiving the signal FT1 output by the output pin, and the four DA lines of the last two columns of pixels are connected to another output pin of the IC for receiving the signal FT2 output by the pin.

[0052] The switch tube may include a metal-oxide-semiconductor field-effect transistor (MOSFET), MOS tube for short. The source and drain of the MOS tube may be connected to the DT line and the pin of the IC respectively, and the gate of the MOS tube may be used to receive a control signal.

[0053] exist Figure 2 In the example shown, the switch connected to the DA1 line and the switch connected to the DA3 line can be connected to the first control line for receiving a first control signal, and the first control signal can control the pixels connected to the DA1 line and the DA3 line to synchronously receive the data signal transmitted by the IC to charge the pixel. The switch connected to the DA2 line and the switch connected to the DA4 line can be connected to the second control line for receiving a second control signal. Similarly, the second control signal can control the pixels connected to the DA2 line and the DA4 line to synchronously receive the data signal transmitted by the IC to charge the pixel. In addition, the switch connected to the DA1' line and the switch connected to the DA3' line can be connected to the third control line for receiving a third control signal. The switch connected to the DA2' line and the switch connected to the DA4' line can be connected to the fourth control line for receiving a fourth control signal.

[0054] Optionally, the control signal may be a control signal output by a multiplexer (MUX). The first control signal, the second control signal, the third control signal and the fourth control signal are MUX1, MUX2, MUX3 and MUX4 respectively, and the four signals may be four output signals of MUX.

[0055] Based on the switch tube connected to each DA line and the control signal it receives, the pixels in the display screen can be controlled to receive the data signal transmitted by the IC, thereby charging the pixels. Figure 3 Shows Figure 2 A timing diagram of each signal in the illustrated embodiment.

[0056] like Figure 3 As shown, GT1 and GT2 can be Figure 2 The row drive signals of two rows of pixels in the embodiment shown are DT1, DT1', etc. Figure 2In the embodiment shown, the data signals transmitted on the 8 DA lines, FT1 and FT2 are the data signals output by two pins of the IC. Figure 3 The signal timing of the illustrated embodiment can control each pixel in the display screen to sequentially receive the data signal transmitted by the IC, so as to realize the picture display of the display screen.

[0057] But see Figure 3 In the signal timing of FT1 and FT2 in the illustrated embodiment, data signals of different colors need to change in real time to meet the display requirements of the display screen. In other words, in this embodiment, the signal output by each pin of the IC is a data signal of color change, and the voltage range corresponding to data signals of different colors is different. Therefore, the voltage of the data signal output by each pin of the IC will fluctuate in real time, resulting in higher power consumption of the IC, which is not conducive to reducing the overall power consumption of the display screen.

[0058] In view of this, the embodiment of the present application provides a new panel architecture and driving technology based on the above-mentioned DDL technology, which can effectively reduce the power consumption of the IC, thereby reducing the overall power consumption of the display screen.

[0059] Figure 4 A schematic diagram of another display screen provided in an embodiment of the present application is shown.

[0060] like Figure 4 As shown, the display screen 400 includes: a display area 401 and a non-display area 402 at least partially surrounding the display area 401 , and the non-display area includes a bonding area 403 located at one side of the display area 401 .

[0061] The display screen 400 includes a pixel array 410 located in a display area 401. The odd-numbered rows of pixels in any column of pixels in the pixel array 410 have the same color, and the odd-numbered rows of pixels are connected to one data line, and the even-numbered rows of pixels in any column of pixels have the same color, and the even-numbered rows of pixels are connected to another data line. The display screen 400 also includes bonding pins 420 located in a bonding area 403. The pixels with the same color in multiple columns of pixels in the pixel array 410 are connected to at least one bonding pin 420 through multiple data lines, and each bonding pin 420 in the at least one bonding pin 420 is used to output pixel signals of the same color.

[0062] As an example, in Figure 4 4 adjacent columns of pixels of the pixel array 410 are shown in FIG. Among the 4 columns of pixels, two columns of pixels include red pixels R and blue pixels B arranged alternately, and the other two columns of pixels include green pixels G. The odd-numbered rows of pixels in each column of pixels are connected to one data line, and the even-numbered rows of pixels in each column of pixels are connected to another data line.

[0063] The red pixels in the two columns of pixels can be connected to the first bonding pin Pin1 through two data lines, and the first bonding pin Pin1 is used to output a red data signal D1, and the blue pixels in the two columns of pixels can be connected to the second bonding pin Pin2 through two data lines, and the second bonding pin Pin2 is used to output a blue data signal D2; a part of the green pixels in the other two columns of pixels are connected to the third bonding pin Pin3, and the third bonding pin Pin3 is used to output a first green data signal D3; another part of the green pixels in the other two columns of pixels are connected to the fourth bonding pin Pin4, and the fourth bonding pin Pin4 is used to output a second green data signal D4.

[0064] In the embodiment of the present application, the display screen 400 may be an OLED display screen. For an OLED display screen, the pixels in its pixel array 410 may include a color light-emitting unit and a pixel circuit. When the light-emitting unit is used to emit a red light signal, the pixel where the light-emitting unit is located may be referred to as a red pixel. Similarly, when the light-emitting unit is used to emit a blue light signal or a green light signal, the pixel where the light-emitting unit is located may be referred to as a blue pixel or a green pixel.

[0065] In the embodiment of the present application and the related embodiments below, the first bonding pin Pin1, the second bonding pin Pin2, the third bonding pin Pin3 and the fourth bonding pin Pin4 in the bonding area are not used to limit the arrangement order of the four pins in the bonding area, and the four bonding pins can be arranged in the bonding area in any order. As an example, the arrangement order of the four bonding pins can be the first bonding pin Pin1, the third bonding pin Pin3, the second bonding pin Pin2 and the fourth bonding pin Pin4.

[0066] In the pixel array 410 of the embodiment of the present application, each column of pixels can be connected to two data lines, so the display screen 400 is a display screen using a DDL architecture. In the DDL architecture, the data lines connecting the same color pixels in multiple columns of pixels can be connected to the same bonding pin in the bonding area through the routing design of the data lines. The bonding pins in the bonding area can be connected to the data driver chip (e.g. Figure 1 The chip pins in the data driving circuit 130) in the illustrated embodiment are connected correspondingly, and the bonding pins can be used to receive the data signal provided by the data driving chip and output the data signal to the data line connected to the pixel array.

[0067] Through the technical solution of the embodiment of the present application, in a display screen with a DDL architecture, the same pin of the bonding area used to provide data signals is used to output pixel signals of the same color without generating conversion of pixel signals of different colors, which is beneficial to saving the power consumption of the data driver chip connected to the bonding pin, thereby helping to further reduce the overall power consumption of the display screen.

[0068] As an example, Figure 4 A schematic diagram of the distribution of pixels of different colors in a pixel array 410 is shown in FIG.

[0069] like Figure 4 As shown, in the four adjacent columns of pixels of the pixel array 410, a column of green pixels G is arranged between two columns of pixels including red pixels R and blue pixels B, and the parity order of the red pixels R and the blue pixels B in the two columns of pixels is different. Figure 4 In the example shown, the first column of pixels and the third column of pixels include red pixels and blue pixels arranged alternately. In the first column of pixels, the red pixels are pixels in odd rows and the blue pixels are pixels in even rows. In the third column of pixels, the blue pixels are pixels in odd rows and the red pixels are pixels in even rows.

[0070] In this implementation, the distribution of red pixels, blue pixels, and green pixels in the pixel array 410 may be relatively uniform, thereby facilitating the improvement of the display performance of the pixel array 410 .

[0071] In some alternative implementations, for four adjacent columns of pixels in the pixel array 410 , two columns of pixels including red pixels R and blue pixels B may be adjacently arranged, and another two columns of green pixels may be adjacently arranged.

[0072] Optionally, in the four adjacent columns of pixels in the pixel array 410, for two columns of pixels including green pixels G, the odd-numbered rows of green pixels G in one column of pixels and the even-numbered rows of green pixels G in the other column of pixels can be connected to the third bonding pin Pin3, and the even-numbered rows of green pixels in one column of pixels and the odd-numbered rows of green pixels in the other column of pixels are connected to the fourth bonding pin Pin4.

[0073] In this embodiment, by designing the distribution of pixels of different colors in the pixel array 410 and the connection method between the data line and the bonding pin 420 , the bonding pin 420 can be easily input to the pixel array 410 to realize the screen display of the pixel array 410 .

[0074] Figure 5 Another schematic diagram of a display screen provided in an embodiment of the present application is shown.

[0075] like Figure 5As shown, the display screen 400 includes: a pixel array 410, a bonding pin 420, a switch tube and a multiplexer circuit (MUX) 430. The switch tube and the MUX 430 can be arranged in a non-display area 402 between a display area 401 and a bonding area 403 of the display screen 400. Each data line of the pixel array 410 is connected to a switch tube, which can be used to receive a control signal of the MUX 430, and the control signal is used to control the switch tube to be turned on or off. Through the control of the switch tube by the MUX 430, the data signal timing of multiple pixels connected to each data line can be effectively controlled.

[0076] In the technical solution of the embodiment of the present application, the data signal timing of the pixels in the pixel array 410 is controlled by MUX430, so the data driver chip connected to the bonding pin only needs to continuously provide the pixel data signal without adding additional timing control. The MUX430 can be used to ensure the accurate display of each pixel in the display screen and the display effect of the display screen. In addition, the data driver chip can also simplify the related timing control, which is conducive to further reducing the power consumption and cost of the data driver chip.

[0077] Figure 5 For illustration only, four adjacent columns of pixels in the pixel array 410 are shown. For the four columns of pixels, eight data lines may be connected in total, and thus eight switch tubes T1 to T8 may be connected accordingly. Optionally, the switch tube includes but is not limited to a MOS tube, which may be a P-type MOS tube, or may also be an N-type MOS tube.

[0078] Optionally, in the display screen 400, a plurality of switch tubes connected to the same bonding pin are used to respectively receive a plurality of different control signals, so that the opening times of the plurality of switch tubes connected to the same bonding pin are staggered.

[0079] Optionally, among the multiple control signals output by MUX430, each control signal is used to control multiple switch tubes connected to different bonding pins, so that the opening time of the multiple switch tubes connected to different bonding pins is the same.

[0080] exist Figure 5In the adjacent 4 columns of pixels shown, the four data lines connected to the odd-numbered rows of pixels are connected to the switch tubes T1, T3, T4 and T7, and the switch tubes T1, T3, T4 and T7 are used to receive the control signal MUX1 output by MUX430, and the control signal MUX1 can be used to control the switch states of the switch tubes T1, T3, T4 and T7. In addition, the four data lines connected to the even-numbered rows of pixels are connected to the switch tubes T2, T4, T6 and T8, and the switch tubes T2, T4, T6 and T8 are used to receive the control signal MUX2 output by MUX430, and the control signal MUX2 can be used to control the switch states of the switch tubes T2, T4, T6 and T8.

[0081] In addition, the switch tubes T1 and T6 are respectively connected to the red pixels in the four columns of pixels, and the red pixels in the four columns of pixels can be connected to the first bonding pin Pin1 through two data lines and the switch tubes T1 and T6, so as to receive the red data signal D1. Similarly, the switch tubes T2 and T5 are respectively connected to the blue pixels in the four columns of pixels, and the blue pixels in the four columns of pixels can be connected to the second bonding pin Pin2 through two data lines and the switch tubes T2 and T5, so as to receive the blue data signal D2. The switch tubes T3 and T8 are respectively connected to some of the green pixels in the four columns of pixels, and the some of the green pixels can be connected to the third bonding pin Pin3 through two data lines and the switch tubes T3 and T8, so as to receive the first green signal D3. The switch tubes T4 and T7 are respectively connected to another part of the green pixels in the four columns of pixels, and the some of the green pixels can be connected to the fourth bonding pin Pin4 through two data lines and the switch tubes T4 and T7, so as to receive the second green signal D4.

[0082] Figure 6 Shows Figure 5 A timing diagram of each signal in the illustrated embodiment.

[0083] like Figure 6 As shown, GT1 and GT2 are Figure 5 The row drive signals of the first two rows of pixels shown in the figure, MUX1 and MUX2 are two control signals output by the multiplexer circuit MUX, Dij is Figure 5 The data signal Di on the jth data line connected to the i-th bonding pin is shown as Figure 5 The data signal output by the i-th bonding pin is shown, where i and j are positive integers and 1≤i≤4, 1≤j≤2.

[0084] exist Figure 6In the example shown, both MUX1 and MUX2 include pulse signals. Optionally, the effective pulses in MUX1 and MUX2 are low-level pulses, or, in other embodiments, the effective pulses in MUX1 and MUX2 may also be high-level pulses. Under the effective pulses of MUX1 and MUX2, the switch tube controlled by them can be turned on, so that the data signal received by the switch tube from the bonding pin is transmitted to the data line of each column of pixels through the switch tube.

[0085] In the embodiment of the present application, the effective pulses of MUX1 and MUX2 are staggered in the time domain, so the opening times of the switches controlled by MUX1 and MUX2 are also staggered. Through the timing control of MUX1 and MUX2, the sequential emission of different pixels in the pixel array can be effectively controlled.

[0086] Combination Figure 5 and Figure 6 As shown, the MUX1 signal is used to control the switch tubes T1, T3, T5 and T7, thereby controlling the D11, D31, D22 and D42 signals on the data lines connected to the switch tubes T1, T3, T5 and T7. When MUX1 is in a valid pulse at a low level, the switch tubes T1, T3, T5 and T7 are turned on, thereby outputting the D11, D31, D22 and D42 signals. The MUX2 signal is used to control the switch tubes T2, T4, T6 and T8, thereby controlling the D21, D41, D12 and D32 signals on the data lines connected to the switch tubes T2, T4, T6 and T8. When MUX2 is in a valid pulse at a low level, the switch tubes T2, T4, T6 and T8 are turned on, thereby outputting the D21, D41, D12 and D32 signals.

[0087] Optionally, in the above Figures 4 to 6 In the illustrated embodiment, four columns of adjacent pixels in a pixel array are used as an example. The pixel array may include multiple groups of pixels, each group of pixels may include four columns of adjacent pixels provided in the above embodiment, and each group of pixels may be connected to four bonding pins. Multiple groups of pixels in the pixel array may share the above two MUX signals, for example, the switch tubes connected to the odd-numbered rows of pixels in the multiple groups of pixels may be used to receive the MUX1 signal, and the switch tubes connected to the even-numbered rows of pixels may be used to receive the MUX2 signal.

[0088] In the above technical solution, the number of output pins of the data driver chip and the number of bonding pins in the bonding area can be the same as the number of pixel columns in the pixel array, and two MUX signals can be used to realize the data input of each pixel in the pixel array, so as to control the reliable display of the display screen. The number of MUX signals in this technical solution is small, which is conducive to simplifying the control and implementation of the MUX circuit.

[0089] Figure 7Another schematic diagram of a display screen provided in an embodiment of the present application is shown.

[0090] like Figure 7 As shown, the display screen 400 includes: a pixel array 410 and bonding pins 420. The pixel array 410 schematically shows 8 adjacent columns of pixels, and the 8 columns of pixels can be connected to 4 bonding pins Pin1 to Pin4. The 4 bonding pins can output color data signals respectively. For example, the first bonding pin Pin1 is connected to the red pixels in the 8 columns of pixels, and is used to output red data signals, the second bonding pin Pin2 is connected to the blue pixels in the 8 columns of pixels, and is used to output blue data signals, and the third bonding pin Pin3 and the fourth bonding pin Pin4 can be connected to the green pixels in the 8 columns of pixels, and are used to output the first green data signal and the second green data signal respectively.

[0091] Optionally, in some embodiments, the arrangement of the color pixels in the adjacent 8 columns of pixels is the same as described above. Figure 4 and Figure 5 The arrangement of the color pixels of the illustrated embodiment is the same. In each of the 8 columns of pixels, a column of green pixels G is arranged between two columns of pixels including red pixels R and blue pixels B, and the red pixels R and blue pixels B have different odd and even orders in the two columns of pixels. Optionally, in each of the 4 adjacent columns of pixels, for two columns of pixels including green pixels G, the odd-numbered rows of green pixels G in one column of pixels and the even-numbered rows of green pixels G in the other column of pixels can be connected to one bonding pin in the bonding area, and the even-numbered rows of green pixels in one column of pixels and the odd-numbered rows of green pixels in the other column of pixels are connected to another bonding pin in the bonding area.

[0092] Optionally, continue to see Figure 7 As shown, the display screen 400 may further include a switch tube and a multiplexer circuit (MUX) 430. The adjacent 8 columns of pixels in the pixel array 410 of the display screen 400 may be connected to 16 data lines, and the 16 data lines are connected to 16 switch tubes T1 to T16 one by one.

[0093] exist Figure 7In the adjacent 8 columns of pixels shown, the 4 data lines connected to the odd-numbered rows of pixels in the first 4 columns of pixels are connected to the switch tubes T1, T3, T5 and T7, and the switch tubes T1, T3, T5 and T7 are used to receive the control signal MUX1 output by MUX, and the control signal MUX1 can be used to control the switch states of the switch tubes T1, T3, T5 and T7. The 4 data lines connected to the odd-numbered rows of pixels in the last 4 columns of pixels are connected to the switch tubes T9, T11, T13 and T15, and the switch tubes T9, T11, T13 and T15 are used to receive the control signal MUX2 output by MUX, and the control signal MUX2 can be used to control the switch states of the switch tubes T9, T11, T13 and T15. In addition, the 4 data lines connected to the even-numbered rows of pixels in the first 4 columns of pixels are connected to the switch tubes T2, T4, T6 and T8, and the switch tubes T2, T4, T6 and T8 are used to receive the control signal MUX3 output by MUX, and the control signal MUX3 can be used to control the switch states of the switch tubes T2, T4, T6 and T8. The 4 data lines connected to the even-numbered rows of pixels in the last 4 columns of pixels are connected to the switch tubes T10, T12, T14 and T16, and the switch tubes T10, T12, T14 and T16 are used to receive the control signal MUX4 output by MUX, and the control signal MUX4 can be used to control the switch states of the switch tubes T10, T12, T14 and T16.

[0094] Further, in the embodiment of the present application, the switch tubes T1, T6, T9 and T14 are respectively connected to the red pixels in the four columns of pixels, and the red pixels in the four columns of pixels can be connected to the first bonding pin Pin1 through the four columns of data lines and the switch tubes T1, T6, T9 and T14, so as to receive the red data signal D1. Similarly, the switch tubes T2, T5, T10 and T13 are respectively connected to the blue pixels in the four columns of pixels, and the blue pixels in the four columns of pixels can be connected to the second bonding pin Pin2 through the four columns of data lines and the switch tubes T2, T5, T10 and T13, so as to receive the blue data signal D2. The switch tubes T3, T8, T11 and T16 are respectively connected to some of the green pixels in the four columns of pixels, and the some of the green pixels can be connected to the third bonding pin Pin3 through the four data lines and the switch tubes T3, T8, T11 and T16, so as to receive the first green signal D3. The switches T4, T7, T12 and T15 are respectively connected to another part of the green pixels in the four columns of pixels. The green pixels can be connected to the fourth bonding pin Pin4 through four data lines and the switches T4, T7, T12 and T15 to receive the second green signal D4.

[0095] Figure 8 Shows Figure 7 A timing diagram of each signal in the illustrated embodiment.

[0096] like Figure 8As shown, GT1 and GT2 are Figure 7 The row drive signals of the first two rows of pixels shown in the figure, MUX1, MUX2, MUX3 and MUX4 are the four control signals output by the multiplexer circuit MUX, Dij is Figure 7 The data signal Di on the jth data line connected to the i-th bonding pin is shown as Figure 7 The data signal output by the i-th bonding pin is shown, where i and j are positive integers and 1≤i≤4, 1≤j≤4.

[0097] exist Figure 8 In the example shown, MUX1, MUX2, MUX3 and MUX4 all include pulse signals, and optionally, the effective pulses in MUX1, MUX2, MUX3 and MUX4 are low-level pulses, or, in other embodiments, the effective pulses of MUX1, MUX2, MUX3 and MUX4 may also be high-level pulses. Under the effective pulses of MUX1, MUX2, MUX3 and MUX4, the switch tubes controlled by them can be turned on, so that the data signal received by the switch tube from the data driving chip is transmitted to the data line of each column of pixels through the switch tube.

[0098] In the embodiment of the present application, the effective pulses of MUX1, MUX2, MUX3 and MUX4 are staggered in the time domain, so the opening times of the switch tubes respectively controlled by MUX1, MUX2, MUX3 and MUX4 are also staggered. Through the timing control of MUX1, MUX2, MUX3 and MUX4, the sequential emission of different pixels in the pixel array can be effectively controlled.

[0099] Combination Figure 7 and Figure 8 As shown, the MUX1 signal is used to control the switch tubes T1, T3, T5 and T7, thereby controlling the D11, D31, D22 and D42 signals on the data lines connected to the switch tubes T1, T3, T5 and T7. When MUX1 is in a valid pulse at a low level, the switch tubes T1, T3, T5 and T7 are turned on, thereby outputting the D11, D31, D22 and D42 signals.

[0100] The MUX2 signal is used to control the switch tubes T9, T11, T13 and T15, thereby controlling the D13, D33, D24 and D44 signals on the data lines connected to the switch tubes T9, T11, T13 and T15. When MUX2 is at a valid pulse of a low level, the switch tubes T9, T11, T13 and T15 are turned on, thereby outputting the D13, D33, D24 and D44 signals.

[0101] The MUX3 signal is used to control the switch tubes T2, T4, T6 and T8, thereby controlling the D21, D41, D12 and D32 signals on the data lines connected to the switch tubes T2, T4, T6 and T8. When MUX3 is at a valid pulse of a low level, the switch tubes T2, T4, T6 and T8 are turned on, thereby outputting the D21, D41, D12 and D32 signals.

[0102] The MUX4 signal is used to control the switch tubes T10, T12, T14 and T16, thereby controlling the D23, D43, D14 and D34 signals on the data lines connected to the switch tubes T10, T12, T14 and T16. When MUX4 is at a valid pulse of a low level, the switch tubes T10, T12, T14 and T16 are turned on, thereby outputting the D23, D43, D14 and D34 signals.

[0103] Optionally, in the above Figures 7 and 8 In the illustrated embodiment, 8 columns of adjacent pixels in a pixel array are used as an example. The pixel array may include multiple groups of pixels, each group of pixels may include the 8 columns of adjacent pixels provided in the above embodiment, and each group of pixels may be connected to 4 bonding pins. The multiple groups of pixels in the pixel array may share the above 4 MUX signals.

[0104] In the technical solution provided in the above embodiment, the display screen can be controlled to display a stable picture through four bonding pins and four MUX signals. In this technical solution, the number of bonding pins and the number of pins of the data driver chip connected to the bonding pins can be reduced, that is, reduced to half the number of columns of the pixel array, which is conducive to further reducing the power consumption of the data driver chip, thereby reducing the overall power consumption of the display screen.

[0105] Combined with the above Figure 6 and Figure 8 In the timing of the illustrated embodiment, in some implementations, the sum of the unit effective pulse widths of the multiple control signals output by the MUX is less than or equal to 2H, where 1H is 1 unit time, which can be the time for turning on a row of pixels in the pixel array.

[0106] For example, in Figure 6 In the illustrated embodiment, the MUX outputs two control signals MUX1 and MUX2, wherein the unit effective pulse width of the MUX1 signal is t1, the unit effective pulse width of the MUX2 signal is t2, and the sum of t1 and t2 may be less than or equal to 2H.

[0107] For example, in Figure 8In the illustrated embodiment, MUX outputs four control signals MUX1, MUX2, MUX3 and MUX4, wherein the unit effective pulse width of the MUX1 signal is t1, the unit effective pulse width of the MUX2 signal is t2, the unit effective pulse width of the MUX3 signal is t3, and the unit effective pulse width of the MUX4 signal is t4, wherein the sum of t1, t2, t3 and t4 may be less than or equal to 2H.

[0108] Optionally, the above t1, t2, t3 and t4 may be equal, so that each pixel in the pixel array has a relatively uniform charging time, thereby ensuring the display effect of the display screen.

[0109] In addition, among the multiple control signals output by the MUX, there is a preset time interval between adjacent unit effective pulses in the time domain, so that the switch tubes controlled by the multiple control signals are turned on in sequence, and the pixels connected to each data line can receive accurate data signals, reducing the possibility of crosstalk and interference between pixel data on different data lines, thereby ensuring the display effect of the display screen.

[0110] exist Figure 6 and Figure 8 In the example shown, the time interval between adjacent unit effective pulses in the time domain is t'. Optionally, the time interval t' may be related to the rise time (Tr) and fall time (Tf) of the data signal of the data driver chip. For example, the time interval t' may be the maximum value of the rise time and the fall time.

[0111] In this implementation, by designing the pulse waveform parameters of the control signal output by the MUX, the control effect of the MUX control signal can be further guaranteed to improve the display effect of the display screen.

[0112] In addition, Figure 6 and Figure 8 In the example shown, the signal timing of the row drive signals GT1 and GT2 is also illustrated. The GT1 and GT2 can be row drive signals for any two adjacent rows of pixels in the pixel array. The row drive signals GT1 and GT2 can be related to the control signal output by the MUX.

[0113] As an example, Figure 6As shown, when MUX outputs two control signals, the unit effective pulse in the GT1 signal can be located between two adjacent unit effective pulses in MUX1. For example, when both the unit effective pulses in GT1 and MUX1 are low-level pulses, the falling edge of GT1 can be located after the falling edge of the previous unit effective pulse in MUX1, and the rising edge of GT1 can be located before the rising edge of the next unit effective pulse in MUX1. Similarly, the unit effective pulse in the GT2 signal can be located between two adjacent unit effective pulses in MUX2.

[0114] As another example, Figure 8 As shown, when MUX outputs 4 control signals, the unit effective pulse in the GT1 signal can be located between two adjacent unit effective pulses in MUX1. The unit effective pulse in the GT2 signal can be located between two adjacent unit effective pulses in MUX3.

[0115] Optionally, in this example, when both the unit effective pulses in GT1 and MUX1 are low-level pulses, the falling edge of GT1 may be located after the rising edge of the previous unit effective pulse in MUX1, and the rising edge of GT1 may be located before the falling edge of the next unit effective pulse in MUX1. Through this implementation, before a row of pixels corresponding to GT1 is turned on, the pixels corresponding to MUX1 can be pre-charged, which is conducive to balancing the charging time of the pixels corresponding to MUX1 and the charging time of the pixels corresponding to MUX2, and further improving the display effect.

[0116] Similarly, when the unit valid pulses in GT2 and MUX3 are both low-level pulses, the falling edge of GT2 can be located after the rising edge of the previous unit valid pulse in MUX3, and the rising edge of GT2 can be located before the falling edge of the next unit valid pulse in MUX3.

[0117] In the above Figures 4 to 6 In the embodiment shown, the data lines of 4 columns of pixels are connected to 4 bonding pins as an example for explanation, and the above Figure 7 and Figure 8 In the illustrated embodiment, the data lines of 8 columns of pixels are connected to 4 bonding pins. In addition to these two embodiments, the data lines of more columns of pixels can be connected to 4 bonding pins.

[0118] In some examples, 4 columns of pixels may be a pixel group in a pixel array, and data lines of multiple columns of pixels in N pixel groups may be connected to 4 bonding pins, where N is a positive integer. The switch tubes on the four data lines connected to the odd-numbered rows of pixels in each pixel group are used to receive a control signal, and the switch tubes on the four data lines connected to the even-numbered rows of pixels in each pixel group are used to receive another control signal, and different pixel groups receive different control signals.

[0119] For example, when N=3, 3 pixel groups have 12 columns of pixels, wherein the first pixel group is the first 4 columns of pixels, the second pixel group is the middle 4 columns of pixels, and the third pixel group is the last 4 columns of pixels. The switch tubes on the four data lines connected to the odd-numbered rows of pixels in the first 4 columns of pixels are used to receive the first control signal, the switch tubes on the four data lines connected to the odd-numbered rows of pixels in the middle 4 columns of pixels are used to receive the second control signal, the switch tubes on the four data lines connected to the odd-numbered rows of pixels in the last 4 columns of pixels are used to receive the third control signal, the switch tubes on the four data lines connected to the even-numbered rows of pixels in the first 4 columns of pixels are used to receive the fourth control signal, the switch tubes on the four data lines connected to the even-numbered rows of pixels in the middle 4 columns of pixels are used to receive the fifth control signal, and the switch tubes on the four data lines connected to the even-numbered rows of pixels in the last 4 columns of pixels are used to receive the sixth control signal. The MUX circuit can provide 2*N control signals to the pixel array, that is, 6 control signals. The effective pulses of the 2*N control signals can be staggered in the time domain, and the effective pulses of the 2*N control signals can be arranged adjacent to each other in the time domain.

[0120] The embodiment of the present application also provides a display device. Fig. 9 A schematic structural block diagram of a display device 600 provided in an embodiment of the present application is shown.

[0121] like Fig. 9 As shown, the display device 600 may include a display screen 400 and a data driving chip 500, and the data driving chip 500 may be used to provide a data signal to the display screen 400. Optionally, the display screen 400 may include the display screen provided in any of the above embodiments.

[0122] The data driver chip 500 may be located in the bonding area of ​​the display screen 400. In some embodiments, the pins in the data driver chip 500 may be connected to the bonding pins in the bonding area in a one-to-one correspondence.

[0123] For the data driver chip in each embodiment of the present application, it is configured to output multiple data signals of a column of pixels in the pixel array through multiple pins respectively, and one pin is used to output data signals of the same color. For example, the data signal of the pixel array received by the data driver chip is still a data signal provided by column, and the data driver chip does not directly provide the data signal to the data line of a column of pixels, but needs to split and reorganize the data signals of multiple columns of pixels so that one pin can output data signals of multiple columns of pixels, and the data signals are data signals of the same color.

[0124] The display device provided in the embodiment of the present application may be, for example, a television, a mobile phone, a computer, a laptop computer, etc., and the embodiment of the present application does not limit its specific type.

[0125] The directional words appearing in the above description are all directions shown in the figures, and do not limit the specific structure of the present application. In the description of the present application, it should also be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection", and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0126] The term "and / or" in this application is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B may mean: A exists, A and B exist at the same time, and B exists.

[0127] Unless otherwise defined, all technical and scientific terms used in this application have the same meanings as those commonly understood by technicians in the technical field of this application; the terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned drawings and any variations thereof are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of this application or the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order or a primary and secondary relationship.

[0128] Reference to "embodiments" in this application means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments.

[0129] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0130] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A display screen, characterized in that: include: A display area and a non-display area at least partially surrounding the display area, wherein the non-display area includes a bonding area located on one side of the display area; The display screen includes a pixel array located in the display area, the odd-numbered rows of pixels in any column of pixels in the pixel array have the same color, and the odd-numbered rows of pixels are connected to one data line, and the even-numbered rows of pixels in any column of pixels have the same color, and the even-numbered rows of pixels are connected to another data line; The bonding pins are located in the bonding area. The pixels with the same color in the multiple columns of pixels in the pixel array are connected to at least one bonding pin through multiple data lines. Each bonding pin in the at least one bonding pin is used to output pixel signals with the same color.

2. The display screen according to claim 1, characterized in that: The display screen further comprises: a switch tube and a multi-way selection circuit, which are located in a non-display area between the display area and the bonding area; Each data line connected to the pixel array is connected to the bonding pin via a switch tube, and the switch tube is used to receive a control signal from the multi-way selection circuit to control the data signal timing of the pixel connected to the data line.

3. The display screen according to claim 2, characterized in that: The multiple switch tubes connected to the same bonding pin in the bonding area are used to respectively receive different multiple control signals, so that the opening times of the multiple switch tubes connected to the same bonding pin are staggered.

4. The display screen according to claim 3, characterized in that: The sum of the unit effective pulse widths of the multiple control signals is less than or equal to 2 unit times, where the unit time is the time during which a row of pixels is turned on.

5. The display screen according to claim 4, characterized in that: In the plurality of control signals, there is a preset time interval between adjacent unit effective pulses.

6. The display screen according to claim 5, characterized in that: The preset time interval is greater than or equal to a maximum value of a rise time and a fall time of a data signal transmitted by the bonding pin.

7. The display screen according to claim 3, characterized in that: Each of the plurality of control signals is used to control a plurality of switch tubes connected to different bonding pins in the bonding area, so that the opening time of the plurality of switch tubes connected to the different bonding pins is the same.

8. The display screen according to any one of claims 1 to 7, characterized in that: The pixel array includes a plurality of pixel groups, each pixel group includes four columns of pixels, the first column of pixels and the third column of pixels in the four columns of pixels include blue pixels and red pixels arranged alternately, the red pixels and the blue pixels have different odd and even orders in the first column of pixels and the third column of pixels, and the second column of pixels and the fourth column of pixels include green pixels; The odd-numbered rows of red pixels in the first column of pixels and the even-numbered rows of red pixels in the third column of pixels are connected to the first bonding pin of the bonding area, and the first bonding pin is used to output a red data signal; The even-numbered blue pixels in the first column and the odd-numbered blue pixels in the third column are connected to the second bonding pin of the bonding area, and the second bonding pin is used to output a blue data signal; The odd-numbered green pixels in the second column of pixels and the even-numbered green pixels in the fourth column of pixels are connected to a third bonding pin in the bonding area, and the third bonding pin is used to output a first green data signal; The even-numbered rows of green pixels in the second column of pixels and the odd-numbered rows of green pixels in the fourth column of pixels are connected to a fourth bonding pin in the bonding area, and the fourth bonding pin is used to output a second green data signal.

9. The display screen according to claim 8, characterized in that: In the four columns of pixels, the four data lines connected to the odd-numbered rows of pixels are respectively connected to four first switch tubes, and the first switch tubes are used to receive a first control signal to control the switch state of the first switch tube; The four data lines connected to the even-numbered rows of pixels are respectively connected to four second switch tubes, and the second switch tubes are used to receive second control signals to control the switch states of the second switch tubes; The opening time of the first switch tube and the opening time of the second switch tube are staggered.

10. The display screen according to claim 9, characterized in that: Two adjacent rows of pixels in the pixel array are used to receive a first row drive signal and a second row drive signal respectively, a unit effective pulse in the first row drive signal is located between two adjacent unit effective pulses in the first control signal, and a unit effective pulse in the second row drive signal is located between two adjacent unit effective pulses in the second control signal.

11. The display screen according to claim 8, characterized in that: Multiple columns of pixels of at least two of the pixel groups are connected to the first bonding pin, the second bonding pin, the third bonding pin and the fourth bonding pin; The switch tubes on the four data lines connected to the odd-numbered rows of pixels in each pixel group are used to receive a control signal, and the switch tubes on the four data lines connected to the even-numbered rows of pixels in each pixel group are used to receive another control signal. Different pixel groups receive different control signals.

12. The display screen according to claim 11, characterized in that: Eight columns of pixels of two pixel groups are connected to the first bonding pin, the second bonding pin, the third bonding pin and the fourth bonding pin; In the eight columns of pixels, the four data lines connected to the odd-numbered rows of pixels in the first four columns of pixels are respectively connected to four first switch tubes, and the first switch tubes are used to receive a first control signal to control the switch state of the first switch tube; The four data lines connected to the odd-numbered rows of pixels in the last four columns of pixels are respectively connected to four second switch tubes, and the second switch tubes are used to receive second control signals to control the switch states of the second switch tubes; The four data lines connected to the even-numbered rows of pixels in the first four columns of pixels are respectively connected to four third switch tubes, and the third switch tubes are used to receive third control signals to control the switch states of the third switch tubes; The four data lines connected to the even-numbered rows of pixels in the last four columns of pixels are respectively connected to four fourth switch tubes, and the fourth switch tubes are used to receive fourth control signals to control the switch states of the fourth switch tubes; The opening times of the first switch tube, the second switch tube, the third switch tube and the fourth switch tube are staggered with each other.

13. The display screen according to claim 12, characterized in that: Two adjacent rows of pixels in the pixel array are used to receive a first row driving signal and a second row driving signal respectively, and unit effective pulses of the first control signal, the second control signal, the third control signal and the fourth control signal are sequentially adjacent in the time domain; The unit effective pulse in the first row driving signal is located between two adjacent unit effective pulses in the first control signal, and the unit effective pulse in the second row driving signal is located between two adjacent unit effective pulses in the third control signal.

14. A display device, characterized in that: include: A data driver chip, and a display screen as claimed in any one of claims 1 to 13, wherein the data driver chip is located in a bonding area in the display screen.

15. The display device according to claim 14, characterized in that: The pins of the data driver chip are correspondingly connected to the bonding pins in the bonding area. The data driver chip is configured to output multiple data signals of a column of pixels in the pixel array through multiple pins respectively, and one pin is used to output data signals of the same color.

Images