Display device

Abstract

The display device includes a display area and a peripheral area as a non-display area. The display device includes: a base substrate; a first data line in the display area on the base substrate; a second data line in the display area on the base substrate, adjacent to the first data line in the first direction; a first connection line partially disposed in the display area and electrically connected to the first data line through the first connection contact hole; a second connection line partially disposed in the display area and electrically connected to the second data line through the second connection contact hole; a data pad disposed in the peripheral area and electrically connected to the data driving chip; a first data spider line disposed in a peripheral area between the data pad and the display area and electrically connected to the first connection line and the data pad; and a second data spider line disposed in a peripheral area between the data pad and the display area, electrically connected to the second connection line and the data pad, while being adjacent to the first data spider line in the first direction.

Description

[0001] This application is a divisional application of a patent application with an application date of July 12, 2019, application number 201980048341.7, and invention name “Display Device”. Technical Field

[0002] Embodiments generally relate to a display device. More particularly, embodiments of the inventive concept relate to a display device in which a width of a peripheral area as a non-display area is reduced. Background Art

[0003] Recently, with the improvement of technology, display products with smaller size, lighter weight and excellent performance have been produced. Conventional cathode ray tube (CRT) televisions have been widely used for display devices due to many advantages in terms of performance and price. However, recently, display devices such as plasma display devices, liquid crystal display devices and organic light emitting diode display devices have received attention, which overcome the weakness of CRT in terms of miniaturization or portability and have advantages such as miniaturization, light weight and low power consumption.

[0004] The display device includes a display area for displaying an image and a peripheral area which is a non-display area around the display area. In this case, efforts have been made to reduce the width of the peripheral area. Summary of the invention

[0005] Technical issues The embodiment provides a display device in which the width of a peripheral area as a non-display area is reduced.

[0006] Technical Solution According to an embodiment, a display device including a display area for displaying an image and a peripheral area serving as a non-display area may include: a base substrate; a first data line disposed in the display area on the base substrate; a first connection line at least partially disposed in the display area on the base substrate and electrically connected to the first data line through a connection contact hole; a data pad disposed in the peripheral area; and a first data spider line disposed in the peripheral area between the data pad and the display area and electrically connected to the first connection line and the data pad.

[0007] In an embodiment, the base substrate may be a flexible substrate. In addition, the display device may further include a bending area, the bending area being disposed between the data pad and the display area and extending in a first direction parallel to an edge of the display area. In addition, the first data spider line may be disposed in a peripheral area between the bending area and the display area, and may extend linearly in a second direction perpendicular to the first direction.

[0008] In an embodiment, a length of the bending area in the first direction may be smaller than a length of the display area in the first direction.

[0009] In an embodiment, the display device may further include: a plurality of data lines, which are arranged in the display area on the base substrate and extend parallel to the first data line; and a plurality of data spider lines, which are arranged in the peripheral area between the data pad and the display area, are electrically connected to the plurality of data lines, respectively, and extend parallel to the first data spider line. In addition, both the first data spider line and the plurality of data spider lines may extend in the second direction.

[0010] In an embodiment, the connection contact hole may be provided in the peripheral region.

[0011] In an embodiment, the first data line may extend in a second direction perpendicular to the first direction. In addition, the first connection line may include a first portion extending in the second direction, a second portion connected to the first portion and extending in the first direction, and a third portion parallel to the first portion.

[0012] In an embodiment, a connection contact hole may be provided in the display region.

[0013] In an embodiment, the display device may further include a second data line disposed on the base substrate in the display region while being adjacent to the first data line. In addition, the first data line and the second data line may be connected to each other in the peripheral region and electrically connected to the first connection line.

[0014] In an embodiment, the display device may further include an n-1th data line, an nth data line, and an n+1th data line that are parallel to the first data line and sequentially arranged in the first direction. In addition, an nth pad electrically connected to the nth data line, an n-1th pad electrically connected to the n-1th data line, an n+1th pad electrically connected to the n+1th data line, and a first pad electrically connected to the first data line may be arranged in the data pad along the first direction.

[0015] In an embodiment, the display device may further include: an n-1th connecting line, at least partially disposed in the display area on the base substrate and electrically connected to the n-1th data line through a connecting contact hole; an n-1th data spider line, disposed in a peripheral area between the data pad and the display area and electrically connected to the n-1th connecting line and the data pad; an nth data spider line, disposed in a peripheral area between the data pad and the display area and electrically connected to the nth data line and the data pad; and an n+1th data spider line, disposed in a peripheral area between the data pad and the display area and electrically connected to the n+1th data line and the data pad.

[0016] In an embodiment, the peripheral area may include a left peripheral area adjacent to the left side of the display area, a right peripheral area adjacent to the right side of the display area, an upper peripheral area adjacent to the upper side of the display area, and a lower peripheral area adjacent to the lower side of the display area. In addition, the data pad may be disposed in the lower peripheral area.

[0017] In an embodiment, the display device may further include a thin film transistor electrically connected to the first data line, a first electrode electrically connected to the thin film transistor, a second electrode disposed on the first electrode, and a light emitting layer disposed between the first electrode and the second electrode.

[0018] In an embodiment, the display device may further include a shielding electrode overlapping the first connection line. In addition, the first power or the second power may be applied to the shielding electrode.

[0019] In an embodiment, the first connection line and the first data spider line may be connected to each other through a spider contact hole formed in the peripheral region.

[0020] According to an embodiment, a display device may include: a base substrate; a thin film transistor disposed on the base substrate; a first data line electrically connected to the thin film transistor; a first connecting line electrically connected to the first data line; a first insulating layer disposed between the first data line and the first connecting line and having a first connecting contact hole through which the first data line and the first connecting line are connected to each other; and a shielding electrode overlapping the first connecting line.

[0021] In an embodiment, the thin film transistor may include an active pattern disposed on the base substrate and a gate electrode overlapping the active pattern. In addition, the display device may further include a first data spider line formed on the same layer as the gate electrode and electrically connected to the first connection line.

[0022] In an embodiment, the shielding electrode may be disposed between the thin film transistor and the first connection line.

[0023] In an embodiment, the shielding electrode may overlap the first data line.

[0024] In an embodiment, the display device may further include a second data line adjacent to the first data line and extending parallel to the first data line. In addition, the first data line and the second data line may be electrically connected to the first connection line. In addition, the shielding electrode may overlap the first data line and the second data line.

[0025] According to an embodiment, a display device may include: a base substrate; a first data line and a second data line, which are arranged on the base substrate; a first connecting line, which is connected to the first data line through a contact hole; a first data spider line, which is connected to the first connecting line through the contact hole; a second data spider line, which is connected to the second data line through the contact hole; and a data pad, which is electrically connected to the first data spider line and the second data spider line and is connected to a data driving chip.

[0026] Beneficial Effects Therefore, a display device according to an embodiment may include a display area for displaying an image and a peripheral area as a non-display area. The display device may include: a base substrate; a first data line, which is arranged in the display area on the base substrate; a first connection line, which is at least partially arranged in the display area on the base substrate and is electrically connected to the first data line through a connection contact hole; a data pad, which is arranged in the peripheral area; and a first data spider line, which is arranged in the peripheral area between the data pad and the display area and is electrically connected to the first connection line and the data pad. Since the first connection line is arranged in the display area except the peripheral area, a display device in which the width of the peripheral area is reduced to reduce the border portion as the non-display area can be realized.

[0027] However, the effects of the inventive concept are not limited thereto. Therefore, the effects of the inventive concept can be expanded without departing from the spirit and scope of the inventive concept. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a plan view showing a display device according to an embodiment.

[0029] Figure 2 It is shown that the Figure 1 A block diagram of an example of a pixel and driver in a display device.

[0030] Figure 3 It is shown Figure 2 An example of a pixel is shown in FIG.

[0031] Figure 4 It is shown Figure 1 An enlarged view of the lower left portion of the display device.

[0032] Figure 5 Is used to describe Figure 4 A diagram showing the connection relationship between data lines and connecting lines of a display device.

[0033] Figure 6 It is shown along Figure 4 A cross-sectional view of the display device taken along line II'.

[0034] Figure 7 It is shown along Figure 4 A cross-sectional view of some layers of the display device taken along line II-II'.

[0035] Figure 8 is a cross-sectional view showing a display device according to an embodiment.

[0036] Fig. 9 is an enlarged view showing a lower left portion of the display device according to the embodiment.

[0037] Fig.10 Is used to describe Fig. 9 A diagram showing the connection relationship between data lines and connecting lines of a display device.

[0038] Fig.11 is a diagram for describing a connection relationship between data lines and connection lines of a display device according to an embodiment.

[0039] Fig.12 is a cross-sectional view showing a display device according to an embodiment.

[0040] Fig.13 is a cross-sectional view showing a display device according to an embodiment.

[0041] Fig.14 is a cross-sectional view showing a display device according to an embodiment.

[0042] Fig.15 is a cross-sectional view showing a display device according to an embodiment.

[0043] Fig.16 is a block diagram illustrating an electronic device according to an embodiment.

[0044] Fig.17a It shows that Fig.16 The electronic device is implemented as an example of a television.

[0045] Fig.17b It shows that Fig.16 The electronic device is implemented as an example of a smart phone. DETAILED DESCRIPTION

[0046] Hereinafter, embodiments of the inventive concept will be explained in detail with reference to the accompanying drawings.

[0047] Figure 1 is a plan view showing a display device according to an embodiment.

[0048] Reference Figure 1, the display device may include a display area AA for displaying an image and a peripheral area PA as a non-display area, the peripheral area PA being adjacent to the display area AA and surrounding the display area AA. The display area AA may have a rectangular shape on a plane defined by a first direction D1 and a second direction D2 perpendicular to the first direction D1, and a corner of the display area AA may have a rounded shape. In the present embodiment, the display area AA may have a rectangular shape including rounded (or referred to as "rounded") corners, but the embodiment is not limited thereto.

[0049] The peripheral area PA may include a left peripheral area adjacent to the left side of the display area AA, a right peripheral area adjacent to the right side of the display area AA, an upper peripheral area adjacent to the upper side of the display area AA, and a lower peripheral area adjacent to the lower side of the display area AA.

[0050] In this case, a data pad (or referred to as a "pad") COP and a gate pad FOP for connecting a driver may be disposed in the lower peripheral region such that the lower peripheral region may have a width greater than that of each of the upper peripheral region, the left peripheral region, and the right peripheral region. The lower peripheral region may include: a first peripheral region PAa directly adjacent to the display region AA; a bending region BA; and a second peripheral region PAb. The data pad COP and the gate pad FOP may be disposed in the second peripheral region PAb.

[0051] The bending area BA may be a portion that is folded to place the second peripheral area PAb on the rear surface of the display device, and the bending area BA may be disposed between the first peripheral area PAa and the second peripheral area PAb.

[0052] In this case, the length of the bending area BA in the first direction D1 may be smaller than the length of the display area AA in the first direction D1. Therefore, the data lines positioned outwardly in the first direction D1 compared to the data spider line (or referred to as the data spider line) DSPL disposed in the lower peripheral area may be connected to the data spider line DSPL through the connection line CL.

[0053] The data spider line DSPL may be electrically connected to the data pad COP and the data line disposed in the display area AA. Meanwhile, a gate spider line GSPL connected to the scan driver or the data driver and to the gate pad FOP may be disposed at a portion adjacent to the data spider line DSPL in the lower peripheral area.

[0054] A chip including a data driver may be connected to the data pad COP. A driving substrate including a timing controller may be connected to the gate pad FOP.

[0055] Figure 2 It is shown that the Figure 1 A block diagram of an example of a pixel and a driver in a display device, Figure 3 It is shown Figure 2 An example of a pixel is shown in FIG. Figure 4 It is shown Figure 1 An enlarged view of the lower left portion of the display device, Figure 5 Is used to describe Figure 4 A diagram showing the connection relationship between data lines and connecting lines of a display device.

[0056] Reference Figures 1 to 5 , a display device may include a plurality of pixels PX, a driver, and a wiring portion.

[0057] The driver may include a scan driver SDV, an emission driver EDV, a data driver DD, and a timing controller TC. Figure 2 In the figure, for the convenience of description, the positions of the scan driver SDV, the emission driver EDV, the data driver DD and the timing controller TC are set. When the actual display device is implemented, the scan driver SDV, the emission driver EDV, the data driver DD and the timing controller TC can be set at different positions in the display device.

[0058] The wiring portion may provide a driver's signal to each pixel PX and may include a scan line SL, a data line DL1, ..., DLn-1, DLn, DLn+1, ..., an emission control line EL, a first and a second power line (not shown), and an initialization power line (not shown).

[0059] A scan line, a data line, and an emission control line may be electrically connected to each pixel PX.

[0060] When the scan signal is supplied from the scan line SL, the pixel PX may receive the data signal from the data lines DL1, ..., DLn-1, DLn, DLn+1, ... The pixel PX having received the data signal may control the amount of current flowing from the first power ELVDD to the second power ELVSS via the organic light emitting diode OLED.

[0061] The scan driver SDV may supply the scan signal to the scan lines SL in response to the first gate control signal GCS1 received from the timing controller TC. When the scan signal is sequentially supplied to the scan lines SL, the pixels PX may be sequentially selected in units of horizontal rows.

[0062] The emission driver EDV may supply the emission control signal to the emission control line EL in response to the second gate control signal GCS2 received from the timing controller TC. The emission driver EDV may sequentially supply the emission control signal to the emission control line EL.

[0063] In addition, the emission control signal may be set to a gate-off voltage (eg, a high voltage) so that the transistor included in the pixel PX may be turned off, and the scan signal may be set to a gate-on voltage (eg, a low voltage) so that the transistor included in the pixel PX may be turned on.

[0064] The data driver DD may supply data signals to the data lines DL1, ..., DLn-1, DLn, DLn+1, ... in response to the data control signal DCS. The data signals supplied to the data lines DL1, ..., DLn-1, DLn, DLn+1, ... may be supplied to the pixels PX selected by the scan signal.

[0065] The timing controller TC may supply the first gate control signal GCS1 and the second gate control signal GCS2 generated based on the timing signal supplied from the outside to the scan driver SDV and the emission driver EDV, and may supply the data control signal DCS to the data driver DD.

[0066] Each of the first gate control signal GCS1 and the second gate control signal GCS2 may include a start pulse and a clock signal. The start pulse may control the timing of the first scan signal or the first emission control signal. The clock signal may be used to shift the start pulse.

[0067] The data control signal DCS may include a source start pulse and a clock signal. The source start pulse may control the data sampling start point. The clock signal may be used to control the sampling operation.

[0068] In this case, the data lines may include a first data line DL1, an (n-1)th data line DLn-1, an n-th data line DLn, and an (n+1)th data line DLn+1.

[0069] The first data line DL1 , the (n−1)th data line DLn−1, the nth data line DLn, and the (n+1)th data line DLn+1 may be arranged in a first direction D1 , and may extend in a second direction D2 perpendicular to the first direction D1 .

[0070] The data line can be connected to the connecting line CL (also represented by the label "CONNECTING LINE") through the connecting contact hole CCNT (also represented by the label "CONTACT"), and the connecting line CL can be connected to the data spider line DSPL through the spider contact hole SCNT (also represented by the label "CONTACT"); or the data line can be directly connected to the data spider line DSPL through the spider contact hole SCNT.

[0071] For example, the first data line DL1 may be connected to the first connection line CL1 through the first connection contact hole CCNT1. The first connection contact hole CCNT1 may be formed in the peripheral area PA. The first connection line CL1 may pass through the display area AA and may be connected to the first data spider line DSPL1 through the first spider contact hole SCNT1 in the peripheral area PA. In this case, the first connection line CL1 may include: a first portion CL1a extending in the second direction D2; a second portion CL1b connected to the first portion CL1a and extending in the first direction D1; and a third portion CL1c parallel to the first portion CL1a.

[0072] The n-1th data line DLn-1 may be connected to the n-1th connection line CLn-1 through the connection contact hole CCNT in the peripheral area PA at the lower side of the display area AA. The n-1th connection line CLn-1 may pass through the display area AA and may be connected to the data spider line DSPL through the spider contact hole SCNT in the peripheral area PA.

[0073] Meanwhile, the nth data line DLn and the (n+1)th data line DLn+1 may be directly connected to the data spider line DSPL through the spider contact holes SCNT in the peripheral area PA without going through the connection lines. Figure 5 A case where n is 589 is conceptually shown.

[0074] In this case, each of the data spider lines DSPL may extend in the second direction while being parallel to each other in the peripheral area PA between the bending area BA and the display area AA. Therefore, compared with the conventional technology in which the data spider lines DSPL are bent at a predetermined angle relative to the second direction D2, a sufficient distance between the data spider lines DSPL may be ensured, so that the wiring resistance of the data spider lines DSPL may be reduced.

[0075] According to the present embodiment, the display device includes a display area for displaying an image and a peripheral area as a non-display area. The display device includes: a base substrate; a first data line, which is arranged in the display area on the base substrate; a first connection line, which is at least partially arranged in the display area on the base substrate and is electrically connected to the first data line through a connection contact hole; a data pad, which is arranged in the peripheral area; and a first data spider line, which is arranged in the peripheral area between the data pad and the display area, and is electrically connected to the first connection line and the data pad. Since the first connection line is arranged in the display area except the peripheral area, a display device in which the width of the peripheral area is reduced to reduce the border portion as the non-display area can be realized.

[0076] Meanwhile, although the present embodiment has described that the scan driver SDV is disposed in the peripheral area PA adjacent to the left side of the display area AA and the emission driver EDV is disposed in the peripheral area PA adjacent to the right side of the display area AA, the embodiment is not limited thereto. For example, the scan driver and the emission driver connected to each other by the scan line and the emission control line may be disposed in both the left peripheral area and the right peripheral area, so that signals synchronized with each other can be supplied to the pixels from the left and right sides.

[0077] Refer again Figure 3 For convenience of description, a pixel connected to an m-th data line Dm and an i-th first scan line S1i will be illustrated.

[0078] According to an embodiment of the present invention, the pixel PX may include an organic light emitting diode OLED, first to seventh transistors T1 to T7 , and a storage capacitor CST.

[0079] The organic light emitting diode OLED may include an anode connected to the first transistor T1 via a sixth transistor T6 and a cathode connected to the second power ELVSS. The organic light emitting diode OLED may generate light having a predetermined brightness in response to the amount of current supplied from the first transistor T1.

[0080] The first power ELVDD may be set to a voltage higher than that of the second power ELVSS so that current may flow through the organic light emitting diode OLED.

[0081] The seventh transistor T7 may be connected between the initialization power VINT and the anode of the organic light emitting diode OLED. In addition, the gate electrode of the seventh transistor T7 may be connected to the i+1-first scan line S1i+1 or the i-1-first scan line S1i-1. When the scan signal is supplied to the i+1-first scan line S1i+1 or the i-1-first scan line S1i-1, the seventh transistor T7 may be turned on so that the voltage of the initialization power VINT may be supplied to the anode of the organic light emitting diode OLED. In this case, the initialization power VINT may be set to a voltage lower than the voltage of the data signal.

[0082] The sixth transistor T6 may be connected between the first transistor T1 and the organic light emitting diode OLED. In addition, a gate electrode of the sixth transistor T6 may be connected to the i-th first emission control line E1i. The sixth transistor T6 may be turned off when the emission control signal is supplied to the i-th first emission control line E1i, and may be turned on in other cases.

[0083] The fifth transistor T5 may be connected between the first power ELVDD and the first transistor T1. In addition, a gate electrode of the fifth transistor T5 may be connected to the i-th first emission control line E1i. The fifth transistor T5 may be turned off when the emission control signal is supplied to the i-th first emission control line E1i, and may be turned on in other cases.

[0084] The first transistor T1 (driving transistor) may include a first electrode connected to the first power ELVDD via the fifth transistor T5 and a second electrode connected to the anode of the organic light emitting diode OLED via the second node N2 and the sixth transistor T6. In addition, the gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 may control the amount of current flowing from the first power ELVDD to the second power ELVSS via the organic light emitting diode OLED in response to the voltage of the first node N1.

[0085] The third transistor T3 may be connected between the second electrode of the first transistor T1 and the first node N1. In addition, the gate electrode of the third transistor T3 may be connected to the i-th first scan line S1i. When the scan signal is supplied to the i-th first scan line S1i, the third transistor T3 may be turned on so that the second electrode of the first transistor T1 may be electrically connected to the first node N1. Therefore, when the third transistor T3 is turned on, the first transistor T1 may be connected in the form of a diode.

[0086] The fourth transistor T4 may be connected between the first node N1 and the initialization power VINT. In addition, the gate electrode of the fourth transistor T4 may be connected to the i-1-th first scan line S1i-1. When the scan signal is supplied to the i-1-th first scan line S1i-1, the fourth transistor T4 may be turned on so that the voltage of the initialization power VINT may be supplied to the first node N1.

[0087] The second transistor T2 may be connected between the mth data line Dm and the first electrode of the first transistor T1. In addition, the gate electrode of the second transistor T2 may be connected to the i-th first scan line S1i. When a scan signal is supplied to the i-th first scan line S1i, the second transistor T2 may be turned on so that the mth data line Dm may be electrically connected to the first electrode of the first transistor T1.

[0088] The storage capacitor CST may be connected between the first power ELVDD and the first node N1. The storage capacitor CST may store the data signal and a voltage corresponding to the threshold voltage of the first transistor T1.

[0089] Figure 6 It is shown along Figure 4 A cross-sectional view of the display device taken along line II', Figure 7 It is shown along Figure 4 A cross-sectional view of some layers of the display device taken along line II-II'.

[0090] Reference Figures 4 to 7 The display device may include a base substrate 100, a buffer layer 110, an active pattern ACT, a first gate insulating layer 120, a first gate pattern, a second gate insulating layer 130, a second gate pattern GAT2, an interlayer insulating layer 140, a first data pattern, a first insulating layer 160, a connecting line pattern, a second insulating layer 170, a pixel defining layer PDL, a light emitting structure 180 and a thin film encapsulation layer TFE.

[0091] The base substrate 100 may include a transparent insulating substrate. For example, the base substrate 100 may be a transparent resin substrate having flexibility. The transparent resin substrate may include polyimide resin, acryl resin, polyacrylate resin, polycarbonate resin, polyether resin, sulfonic acid resin, polyethylene terephthalate resin, etc. Preferably, the base substrate 100 may be a polyimide (PI) resin film.

[0092] The buffer layer 110 may prevent metal atoms or impurities from diffusing from the base substrate 100, and may control a heat transfer rate during a crystallization process for forming the active pattern ACT to be described below, so as to obtain a substantially uniform active pattern ACT. In addition, when the surface of the base substrate 100 is uneven, the buffer layer 110 may be used to improve the flatness of the surface of the base substrate 100. The buffer layer 110 may be formed by using a material such as silicon oxide (SiO x )、Silicon Nitride(SiN x ), silicon oxynitride (SiO x N y ), Silicon Oxycarbide (SiO x C y ) and silicon carbonitride (SiC x N y ) is formed by silicon compounds.

[0093] The buffer layer 110 may not be formed in the bending area BA of the peripheral area PA. In other words, the buffer layer 110 may not be formed in the bending area BA, or may be removed from the bending area BA. This is because since the bending area BA is a portion that is folded in the final product, when the buffer layer 110, which is an inorganic layer, is formed in the bending area BA, damage such as cracks may occur in the buffer layer 110. Similarly, the insulating layers 120, 130, etc. formed of an inorganic film may not be formed in the bending area BA.

[0094] The active pattern ACT may be disposed on the buffer layer 110. The active pattern ACT may include: an active pattern ACT2 of a thin film transistor TFT2 and an active pattern ACT6 of a thin film transistor TFT6, disposed in the display area AA to constitute a pixel structure; and an active pattern (not shown) disposed in the peripheral area PA to constitute a driving circuit. The driving circuit may be an amorphous silicon gate (ASG) circuit.

[0095] The active pattern ACT2 of the thin film transistor TFT2 may include a drain region D2 and a source region S2 doped with impurities, and a channel region C2 disposed between the drain region D2 and the source region S2. The active pattern ACT6 of the thin film transistor TFT6 may include a drain region D6 and a source region S6 doped with impurities, and a channel region C6 disposed between the drain region D6 and the source region S6. The thin film transistors TFT2 and TFT6 may be Figure 3 The second transistor and the sixth transistor.

[0096] The first gate insulating layer 120 may be disposed on the buffer layer 110 on which the active patterns ACT2 and ACT6 are disposed. The first gate insulating layer 120 may include a silicon compound, a metal oxide, or the like.

[0097] The first gate pattern may be disposed on the first gate insulating layer 120. The first gate pattern may include a gate electrode GE2 of the thin film transistor TFT2 and a gate electrode GE6 of the thin film transistor TFT6, a signal line such as a gate line configured to transmit a signal for driving a pixel, etc. The first gate pattern may be formed by using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. For example, the first gate pattern may be formed of a metal such as copper, aluminum, and molybdenum. In addition, the first gate pattern may have a layered structure (or referred to as a layered structure or a layered structure) including a plurality of layers. For example, the first gate pattern may include a copper layer and a molybdenum layer disposed on the copper layer.

[0098] The second gate insulating layer 130 may be disposed on the first gate insulating layer 120 on which the first gate pattern is disposed. The second gate insulating layer 130 may be formed by using, for example, silicon oxide (SiO x )、Silicon Nitride(SiN x ), silicon oxynitride (SiO x N y ), Silicon Oxycarbide (SiO x C y ) and silicon carbonitride (SiC x N y ) is formed by silicon compounds.

[0099] The second gate pattern GAT2 may be disposed on the second gate insulating layer 130. The second gate pattern GAT2 may be formed by using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. For example, the second gate pattern GAT2 may be formed of a metal such as copper, aluminum, and molybdenum. In addition, the second gate pattern GAT2 may have a layer structure including a plurality of layers. For example, the second gate pattern GAT2 may include a copper layer and a molybdenum layer disposed on the copper layer.

[0100] In this case, the data spider line DSPL may include first and second gate patterns that are alternately arranged. Figure 7 As shown in , two adjacent data spider lines DSPL may be formed on mutually different layers so that the line width of each data spider line DSPL may be maximized. Therefore, the width W for arranging one data spider line DSPL may be minimized.

[0101] The interlayer insulating layer 140 may be disposed on the second gate insulating layer 130 on which the second gate pattern GAT2 is disposed.

[0102] The first data pattern may be disposed on the interlayer insulating layer 140. The first data pattern may include a data line DL, a shielding electrode SH, and a first contact pad CP1. The first data pattern may be formed by using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. For example, the first data pattern may be formed of a metal having high conductivity such as copper and aluminum. The first data pattern may have a layer structure including a plurality of layers. For example, the first data pattern may include: a titanium layer; an aluminum layer disposed on the titanium layer; and a titanium layer disposed on the aluminum layer.

[0103] The first power ELVDD may be applied to the shielding electrode SH to prevent a coupling capacitor from appearing between the first connection line CL1 and other pixel structures. The shielding electrode SH may be disposed between the thin film transistors TFT2 and TFT6 and the first connection line CL1. The shielding electrode SH may be a portion of the first power line extending parallel to the data line DL.

[0104] Meanwhile, although not shown in detail, the first data pattern may include wiring constituting the data spider line DSPL in the bending area BA. In other words, the data spider line DSPL may be formed with the first data pattern in the bending area BA, may be formed with the first gate pattern or the second gate pattern at a portion connected to the connection line CL, and may be connected to the connection line CL through a contact hole.

[0105] The first insulating layer 160 may be disposed on the interlayer insulating layer 140 on which the first data pattern is disposed. The first insulating layer 160 may include an organic insulating material, and may have a substantially flat top surface while substantially covering the first data pattern.

[0106] The connection line pattern may be disposed on the first insulating layer 160. The connection line pattern may include a first connection line CL1 and a second contact pad CP2. The connection line pattern may be formed by using metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, or the like.

[0107] The second insulating layer 170 may be disposed on the first insulating layer 160 on which the connection line pattern is disposed. The second insulating layer 170 may include an organic insulating material, and may have a substantially flat top surface while sufficiently covering the connection line pattern.

[0108] The light emitting structure 180 may include a first electrode 181 , a light emitting layer 182 , and a second electrode 183 .

[0109] The first electrode 181 may be disposed on the second insulating layer 170. The first electrode 181 may be electrically connected to the thin film transistor TFT6 through a contact hole formed through the second insulating layer 170. For example, the first electrode 181 may be connected to the thin film transistor TFT6 through the second contact pad CP2 and the first contact pad CP1.

[0110] According to the light emitting scheme of the display device, the first electrode 181 can be formed by using a reflective material or a transmissive material. For example, the first electrode 181 may include aluminum, aluminum-containing alloys, aluminum nitride, silver, silver-containing alloys, tungsten, tungsten nitride, copper, copper-containing alloys, nickel, chromium, chromium nitride, molybdenum, molybdenum-containing alloys, titanium, titanium nitride, platinum, tantalum, tantalum nitride, neodymium, scandium, strontium ruthenium oxide, zinc oxide, indium tin oxide, tin oxide, indium oxide, gallium oxide, indium zinc oxide, etc. These can be used alone or in combination with each other. In an exemplary embodiment, the first electrode 181 may have a single-layer structure or a multilayer structure including a metal film, an alloy film, a metal nitride film, a conductive metal oxide film and / or a transparent conductive material film.

[0111] The pixel defining layer PDL may be disposed on the second insulating layer 170 on which the first electrode 181 is disposed. The pixel defining layer PDL may be formed by using an organic material, an inorganic material, or the like. For example, the pixel defining layer PDL may be formed by using a photoresist, a polyacryl resin, a polyimide resin, an acryl resin, a silicone compound, or the like. According to an exemplary embodiment, the pixel defining layer PDL may be etched to form an opening partially exposing the first electrode 181. The display area and the non-display area of ​​the display device may be defined by the opening of the pixel defining layer PDL. For example, the portion where the opening of the pixel defining layer PDL is located may correspond to the display area, and the non-display area may correspond to the portion adjacent to the opening of the pixel defining layer PDL.

[0112] The light emitting layer 182 may be disposed on the first electrode 181 exposed by the opening of the pixel defining layer PDL. In addition, the light emitting layer 182 may extend onto the sidewall of the opening of the pixel defining layer PDL. In an exemplary embodiment, the light emitting layer 182 may have a multilayer structure including an organic emission layer, a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, and the like. In another embodiment, in addition to the organic emission layer, the hole injection layer, the hole transport layer, the electron transport layer, the electron injection layer, and the like may be formed in common to correspond to a plurality of pixels. The organic emission layer of the light emitting layer 182 may be formed by using a light emitting material for generating light of different colors (such as red light, green light, and blue light) according to each of the pixels of the display device. According to other exemplary embodiments, the organic emission layer of the light emitting layer 182 may have a structure in which a plurality of light emitting materials for realizing light of different colors (such as red light, green light, and blue light) are stacked to emit white light. In this case, the above light emitting structure may be formed in common to correspond to a plurality of pixels, and the pixels may be classified by a color filter layer.

[0113] The second electrode 183 may be disposed on the pixel defining layer PDL and the light emitting layer 182. According to the light emitting scheme of the display device, the second electrode 183 may include a transmissive material or a reflective material. For example, the second electrode 183 may include aluminum, aluminum alloy, aluminum nitride, silver, silver alloy, tungsten, tungsten nitride, copper, copper alloy, nickel, chromium, chromium nitride, molybdenum, molybdenum alloy, titanium, titanium nitride, platinum, tantalum, tantalum nitride, neodymium, scandium, strontium ruthenium oxide, zinc oxide, indium tin oxide, tin oxide, indium oxide, gallium oxide, indium zinc oxide, etc. These may be used alone or in combination with each other. In an exemplary embodiment, the second electrode 183 may also have a single-layer structure or a multilayer structure including a metal film, an alloy film, a metal nitride film, a conductive metal oxide film and / or a transparent conductive material film.

[0114] The thin film encapsulation layer TFE may be disposed on the second electrode 183. The thin film encapsulation layer TFE may prevent moisture and oxygen from penetrating from the outside. The thin film encapsulation layer TFE may include at least one organic layer and at least one inorganic layer. The at least one organic layer and the at least one inorganic layer may be alternately stacked with each other. For example, the thin film encapsulation layer TFE may include two inorganic layers and an organic layer disposed between the two inorganic layers, but the embodiment is not limited thereto. In another embodiment, a sealing substrate may be provided instead of a thin film encapsulation layer to block external air and moisture from penetrating into the display device.

[0115] Figure 8 is a cross-sectional view showing a display device according to an embodiment.

[0116] Reference Figure 8 , except that the display device further includes an inorganic insulating layer 150 and the shielding electrode SH overlaps the data line DL, the display device and Figure 6 The display devices of FIG. 1 and FIG. 2 are substantially the same. Therefore, a redundant description thereof will be omitted.

[0117] The display device may further include an inorganic insulating layer 150 disposed between the interlayer insulating layer 140 and the first insulating layer 160. The inorganic insulating layer 150 may include an inorganic insulating material.

[0118] The shielding electrode SH may overlap the first connection line CL1 and the data line DL. Therefore, the shielding electrode SH may shield the data line DL and the first connection line CL1, so that the occurrence of a coupling capacitor between different pixel structures may be prevented.

[0119] Fig. 9 is an enlarged view showing a lower left portion of a display device according to an embodiment, Fig.10 Is used to describe Fig. 9 A diagram showing the connection relationship between data lines and connecting lines of a display device.

[0120] Reference Figure 1 , Fig. 9 and Fig.10 , except that a connection contact hole in which a connection line and a data line are connected to each other is provided in a display area other than a peripheral area so that data lines electrically connected to the data spider line are sequentially arranged, the display device and Figure 4 and Figure 5 The display devices of FIG. 1 and FIG. 2 are substantially the same. Therefore, a redundant description thereof will be omitted.

[0121] The first connection line CL1 may be connected to the first data line DL1 through the first connection contact hole CCNT1 disposed in the display area AA. The first connection line CL1 may include a portion CL1b extending in the first direction D1 and a portion CL1c extending in a second direction D2 perpendicular to the first direction D1.

[0122] Refer again Fig.10 , the data lines DATA LINE (also indicated by the mark “DL”) can be electrically connected to the data spider lines DATASPIDER LINE in the same order as the data spider lines DATA SPIDER LINE (also indicated by the mark “DSPL”). Figure 4 and Figure 5 Unlike the display device of the present invention, there is no need to change the order of output signals of the data driving chip connected to the data spider line, and a data driving chip of general design can be used.

[0123] Fig.11 is a diagram for describing a connection relationship between data lines and connection lines of a display device according to an embodiment.

[0124] Reference Fig.11 In addition to a CONNECTING LINE connected to two DATA LINES, the display device can be connected to Figure 4 and Figure 5 The display device of the embodiment is substantially the same. Since one connection line and one data spider line DATASPIDER LINE correspond to two data lines, the present embodiment can correspond to a display device to which a demultiplexer (demux, demultiplexer) structure is applied, for example. Therefore, the number of connection lines arranged in the display area can be reduced.

[0125] Fig.12 is a cross-sectional view showing a display device according to an embodiment, Fig.13 is a cross-sectional view showing a display device according to an embodiment, Fig.14 is a cross-sectional view showing a display device according to an embodiment, Fig.15 is a cross-sectional view showing a display device according to an embodiment.

[0126] Figures 12 to 15 An embodiment of a display device in which the positions of the connection lines CL, the data lines DL_E and DL_O, and the shielding electrode SH are changed differently is shown. In this case, the data lines may include even data lines DL_E and odd data lines DL_O, and the present embodiment may correspond to a display device to which a double data line (TDL) structure in which two data lines correspond to one pixel, a demultiplexer (demux) structure, etc. are applied.

[0127] Fig.16 is a block diagram showing an electronic device according to an embodiment, Fig.17a It shows that Fig.16 FIG. 1 is a diagram of an example in which the electronic device is implemented as a television, Fig.17b It shows that Fig.16 The electronic device is implemented as an example of a smart phone.

[0128] Reference Figure 16 to Figure 17b , the electronic device 500 may include a processor 510, a memory device 520, a storage device 530, an input / output (I / O) device 540, a power supply 550, and a display device 560. Here, the display device 560 may be Figure 1 In addition, the electronic device 500 may also include multiple ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, etc. In an embodiment, as Fig.17a As shown in , the electronic device 500 can be implemented as a television. In another embodiment, as Fig.17b As shown in , the electronic device 500 may be implemented as a smart phone. However, the electronic device 500 is not limited thereto. For example, the electronic device 500 may be implemented as a cellular phone, a video phone, a smart tablet, a smart watch, a tablet PC, a vehicle navigation system, a computer monitor, a laptop computer, a head mounted display (HMD) device, etc.

[0129] The processor 510 may perform various computing functions. The processor 510 may be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 510 may be coupled to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 510 may be coupled to an expansion bus such as a peripheral component interconnect (PCI) bus. The memory device 520 may store data used for the operation of the electronic device 500. For example, the memory device 520 may include at least one non-volatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc.). The storage device 530 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 540 may include an input device such as a keyboard, a keypad, a mouse device, a touch pad, a touch screen, etc., and an output device such as a printer, a speaker, etc. The power supply 550 may provide power for the operation of the electronic device 500.

[0130] The display device 560 may be coupled to other components via a bus or other communication link. In some embodiments, the I / O device 540 may include the display device 560. As described above, the display device 560 may have a structure in which a data spider line for a portion of the edge of the display area is connected to the data line by a connection line, so that the L-shaped cutout portion of the edge of the display device can be reduced (see FIG. Figure 4 In addition, the connection line can be shielded from other signal wirings by the shielding electrode. Since these are described above, the repeated description related thereto will not be repeated.

[0131] Industrial Applicability The inventive concept can be applied to display devices (e.g., organic light-emitting display devices, etc.) and electronic devices including display devices. For example, the inventive concept can be applied to smart phones, cellular phones, video phones, smart tablets, smart watches, tablet PCs, vehicle navigation systems, televisions, computer monitors, laptop computers, head-mounted display devices, etc.

[0132] The foregoing is an illustration of the embodiments and is not to be construed as limiting them. Although some embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications are possible in the embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. Therefore, it will be understood that the foregoing is an illustration of various embodiments and is not to be construed as being limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims.

[0133] Description of Reference Numerals 100: Base substrate 110: Buffer layer 120: first gate insulating layer 130: second gate insulating layer 140: interlayer insulating layer 160: first insulating layer 170: second insulating layer 180: light emitting structure TFT: Thin Film Transistor CL: Connecting Line DL: data line.

Claims

1. A display device, comprising a display area for displaying an image and a peripheral area as a non-display area, the display device comprising: base substrate; A first data line, arranged in the display area on the base substrate; A second data line is disposed on the base substrate in the display area and is adjacent to the first data line in a first direction; A first connection line, partially disposed in the display area on the base substrate, and electrically connected to the first data line through a first connection contact hole; a second connection line, partially disposed in the display area on the base substrate and electrically connected to the second data line through a second connection contact hole; a data pad disposed in the peripheral region and electrically connected to a data driving chip; a first data spider line disposed in the peripheral area between the data pad and the display area and electrically connected to the first connection line and the data pad; as well as A second data spider line is disposed in the peripheral area between the data pad and the display area and is electrically connected to the second connection line and the data pad while being adjacent to the first data spider line in the first direction.

2. The display device according to claim 1, wherein: The second connection contact hole is adjacent to the first connection contact hole in the display area in the first direction.

3. The display device according to claim 1, wherein: The first connection line is electrically connected to the first data spider line through a first spider contact hole, and the second connection line is electrically connected to the second data spider line through a second spider contact hole.

4. The display device according to claim 3, wherein: The second spider contact hole is adjacent to the first spider contact hole in the first direction in the peripheral region.

5. The display device according to claim 1, wherein: The base substrate is a flexible substrate, The display device further comprises a bending area, which is arranged between the data pad and the display area and extends in the first direction, and Each of the first data spider line and the second data spider line is disposed in the peripheral area between the bending area and the display area, and extends linearly in a second direction perpendicular to the first direction.

6. The display device according to claim 5, wherein: A length of the bending area in the first direction is smaller than a length of the display area in the first direction.

7. The display device according to claim 1, wherein: Each of the first data line and the second data line extends in a second direction perpendicular to the first direction, and Each of the first connection line and the second connection line includes a first portion extending in the second direction and a second portion connected to the first portion and extending in the first direction.

8. The display device according to claim 7, wherein: The first portion of the first connection line is electrically connected to the first data spider line, and the second portion of the first connection line is electrically connected to the first data line, and The first portion of the second connection line is electrically connected to the second data spider line, and the second portion of the second connection line is electrically connected to the second data line.

9. The display device according to claim 1, wherein: The peripheral area includes a left peripheral area adjacent to the left side of the display area, a right peripheral area adjacent to the right side of the display area, an upper peripheral area adjacent to the upper side of the display area, and a lower peripheral area adjacent to the lower side of the display area, and Wherein, the data pad is arranged in the lower peripheral area.

10. The display device according to claim 1, further comprising: a shielding electrode, overlapping the first connecting line and the second connecting line, The first power or the second power is applied to the shielding electrode.

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