Display panel, display device, preparation method, test method and test device

Abstract

The embodiment of the invention provides a display panel, a display device, a preparation method, a testing method and a testing device.The display panel comprises a display area and a non-display area at least partially surrounding the display area, and the non-display area comprises a testing area. The display panel comprises a substrate, a first isolation structure, a first test electrode, a protective layer, a first test structure and a second test structure, the first isolation structure is located in a test area, and a first opening is defined by the first isolation structure; the protection layer is arranged on one side of the first isolation structure away from the substrate; the first test structure is electrically connected with the first isolation structure; the second test structure is electrically connected with the first test electrode. The appearance of the first isolation structure and the appearance of the second isolation structure of the display area can be more consistent, the accuracy of evaluating the lap resistance of the first electrode and the second isolation structure of the light-emitting unit in the display area can be further improved, and finally the performance of the display panel can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel, a display device, a preparation method, a testing method and a testing device. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat display panels based on technologies such as Light Emitting Diode (LED) are widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display panels.

[0003] However, there are still some problems with display panels that need to be solved urgently. Summary of the invention

[0004] In order to overcome the technical problems mentioned in the above technical background, an embodiment of the present application provides a display panel, wherein the display panel includes a display area and a non-display area at least partially surrounding the display area, wherein the non-display area includes a test area, and the display panel includes:

[0005] substrate;

[0006] A first isolation structure, located in the test area, the first isolation structure encloses a first opening;

[0007] A first test electrode, disposed in the first opening and overlapping the first isolation structure;

[0008] A protective layer, disposed on a side of the first isolation structure away from the substrate, the protective layer at least covering a portion of a surface of the first isolation structure away from the substrate;

[0009] a first test structure, electrically connected to the first isolation structure;

[0010] The second test structure is electrically connected to the first test electrode.

[0011] In some possible implementations, the protection layer is reused as the first test structure, and the material of the protection layer is a conductive material;

[0012] Preferably, at least two of the second test structures are included, wherein the two second test structures are symmetrical;

[0013] Preferably, a second test electrode, a light-emitting test portion and the first test electrode are sequentially stacked in the first opening in a direction away from the substrate;

[0014] Preferably, the orthographic projection of the second test structure on the substrate is located within the orthographic projection of the first opening on the substrate;

[0015] Preferably, the display panel further comprises a second isolation structure located at one side of the substrate, the second isolation structure is located in the display area, and the second isolation structure encloses to form a second opening;

[0016] Preferably, the shape of the orthographic projection of the first opening on the substrate is the same as the shape of the orthographic projection of the second opening on the substrate;

[0017] Preferably, the second isolation structure is arranged at the same layer as the first isolation structure;

[0018] Preferably, the display panel further comprises a light emitting unit at least partially located in the second opening;

[0019] Preferably, the light-emitting unit comprises a second electrode, a light-emitting portion and a first electrode which are sequentially stacked in a direction away from the substrate;

[0020] Preferably, the second test electrode is arranged in the same layer as the second electrode;

[0021] Preferably, the light emitting test part and the light emitting part are arranged on the same layer;

[0022] Preferably, the first test electrode is arranged in the same layer as the first electrode;

[0023] Preferably, the second electrode comprises an anode, and / or the first electrode comprises a cathode;

[0024] Preferably, a side of the protective layer close to the substrate is at least partially in electrical contact with a side of the first isolation structure away from the substrate;

[0025] Preferably, the material of the protective layer includes titanium or molybdenum.

[0026] In some possible implementations, the present application further provides a display panel, the display panel comprising a display area and a non-display area at least partially surrounding the display area, the non-display area comprising a test area, and the display panel comprising:

[0027] substrate;

[0028] A pixel defining layer, located on one side of the substrate, and having a pixel test opening;

[0029] A first isolation structure, located in the test area, the first isolation structure encloses a first opening;

[0030] A first test electrode, disposed in the first opening and overlapping the first isolation structure;

[0031] a first test structure, electrically connected to the first isolation structure;

[0032] The second test structure is electrically connected to the second test electrode.

[0033] In some possible implementations, the present application further provides a testing device, the testing device comprising:

[0034] substrate;

[0035] A first isolation structure, wherein the first isolation structure encloses and forms a first opening;

[0036] A first test electrode, disposed in the first opening and overlapping the first isolation structure;

[0037] A protective layer, disposed on a side of the first isolation structure away from the substrate, the protective layer at least covering a portion of a surface of the first isolation structure away from the substrate;

[0038] a first test structure, electrically connected to the first isolation structure;

[0039] The second test structure is electrically connected to the second test electrode.

[0040] In some possible implementations, the present application further provides a method for preparing a display panel, wherein the display panel includes a display area and a non-display area at least partially surrounding the display area, wherein the non-display area includes a test area, and the method includes:

[0041] providing a substrate;

[0042] A first isolation structure is formed on one side of the substrate, the first isolation structure is located in the test area, and the first isolation structure surrounds a first opening;

[0043] forming a first test electrode in the first opening, wherein the first test electrode overlaps the first isolation structure;

[0044] forming a protective layer on a side of the first isolation structure away from the substrate, wherein the protective layer at least covers a portion of a surface of the first isolation structure away from the substrate;

[0045] forming a first test structure electrically connected to the first isolation structure;

[0046] A second test structure electrically connected to the first test electrode is formed.

[0047] In some possible implementations, the present application further provides a method for testing a display panel, wherein the display panel includes the display panel described in the present application, and the testing method includes:

[0048] The first test trace electrically connected to the protective layer is electrically connected to a resistance test device, and the second test trace electrically connected to the second test structure is electrically connected to the resistance test device; or, the first test trace electrically connected to the protective layer is electrically connected to a resistance test device, and the third test trace electrically connected to the second test structure close to the substrate is electrically connected to the resistance test device; or, the fourth test trace electrically connected to the first isolation structure is electrically connected to a resistance test device, and the third test trace electrically connected to the second test structure close to the substrate is electrically connected to the resistance test device;

[0049] Testing the lap resistance between the first isolation structure and the test electrode by the resistance testing device;

[0050] Based on the overlap resistance between the first isolation structure and the test electrode, the overlap effect between the second isolation structure and the first electrode in the display area is determined.

[0051] In some possible implementations, the present application further provides a display device, which includes the display panel described in the present application.

[0052] Compared with the prior art, this application has the following beneficial effects:

[0053] The present application provides a display panel, a display device, a preparation method, a testing method and a testing device. By providing a protective layer that is at least partially in contact with the side of the first isolation structure away from the substrate, the side of the second isolation structure away from the substrate can be protected, so that the morphology of the first isolation structure and the second isolation structure of the display area can be more consistent, thereby improving the accuracy of evaluating the overlap resistance between the first electrode and the second isolation structure of the light-emitting unit in the display area, and ultimately improving the performance of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0055] Figure 1 A schematic top view of a display panel provided in an embodiment of the present application;

[0056] Figure 2 One of the top view schematic diagrams of the test element group provided in the embodiment of the present application;

[0057] Figure 3 Provided for the embodiments of this application Figure 2 Schematic cross-sectional view at AA in the middle;

[0058] Figure 4 One of the cross-sectional schematic diagrams of a portion of the display area and a portion of the test area provided in an embodiment of the present application;

[0059] Figure 5 The second cross-sectional schematic diagram of a portion of the display area and a portion of the test area provided in the embodiment of the present application;

[0060] Figure 6 The third cross-sectional schematic diagram of a portion of the display area and a portion of the test area provided in the embodiment of the present application;

[0061] Figure 7 A second schematic top view of a test element group provided in an embodiment of the present application;

[0062] Figure 8 Provided for the embodiments of this application Figure 7 One of the cross-sectional views at the middle BB;

[0063] Fig. 9 Provided for the embodiments of this application Figure 7 The second cross-sectional view of the middle BB;

[0064] Fig.10 Provided for the embodiments of this application Figure 7 The third cross-sectional view of the middle BB;

[0065] Fig.11 A fourth cross-sectional schematic diagram of a portion of the display area and a portion of the test area provided in an embodiment of the present application;

[0066] Fig.12 Provided for the embodiments of this application Figure 7 The fourth cross-sectional view of the middle BB;

[0067] Fig.13 Provided for the embodiments of this application Figure 7 The fifth cross-sectional view of the middle BB;

[0068] Fig.14 A schematic diagram of a process for preparing a display panel provided in an embodiment of the present application;

[0069] Fig.15 A cross-sectional view of forming a first isolation structure on one side of a substrate provided in an embodiment of the present application;

[0070] Fig.16A cross-sectional view of sequentially forming a light-emitting test portion and a first test electrode in a first opening in a direction away from the substrate according to an embodiment of the present application;

[0071] Fig.17 A cross-sectional schematic diagram of a first insulating portion and a second insulating portion being sequentially formed on a side of a first test electrode away from a substrate provided in an embodiment of the present application;

[0072] Fig.18 A cross-sectional view of forming a conductive layer on one side of a substrate provided in an embodiment of the present application;

[0073] Fig.19 A cross-sectional view of forming a planarization layer on a side of the conductive layer away from the substrate provided in an embodiment of the present application;

[0074] Fig. 20 The cross-sectional intention of forming a pixel defining layer on a side of the planarization layer away from the substrate provided in an embodiment of the present application;

[0075] Fig.21 A cross-sectional view of forming a first isolation structure on a side of a pixel defining layer away from a substrate provided in an embodiment of the present application;

[0076] Fig. 22 A schematic top view of a display panel after removing the test area provided in an embodiment of the present application;

[0077] Fig.23 A schematic flow chart of a display panel testing method provided in an embodiment of the present application.

[0078] Figure numerals: 1, test element group; 2, pin; 3, first test trace; 4, first isolation structure; 401, first isolation test part; 402, second isolation test part; 403, third isolation test part; 5, protective layer; 51, first electrical connection part; 52, first inclined part; 53, first horizontal part; 6, first opening; 7, second test structure; 71, second electrical connection part; 72, second inclined part; 73, second horizontal part; 8, second test trace; 9, substrate; 91, substrate; 10, second test electrode; 101, fourth via hole; 11, light-emitting test part; 12, first test electrode; 13, pixel defining layer; 131, pixel opening; 132, pixel test opening; 133, fifth via hole; 134, seventh via hole; 14, second electrode; 15, light-emitting part; 16, first electrode pole; 17, first packaging layer; 171, packaging unit; 18, second gap; 19, second opening; 20, first insulating layer; 201, first insulating part; 2011, first via hole; 2012, eighth via hole; 21, second insulating layer; 211, second insulating part; 2111, second via hole; 22, first gap; 23, second packaging layer; 24, third packaging layer; 25, touch insulating layer; 26, touch layer; 261, first touch layer; 262, second touch layer; 27, planarization layer; 271, third via hole; 272, sixth via hole; 28, second isolation structure; 281, first isolation part; 282, second isolation part; 283, third isolation part; 29, conductive layer; 291, third test trace; 292, fourth test trace; 30, light-emitting unit; 31, third gap. DETAILED DESCRIPTION

[0079] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0080] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0081] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0082] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the inventive product is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0083] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.

[0084] Improving the density of light-emitting units in a display panel (i.e., pixel density) is an important way to improve the display effect. However, the display panels currently made using the fine metal evaporation mask (FMM) technology cannot further increase the density of light-emitting units due to technical limitations. The inventors have found through long-term research that in order to solve the technical problem that the density of light-emitting units cannot be further increased, a second isolation structure is set in some display panels. When the light-emitting functional layer and the first electrode are evaporated in the entire layer, the light-emitting functional layer and the first electrode can be disconnected at the second isolation structure. Through multiple evaporation and multiple etching processes (i.e., light-emitting unit patterning), light-emitting units of different colors can be formed in different second openings.

[0085] Among them, patent CN118251982A, patent 202410864269.8, patent PCT / CN2024 / 098407, patent PCT / CN2024 / 102783, patent PCT / CN2024 / 098217, patent PCT / CN20241099419 and patent PCT / CN20241099072 record relevant technical solutions of the second isolation structure and the encapsulation layer, and their contents are incorporated into this application by reference for reference.

[0086] The display panel in the related art includes a display area and a non-display area, the non-display area includes a test area, and the test area is provided with a test element group, which is used to test the overlap resistance between the first electrode (such as the cathode) of the emulated light-emitting unit and the second isolation structure, so as to evaluate the overlap effect between the first electrode of the light-emitting unit and the second isolation structure in the display area. However, the overlap resistance between the first electrode of the emulated light-emitting unit and the second isolation structure tested in the test area in the related art is not accurate enough, thereby affecting the accuracy of evaluating the overlap resistance between the first electrode of the light-emitting unit and the second isolation structure in the display area, and ultimately affecting the performance of the display panel.

[0087] In order to solve the above-mentioned technical problems, the inventor innovatively designed the following technical solutions, and the specific implementation solutions of the present application will be described in detail below in conjunction with the accompanying drawings. It should be noted that the defects existing in the solutions in the above-mentioned prior art are the results obtained by the inventor after practice and careful research. Therefore, the discovery process of the above-mentioned technical problems and the solutions proposed in this embodiment below for the above-mentioned problems should all be the contributions made by the inventor to the present application in the process of invention and creation, and should not be understood as the technical content known to those skilled in the art.

[0088] See also Figure 1-Figure 3 This embodiment provides a display panel, which includes a display area AA and a non-display area AB that at least partially surrounds the display area AA, the non-display area AB includes a test area AC, and the display panel includes a substrate 9, a first isolation structure 4, a first test electrode 12, a protective layer 5, a first test structure and a second test structure 7.

[0089] The first isolation structure 4 is located in the test area AC, and the first isolation structure 4 surrounds a first opening 6 .

[0090] The first test electrode 12 is disposed in the first opening 6 and overlaps the first isolation structure 4 .

[0091] The protection layer 5 is disposed on a side of the first isolation structure 4 away from the substrate 9 , and the protection layer 5 at least covers a portion of the surface of the first isolation structure 4 away from the substrate 9 .

[0092] The first test structure is electrically connected to the first isolation structure 4 ; the second test structure 7 is electrically connected to the first test electrode 12 .

[0093] The first isolation structure 4 , the first test electrode 12 , the protection layer 5 , the first test structure and the second test structure 7 form at least a part of the test element group 1 .

[0094] Figure 3 The position of the cross-section line in indicates that the substrate 9 and the film layer structure on the substrate 9 may be other structures.

[0095] In the related art, the side of the first isolation structure 4 away from the substrate 9 is exposed. Therefore, during the manufacturing process of the display panel, the side of the first isolation structure 4 away from the substrate 9 is easily over-etched, resulting in a large difference between the morphology of the first isolation structure 4 and the morphology of the second isolation structure 28 of the display area AA, thereby making the evaluation of the lap resistance between the second isolation structure 28 of the display area AA and the first electrode 16 inaccurate.

[0096] In this embodiment, a protective layer 5 is provided on a side of the first isolation structure 4 away from the substrate 9, and the protective layer 5 is in at least partial contact with the side of the first isolation structure 4 away from the substrate 9. The protective layer 5 can protect the side of the first isolation structure 4 away from the substrate 9. In the subsequent manufacturing process of the display panel, it is not easy to over-etch the side of the first isolation structure 4 away from the substrate 9, so that the morphology of the first isolation structure 4 can be closer to the morphology of the second isolation structure 28 of the display area AA, thereby improving the test accuracy of the test element group 1 on the overlap resistance between the second isolation structure 28 in the display area AA and the first electrode 16, and ultimately improving the performance of the display panel.

[0097] In this embodiment, by electrically connecting the resistance testing equipment to the first test structure and the second test structure 7, the overlap resistance between the first test electrode 12 and the first isolation structure 4 can be tested. Through the overlap resistance between the first test electrode 12 and the first isolation structure 4, the overlap resistance between the first electrode 16 and the second isolation structure 28 in the display area AA can be evaluated.

[0098] Based on the above design, this embodiment can protect the side of the second isolation structure 28 away from the substrate 9 by providing a protective layer 5 that is at least partially in contact with the side of the first isolation structure 4 away from the substrate 9, so that the morphology of the first isolation structure 4 and the second isolation structure 28 in the display area AA can be more consistent, thereby improving the accuracy of evaluating the overlap resistance between the first electrode 16 of the light-emitting unit 30 and the second isolation structure 28 in the display area AA, and ultimately improving the performance of the display panel.

[0099] For some possible implementations, see Figure 2 and Figure 3 , the protection layer 5 is reused as the first test structure, and the material of the protection layer is a conductive material.

[0100] By electrically connecting the resistance testing equipment to the protective layer and the second test structure 7, the overlap resistance between the first test electrode 12 and the first isolation structure 4 can be tested. In this way, by reusing the protective layer 5 as the first test structure, it is easier to test the overlap resistance between the first test electrode 12 and the first isolation structure 4.

[0101] Preferably, at least two second test structures 7 are included, wherein the two second test structures 7 are symmetrical. In this way, the lap resistance between the first test electrode 12 and the first isolation structure 4 can be tested more conveniently and accurately.

[0102] Preferably, the second test electrode 10 , the light emitting test portion 11 and the first test electrode 12 are sequentially stacked in the first opening 6 in a direction away from the substrate 9 , and the orthographic projection of the second test structure 7 on the substrate 9 is located within the orthographic projection of the first opening 6 on the substrate 9 .

[0103] See also Figure 4 The display panel also includes a second isolation structure 28 located on one side of the substrate 9, the second isolation structure 28 is located in the display area AA, and the second isolation structure 28 encloses a second opening 19; the display panel also includes a light-emitting unit 30 at least partially located in the second opening 19, and the light-emitting unit 30 includes a second electrode 14, a light-emitting portion 15 and a first electrode 16 that are stacked in sequence in a direction away from the substrate 9.

[0104] The second isolation structure 28 is provided so that the display panel can form film layers of light-emitting units 30 of different colors in different second openings 19 without the need for a fine metal mask. Specifically, when forming a light-emitting functional layer, the light-emitting functional layer will be separated by the second isolation structure 28 to form a plurality of light-emitting portions 15 arranged at intervals, and when forming a first electrode layer, the first electrode layer will be separated by the second isolation structure 28 to form a plurality of first electrodes 16 arranged at intervals, the second isolation structure 28 includes a conductive material, the first electrode 16 is electrically connected to the second isolation structure 28, and a second electrode 14, a light-emitting portion 15 and a first electrode 16 form a light-emitting unit 30. Among them, the second electrode 14 can be an anode, and the first electrode 16 can be a cathode.

[0105] In this way, different light-emitting units 30 can be made independent of each other, thereby improving the crosstalk between adjacent light-emitting units 30 and improving the display effect of the display panel. At the same time, due to the presence of the second isolation structure 28, the light-emitting functional layer and the first electrode layer in the light-emitting unit 30 of each color in the display panel can be first prepared on the entire surface and then patterned, thereby eliminating the need for a fine metal mask, thereby saving the manufacturing cost of the display panel.

[0106] The second electrode layer forms the second electrode 14 in the display area AA and the second test electrode 10 in the test area AC, so the second test electrode 10 is arranged in the same layer as the second electrode 14; the light-emitting functional layer forms the light-emitting portion 15 in the second opening 19 in the display area AA and forms the light-emitting test portion 11 in the first opening 6 in the test area AC, so the light-emitting test portion 11 is arranged in the same layer as the light-emitting portion 15; the first electrode layer forms the first electrode 16 in the second opening 19 in the display area AA and forms the first test electrode 12 in the first opening 6 in the test area AC, so the first test electrode 12 is arranged in the same layer as the first electrode 16. In this way, there is no need to set up a special process to form the second test electrode 10, the light-emitting test portion 11 and the first test electrode 12, thereby reducing the manufacturing cost of forming the test element group 1.

[0107] At the same time, the overlapping morphology between the first test electrode 12 and the first isolation structure 4 in the test element group 1 is more consistent with the overlapping morphology between the first electrode 16 and the second isolation structure 28. Therefore, by testing the overlapping resistance between the first test electrode 12 and the isolation test structure, the overlapping resistance between the first electrode 16 and the second isolation structure 28 can be more accurately evaluated.

[0108] Preferably, the shape of the orthographic projection of the first opening 6 on the substrate 9 is the same as the shape of the orthographic projection of the second opening 19 on the substrate 9. In this way, the overlapping morphology of the first isolation structure 4 and the first test electrode 12 is more consistent with the overlapping morphology of the second isolation structure 28 and the first electrode 16, thereby further improving the accuracy of testing the overlapping resistance of the first isolation structure 4 and the first test electrode 12, and further improving the accuracy of evaluating the overlapping resistance of the second isolation structure 28 and the first electrode 16.

[0109] Preferably, see again Figure 4 The second isolation structure 28 is arranged on the same layer as the first isolation structure 4; while forming the second isolation structure 28, the first isolation structure 4 is formed in the test area AC. In this way, there is no need to set up a process specifically for forming the first isolation structure 4, thereby reducing the manufacturing cost of forming the first isolation structure 4.

[0110] Preferably, the side of the protective layer 5 close to the substrate 9 is at least partially in electrical contact with the side of the first isolation structure 4 away from the substrate 9. In this way, the protective layer 5 can not only protect the side of the first isolation structure 4 away from the substrate 9, but also electrically connect the protective layer 5 to the resistance testing equipment, so that the test of the lap resistance between the first isolation structure 4 and the first test electrode 12 can be more convenient.

[0111] Preferably, the material of the protection layer 5 includes titanium or molybdenum, which is less likely to be etched. Therefore, the protection layer 5 can better protect the side of the first isolation structure 4 away from the substrate 9 .

[0112] For some possible implementations, see again Figure 4 The display panel further includes a pixel defining layer 13 located between the substrate 9 and the second isolation structure 28 . The pixel defining layer 13 is provided with a pixel opening 131 located in the display area AA. The pixel opening 131 exposes at least a portion of the second electrode 14 .

[0113] Optionally, the pixel defining layer 13 extends from the display area AA to the test area AC. The pixel defining layer 13 is further provided with a pixel test opening 132 located in the test area AC. The pixel test opening 132 exposes at least a portion of the second test electrode 10 .

[0114] Optionally, the orthographic projection shape of the pixel test opening 132 on the substrate 9 is the same as the orthographic projection shape of the pixel opening 131 on the substrate 9 .

[0115] A pixel test opening 132 corresponding to the pixel opening 131 of the display area AA is set at the pixel definition layer 13 of the test area AC, so that the overlap morphology of the first test electrode 12 and the first isolation structure 4 at the test area AC can be further improved, and the overlap morphology of the second isolation structure 28 and the first electrode 16 can be more consistent.

[0116] Preferably, the pixel defining layer 13 covers the opposite sidewalls between adjacent second test electrodes 10. In this way, it is not easy for adjacent second test electrodes 10 to be electrically connected through the first isolation structure 4, thereby further improving the accuracy of measuring the lap resistance between the first test electrode 12 and the first isolation structure 4.

[0117] For some possible implementations, see again Figure 4 The test element group 1 further includes a first insulating layer 20 located on a side of the first test electrode 12 away from the substrate 9 , and the first insulating layer 20 includes a plurality of first insulating portions 201 arranged at intervals.

[0118] Optionally, at least a portion of the first insulating portion 201 extends from a side of the first isolation structure 4 facing the first opening 6 to a side of the first isolation structure 4 away from the substrate 9 .

[0119] Optionally, a first gap 22 is provided between the first insulating portion 201 located on a side of the first isolation structure 4 away from the substrate 9 and a side of the first isolation structure 4 away from the substrate 9 .

[0120] Preferably, the plurality of first insulating portions 201 are arranged at intervals on a side of the first isolation structure 4 away from the substrate 9 .

[0121] The first insulating layer 20 may encapsulate the first test electrode 12 and the sidewall of the first isolation structure 4 facing the first opening 6 .

[0122] Further, please see again Figure 4 The display panel further includes a first encapsulation layer 17 located on a side of the light emitting unit 30 away from the substrate 9 , and the first insulating layer 20 is disposed on the same layer as the first encapsulation layer 17 .

[0123] Optionally, the first encapsulation layer 17 includes a plurality of spaced-apart encapsulation units 171 , and at least some of the encapsulation units 171 extend from a side of the second isolation structure 28 toward the second opening 19 to a side of the second isolation structure 28 away from the substrate 9 .

[0124] Optionally, the packaging units 171 are spaced apart on a side of the second isolation structure 28 away from the substrate 9 .

[0125] Optionally, a second gap 18 is provided between the packaging unit 171 located on the side of the second isolation structure 28 away from the substrate 9 and the side of the second isolation structure 28 away from the substrate 9 .

[0126] Optionally, along the thickness direction of the substrate 9 , a height H2 of the second gap 18 is equal to a height H1 of the first gap 22 .

[0127] During the patterning process of the light emitting unit 30 , the first encapsulation layer 17 is disconnected at the second isolation structure 28 to form an encapsulation unit 171 . The encapsulation unit 171 can completely and independently encapsulate the corresponding light emitting unit 30 , thereby improving the display characteristics of the display panel.

[0128] The first encapsulation layer 17 extends to the test area AC, and the first encapsulation layer 17 located in the test area AC serves as the first insulating layer 20. Therefore, while the encapsulation unit 171 encapsulating the light-emitting unit 30 is formed in the display area AA, the first insulating portion 201 encapsulating the first test electrode 12 and the light-emitting test portion 11 is formed in the test area AC. In this way, there is no need to specially set up a process for forming the first insulating portion 201, thereby reducing the cost of forming the first insulating portion 201.

[0129] At the same time, the morphology of the first insulating part 201 is similar to the morphology of the packaging unit 171. Therefore, the overlap morphology between the first test electrode 12 and the first isolation structure 4 and the overlap morphology between the first electrode 16 and the second isolation structure 28 can be further improved, thereby further improving the accuracy of evaluating the overlap resistance between the first electrode 16 and the second isolation structure 28.

[0130] For some possible implementations, see again Figure 4 The test element group 1 further includes a second insulating layer 21 located on a side of the first insulating layer 20 away from the substrate 9 , and the second insulating layer 21 includes a plurality of second insulating portions 211 arranged at intervals.

[0131] Optionally, at least a portion of the second insulating portion 211 extends from a side of the first isolation structure 4 facing the first opening 6 to a side of the first isolation structure 4 away from the substrate 9 .

[0132] Optionally, the orthographic projection of the second insulating portion 211 on the substrate 9 covers the orthographic projection of the first insulating portion 201 on the substrate 9 .

[0133] Optionally, a plurality of second insulating portions 211 are arranged at intervals on a side of the first isolation structure 4 away from the substrate 9 .

[0134] Optionally, the second insulating portion 211 wraps around a side wall of the first insulating portion 201 away from the first opening 6 .

[0135] Optionally, the protection layer 5 is in electrical contact with a side of the first isolation structure 4 away from the substrate 9 through a gap between two adjacent second insulating portions 211 and a gap between two adjacent first insulating portions 201 .

[0136] Optionally, at least part of the protection layer 5 extends from a side of the second insulating portion 211 away from the first opening 6 to a side of the second insulating portion 211 away from the substrate 9 .

[0137] The second insulating portion 211 has a similar morphology to the first insulating portion 201. The second insulating portion 211 covers the side of the first insulating portion 201 away from the substrate 9. The second insulating portion 211 extends to wrap the side wall of the first insulating portion 201 away from the first opening 6. The protective layer 5 extends from the side of the second insulating portion 211 away from the first opening 6 to the side of the second insulating portion 211 away from the substrate 9. In this way, the second insulating portion 211 can better encapsulate the first test electrode 12 and the light-emitting test portion 11.

[0138] Preferably, see again Figure 4 The protective layer 5 includes a first electrical connection portion 51, which is located between two adjacent second insulating portions 211, and the side of the first electrical connection portion 51 facing the substrate 9 contacts the side of the first isolation structure 4 away from the substrate 9. In this way, the protective layer 5 is more convenient to be electrically connected to the first isolation structure 4.

[0139] Preferably, the protective layer 5 further includes a first inclined portion 52 connected to a side of the first electrical connection portion 51 away from the substrate 9, and the first inclined portion 52 covers the side wall of the second insulating portion 211 away from the first opening 6. In this way, it is easier for the protective layer 5 to cover the side wall of the second insulating portion 211 away from the first opening 6, so that water vapor is not easily transferred to the display area AA through the gap between two adjacent second insulating portions 211.

[0140] Preferably, the protective layer 5 further includes a first horizontal portion 53 connected to the side of the first inclined portion 52 away from the substrate 9, and the side of the first horizontal portion 53 facing the substrate contacts the side of the second insulating portion 211 away from the substrate 9. In this way, the protective layer 5 can be more stably disposed on the side of the first isolation structure 4 away from the substrate 9, and more stably disposed on the second insulating portion 211.

[0141] Along a direction perpendicular to the substrate 9 , the cross section of the protection layer 5 presents an eaves structure, and the first electrical connection portion 51 , the first inclined portion 52 and the first horizontal portion 53 are integrally formed in sequence.

[0142] For some possible implementations, see Figure 5The display panel further includes a second encapsulation layer 23 and a third encapsulation layer 24 which are sequentially stacked on the side of the first encapsulation layer 17 away from the substrate 9; the materials of the first encapsulation layer 17 and the third encapsulation layer 24 both include inorganic materials; the material of the second encapsulation layer 23 includes organic materials.

[0143] For example, the first encapsulation layer 17 and the third encapsulation layer 24 can be formed by chemical vapor deposition (CVD), and the second encapsulation layer 23 can be formed by inkjet printing (IJP). The second encapsulation layer 23 and the third encapsulation layer 24 can provide a better encapsulation effect on the light-emitting unit 30, thereby further improving the encapsulation quality of the display panel.

[0144] Preferably, see again Figure 5 The display panel further includes a touch insulating layer 25 located on a side of the third encapsulation layer 24 away from the substrate 9 , and the second insulating layer 21 and the touch insulating layer 25 are arranged on the same layer.

[0145] While the touch insulating layer 25 is formed in the display area AA, the second insulating layer 21 is formed in the test area AC. Thus, there is no need to specially set up a process for forming the second insulating layer 21 , thereby reducing the manufacturing cost of forming the second insulating layer 21 .

[0146] Preferably, see again Figure 5 The display panel further includes a touch wiring layer 26 located on a side of the touch insulation layer 25 far from the substrate 9 , and the protection layer 5 is on the same layer as the touch wiring layer 26 .

[0147] The touch wiring layer 26 includes touch wiring. When the touch wiring is formed in the display area AA, a protection layer 5 is formed in the test area AC. Thus, there is no need to specially set a process for forming the protection layer 5, thereby reducing the cost of manufacturing the protection layer 5.

[0148] Preferably, see Figure 6 The touch wiring layer 26 includes a first touch wiring layer 261 and a second touch wiring layer 262 stacked in sequence in a direction away from the substrate 9 , the touch insulation layer 25 is located between the first touch wiring layer 261 and the second touch wiring layer 262 , and the protection layer 5 is in the same layer as the second touch wiring layer 262 .

[0149] The first touch wiring layer 261 includes a first touch wiring, and the second touch wiring layer 262 includes a second touch wiring. The first touch wiring can be a touch transmitting electrode, and the second touch wiring can be a touch receiving electrode. While the second touch wiring is formed in the display area AA, a protective layer 5 is formed in the test area AC. In this way, there is no need to specially set up a process for forming the protective layer 5, thereby reducing the cost of manufacturing the protective layer 5.

[0150] For some possible implementations, see again Figure 4 The second test structure 7 is arranged on the same layer as the protective layer 5 .

[0151] In this embodiment, the second test structure 7 is formed while the protective layer is formed, that is, while the touch wiring is formed in the display area AA, the second test structure 7 and the protective layer are formed in the test area AC. In this way, there is no need to set up a special process for forming the second test structure 7, thereby reducing the cost of forming the second test structure 7.

[0152] Preferably, see again Figure 2 and Figure 4 The test element group 1 further includes a first test trace 3 and a second test trace 8 . The first test trace 3 is electrically connected to the protection layer 5 , and the second test trace 8 is electrically connected to a side of the second test structure 7 away from the substrate 9 .

[0153] Preferably, the test element group 1 inputs signals through the first test trace 3 electrically connected to the protection layer 5 , and the test element group 1 outputs signals through the second test trace 8 electrically connected to the second test structure 7 .

[0154] Preferably, the first test trace 3 electrically connected to the protection layer 5 is electrically connected to at least two pins 2 , and the second test trace 8 electrically connected to the second test structure 7 is electrically connected to at least two pins 2 .

[0155] The resistance testing device is electrically connected to the protective layer 5 through the pin 2 and the first test trace 3 in sequence, and the resistance testing device is also electrically connected to the second test structure 7 through the pin 2 and the second test trace 8 in sequence. In this way, the resistance testing device can be electrically connected to at least four pins 2, thereby improving the accuracy of the test element group 1 in testing the overlap resistance between the first test electrode 12 and the first isolation structure 4.

[0156] For some possible implementations, see again Figure 5 , along a direction perpendicular to the substrate 9 , a first via hole 2011 exposing at least a portion of the first test electrode 12 is provided on the first insulating portion 201 , a second via hole 2111 is provided on the second insulating portion 211 , and the second test structure 7 is electrically connected to the first test electrode 12 through the second via hole 2111 and the first via hole 2011 .

[0157] While the protection layer 5 is formed, a second test structure 7 is formed in the first opening 6 . The second test structure 7 is electrically connected to the first test electrode 12 through the second via hole 2111 and the first via hole 2011 .

[0158] Preferably, the orthographic projection of the first via hole 2011 on the substrate 9 is located within the orthographic projection of the second via hole 2111 on the substrate 9, and the center of the orthographic projection of the first via hole 2011 on the substrate 9 coincides with the center of the orthographic projection of the second via hole 2111 on the substrate 9. In this way, the second test structure 7 is more easily electrically connected to the first test electrode 12 through the second via hole 2111 and the first via hole 2011.

[0159] Preferably, the second test structure 7 includes a second electrical connection portion 71, which is located in the first via hole 2011, and the side of the second electrical connection portion 71 facing the substrate 9 contacts the side of the first test electrode 12 away from the substrate 9. In this way, it is easier to electrically connect the second test structure 7 to the first test electrode 12.

[0160] Preferably, the second test structure 7 further includes a second inclined portion 72 connected to a side of the second electrical connection portion 71 away from the substrate 9, and the second inclined portion 72 covers the side walls of the first via hole 2011 and the second via hole 2111. In this way, it is easier for the second test structure 7 to cover the side walls of the first via hole 2011 and the second via hole 2111, so that water vapor is not easily transferred to the display area AA through the side walls of the first via hole 2011 and the second via hole 2111.

[0161] Preferably, the second test structure 7 further includes a second horizontal portion 73 connected to the side of the second inclined portion 72 away from the substrate 9, and the side of the second horizontal portion 73 facing the substrate 9 contacts the side of the second insulating portion 211 away from the substrate 9. In this way, the second test structure 7 can be more stably arranged on the second insulating portion 211.

[0162] Along the direction perpendicular to the substrate 9 , the cross section of the second test structure 7 is an eaves structure, and the second electrical connection portion 71 , the second inclined portion 72 and the second horizontal portion 73 are integrally formed in sequence.

[0163] For some possible implementations, see Figure 7 and Figure 8 The second test structure 7 and the first isolation structure 4 are arranged at the same layer.

[0164] In the present embodiment, the second test structure 7 is formed while the first isolation structure 4 is formed, that is, while the second isolation structure 28 is formed in the display area AA, the second test structure 7 and the first isolation structure 4 are formed in the test area AC. In this way, there is no need for a special process for forming the second test structure 7, thereby reducing the cost of forming the second test structure 7.

[0165] Preferably, see Fig. 9The substrate includes a substrate 91, a conductive layer 29 and a planarization layer 27. The conductive layer 29 is located on one side of the substrate 91. The conductive layer 29 includes a third test trace 291. The test element group 1 includes the third test trace 291. The planarization layer 27 is located on a side of the conductive layer 29 away from the substrate 91. A third via 271 exposing at least a portion of the third test trace 291 is provided on the planarization layer 27 in a direction perpendicular to the substrate 91. The second test electrode 10 is located on a side of the planarization layer 27 away from the substrate 91.

[0166] The display panel includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked in sequence in a direction away from the substrate 91, and an insulating layer is arranged between each film layer. The conductive layer 29 in the present application can be the fourth conductive layer in the display panel, and the power supply line is located in the fourth conductive layer.

[0167] Among them, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer are all metal layers, the semiconductor layer includes a source region, a drain region and a channel region, the first conductive layer includes a gate and a first capacitor plate, the second conductive layer includes a second capacitor plate, the first capacitor plate and the second capacitor plate form a capacitor, the third conductive layer includes a drain and a source, the drain is electrically connected to the drain region, the source is electrically connected to the source region, and the gate, source and drain form a switching device.

[0168] Along the direction perpendicular to the substrate 91 , a fourth via 101 is provided on the second test electrode 10 , a fifth via 133 is provided on the pixel defining layer 13 , and the second test structure 7 is electrically connected to the third test trace 291 through the fifth via 133 , the fourth via 101 and the third via 271 .

[0169] When forming the second test structure 7, the material of the second test structure 7 will flow into the fifth via 133, the fourth via 101 and the third via 271 in sequence, and finally contact the side of the third test trace 291 away from the substrate 91, which makes it easier for the second test structure 7 to be electrically connected to the third test trace 291.

[0170] Preferably, the center of the orthographic projection of the third via 271 on the substrate 9 coincides with the center of the orthographic projection of the fourth via 101 on the substrate 9, and the center of the orthographic projection of the fourth via 101 on the substrate 9 coincides with the center of the orthographic projection of the fifth via 133 on the substrate 9. In this way, it is easier for the material of the second test structure 7 to flow into the fifth via 133, the fourth via 101 and the third via 271 in sequence and contact the side of the third test trace 291 away from the substrate 9.

[0171] Preferably, at least a portion of the pixel defining layer 13 extends to the side walls of the fourth via hole 101 and the third via hole 271 , and the pixel defining layer 13 wraps the side walls of the fourth via hole 101 and the third via hole 271 .

[0172] The pixel defining layer 13 includes inorganic materials, and the planarizing layer 27 includes organic materials. Water vapor is easily transferred in organic materials but not easily transferred in inorganic materials. Therefore, by wrapping the side walls of the fourth via 101 and the third via 271 with the pixel defining layer 13, water vapor in the planarizing layer 27 is not easily transferred to the light-emitting test part 11. At the same time, the pixel defining layer 13 can insulate the second test structure 7 from the second test electrode 10, thereby improving the accuracy of testing the overlap resistance between the first test electrode 12 and the first isolation structure 4.

[0173] For some possible implementations, see Fig.11 The conductive layer 29 includes a fourth test trace 292, the test element group 1 includes the fourth test trace 292, and along the direction perpendicular to the substrate 91, the planarization layer 27 is provided with a sixth via 272 exposing at least a portion of the fourth test trace 292, and the pixel defining layer 13 is provided with a seventh via 134, and the first isolation structure 4 is electrically connected to the fourth test trace 292 through the seventh via 134, the gap between adjacent second test electrodes 10 and the sixth via 272 in sequence.

[0174] Optionally, the center of the orthographic projection of the sixth via hole 272 on the substrate 91 coincides with the center of the orthographic projection of the seventh via hole 134 on the substrate 91 .

[0175] When the first isolation structure 4 is formed, the material of the first isolation structure 4 will flow into the seventh via 134, the gap between adjacent second test electrodes 10 and the sixth via 272 in sequence, and finally contact the side of the fourth test trace 292 away from the substrate 91, which makes it easier for the first isolation structure 4 to be electrically connected to the fourth test trace 292.

[0176] Preferably, see again Fig.10 At least a portion of the pixel defining layer 13 extends to the sidewalls opposite to the adjacent second test electrode 10 and the sidewalls of the sixth via hole 272 , and the pixel defining layer 13 wraps the sidewalls opposite to the adjacent second test electrode 10 and the sidewalls of the sixth via hole 272 .

[0177] By wrapping the opposite side walls of the adjacent second test electrode 10 and the side walls of the sixth via 272 with the pixel defining layer 13, water vapor in the planarization layer 27 is not easily transferred to the light-emitting test part 11. At the same time, the pixel defining layer 13 can insulate the first isolation structure 4 from the second test electrode 10, thereby improving the accuracy of testing the overlap resistance between the first test electrode 12 and the first isolation structure 4.

[0178] For some possible implementations, see again Figure 7-10, the test element group 1 inputs signals through the first test trace 3 electrically connected to the protection layer 5 ; or, the test element group 1 inputs signals through the fourth test trace 292 electrically connected to the first isolation structure 4 .

[0179] Optionally, the test element group 1 outputs a signal through a third test trace 291 electrically connected to the second test structure 7 .

[0180] Optionally, the first test trace 3 electrically connected to the protection layer 5 is electrically connected to at least two pins 2 ; or, the fourth test trace 292 electrically connected to the first isolation structure 4 is electrically connected to at least two pins 2 .

[0181] Optionally, the third test trace 291 electrically connected to the second test structure 7 is electrically connected to at least two pins 2 .

[0182] In some embodiments, please refer again to Figure 7 and Fig. 9 The resistance testing device is electrically connected to the protection layer 5 through the pin 2 and the first test trace 3 in sequence, and the resistance testing device is also electrically connected to the second test structure 7 through the pin 2 and the third test trace 291 in sequence.

[0183] In this embodiment, the protection layer 5 can not only protect the side of the first isolation structure 4 away from the substrate 9, but also be used for signal input.

[0184] In other embodiments, please refer again to Figure 7 and Fig.10 The resistance testing device is electrically connected to the protection layer 5 through the pin 2 and the fourth test trace 292 in sequence, and the resistance testing device is also electrically connected to the second test structure 7 through the pin 2 and the third test trace 291 in sequence.

[0185] In this embodiment, the protective layer 5 protects the side of the first isolation structure 4 away from the substrate 9. The test element group 1 inputs signals through the fourth test trace 292 electrically connected to the first isolation structure 4. Therefore, after the first test electrode 12 is formed, the overlap resistance between the first test electrode 12 and the first isolation structure 4 can be tested, so that the overlap resistance between the first electrode 16 and the second isolation structure 28 in the display area AA can be evaluated more timely.

[0186] For some possible implementations, see again Figure 4 and Figure 8 At least a portion of the first insulating portion 201 extends from a side of the second test structure 7 facing the first opening 6 to a side of the second test structure 7 away from the substrate 9 .

[0187] Optionally, a third gap 31 is provided between the first insulating portion 201 located on the side of the second test structure 7 away from the substrate 9 and the side of the second test structure 7 away from the substrate 9 .

[0188] Optionally, along a direction perpendicular to the substrate 9 , a height H3 of the third gap 31 is equal to a height H1 of the first gap 22 .

[0189] Optionally, the plurality of first insulating portions 201 are arranged at intervals on a side of the second test structure 7 away from the substrate 9 .

[0190] In this way, the overlapping morphology between the first test electrode 12 and the first isolation structure 4 is more similar to the overlapping morphology between the first electrode 16 and the second isolation structure 28 .

[0191] Preferably, see again Figure 8 , along a direction perpendicular to the substrate 9, the first insulating portion 201 is provided with an eighth via hole 2012 exposing at least a portion of the second test structure 7 away from the substrate 9, and the second insulating portion 211 extends to the side wall of the eighth via hole 2012 and contacts the side of the second test structure 7 away from the substrate 9. The first test electrode 12 and the first isolation structure 4 can be better packaged by the second insulating portion 211.

[0192] For some possible implementations, see again Figure 6 The second isolation structure 28 includes a first isolation portion 281 and a second isolation portion 282 which are stacked in sequence along a direction away from the substrate 9 , and the orthographic projection of the side of the first isolation portion 281 away from the substrate 9 on the substrate 9 is located within the orthographic projection of the second isolation portion 282 on the substrate 9 .

[0193] Since the second isolation portion 282 is located on the side of the first isolation portion 281 away from the substrate, and the lateral width of the second isolation portion 282 is greater than the lateral width of the first isolation portion 281 in a plane parallel to the substrate, the second isolation portion 282 disconnects the light-emitting functional layer and the first electrode layer at the second isolation structure 28. In this way, the second isolation structure 28 formed by the first isolation portion 281 and the second isolation portion 282 can make it easier to independently package each light-emitting unit 30, thereby improving the packaging yield of the display panel.

[0194] Preferably, see again Figure 6 The first electrode 16 of the light-emitting unit 30 is electrically connected to the first isolation portion 281; the first isolation portion 281 includes a conductive material, and the first electrode 16 corresponding to the light-emitting unit 30 extends to contact the side wall of the first isolation portion 281 to achieve electrical connection between the first electrode 16 corresponding to the light-emitting unit 30 and the first isolation portion 281.

[0195] Please see again Fig.11The second isolation structure 28 also includes a third isolation portion 283 located on the side of the first isolation portion 281 facing the substrate 9, and the first electrode 16 of the light-emitting unit 30 is electrically connected to the third isolation portion 283; the third isolation portion 283 includes a conductive material, and the first electrode 16 corresponding to the light-emitting unit 30 extends to contact the side wall of the third isolation portion 283 to achieve electrical connection between the first electrode 16 corresponding to the light-emitting unit 30 and the third isolation portion 283.

[0196] Preferably, see again Fig.10 When the second test structure 7 is in the same layer as the first isolation structure 4, the first isolation structure 4 and the second test structure 7 both include a first isolation test portion 401 and a second isolation test portion 402 which are stacked in sequence in a direction away from the substrate 9, and the orthographic projection of the side of the first isolation test portion 401 away from the substrate 9 on the substrate 9 is located within the orthographic projection of the second isolation test portion 402 on the substrate 9.

[0197] Since the second isolation test part 402 is located on the side of the first isolation test part 401 away from the substrate, and in a plane parallel to the substrate, the lateral width of the second isolation test part 402 is greater than the lateral width of the first isolation test part 401, the second isolation test part 402 will cause the light-emitting functional layer and the first electrode layer to be disconnected at the first isolation structure 4 and the second test structure 7, forming the first test electrode 12 and the light-emitting test part 11, respectively.

[0198] Please see again Fig.11 The first isolation structure 4 also includes a third isolation test part 403 located on the side of the first isolation test part 401 facing the substrate 9, and the first test electrode 12 is electrically connected to the third isolation test part 403; the third isolation test part 403 includes a conductive material, and the first test electrode 12 extends to contact the side wall of the third isolation test part 403 to achieve overlapping between the first test electrode 12 and the first isolation structure 4.

[0199] Preferably, the material of the third isolation part 283 and the third isolation test part 403 both include molybdenum metal; and / or, the material of the first isolation part 281 and the first isolation test part 401 includes aluminum metal; and / or, the material of the second isolation part 282 and the second isolation test part 402 includes titanium metal.

[0200] For some possible implementations, see Figure 1 , Figure 7 and Fig.13 The present application also provides a display panel, which includes a display area AA and a non-display area AB at least partially surrounding the display area AA, the non-display area AB includes a test area AC, and the display panel includes a substrate 9, a pixel defining layer 13, a first isolation structure 4, a first test electrode 12, a first test structure and a second test structure 7.

[0201] The structure between the display area AA and the test area AC may not be limited to Figure 1 The structure shown in the figure may also be other structures, which will not be described in detail here.

[0202] The pixel defining layer 13 is located on one side of the substrate 9 , and a pixel testing opening 132 is disposed on the pixel defining layer 13 .

[0203] The first isolation structure 4 is located in the test area AC, and the first isolation structure 4 surrounds a first opening 6 .

[0204] The first test electrode 12 is disposed in the first opening 6 and overlaps the first isolation structure 4 .

[0205] The first test structure is electrically connected to the first isolation structure 4 ; the second test structure 7 is electrically connected to the first test electrode 12 .

[0206] The first isolation structure 4 , the first test electrode 12 , the first test structure and the second test structure 7 form at least a part of the test element group 1 .

[0207] In the present embodiment, a pixel test opening 132 corresponding to the pixel opening 131 of the display area AA is provided at the pixel defining layer 13 of the test area AC. In this way, the overlap morphology between the first test electrode 12 and the first isolation structure 4 at the test area AC and the overlap morphology between the second isolation structure 28 and the first electrode 16 can be improved, so that the overlap resistance between the first test electrode 12 and the first isolation structure 4 can be tested more accurately, thereby improving the accuracy of evaluating the overlap resistance between the first electrode 16 and the second isolation structure 28 of the light-emitting unit 30 in the display area AA, and ultimately improving the performance of the display panel.

[0208] In some possible implementations, the present application further provides a testing device, which includes a substrate 9 , a first isolation structure 4 , a first testing electrode 12 , a protective layer 5 , a first testing structure, and a second testing structure 7 .

[0209] The first isolation structure 4 is located in the test area AC, and the first isolation structure 4 surrounds a first opening 6 .

[0210] The first test electrode 12 is disposed in the first opening 6 and overlaps the first isolation structure 4 .

[0211] The protection layer 5 is disposed on a side of the first isolation structure 4 away from the substrate 9 , and the protection layer 5 at least covers a portion of the surface of the first isolation structure 4 away from the substrate 9 .

[0212] The first test structure is electrically connected to the first isolation structure 4 ; the second test structure 7 is electrically connected to the first test electrode 12 .

[0213] The first isolation structure 4 , the first test electrode 12 , the protection layer 5 , the first test structure and the second test structure 7 form at least a part of the test element group 1 .

[0214] The test element group 1 further includes a first test trace 3 and a second test trace 8 . The first test trace 3 is electrically connected to the protection layer 5 , and the second test trace 8 is electrically connected to a side of the second test structure 7 away from the substrate 9 .

[0215] The test element group 1 inputs signals through the first test trace 3 electrically connected to the protection layer 5 , and outputs signals through the second test trace 8 electrically connected to the second test structure 7 .

[0216] The first test trace 3 electrically connected to the protection layer 5 is electrically connected to at least two pins 2 , and the second test trace 8 electrically connected to the second test structure 7 is electrically connected to at least two pins 2 .

[0217] The resistance testing device is electrically connected to the protective layer 5 through the pin 2 and the first test trace 3 in sequence, and the resistance testing device is also electrically connected to the second test structure 7 through the pin 2 and the second test trace 8 in sequence. In this way, the resistance testing device can be electrically connected to at least four pins 2, thereby improving the accuracy of the test element group 1 in testing the overlap resistance between the first test electrode 12 and the first isolation structure 4.

[0218] In this embodiment, by electrically connecting the resistance testing equipment to the first test structure and the second test structure 7, the overlap resistance between the first test electrode 12 and the first isolation structure 4 can be tested. Through the overlap resistance between the first test electrode 12 and the first isolation structure 4, the overlap resistance between the first electrode 16 and the second isolation structure 28 in the display area AA can be evaluated.

[0219] For some possible implementations, see Figure 1 and Fig.14 The present application also provides a method for preparing a display panel, the display panel comprising a display area AA and a non-display area AB at least partially surrounding the display area AA, the non-display area AB comprising a test area AC, the method comprising:

[0220] S10: providing a substrate 9.

[0221] S11 : forming a first isolation structure 4 on one side of the substrate 9 , the first isolation structure 4 being located in the test area AC, and the first isolation structure 4 enclosing a first opening 6 .

[0222] See also Fig.15 A first isolation structure 4 is formed on one side of the substrate 9 , and the first isolation structure 4 is provided with a first opening 6 .

[0223] S12 : forming a first test electrode 12 in the first opening 6 , and the first test structure is electrically connected to the first isolation structure 4 .

[0224] See also Fig.16 A light emitting test portion 11 and a first test electrode 12 are sequentially formed in the first opening 6 along a direction away from the substrate 9 .

[0225] When the light-emitting functional layer forms the light-emitting portion 15 in the second opening 19 of the display area AA, the light-emitting test portion 11 is formed in the first opening 6 of the test area AC. Therefore, the light-emitting test portion 11 is arranged in the same layer as the light-emitting portion 15. When the first electrode layer forms the first electrode 16 in the second opening 19 of the display area AA, the first test electrode 12 is formed in the first opening 6 of the test area AC. Therefore, the first test electrode 12 is arranged in the same layer as the first electrode 16. In this way, there is no need to set up a special process to form the light-emitting test portion 11 and the first test electrode 12, thereby reducing the manufacturing cost of forming the test element group 1.

[0226] See also Fig.17 A first insulating portion 201 and a second insulating portion 211 are sequentially formed on a side of the first test electrode 12 away from the substrate 9 , and at least part of the first insulating portion 201 extends from a side of the first isolation structure 4 toward the first opening 6 to a side of the first isolation structure 4 away from the substrate 9 .

[0227] The first encapsulation layer 17 extends to the test area AC, and the first encapsulation layer 17 located in the test area AC serves as the first insulating layer 20. Therefore, while the encapsulation unit 171 encapsulating the light-emitting unit 30 is formed in the display area AA, the first insulating portion 201 encapsulating the first test electrode 12 and the light-emitting test portion 11 is formed in the test area AC. In this way, there is no need to specially set up a process for forming the first insulating portion 201, thereby reducing the cost of forming the first insulating portion 201.

[0228] While the touch insulating layer 25 is formed in the display area AA, the second insulating layer 21 is formed in the test area AC. Thus, there is no need to specially set up a process for forming the second insulating layer 21 , thereby reducing the manufacturing cost of forming the second insulating layer 21 .

[0229] S13 : forming a protection layer 5 on a side of the first isolation structure 4 away from the substrate 9 , wherein the protection layer 5 at least covers a portion of the surface of the first isolation structure 4 away from the substrate 9 .

[0230] S14 : forming a first test structure electrically connected to the first isolation structure 4 .

[0231] S15 : forming a second test structure 7 electrically connected to the first test electrode 12 .

[0232] In some implementations, the step of sequentially forming the first insulating portion 201 and the second insulating portion 211 on a side of the first test electrode 12 away from the substrate 9 includes:

[0233] Please see again Fig.17 A first insulating portion 201 and a second insulating portion 211 are formed on a side of the first test electrode 12 away from the substrate 9 , and a second via hole 2111 and a first via hole 2011 are sequentially formed on the second insulating portion 211 and the first insulating portion 201 in a direction perpendicular to the substrate 9 .

[0234] Please see again Figure 4 A protective layer 5 is formed on the side of the first isolation structure 4 away from the substrate 9, and a second test structure 7 is formed in the first opening 6 in the same layer as the protective layer 5. The second test structure 7 is electrically connected to the first test electrode 12 through the second via 2111 and the first via 2011.

[0235] In this embodiment, the second test structure 7 is formed while the protective layer is formed, that is, while the touch wiring is formed in the display area AA, the second test structure 7 and the protective layer are formed in the test area AC. In this way, there is no need to set up a special process for forming the second test structure 7, thereby reducing the cost of forming the second test structure 7.

[0236] In this embodiment, the protective layer 5 can not only protect the side of the first isolation structure 4 away from the substrate 9, but also input signals. The resistance test device is electrically connected to the protective layer 5 through the pin 2 and the first test trace 3 in sequence, and the resistance test device is also electrically connected to the second test structure 7 through the pin 2 and the third test trace 291 in sequence, so that the lap resistance between the first test electrode 12 and the first isolation structure 4 can be tested by the resistance test device.

[0237] In some other embodiments, the step of providing a substrate includes:

[0238] A substrate 91 is provided.

[0239] See also Fig.18 A conductive layer 29 is formed on one side of the substrate 91 , the conductive layer 29 includes a third test trace 291 , and the test element group 1 includes the third test trace 291 .

[0240] See also Fig.19 A planarization layer 27 is formed on a side of the conductive layer 29 away from the substrate 91 , and a third via 271 exposing at least a portion of the third test trace 291 is provided on the planarization layer 27 in a direction perpendicular to the substrate 91 .

[0241] See also Fig. 20A pixel defining layer 13 is formed on a side of the planarization layer 27 away from the substrate 91 , and a fourth via hole 101 communicating with the third via hole 271 is provided on the pixel defining layer 13 along a direction perpendicular to the substrate 91 .

[0242] See also Fig.21 A first isolation structure 4 is formed on the side of the pixel defining layer 13 away from the substrate 91, and a second test structure 7 on the same layer as the first isolation structure 4 is formed in the first opening 6. The second test structure 7 is electrically connected to the first test electrode 12 through the fourth via 101 and the third via 271 in sequence.

[0243] In this embodiment, the conductive layer 29 may further include a fourth test line 292. When the conductive layer 29 includes the third test line 291, the following is finally formed: Fig.10 When the conductive layer 29 includes the third test trace 291 and the fourth test trace 292, the test element group 1 shown in FIG. Fig.11 Test element group 1 is shown.

[0244] In the display panel formed by the above embodiment, a protective layer 5 is arranged on the side of the first isolation structure 4 away from the substrate 9, and the protective layer 5 is in at least partial contact with the side of the first isolation structure 4 away from the substrate 9. The protective layer 5 can protect the side of the first isolation structure 4 away from the substrate 9. In the subsequent manufacturing process of the display panel, it is not easy to over-etch the side of the first isolation structure 4 away from the substrate 9, so that the morphology of the first isolation structure 4 can be closer to the morphology of the second isolation structure 28 of the display area AA, thereby improving the test accuracy of the test element group 1 on the overlap resistance between the second isolation structure 28 of the display area AA and the first electrode 16, and ultimately improving the performance of the display panel.

[0245] Preferably, after the step of forming the test element group 1 on one side of the substrate 9 , the method further includes: removing the test area AC.

[0246] See also Fig. 22 The final display panel does not include the test area AC, so the test area AC needs to be removed. During the preparation of the display panel, the test element group 1 of the test area AC can accurately determine the overlap effect between the second isolation structure 28 and the first electrode 16 of the display area AA.

[0247] For some possible implementations, see Fig.23 The present application also provides a method for testing a display panel, the display panel including the display panel in the present application, and the testing method includes:

[0248] S20: electrically connect the first test trace 3 electrically connected to the protective layer 5 to the resistance testing equipment, and electrically connect the second test trace 8 electrically connected to the second test structure 7 to the resistance testing equipment; or, electrically connect the first test trace 3 electrically connected to the protective layer 5 to the resistance testing equipment, and electrically connect the third test trace 291 electrically connected to the second test structure 7 on the side close to the substrate 9 to the resistance testing equipment; or, electrically connect the fourth test trace 292 electrically connected to the first isolation structure 4 to the resistance testing equipment, and electrically connect the third test trace 291 electrically connected to the second test structure 7 on the side close to the substrate 9 to the resistance testing equipment.

[0249] When the second test structure 7 is in the same layer as the protection layer 5 , the first test trace 3 electrically connected to the protection layer 5 is electrically connected to the resistance test device, and the second test trace 8 electrically connected to the second test structure 7 is electrically connected to the resistance test device.

[0250] When the second test structure 7 is in the same layer as the isolation test part, the first test trace 3 electrically connected to the protective layer 5 is electrically connected to the resistance testing equipment, and the third test trace 291 electrically connected to the side of the second test structure 7 close to the substrate 9 is electrically connected to the resistance testing equipment; or, the fourth test trace 292 electrically connected to the first isolation structure 4 is electrically connected to the resistance testing equipment, and the third test trace 291 electrically connected to the side of the second test structure 7 close to the substrate 9 is electrically connected to the resistance testing equipment.

[0251] S21: Testing the lap resistance between the first isolation structure 4 and the test electrode by means of a resistance testing device.

[0252] S22: Determine the overlapping effect between the second isolation structure 28 and the first electrode 16 in the display area AA based on the overlapping resistance between the first isolation structure 4 and the test electrode.

[0253] Since a protective layer 5 is provided on the side of the first isolation structure 4 away from the substrate 9 in the display panel in this embodiment, and the protective layer 5 is in at least partial contact with the side of the first isolation structure 4 away from the substrate 9, the protective layer 5 can protect the side of the first isolation structure 4 away from the substrate 9. In the subsequent manufacturing process of the display panel, it is not easy to over-etch the side of the first isolation structure 4 away from the substrate 9, so that the morphology of the first isolation structure 4 can be closer to the morphology of the second isolation structure 28 of the display area AA.

[0254] In this way, the above-mentioned testing method can more accurately measure the overlapping electrode between the first test electrode 12 and the first isolation structure 4, so that the overlapping resistance between the second isolation structure 28 and the first electrode 16 can be more accurately evaluated, and then the overlapping effect between the second isolation structure 28 and the first electrode 16 can be more accurately evaluated, and finally the performance of the display panel can be improved.

[0255] In some possible implementations, the present application further provides a display device, which includes the display panel in the present application. Since the display device includes the display panel in the present application, the performance of the display device is higher.

[0256] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0257] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A display panel, characterized in that: The display panel includes a display area and a non-display area at least partially surrounding the display area, the non-display area includes a test area, and the display panel includes: substrate; A first isolation structure, located in the test area, the first isolation structure encloses a first opening; A first test electrode, disposed in the first opening and overlapping the first isolation structure; A protective layer, disposed on a side of the first isolation structure away from the substrate, the protective layer at least covering a portion of a surface of the first isolation structure away from the substrate; a first test structure, electrically connected to the first isolation structure; The second test structure is electrically connected to the first test electrode.

2. The display panel according to claim 1, characterized in that: The protection layer is reused as the first test structure, and the material of the protection layer is a conductive material; Preferably, at least two of the second test structures are included, wherein the two second test structures are symmetrical; Preferably, a second test electrode, a light-emitting test portion and the first test electrode are sequentially stacked in the first opening in a direction away from the substrate; Preferably, the orthographic projection of the second test structure on the substrate is located within the orthographic projection of the first opening on the substrate; Preferably, the display panel further comprises a second isolation structure located at one side of the substrate, the second isolation structure is located in the display area, and the second isolation structure encloses to form a second opening; Preferably, the shape of the orthographic projection of the first opening on the substrate is the same as the shape of the orthographic projection of the second opening on the substrate; Preferably, the second isolation structure is arranged at the same layer as the first isolation structure; Preferably, the display panel further comprises a light emitting unit at least partially located in the second opening; Preferably, the light-emitting unit comprises a second electrode, a light-emitting portion and a first electrode which are sequentially stacked in a direction away from the substrate; Preferably, the second test electrode is arranged in the same layer as the second electrode; Preferably, the light emitting test part and the light emitting part are arranged on the same layer; Preferably, the first test electrode is arranged in the same layer as the first electrode; Preferably, the second electrode comprises an anode, and / or the first electrode comprises a cathode; Preferably, a side of the protective layer close to the substrate is at least partially in electrical contact with a side of the first isolation structure away from the substrate; Preferably, the material of the protective layer includes titanium or molybdenum.

3. The display panel according to claim 2, characterized in that: It also includes a first insulating layer located on a side of the first test electrode away from the substrate, the first insulating layer including a plurality of first insulating portions arranged at intervals; Preferably, at least part of the first insulating portion extends from a side of the first isolation structure toward the first opening to a side of the first isolation structure away from the substrate; Preferably, a first gap is provided between the first insulating portion located on a side of the first isolation structure away from the substrate and a side of the first isolation structure away from the substrate; Preferably, it further comprises a second insulating layer located on a side of the first insulating layer away from the substrate, wherein the second insulating layer comprises a plurality of second insulating portions arranged at intervals; Preferably, at least a portion of the second insulating portion extends from a side of the first isolation structure toward the first opening to a side of the first isolation structure away from the substrate; Preferably, the orthographic projection of the second insulating portion on the substrate covers the orthographic projection of the first insulating portion on the substrate; Preferably, a plurality of the first insulating portions are arranged at intervals on a side of the first isolation structure away from the substrate; Preferably, a plurality of the second insulating portions are arranged at intervals on a side of the first isolation structure away from the substrate; Preferably, the second insulating portion wraps a side wall of the first insulating portion away from the first opening; Preferably, the protection layer is in electrical contact with a side of the first isolation structure away from the substrate through a gap between two adjacent second insulating parts and a gap between two adjacent first insulating parts; Preferably, at least part of the protection layer extends from a side of the second insulating portion away from the first opening to a side of the second insulating portion away from the substrate; Preferably, the protection layer comprises a first electrical connection portion, the first electrical connection portion is located between two adjacent second insulating portions, and a side of the first electrical connection portion facing the substrate contacts a side of the first isolation structure away from the substrate; Preferably, the protective layer further comprises a first inclined portion connected to a side of the first electrical connection portion away from the substrate, and the first inclined portion covers a side wall of the second insulating portion away from the first opening; Preferably, the protection layer further includes a first horizontal portion connected to a side of the first inclined portion away from the substrate, and a side of the first horizontal portion facing the substrate contacts a side of the second insulating portion away from the substrate.

4. The display panel according to claim 3, characterized in that: The display panel further comprises a first encapsulation layer located at a side of the light emitting unit away from the substrate, and the first insulating layer is arranged on the same layer as the first encapsulation layer; Preferably, the first encapsulation layer comprises a plurality of encapsulation units arranged at intervals, and at least part of the encapsulation units extend from a side of the second isolation structure toward the second opening to a side of the second isolation structure away from the substrate; Preferably, the packaging unit is spaced apart on a side of the second isolation structure away from the substrate; Preferably, a second gap is provided between the packaging unit located on a side of the second isolation structure away from the substrate and a side of the second isolation structure away from the substrate; Preferably, along the thickness direction of the substrate, the height of the second gap is equal to the height of the first gap.

5. The display panel according to claim 4, characterized in that: The display panel further comprises a second encapsulation layer and a third encapsulation layer which are sequentially stacked on a side of the first encapsulation layer away from the substrate; Preferably, the display panel further comprises a touch insulating layer located on a side of the third encapsulation layer away from the substrate, and the second insulating layer is arranged on the same layer as the touch insulating layer; Preferably, the display panel further comprises a touch wiring layer located on a side of the touch insulation layer far from the substrate, and the protection layer is in the same layer as the touch wiring layer; Preferably, the touch wiring layer comprises a first touch wiring layer and a second touch wiring layer stacked in sequence in a direction away from the substrate, the touch insulation layer is located between the first touch wiring layer and the second touch wiring layer, and the protection layer is in the same layer as the second touch wiring layer.

6. The display panel according to claim 2, characterized in that: The second isolation structure comprises a first isolation portion and a second isolation portion which are sequentially stacked in a direction away from the substrate, wherein the orthographic projection of a side of the first isolation portion away from the substrate on the substrate is located within the orthographic projection of the second isolation portion on the substrate; Preferably, the first electrode of the light-emitting unit is electrically connected to the first isolation portion; and / or the second isolation structure further includes a third isolation portion located on a side of the first isolation portion facing the substrate, and the first electrode of the light-emitting unit is electrically connected to the third isolation portion; Preferably, the material of the third isolation portion includes molybdenum metal; and / or, the material of the first isolation portion includes aluminum metal; and / or, the material of the second isolation portion includes titanium metal; Preferably, the first isolation structure comprises a first isolation test portion and a second isolation test portion which are sequentially stacked in a direction away from the substrate, and the orthographic projection of a side of the first isolation test portion away from the substrate on the substrate is located within the orthographic projection of the second isolation test portion on the substrate; Preferably, the first test electrode is electrically connected to the first isolation test portion; and / or, the first isolation structure further comprises a third isolation test portion located on a side of the first isolation test portion facing the substrate, and the first test electrode is electrically connected to the third isolation test portion; Preferably, the material of the third isolation test part includes molybdenum metal; and / or the material of the first isolation test part includes aluminum metal; and / or the material of the second isolation test part includes titanium metal.

7. The display panel according to claim 2, characterized in that: The display panel further comprises a pixel defining layer located between the substrate and the second isolation structure, the pixel defining layer is provided with a pixel opening located in the display area, and the pixel opening exposes at least a portion of the second electrode; Preferably, the pixel defining layer extends from the display area to the test area, and the pixel defining layer is further provided with a pixel test opening located in the test area, and the pixel test opening exposes at least a portion of the second test electrode; Preferably, the orthographic projection shape of the pixel test opening on the substrate is the same as the orthographic projection shape of the pixel opening on the substrate; Preferably, the pixel defining layer covers opposite side walls between adjacent second test electrodes.

8. The display panel according to any one of claims 1 to 7, characterized in that: The second test structure is arranged on the same layer as the protection layer; Preferably, it further comprises a first test trace and a second test trace, wherein the first test trace is electrically connected to the protective layer, and the second test trace is electrically connected to a side of the second test structure away from the substrate; Preferably, the first test trace electrically connected to the protection layer is electrically connected to at least two pins; Preferably, the second test trace electrically connected to the second test structure is electrically connected to at least two pins.

9. The display panel according to any one of claims 3 to 5, characterized in that: The second test structure is arranged in the same layer as the protective layer; along a direction perpendicular to the substrate, the first insulating portion is provided with a first via hole exposing at least a portion of the first test electrode, the second insulating portion is provided with a second via hole, and the second test structure is electrically connected to the first test electrode through the second via hole and the first via hole; Preferably, the orthographic projection of the first via hole on the substrate is located within the orthographic projection of the second via hole on the substrate; Preferably, the center of the orthographic projection of the first via hole on the substrate coincides with the center of the orthographic projection of the second via hole on the substrate; Preferably, the second test structure comprises a second electrical connection portion, the second electrical connection portion is located in the first via hole, and a side of the second electrical connection portion facing the substrate contacts a side of the first test electrode away from the substrate; Preferably, the second test structure further comprises a second inclined portion connected to a side of the second electrical connection portion away from the substrate, and the second inclined portion covers side walls of the first via hole and the second via hole; Preferably, the second test structure further includes a second horizontal portion connected to a side of the second inclined portion away from the substrate, and a side of the second horizontal portion facing the substrate contacts a side of the second insulating portion away from the substrate.

10. The display panel according to any one of claims 2 to 6, characterized in that: The second test structure is arranged at the same layer as the first isolation structure; Preferably, the substrate comprises: substrate; A conductive layer, located on one side of the substrate, the conductive layer includes a third test trace, and the test element group includes the third test trace; a planarization layer, located on a side of the conductive layer away from the substrate, wherein a third via hole exposing at least a portion of the third test trace is provided on the planarization layer in a direction perpendicular to the substrate, and wherein the second test electrode is located on a side of the planarization layer away from the substrate; The display panel further includes a pixel defining layer located between the film layer where the second test electrode is located and the first isolation structure, wherein a fourth via hole is provided on the second test electrode in a direction perpendicular to the substrate, a fifth via hole is provided on the pixel defining layer, and the second test structure is electrically connected to the third test trace through the fifth via hole, the fourth via hole, and the third via hole; Preferably, the center of the orthographic projection of the third via hole on the substrate coincides with the center of the orthographic projection of the fourth via hole on the substrate; Preferably, the center of the orthographic projection of the fourth via hole on the substrate coincides with the center of the orthographic projection of the fifth via hole on the substrate; Preferably, at least a portion of the pixel defining layer extends to the sidewalls of the fourth via hole and the third via hole; Preferably, the pixel defining layer wraps around side walls of the fourth via hole and the third via hole.

11. The display panel according to claim 10, characterized in that: The conductive layer includes a fourth test trace, and along a direction perpendicular to the substrate, a sixth via hole is provided on the planarization layer to expose at least a portion of the fourth test trace, a seventh via hole is provided on the pixel defining layer, and the first isolation structure is electrically connected to the fourth test trace in sequence through the seventh via hole, a gap between adjacent second test electrodes, and the sixth via hole; Preferably, the center of the orthographic projection of the sixth via hole on the substrate coincides with the center of the orthographic projection of the seventh via hole on the substrate; Preferably, at least a portion of the pixel defining layer extends to a side wall opposite to the adjacent second test electrode and a side wall of the sixth via hole; Preferably, the pixel defining layer wraps the sidewalls opposite to the adjacent second test electrode and the sidewalls of the sixth via hole.

12. The display panel according to claim 11, characterized in that: The first test trace electrically connected to the protection layer is electrically connected to at least two pins; or the fourth test trace electrically connected to the first isolation structure is electrically connected to at least two pins; Preferably, the third test trace electrically connected to the second test structure is electrically connected to at least two pins.

13. The display panel according to any one of claims 3 to 5, characterized in that: At least a portion of the first insulating portion extends from a side of the second test structure facing the first opening to a side of the second test structure away from the substrate; Preferably, a third gap is provided between the first insulating portion located on a side of the second test structure away from the substrate and a side of the second test structure away from the substrate; Preferably, along a direction perpendicular to the substrate, a height of the third gap is equal to a height of the first gap; Preferably, a plurality of the first insulating portions are arranged at intervals on a side of the second test structure away from the substrate; Preferably, along a direction perpendicular to the substrate, an eighth via hole is provided on the first insulating portion, exposing at least a portion of the second test structure away from the substrate; Preferably, the second insulating portion extends to a side wall of the eighth via hole and contacts a side of the second test structure away from the substrate.

14. The display panel according to any one of claims 2 to 5, characterized in that: The second test structure comprises a first isolation test portion and a second isolation test portion which are sequentially stacked in a direction away from the substrate, wherein the orthographic projection of a side of the first isolation test portion away from the substrate on the substrate is located within the orthographic projection of the second isolation test portion on the substrate; Preferably, the first test electrode is electrically connected to the first isolation test portion; and / or the second test structure further comprises a third isolation test portion located on a side of the first isolation test portion facing the substrate, and the first test electrode is electrically connected to the third isolation test portion; Preferably, the material of the third isolation test part includes molybdenum metal; and / or the material of the first isolation test part includes aluminum metal; and / or the material of the second isolation test part includes titanium metal.

15. A display panel, characterized in that: The display panel includes a display area and a non-display area at least partially surrounding the display area, the non-display area includes a test area, and the display panel includes: substrate; A pixel defining layer, located on one side of the substrate, and having a pixel test opening; A first isolation structure, located in the test area, the first isolation structure encloses a first opening; A first test electrode is disposed in the first opening and overlapped with the first isolation structure; a first test structure, electrically connected to the first isolation structure; The second test structure is electrically connected to the second test electrode.

16. A testing device, characterized in that: The testing device comprises: substrate; A first isolation structure, wherein the first isolation structure encloses and forms a first opening; A first test electrode, disposed in the first opening and overlapping the first isolation structure; A protective layer, disposed on a side of the first isolation structure away from the substrate, the protective layer at least covering a portion of a surface of the first isolation structure away from the substrate; a first test structure, electrically connected to the first isolation structure; The second test structure is electrically connected to the second test electrode.

17. The testing device according to claim 16, characterized in that: The second test structure is arranged on the same layer as the protection layer; Preferably, it further comprises a first test trace and a second test trace, wherein the first test trace is electrically connected to the protective layer, and the second test trace is electrically connected to a side of the second test structure away from the substrate; Preferably, the first test trace electrically connected to the protection layer is electrically connected to at least two pins; Preferably, the second test trace electrically connected to the second test structure is electrically connected to at least two pins.

18. A method for preparing a display panel, characterized in that: The display panel includes a display area and a non-display area at least partially surrounding the display area, the non-display area includes a test area, and the method includes: providing a substrate; A first isolation structure is formed on one side of the substrate, the first isolation structure is located in the test area, and the first isolation structure surrounds a first opening; forming a first test electrode in the first opening, wherein the first test electrode overlaps the first isolation structure; forming a protective layer on a side of the first isolation structure away from the substrate, wherein the protective layer at least covers a portion of a surface of the first isolation structure away from the substrate; forming a first test structure electrically connected to the first isolation structure; A second test structure electrically connected to the first test electrode is formed.

19. The method for preparing a display panel according to claim 18, characterized in that: The step of forming a first test electrode in the first opening includes: forming light-emitting test parts in sequence in the first opening; forming a first test electrode on a side of the light emitting test portion away from the substrate; Before the step of forming a protective layer on a side of the first isolation structure away from the substrate, the method further includes: A first insulating portion and a second insulating portion are sequentially formed on a side of the first test electrode away from the substrate, and at least a portion of the first insulating portion extends from a side of the first isolation structure toward the first opening to a side of the first isolation structure away from the substrate.

20. The method for preparing a display panel according to claim 19, characterized in that: The step of sequentially forming a first insulating portion and a second insulating portion on a side of the first test electrode away from the substrate comprises: forming a first insulating portion and a second insulating portion on a side of the first test electrode away from the substrate, and sequentially forming a second via hole and a first via hole on the second insulating portion and the first insulating portion in a direction perpendicular to the substrate; The step of forming a protective layer on a side of the first isolation structure away from the substrate comprises: A protection layer is formed on a side of the first isolation structure away from the substrate, and a second test structure is formed in the first opening on the same layer as the protection layer. The second test structure is electrically connected to the first test electrode through the second via hole and the first via hole.

21. The method for preparing a display panel according to claim 19, characterized in that: The step of providing a substrate comprises: providing a substrate; forming a conductive layer on one side of the substrate, the conductive layer comprising a third test trace, and the test element group comprising the third test trace; A planarization layer is formed on a side of the conductive layer away from the substrate, and a third via hole exposing at least a portion of the third test trace is provided on the planarization layer in a direction perpendicular to the substrate; A pixel defining layer is formed on a side of the planarization layer away from the substrate, and a fourth via hole connected to the third via hole is provided on the pixel defining layer in a direction perpendicular to the substrate; Preferably, the step of forming a first isolation structure on one side of the substrate includes: A first isolation structure is formed on one side of the substrate, and a second test structure is formed in the first opening on the same layer as the first isolation structure, wherein the second test structure is electrically connected to the first test electrode through the fourth via hole and the third via hole in sequence; Preferably, after the step of forming a second test structure electrically connected to the first test electrode, the method further comprises: The test area is removed.

22. A method for testing a display panel, characterized in that: The display panel comprises the display panel according to claim 8 or claim 11, and the testing method comprises: The first test trace electrically connected to the protective layer is electrically connected to a resistance test device, and the second test trace electrically connected to the second test structure is electrically connected to the resistance test device; or, the first test trace electrically connected to the protective layer is electrically connected to a resistance test device, and the third test trace electrically connected to the second test structure close to the substrate is electrically connected to the resistance test device; or, the fourth test trace electrically connected to the first isolation structure is electrically connected to a resistance test device, and the third test trace electrically connected to the second test structure close to the substrate is electrically connected to the resistance test device; Testing the lap resistance between the first isolation structure and the test electrode by the resistance testing device; Based on the overlap resistance between the first isolation structure and the test electrode, the overlap effect between the second isolation structure and the first electrode in the display area is determined.

23. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 15.

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