Method for producing power semiconductor having electrode in package, package of power semiconductor
By forming nanowires with high aspect ratios on the electrodes of the power semiconductor, and using the high elasticity and high density of the nanowires to absorb thermal mechanical stress, the problem of traditional interconnections being easily damaged under thermal mechanical stress is solved, and a high-stable power semiconductor packaging is achieved.
Patent Information
- Application Number
- CN202380068000.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2022-09-27
- Filing Date
- 2023-04-18
- Publication Date
- 2025-04-29
AI Technical Summary
The interconnections of conventional power semiconductors are prone to damage under thermal mechanical stress, resulting in failure, and alternatives such as insufficient flexibility of micro-through holes.
Micron/nanocopper wires are used as soft interconnects, and thermal mechanical stress is absorbed by forming nanowires with high aspect ratios on electrodes of power semiconductors.
A power semiconductor package that withstands mechanical deformation while conducting current and heat is realized, improving the robustness of thermal mechanical stress and avoiding the problem of interconnection damage.
Smart Images
Figure CN119908027A_ABST
Abstract
Description
Technical Field
[0001] The present invention generally relates to methods and systems for manufacturing assemblies of power semiconductors in packages. Background Art
[0002] Traditionally, power semiconductors are electrically connected to external components through wire bonding, soldering, and thermal contact with a conductive substrate for heat transfer. Multiple layers are required to implement the wiring of wire bonds on power semiconductors, such as aluminum metallization, solder layers, and passivation layers.
[0003] When components are subjected to thermomechanical stresses due to thermal expansion coefficient mismatch and thermal gradients, interconnects can be damaged, ultimately leading to failure of the power semiconductor.
[0004] An alternative to wire bonding is to embed the power semiconductor into a printed circuit board (PCB). The connections are made using laser-drilled microvias. While the parasitic inductance of the connections is improved, the flexibility of the microvias under thermal and mechanical stress is suboptimal.
[0005] To overcome these challenges, soft interconnects made of micron / nanoscale copper wires have been proposed. Nanowires have a high aspect ratio, meaning their height is many times greater than their diameter. This size allows for flexible deformation under mechanical stress. They are also relatively dense, forming a nanowire forest that efficiently transports current and heat.
[0006] Mechanical displacements due to thermal effects between the power semiconductor and the printed circuit board are absorbed by the deformation of the nanowires without damaging them. The copper nanowire fabrication method can be performed by electrodeposition through a porous membrane used as a template, which is dissolved after the nanowires are formed. Summary of the Invention
[0007] The present disclosure aims to provide a very reliable and easy to implement method and assembly for manufacturing a power semiconductor in a package, as well as a package comprising a power semiconductor that is very robust against stresses.
[0008] To this end, the present disclosure relates to a method for producing a power semiconductor having electrodes in a package, the method comprising the following steps:
[0009] - a masking film is provided on the entire top and bottom surfaces of the power semiconductor and an opening is formed above the electrode,
[0010] - providing a conductive layer on the top and bottom surfaces of the masked power semiconductor,
[0011] - Positioning the template over the electrodes and nanowires of the power semiconductor,
[0012] - electrodeposition of a conductive material on top of the electrodes of the power semiconductor for nanowire formation, the nanowire formation being performed within the template,
[0013] - removing the masking film and the material on top of the masking film,
[0014] - Inserting power semiconductors into the cavities of the prepreg panels,
[0015] - Curing of prepreg panels,
[0016] - dissolving template,
[0017] - placing prepreg on the top and bottom of the cured prepreg panel and over the portion of the power semiconductor between the two electrode metallizations,
[0018] - depositing a conductive layer on the surface of the provided prepreg,
[0019] - curing the provided prepreg,
[0020] - after curing the prepreg, providing conductive layers on the top and bottom of the panel comprising at least one power semiconductor,
[0021] - etching a portion of the electrically conductive layer over the cured prepreg which is located over the portion of the power semiconductor between the two electrode metallizations.
[0022] This allows the growth of high-aspect-ratio nanowires on each electrode of a power semiconductor. The size of the nanowires is determined by the size of the membrane's pores. Compared to copper-filled microvias, nanowires are more elastic.
[0023] Furthermore, the nanowires are protected by the membrane during the handling and removal steps, and the membrane is dissolved at the very last moment.
[0024] According to particular characteristics, each template re-covers the portion of the conductive layer situated above the electrode and the portion of the conductive layer situated above the masking film.
[0025] The present invention also relates to a power semiconductor package, comprising:
[0026] - a conductive layer above each electrode of the power semiconductor,
[0027] - a nanowire located over the portion of the conductive layer above the electrode,
[0028] a cured prepreg located on each side of the power semiconductor and over the portion of the masking film separating the two electrodes,
[0029] - a conductive layer above the nanowire, a conductive layer above each electrode of the power semiconductor, the nanowire and the conductive layer above the nanowire forming a single conductor unit.
[0030] The resulting structure is therefore suitable for conducting electrical current and heat while simultaneously undergoing mechanical deformation.
[0031] Depending on the particular feature, the height of the nanowire is between 30 and 100 times the width of the nanowire.
[0032] Thus, a flexible bond between the die and the package is achieved even despite the different coefficients of thermal expansion (CTE) in the stack.
[0033] According to particular features, the conductive layer above each electrode of the power semiconductor acts as a thermal interface that transfers heat away from the power semiconductor.
[0034] Thus, the junction temperature of the power device is controlled.According to particular characteristics, the nanowires are made of an electrically and thermally conductive material such as copper, nickel, aluminum, silver, gold or carbon, or alloys thereof.
[0035] Thus, an electrical link between the die and the power package is achieved.Depending on the particular characteristics, the nanowires cover 50% to 90% of the electrode surface. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] [ Figure 1 ]
[0037] Figure 1 An example of an algorithm for manufacturing an assembly of power semiconductors in a package is presented.
[0038] [ Figure 2 ]
[0039] Figure 2 An example showing the deposition of different layers on a power semiconductor.
[0040] [ Figure 3 ]
[0041] Figure 3 An enlarged view of a portion of a power semiconductor showing the deposition of different layers on the power semiconductor.
[0042] [ Figure 4 ]
[0043] Figure 4 Represents an example of template deposition on a power semiconductor for nanowire realization.
[0044] [ Figure 5 ]
[0045] Figure 5 Figure 4 shows an example of nanowires on a power semiconductor.
[0046] [ Figure 6 ]
[0047] Figure 6 This shows an example of inserting power semiconductors into a printed circuit board.
[0048] [ Figure 7 ]
[0049] Figure 7 This shows an example of inserting power semiconductors into a printed circuit board.
[0050] [ Figure 8 ]
[0051] Figure 8 shows an example of a power semiconductor after template removal.
[0052] [ Figure 9 ]
[0053] Figure 9 This shows an example of a completed printed circuit board.
[0054] [ Figure 10 ]
[0055] Figure 10 This shows an example of a completed printed circuit board.
[0056] [ Figure 11 ]
[0057] Figure 11 This shows an example of a completed printed circuit board.
[0058] [ Figure 12 ]
[0059] Figure 12 An example of an apparatus for manufacturing an assembly of power semiconductors in a package is shown. DETAILED DESCRIPTION
[0060] The features of the present invention will appear more clearly on reading the following description of exemplary embodiments, which is made with reference to the accompanying drawings.
[0061] Figure 1 An example of an algorithm for manufacturing an assembly of power semiconductors in a package is presented.
[0062] The present algorithm is executed, for example, by the processor 120 of the system 12 for manufacturing components of power semiconductors in packages, as will be described with reference to FIG. Figure 12 The public.
[0063] In step S100, processor 120 commands the deposition of a masking film across the entire top and bottom surfaces of the power semiconductor. For example, the masking film is placed on the top and bottom surfaces of a wafer containing the power semiconductor. In the same step, processor 120 commands the creation of openings in the surfaces of the top and / or bottom electrodes.
[0064] In step S101, processor 120 commands the sequential deposition of a seed layer, a diffusion barrier layer, and a conductive layer on the top and bottom surfaces of a masked wafer. For proper compatibility with standard PCB processes, the conductive layer is typically made of copper. The conductive layer serves as a front-end distribution layer for the following process steps and will be stripped prior to singulation.
[0065] refer to Figure 2 Examples are given.
[0066] Figure 2 An example showing the deposition of different layers on a power semiconductor.
[0067] The power semiconductor 200 has at least three electrodes, which are labeled 250 a , 250 b and 250 c .
[0068] The remaining portions of the masking film are labeled 220a, 220b, 220c, 220d, and 220e.
[0069] The conductive layers are labeled 240a, 240b, and 240c.
[0070] Portion 220b of the masking film separates electrodes 250a and 250b.
[0071] To simplify, Figure 2 The seed layer and diffusion barrier layer are not shown.
[0072] Figure 3 An enlarged view of a portion of a power semiconductor showing the deposition of different layers on the power semiconductor.
[0073] Figure 1 The enlarged view of the portion of the power semiconductor in FIG. 2 marked with 300 shows the power semiconductor 200 on which the deposition of the seed layer 320 and the diffusion barrier layer 310 is performed.
[0074] At step S102, processor 120 commands the positioning of a template over the electrode metallization of the power semiconductor. Template 400a re-covers the portion of conductive layer 240a located over electrode 250a and the portion of the conductive layer located over masking films 220a and 220b. For example, template 400a overlaps masking films 220a and 220b by 200 microns.
[0075] Template 400b re-covers the portion of conductive layer 240a located above electrode 250b and the portion of the conductive layer located above masking films 220b and 220c. For example, template 400b overlaps masking films 220b and 220c by 200 microns.
[0076] Template 400c re-covers the portion of conductive layer 240b located above electrode 250c and the portion of the conductive layer located above masking films 220d and 220e. For example, template 400c overlaps masking films 220d and 220e by 200 microns.
[0077] An example of template positioning is in Figure 4 Shown in.
[0078] Figure 4 Represents an example of template deposition on a power semiconductor for nanowire realization.
[0079] The templates are labeled 400a, 400b, and 400c. The templates are, for example, an AAO matrix clamped on top of power semiconductor electrodes 250a, 250b, and 250c across the entire wafer surface. Pressing the templates onto the wafer ensures good contact at the film-copper interface for initiating nanowire deposition. The template surface is typically larger than the surface of the power semiconductor electrodes. Sufficient margin is added to mitigate constraints on positioning accuracy.
[0080] At step S103 , the processor 120 commands an electrodeposition process for nanowire formation.
[0081] Redistributed copper layers 240a and 240b are connected to a potential and act as cathodes in the reaction. A copper electrode (anode) is placed near the electroplating wafer. Both electrodes (wafer and anode) are immersed in the electrolytic bath. Nanowire growth stops before reaching the top of the template. Due to the fine structure of the nanowires and template, the clamping pressure can be released.
[0082] The nanowire has a height that is 30 to 100 times greater than the width of the nanowire.
[0083] The nanowires are made of electrically and thermally conductive materials such as copper, nickel, aluminum, silver, gold or carbon, or alloys of the above materials.
[0084] refer to Figure 5 Examples are given.
[0085] Figure 5 An example showing nanowires on a power semiconductor.
[0086] Nanowires 500a, 500b, 500c Figure 5 Shown in.
[0087] The photoresist films 220a to 220e and the material above them are removed using a lift-off technique, exposing the power semiconductor having copper pads and a template having nanowires stacked on top of each electrode of the power semiconductor. The power semiconductor is separated using a laser or a blade. The template acts as a protective shell for the nanowires during die processing.
[0088] The nanowires cover 50% to 90% of the electrode surface. In step S104, one or several tube cores are forced into a prepreg panel, each with a dedicated cavity. The thickness of the uncured dielectric is approximately the same as the thickness of the power semiconductor. Optionally, a small amount of glue or a frame can be added to prevent the power semiconductor from falling out of the cavity. The first lamination stage is carried out using a press plate made of non-stick material with an opening above the power semiconductor. During this first lamination, the prepreg flows into the gap between the tube core and the cavity and mechanically attaches the power semiconductor to the panel of the printed circuit board. The PCB panel is now used as a holder for the power semiconductor throughout the rest of the process.
[0089] An example of a power semiconductor being inserted into a prepreg 600a 600b is shown in FIG. Figure 6 Shown in.
[0090] In step S105 , the processor 120 commands curing of the prepreg.
[0091] Examples of cured prepregs 700a and 700b are shown in FIG. Figure 7 Shown in.
[0092] In step S106 , the processor 120 commands the dissolution of the templates 400 a , 400 b , and 400 c .
[0093] At this stage, the template is dissolved to reveal the nanowire array, e.g. Figure 8 shown.
[0094] The cavity 800 between the electrodes is shown.
[0095] In step S107 , the processor 120 commands deposition of prepregs on the top and bottom of the cured prepregs 600 a and 600 b and in the cavity 800 .
[0096] Prepreg layers labeled 910 a , 910 b , 910 c , 910 d , and 910 e are disposed on the cured prepregs 700 a and 700 b and in the cavity 800 .
[0097] The processor 120 also commands the deposition of a conductive layer on the surface of the disposed prepreg.
[0098] refer to Figure 9 Examples are given.
[0099] Copper layers 900a, 900b, 900c, 900d, and 900e have one or more openings on top of the electrodes. The area of the openings is slightly smaller than the area of the nanowires. Copper layers 900a, 900b, 900c, 900d, and 900e overlap the outer edges of the nanowire array, forming a narrow strip for electrical contact after lamination. The width of this strip is directly dependent on the accuracy of the foil's positioning on the panel containing at least one power semiconductor. In practice, an accuracy of 50 to 100 microns is foreseen.
[0100] Figure 10 A panel including at least one power semiconductor is disclosed after curing prepregs 910a, 910b, 910c, 910d, and 910e in step S108. Cured prepreg 100a is a combination of cured prepreg 700a and prepregs 910a and 910e. Cured prepreg 100b is cured prepreg 910b, and prepreg 100c is a combination of cured prepreg 700b and prepregs 910a and 910e.
[0101] At step S109, after curing the prepreg, the processor 120 commands the electrodeposition of copper layers 110a and 110b on each side of the panel comprising at least one power semiconductor. Electrodeposition is now a plating process in which copper bridges connect the ends of the nanowires and form a continuous copper layer that combines with the initial copper layer.
[0102] Portions of the copper layer on the cured prepreg 100 b are etched.
[0103] Copper layers 110a, 110b and 110c are Figure 11 Shown in.
[0104] The obtained double-layer PCB will continue to be manufactured using standard PCB manufacturing steps to obtain a power module.
[0105] The method enables the manufacture of a power semiconductor package, said package comprising:
[0106] - a conductive layer above each electrode of the power semiconductor,
[0107] - nanowires located on a portion of the conductive layer above the electrode,
[0108] - a cured prepreg, the cured prepreg being located on each side of the power semiconductor and between the two electrodes,
[0109] - The conductive layer above the nanowire, the conductive layer above each electrode of the power semiconductor, the nanowire and the conductive layer above the nanowire form a single conductor unit.
[0110] The conductive layer above each electrode of the power semiconductor acts as a thermal interface that transfers heat away from the power semiconductor.
[0111] Figure 12 An example of an apparatus for manufacturing an assembly of power semiconductors in a package is shown.
[0112] The device 12 has components connected by a bus 121 and a Figure 1 The architecture of the program-controlled processor 120 disclosed in .
[0113] The bus 121 links the processor 120 to a read-only memory ROM 122, a random access memory RAM 123, and an input / output I / O IF interface 125. The input / output I / O IF interface 125 enables the device 12 to control different processes of the manufacturing process.
[0114] Memory 123 contains data intended to receive variables and to communicate with Figure 1 The read-only memory (or possibly the flash memory 122) contains registers for instructions of the program related to the algorithm disclosed in Figure 1 These instructions are loaded into the random access memory 123 when the device 12 is powered on. Alternatively, the program can also be executed directly from the ROM memory 122.
[0115] The processing performed by device 12 may be implemented in software by execution of a set of instructions or a program by a programmable computing machine, such as a PC (personal computer), a DSP (digital signal processor), or a microcontroller; or it may be implemented in hardware by a machine or dedicated component, such as an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).
[0116] In other words, the device 12 includes a device that enables the device 12 to perform the same Figure 1 A circuit or a device including a circuit that carries a program related to the algorithm disclosed in.
Claims
1. A method for manufacturing a power semiconductor having electrodes in a package, the method comprising the following steps: - providing a masking film on the entire top and bottom surfaces of the power semiconductor and forming an opening above the electrode, - providing a conductive layer on the masked top surface and the bottom surface of the power semiconductor, - positioning a template over said electrodes and nanowires of said power semiconductor, - electrodepositing a conductive material over said electrode of said power semiconductor for nanowire formation, said nanowire formation being performed within said template, - removing the masking film and the material on the masking film, - inserting the power semiconductor into the cavity of the prepreg panel, - curing the prepreg panel, - dissolving the template, - placing prepreg over the top and bottom of the cured prepreg panel and over the portion of the power semiconductor between two electrode metallizations, - depositing a conductive layer on the surface of the provided prepreg, - curing the deposited prepreg, - after curing the prepreg, providing conductive layers on the top and bottom of a panel comprising at least one power semiconductor, - etching a portion of the electrically conductive layer over the cured prepreg which is located over a portion of the power semiconductor between two electrode metallizations.
2. The method according to claim 1, characterized in that: Each template re-covers the portion of the conductive layer located above the electrode and the portion of the conductive layer located above the masking film.
3. A power semiconductor package, the package comprising: - a conductive layer above each electrode of said power semiconductor, - a nanowire over the portion of the conductive layer over the electrode, - a cured prepreg on each side of the power semiconductor and over the portion of the masking film separating the two electrodes, - a conductive layer above the nanowire, the conductive layer above each electrode of the power semiconductor, the nanowire and the conductive layer above the nanowire forming a single conductor unit.
4. The package according to claim 3, characterized in that The height of the nanowire is between 30 and 100 times the width of the nanowire.
5. The package according to claim 3 or 4, characterized in that: The conductive layer over each electrode of the power semiconductor acts as a thermal interface that transfers heat away from the power semiconductor.
6. The package according to any one of claims 3 to 5, characterized in that The nanowires are made of an electrically and thermally conductive material such as copper, nickel, aluminum, silver, gold or carbon, or alloys of the above materials.
7. The package according to any one of claims 3 to 6, characterized in that The nanowires cover 50% to 90% of the electrode surface.