Display device

Abstract

The display device includes: a first pixel and a second pixel, the first pixel and the second pixel including a first sub-pixel to a third sub-pixel; a first data line connected to a first sub-pixel of the first pixel; a second data line connected to the first sub-pixel of the second pixel; and a first connection line connecting the first data line and the second data line. Each of the first to third sub-pixels includes a first region, a second region, a light emitting element, and an electrode electrically connecting the light emitting element and the pixel circuit. An electrode of a first sub-pixel of the first pixel is electrically connected to the pixel circuit in a first region and includes a first extension portion overlapping a second region in a plan view, and an electrode of a first sub-pixel of the second pixel is electrically connected to the pixel circuit in the second region and includes a second extension portion overlapping the first region in a plan view.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] Recently, as interest in information display increases, research and development of display devices are also continuously conducted. Summary of the invention

[0003] Technical issues

[0004] An object to be solved by the present disclosure is to provide a display device capable of reducing the load of a data line and minimizing the capacitance deviation of a sub-pixel.

[0005] The objects of the present disclosure are not limited to the objects described above, and other objects will be clearly understood from the following description by those skilled in the art.

[0006] Technical Solution

[0007] According to an embodiment of the present disclosure, a display device may include a first pixel and a second pixel, each of which includes a first sub-pixel, a second sub-pixel, and a third sub-pixel; a first data line electrically connected to the first sub-pixel of the first pixel; a second data line electrically connected to the first sub-pixel of the second pixel; and a first connection line electrically connecting the first data line and the second data line. Each of the first sub-pixel, the second sub-pixel, and the third sub-pixel may include: a first region disposed at one side of a pixel circuit; a second region disposed on the other side of the pixel circuit; a light-emitting element electrically connected to the pixel circuit; and an electrode electrically connecting the light-emitting element and the pixel circuit. The electrode of the first sub-pixel of the first pixel may be electrically connected to the pixel circuit in the first region and include a first extension portion overlapping the second region in a plan view, and the electrode of the first sub-pixel of the second pixel may be electrically connected to the pixel circuit in the second region and include a second extension portion overlapping the first region in a plan view.

[0008] The first pixel and the second pixel may be adjacent to each other in the same pixel row.

[0009] The first sub-pixel, the second sub-pixel, and the third sub-pixel may be sequentially disposed in the first direction.

[0010] The first data line and the second data line may be disposed in the first direction and may extend in the second direction.

[0011] The first data line may be disposed between the first sub-pixel and the second sub-pixel of the first pixel, and the second data line may be disposed between the first sub-pixel and the second sub-pixel of the second pixel.

[0012] The electrode of the first subpixel of the first pixel and the electrode of the first subpixel of the second pixel may have the same shape.

[0013] The electrode of the first subpixel of the first pixel and the electrode of the first subpixel of the second pixel may have the same area.

[0014] The first subpixel may emit light of a first color, the second subpixel may emit light of a second color, and the third subpixel may emit light of a third color.

[0015] The light emitting element may include a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer; and an active layer disposed between the first semiconductor layer and the second semiconductor layer.

[0016] The display device may further include: a third data line electrically connected to the second subpixel of the first pixel; a fourth data line electrically connected to the second subpixel of the second pixel; and a second connection line electrically connecting the third data line and the fourth data line.

[0017] The display device may further include: a fifth data line electrically connected to the third subpixel of the first pixel; a sixth data line electrically connected to the third subpixel of the second pixel; and a third connection line electrically connecting the fifth data line and the sixth data line.

[0018] According to an embodiment of the present disclosure, a display device may include: a first pixel and a second pixel, each of the first pixel and the second pixel including a sub-pixel emitting light of the same color; a first data line electrically connected to the sub-pixel of the first pixel; a second data line electrically connected to the sub-pixel of the second pixel; and a connection line electrically connecting the first data line and the second data line. The sub-pixel may include: a first region disposed at one side of a pixel circuit; a second region disposed on the other side of the pixel circuit; a light-emitting element electrically connected to the pixel circuit; and an electrode electrically connecting the pixel circuit and the light-emitting element. The electrode of the sub-pixel of the first pixel may be electrically connected to the pixel circuit in the first region and include a first extension portion overlapping the second region in a plan view, and the electrode of the sub-pixel of the second pixel may be electrically connected to the pixel circuit in the second region and include a second extension portion overlapping the first region in a plan view.

[0019] The first pixel and the second pixel may be adjacent to each other in the first direction in the same pixel row.

[0020] The first data line and the second data line may be disposed in the first direction and may extend in the second direction.

[0021] The electrode of the sub-pixel of the first pixel and the electrode of the sub-pixel of the second pixel may have the same shape.

[0022] The electrode of the sub-pixel of the first pixel and the electrode of the sub-pixel of the second pixel may have the same area.

[0023] The light emitting element may include: a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer; and an active layer disposed between the first semiconductor layer and the second semiconductor layer.

[0024] The display device may further include alignment electrodes spaced apart from each other, and the light emitting element may be disposed between the alignment electrodes.

[0025] The display device may further include a bridge electrode, the bridge electrode and the alignment electrode are disposed on the same layer, and the electrode of the sub-pixel may be electrically connected to the pixel circuit through the bridge electrode.

[0026] The display device may further include: a color conversion layer disposed on the light emitting element; and a color filter layer disposed on the color conversion layer.

[0027] Technical Effects

[0028] According to an embodiment of the present disclosure, since two sub-pixels share one data line, the number of channels of a driver and an overall load according to the number of channels may be reduced compared to a case where two sub-pixels are connected to two data lines.

[0029] Although electrodes of two sub-pixels are electrically connected to the pixel circuit in different regions, since the electrodes of the two sub-pixels may be formed at the same position or similar positions by including an extension extending to the remaining region, capacitance deviation of the two sub-pixels may be minimized.

[0030] The effects according to the embodiments are not limited to the contents described above, and more various effects are included in the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a schematic plan view showing a display device according to an embodiment;

[0032] Figures 2 to 4 is a schematic diagram showing an equivalent circuit of a sub-pixel according to an embodiment;

[0033] Figure 5 is a schematic diagram showing an equivalent circuit of a first pixel and a second pixel according to an embodiment;

[0034] Figure 6 and Figure 7 is a schematic plan view showing a first pixel and a second pixel according to an embodiment;

[0035] Figure 8 is a schematic plan view showing a sub-pixel according to an embodiment;

[0036] Fig. 9 is a schematic cross-sectional view showing a sub-pixel according to an embodiment;

[0037] Fig.10 and Fig.11 is a schematic cross-sectional view showing a pixel according to an embodiment;

[0038] Fig.12 is a schematic perspective view showing a light emitting element according to an embodiment; and

[0039] Fig.13 is a schematic cross-sectional view showing a light emitting element according to an embodiment. DETAILED DESCRIPTION

[0040] The present disclosure can be modified in various ways and have various forms. Therefore, specific embodiments will be shown in the drawings and will be described in detail in the specification. However, it should be understood that the present disclosure is not intended to be limited to the specific forms disclosed, and the present disclosure includes all modifications, equivalents and substitutions within the spirit and technical scope of the present disclosure.

[0041] The terms "first", "second", etc. may be used to describe various components, but these components should not be limited by these terms. These terms are only used for the purpose of distinguishing one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component without departing from the scope of the present disclosure. Unless the context clearly indicates otherwise, in the following description, a singular expression includes a plural expression.

[0042] It should be understood that in the present application, the terms "including", "having" and the like are used to specify the presence of features, numbers, steps, operations, components, parts or combinations thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof. A portion of a layer, region, plate, etc. is referred to as being "on" another portion, which includes not only the case where the portion is "directly on" another portion, but also the case where another portion exists between the portion and the other portion. In the present specification, when a portion of a layer, film, region, plate, etc. is formed on another portion, the formation direction is not limited to the upper direction, but includes forming the portion on the side surface or in the lower direction. Conversely, when a portion of a layer, region, plate, etc. is formed "under" another portion, this includes not only the case where the portion is "directly below" another portion, but also the case where another portion exists between the portion and the other portion.

[0043] With reference to the embodiments described in detail later in conjunction with the accompanying drawings, the advantages and features of the present disclosure and the methods for achieving them will become apparent. However, the present disclosure is not limited to the embodiments disclosed below and can be implemented in various different forms. In the following description, the case where one part is connected to another part includes the case where they are electrically connected to each other and another element is inserted between them and the case where they are directly connected to each other. In the embodiments of the present disclosure, the term "connection" between two configurations can mean the use of both electrical connection and physical connection in an inclusive manner.

[0044] Hereinafter, a display device according to an embodiment of the present disclosure is described with reference to the accompanying drawings related to the embodiment of the present disclosure.

[0045] Figure 1 is a schematic plan view showing a display device according to an embodiment. Figure 1 A display panel PNL provided in a display device is shown.

[0046] exist Figure 1 , the structure of the display panel PNL is briefly shown based on the display area DA. However, according to an embodiment, at least one driving circuit unit (eg, at least one of a scan driver and a data driver), a line and / or a pad not shown may also be provided on the display panel PNL.

[0047] refer to Figure 1 , the display panel PNL may include a substrate SUB and pixels PXL disposed on the substrate SUB.

[0048] The substrate SUB may form a base member of the display panel PNL and may be a rigid or flexible substrate or film. For example, the substrate SUB may be a rigid substrate formed of glass or tempered glass, a flexible substrate (or film) of a plastic or metal material, or at least one insulating layer. The material and / or physical properties of the substrate SUB are not particularly limited.

[0049] The display panel PNL and the substrate SUB for forming the display panel PNL may include a display area DA for displaying an image and a non-display area NDA except the display area DA.

[0050] The pixels PXL may be disposed in the display area DA. Various lines, pads, and / or built-in circuits connected to the pixels PXL in the display area DA may be disposed in the non-display area NDA.

[0051] The pixel PXL may include sub-pixels SPX1 , SPX2 , and SPX3 , and for example, the pixel PXL may include a first sub-pixel SPX1 , a second sub-pixel SPX2 , and a third sub-pixel SPX3 .

[0052] The sub-pixels SPX1, SPX2, and SPX3 may emit light of different colors. For example, the first sub-pixel SPX1 may emit light of a first color, the second sub-pixel SPX2 may emit light of a second color, and the third sub-pixel SPX3 may emit light of a third color. For example, the first sub-pixel SPX1 may be a red pixel emitting red light, the second sub-pixel SPX2 may be a green pixel emitting green light, and the third sub-pixel SPX3 may be a blue pixel emitting blue light, but the present disclosure is not limited thereto.

[0053] In an embodiment, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may respectively emit light of a first color, light of a second color, and light of a third color by including a light-emitting element of a first color, a light-emitting element of a second color, and a light-emitting element of a third color. In an embodiment, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may include light-emitting elements that emit light of the same color, and may respectively emit light of a first color, light of a second color, and light of a third color by including color conversion layers and / or color filters of different colors disposed on the corresponding light-emitting elements. However, the colors, types, quantities, etc. of the sub-pixels SPX1, SPX2, and SPX3 configuring each pixel PXL are not particularly limited. For example, the color of the light emitted by each pixel PXL may be variously changed.

[0054] The sub-pixels SPX1, SPX2, and SPX3 may be arranged in accordance with stripes or PENTILE TM The arrangement structure of the sub-pixels SPX1, SPX2, and SPX3 is regularly arranged (or arranged). For example, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be sequentially arranged along the first direction (X-axis direction), and repeatedly arranged along the second direction (Y-axis direction). The first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 adjacent to each other may form a pixel PXL capable of emitting light of various colors. However, the arrangement structure of the sub-pixels SPX1, SPX2, and SPX3 is not limited thereto, and the sub-pixels SPX1, SPX2, and SPX3 may be arranged in the display area DA in various structures and / or methods.

[0055] In an embodiment, each of the sub-pixels SPX1, SPX2, and SPX3 may be an active pixel. For example, each of the sub-pixels SPX1, SPX2, and SPX3 may include at least one light source (e.g., a light-emitting element) driven by a control signal (e.g., a scan signal and a data signal) and / or power (e.g., a first power and a second power). However, the type, structure, and / or driving method of the sub-pixels SPX1, SPX2, and SPX3 applicable to the display device are not particularly limited.

[0056] Figures 2 to 4 is a schematic diagram showing an equivalent circuit of a sub-pixel according to an embodiment.

[0057] According to an embodiment, Figures 2 to 4 The sub-pixel SPX shown in FIG. 1 may be arranged in Figure 1 Any one of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 in the display panel PNL of the display panel PNL. The first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may have the same or similar structures as each other.

[0058] refer to Figures 2 to 4 , the sub-pixel SPX may include a light source unit LSU for generating light having brightness corresponding to the data signal and a pixel circuit PXC for driving the light source unit LSU.

[0059] The light source unit LSU may include at least one light emitting element LD electrically connected between a first power VDD and a second power VSS. The first power VDD and the second power VSS may have different potentials so that the light emitting element LD emits light. For example, the first power VDD may be set to a high potential power, and the second power VSS may be set to a low potential power. At this time, at least during the emission period of the sub-pixel SPX, the potential difference between the first power VDD and the second power VSS may be set to be equal to or greater than the threshold voltage of the light emitting element LD.

[0060] The light emitting element LD may emit light having a brightness corresponding to the driving current provided by the pixel circuit PXC. The light emitting element LD may be formed of an organic light emitting diode or an inorganic light emitting diode (such as a micro light emitting diode or a quantum dot light emitting diode). In an embodiment, the light emitting element LD may be an ultra-small size (e.g., as small as a nanometer to micrometer size) light emitting diode using a material of an inorganic crystal structure.

[0061] In an embodiment, the light source unit LSU may include light emitting elements LD connected in parallel to each other. Figure 3 As shown in , the light source unit LSU may include a first electrode CNE1 electrically connected to a first power VDD via a pixel circuit PXC and a first power line PL1, a second electrode CNE2 electrically connected to a second power VSS through a second power line PL2, and a light emitting element LD electrically connected between the first electrode CNE1 and the second electrode CNE2. In an embodiment, the first electrode CNE1 may be an anode electrode or may correspond to an anode electrode, and the second electrode CNE2 may be a cathode electrode or may correspond to a cathode electrode.

[0062] The light emitting element LD may include a first end (e.g., a p-type end) electrically connected to the first power VDD through the first electrode CNE1 and / or the pixel circuit PXC and a second end (e.g., an n-type end) electrically connected to the second power VSS through the second electrode CNE2. For example, the light emitting element LD may be connected in parallel between the first electrode CNE1 and the second electrode CNE2 in the forward direction. Each of the light emitting elements LD connected between the first power VDD and the second power VSS in the forward direction may form a respective effective light source, and the effective light sources may collectively form a light source unit LSU of the pixel PXL.

[0063] A first end of the light emitting element LD may be commonly connected to the pixel circuit PXC through one electrode (e.g., the first electrode CNE1) of the light source unit LSU, and may be electrically connected to the first power VDD through the pixel circuit PXC and the first power line PL1. A second end of the light emitting element LD may be commonly connected to the second power VSS through another electrode (e.g., the second electrode CNE2) of the light source unit LSU and the second power line PL2.

[0064] In an embodiment, the light source unit LSU may include light emitting elements LD connected in series. The light source unit LSU may include at least one series connection. Each series connection may include a pair of electrodes (e.g., two electrodes) and at least one light emitting element LD connected between the pair of electrodes in a forward direction. Here, the number of series connections configuring the light source unit LSU and the number of light emitting elements LD configuring each series connection are not particularly limited. For example, the number of light emitting elements LD configuring each series connection may be the same as or different from each other, and the number of light emitting elements LD is not particularly limited.

[0065] The light source unit LSU may include a first series stage including at least one first light emitting element LD1, a second series stage including at least one second light emitting element LD2, a third series stage including at least one third light emitting element LD3, and a fourth series stage including at least one fourth light emitting element LD4.

[0066] The first series stage may include a first electrode CNE1 and a first intermediate electrode IET1 and at least one first light emitting element LD1 electrically connected between the first electrode CNE1 and the first intermediate electrode IET1. For example, a first end of the first light emitting element LD1 may be electrically connected to the first electrode CNE1, and a second end of the first light emitting element LD1 may be electrically connected to the first intermediate electrode IET1.

[0067] The second series stage may include a first intermediate electrode IET1 and a second intermediate electrode IET2 and at least one second light emitting element LD2 electrically connected between the first intermediate electrode IET1 and the second intermediate electrode IET2. For example, a first end of the second light emitting element LD2 may be electrically connected to the first intermediate electrode IET1, and a second end of the second light emitting element LD2 may be electrically connected to the second intermediate electrode IET2.

[0068] The third series stage may include a second intermediate electrode IET2 and a third intermediate electrode IET3 and at least one third light emitting element LD3 electrically connected between the second intermediate electrode IET2 and the third intermediate electrode IET3. For example, a first end of the third light emitting element LD3 may be electrically connected to the second intermediate electrode IET2, and a second end of the third light emitting element LD3 may be electrically connected to the third intermediate electrode IET3.

[0069] The fourth series stage may include a third intermediate electrode IET3 and a second electrode CNE2 and at least one fourth light emitting element LD4 electrically connected between the third intermediate electrode IET3 and the second electrode CNE2. For example, a first end of the fourth light emitting element LD4 may be electrically connected to the third intermediate electrode IET3, and a second end of the fourth light emitting element LD4 may be electrically connected to the second electrode CNE2.

[0070] In the case where the light emitting elements LD are connected in series / parallel, power efficiency can be improved compared to the case where the same number of light emitting elements LD are connected only in parallel. In the sub-pixel SPX in which the light emitting elements LD are connected in series / parallel, even if a short circuit defect or the like occurs in some series stages, since the brightness can be represented by the light emitting elements LD of the remaining series stages, the possibility of a dark spot defect in the sub-pixel SPX can be reduced. However, the present disclosure is not limited thereto, and the light source unit LSU may be formed by connecting only the light emitting elements LD in series, or the light source unit LSU may be formed by connecting only the light emitting elements LD in parallel.

[0071] The pixel circuit PXC may be electrically connected between the first power VDD and the light source unit LSU. The pixel circuit PXC may be electrically connected to the scan line Si (or gate line) and the data line Dj. The pixel circuit PXC may also be electrically connected to the sensing control line SSi and the sensing line SLj. For example, in the case where the sub-pixel SPX is arranged on the i-th (i is a natural number greater than 0) horizontal line (row or pixel row) and the j-th (j is a natural number greater than 0) vertical line (column or pixel column) of the display area DA, the pixel circuit PXC of the sub-pixel SPX may be electrically connected to the i-th scan line Si, the i-th sensing control line SSi, the j-th data line Dj and the sensing line SLj of the display area DA.

[0072] According to an embodiment, the pixel circuit PXC may include a transistor and at least one capacitor. For example, the pixel circuit PXC may include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst.

[0073] The first transistor T1 may be electrically connected between the first power VDD and the light source unit LSU. For example, the first electrode (e.g., the drain electrode) of the first transistor T1 may be electrically connected to the first power VDD, and the second electrode (e.g., the source electrode) of the first transistor T1 may be electrically connected to an electrode (e.g., the anode electrode) of the light source unit LSU. The gate electrode of the first transistor T1 may be electrically connected to the first node N1. The back gate electrode of the first transistor T1 may be electrically connected to the second node N2. The first transistor T1 may control the driving current provided to the light source unit LSU in response to the voltage of the first node N1. For example, the first transistor T1 may be a driving transistor that controls the driving current of the sub-pixel SPX.

[0074] The second transistor T2 is electrically connected between the data line Dj and the first node N1. For example, the first electrode (e.g., source electrode) of the second transistor T2 may be electrically connected to the data line Dj, and the second electrode (e.g., drain electrode) of the second transistor T2 may be electrically connected to the first node N1. The gate electrode of the second transistor T2 may be electrically connected to the scan line Si. In the case where a scan signal SCi providing a gate-on voltage (e.g., a high-level voltage) is provided from the scan line Si, the second transistor T2 may be turned on to electrically connect the data line Dj and the first node N1. In each frame period, a data signal DSj of a corresponding frame may be provided to the data line Dj, and the data signal DSj may be transmitted to the first node N1 by the second transistor T2 turned on during the period of the scan signal SCi providing the gate-on voltage. For example, the second transistor T2 may be a switching transistor for transmitting each data signal DSj to the inside of the sub-pixel SPX.

[0075] The third transistor T3 may be electrically connected between the first transistor T1 and the sensing line SLj. For example, the first electrode of the third transistor T3 may be electrically connected to the sensing line SLj, and the second electrode of the third transistor T3 may be electrically connected to the second node N2 (or the second electrode of the first transistor T1). The gate electrode of the third transistor T3 may be connected to the sensing control line SSi. In the case where the sensing control line SSi is omitted, the gate electrode of the third transistor T3 may be connected to the scan line Si (the previous scan line in the row before the scan line Si or the next scan line in the row after the scan line Si). The third transistor T3 may be turned on by the sensing control signal SSCi of the gate-on voltage provided to the sensing control line SSi during the sensing period to electrically connect the sensing line SLj and the first transistor T1.

[0076] According to an embodiment, the sensing period may be a period for extracting characteristics of the sub-pixel SPX provided in the display area DA (e.g., a threshold voltage of the first transistor T1, etc.). During the sensing period, a reference voltage by which the first transistor T1 may be turned on may be provided to the first node N1 through the data line Dj and the second transistor T2, or each sub-pixel SPX may be connected to a current source, etc., to turn on the first transistor T1. Since the third transistor T3 is turned on by the sensing control signal SSCi that provides the gate-on voltage to the third transistor T3, the first transistor T1 may be electrically connected to the sensing line SLj. Thereafter, the sensing signal SENj may be output to an external device through the sensing line SLj, and the characteristics of each sub-pixel SPX including the threshold voltage of the first transistor T1, etc. may be detected using the sensing signal SENj.

[0077] A first electrode of the storage capacitor Cst may be electrically connected to the second node N2, and a second electrode of the storage capacitor Cst may be electrically connected to the first node N1. The storage capacitor Cst may be charged with a voltage corresponding to the data signal DSj supplied to the first node N1 during each frame period.

[0078] exist Figures 2 to 4 In the embodiment, all transistors (e.g., the first transistor T1, the second transistor T2, and the third transistor T3) included in the pixel circuit PXC are N-type transistors, but the present disclosure is not limited thereto. At least one of the first transistor T1, the second transistor T2, and the third transistor T3 may be changed to a P-type transistor. The pixel circuit PXC may be a pixel circuit of various structures and / or driving methods.

[0079] Figure 5 is a schematic diagram showing an equivalent circuit of a first pixel and a second pixel according to an embodiment. Figure 5 Some or a plurality of sub-pixels SPX1_O, SPX2_O, SPX3_O, SPX1_E, SPX2_E, and SPX3_E included in one horizontal line are shown.

[0080] refer to Figure 5, the first pixel PXL_ODD (odd pixel or pixel of odd column) and the second pixel PXL_EVEN (even pixel or pixel of even column) may be located on the same horizontal line (or the same pixel row). The first pixel PXL_ODD and the second pixel PXL_EVEN may be adjacent to each other in the same pixel row. The first pixel PXL_ODD and the second pixel PXL_EVEN are two adjacent pixels PXL named according to their positions, and each of the first pixel PXL_ODD and the second pixel PXL_EVEN may be the same as the pixel PXL. The first pixel PXL_ODD and the second pixel PXL_EVEN may be arranged sequentially and repeatedly in the first direction (X-axis direction).

[0081] The first pixel PXL_ODD may include a first subpixel SPX1_O, a second subpixel SPX2_O, and a third subpixel SPX3_O, and the second pixel PXL_EVEN may include a first subpixel SPX1_E, a second subpixel SPX2_E, and a third subpixel SPX3_E.

[0082] The first, second, and third subpixels SPX1_O, SPX2_O, and SPX3_O of the first pixel PXL_ODD may have the same pixel structure, and the first, second, and third subpixels SPX1_E, SPX2_E, and SPX3_E of the second pixel PXL_EVEN may have the same pixel structure.

[0083] The first gate line SC_ODD and the second gate line SC_EVEN may extend in the first direction (X-axis direction) and may be arranged in the second direction (Y-axis direction).

[0084] The first subpixel SPX1_O, the second subpixel SPX2_O, and the third subpixel SPX3_O of the first pixel PXL_ODD may be electrically connected to the first gate line SC_ODD, and the first subpixel SPX1_E, the second subpixel SPX2_E, and the third subpixel SPX3_E of the second pixel PXL_EVEN may be electrically connected to the second gate line SC_EVEN. The subpixels SXP1_O, SPX2_O, SPX3_O, SPX1_E, SPX2_E, and SPX3_E included in one horizontal line may be sequentially arranged along the first direction (X-axis direction).

[0085] The data lines D1, D2, D3, D4, D5, and D6 may extend in the second direction (Y-axis direction) and may be arranged along the first direction (X-axis direction). The distance between the data lines D1, D2, D3, D4, D5, and D6 may be the same as the distance between the sub-pixels SXP1_O, SPX2_O, SPX3_O, SPX1_E, SPX2_E, and SPX3_E. For example, the data lines D1, D2, D3, D4, D5, and D6 may be spaced apart from each other, and one of the sub-pixels SXP1_O, SPX2_O, SPX3_O, SPX1_E, SPX2_E, and SPX3_E may be interposed therebetween.

[0086] The sensing lines SL1, SL2, SL3, SL4, SL5, and SL6 may extend in the second direction (Y-axis direction) and may be arranged along the first direction (X-axis direction). The distance between the sensing lines SL1, SL2, SL3, SL4, SL5, and SL6 may be the same as the distance between the data lines D1, D2, D3, D4, D5, and D6, but is not limited thereto.

[0087] The data lines D1, D2, D3, D4, D5, and D6 and the sensing lines SL1, SL2, SL3, SL4, SL5, and SL6 may be disposed in pairs. One of the data lines D1, D2, D3, D4, D5, and D6 and one of the sensing lines SL1, SL2, SL3, SL4, SL5, and SL6 may be disposed in pairs between two adjacent sub-pixels SXP1_O, SPX2_O, SPX3_O, SPX1_E, SPX2_E, and SPX3_E.

[0088] Subpixels SXP1_O, SPX2_O, SPX3_O, SPX1_E, SPX2_E, and SPX3_E may be connected to the nearest data lines D1, D2, D3, D4, D5, and D6, respectively. The first subpixel SPX1_O of the first pixel PXL_ODD may be electrically connected to the first data line D1, and the first subpixel SPX1_E of the second pixel PXL_EVEN may be electrically connected to the second data line D2. The second subpixel SPX2_O of the first pixel PXL_ODD may be electrically connected to the third data line D3, and the second subpixel SPX2_E of the second pixel PXL_EVEN may be electrically connected to the fourth data line D4. The third subpixel SPX3_O of the first pixel PXL_ODD may be electrically connected to the fifth data line D5, and the third subpixel SPX3_E of the second pixel PXL_EVEN may be electrically connected to the sixth data line D6.

[0089] The data lines D1, D2, D3, D4, D5, and D6 electrically connected to the sub-pixels SXP1_O, SPX2_O, SPX3_O, SPX1_E, SPX2_E, and SPX3_E emitting light of the same color may be electrically connected to each other. For example, the first data line D1 and the second data line D2 may be electrically connected to each other through the first connection line CL1. The third data line D3 and the fourth data line D4 may be electrically connected to each other through the second connection line CL2. The fifth data line D5 and the sixth data line D6 may be electrically connected to each other through the third connection line CL3.

[0090] Since two sub-pixels SXP1_O, SPX2_O, SPX3_O, SPX1_E, SPX2_E and SPX3_E emitting light of the same color share the data lines D1, D2, D3, D4, D5 and D6, respectively, the number of channels of the driver providing signals to the data lines D1, D2, D3, D4, D5 and D6 and the overall load according to the number of channels can be reduced.

[0091] The first data line D1 may be disposed between the first subpixel SPX1_O and the second subpixel SPX2_O of the first pixel PXL_ODD. The second data line D2 may be disposed between the first subpixel SPX1_E and the second subpixel SPX2_E of the second pixel PXL_EVEN. The third data line D3 may be disposed between the second subpixel SPX2_O and the third subpixel SPX3_O of the first pixel PXL_ODD. The fourth data line D4 may be disposed between the second subpixel SPX2_E and the third subpixel SPX3_E of the second pixel PXL_EVEN. The fifth data line D5 may be disposed between the third subpixel SPX3_O of the first pixel PXL_ODD and the first subpixel SPX1_E of the second pixel PXL_EVEN. The sixth data line D6 may be disposed between the third subpixel SPX3_E of the second pixel PXL_EVEN and the first subpixel SPX1_O of the first pixel PXL_ODD.

[0092] The respective sub-pixels SXP1_O, SPX2_O, SPX3_O, SPX1_E, SPX2_E, and SPX3_E may be connected to the most adjacent sensing lines SL1, SL2, SL3, SL4, SL5, and SL6. The first sub-pixel SPX1_O of the first pixel PXL_ODD may be electrically connected to the first sensing line SL1. The second sub-pixel SPX2_O of the first pixel PXL_ODD may be electrically connected to the second sensing line SL2. The third sub-pixel SPX3_O of the first pixel PXL_ODD may be electrically connected to the third sensing line SL3. The first sub-pixel SPX1_E of the second pixel PXL_EVEN may be electrically connected to the fourth sensing line SL4. The second sub-pixel SPX2_E of the second pixel PXL_EVEN may be electrically connected to the fifth sensing line SL5. The third sub-pixel SPX3_E of the second pixel PXL_EVEN may be electrically connected to the sixth sensing line SL6.

[0093] The first sensing line SL1 may be disposed between the first subpixel SPX1_O and the second subpixel SPX2_O of the first pixel PXL_ODD. The second sensing line SL2 may be disposed between the second subpixel SPX2_O and the third subpixel SPX3_O of the first pixel PXL_ODD. The third sensing line SL3 may be disposed between the third subpixel SPX3_O of the first pixel PXL_ODD and the first subpixel SPX1_E of the second pixel PXL_EVEN. The fourth sensing line SL4 may be disposed between the first subpixel SPX1_E and the second subpixel SPX2_E of the second pixel PXL_EVEN. The fifth sensing line SL5 may be disposed between the second subpixel SPX2_E and the third subpixel SPX3_E of the second pixel PXL_EVEN. The sixth sensing line SL6 may be disposed between the third subpixel SPX3_E of the second pixel PXL_EVEN and the first subpixel SPX1_O of the first pixel PXL_ODD.

[0094] The sensing lines SL1 , SL2 , SL3 , SL4 , SL5 , and SL6 may be electrically connected to each other, but are not limited thereto.

[0095] Figure 6 and Figure 7 is a schematic plan view showing a first pixel and a second pixel according to an embodiment. Figure 6 , a schematic plan view of a first pixel PXL_ODD and a second pixel PXL_EVEN is shown based on a pixel circuit PXC (or a pixel circuit layer). Figure 7 , a schematic plan view of a first pixel PXL_ODD and a second pixel PXL_EVEN is shown based on a display element layer. Figure 8 is a schematic plan view showing a sub-pixel according to an embodiment. Figure 8, the sub-pixel SPX is briefly shown based on the light source unit LSU. For example, Figure 8 The sub-pixel SPX may be any one of the sub-pixels SPX1_O, SPX2_O, and SPX3_O of the first pixel PXL_ODD and / or the sub-pixels SPX1_E, SPX2_E, and SPX3_E of the second pixel PXL_EVEN, and the light source units LSU of the sub-pixels SPX may have the same or similar structures as each other. Figure 8 In the disclosure, a sub-pixel SPX may include Figure 4 Although the embodiment shown in FIG. 1 is an embodiment in which the light emitting element LD is arranged in four series stages, the number of series stages for each sub-pixel SPX may be variously changed according to the embodiment.

[0096] refer to Figures 6 to 8 , the first subpixel SPX1_O, the second subpixel SPX2_O and the third subpixel SPX3_O of the first pixel PXL_ODD may have the same or similar pixel structure (or circuit structure) to each other. The first subpixel SPX1_E, the second subpixel SPX2_E and the third subpixel SPX3_E of the second pixel PXL_EVEN may have the same or similar pixel structure (or circuit structure) to each other. Each of the first subpixel SPX1_O, the second subpixel SPX2_O and the third subpixel SPX3_O of the first pixel PXL_ODD and the first subpixel SPX1_E, the second subpixel SPX2_E and the third subpixel SPX3_E of the second pixel PXL_EVEN may have a mutually inverted pixel structure (or circuit structure) in the second direction (Y-axis direction). Therefore, the subpixel SPX based on the first subpixel SPX1_O of the first pixel PXL_ODD and the first subpixel SPX1_E of the second pixel PXL_EVEN describes the common configuration of the subpixel SPX, and the overlapping description may be omitted.

[0097] The first vertical power line PL1_V, the sensing lines SL1, SL2, SL3, SL4, SL5 and SL6, the data lines D1, D2, D3, D4, D5 and D6, and the second vertical power line PL2_V may extend in the second direction (Y-axis direction) and may be arranged along the first direction (X-axis direction). The first vertical power line PL1_V, the sensing lines SL1, SL2, SL3, SL4, SL5 and SL6, the data lines D1, D2, D3, D4, D5 and D6, and / or the second vertical power line PL2_V may have a partially bent shape, but are not limited thereto.

[0098] In the first pixel PXL_ODD, the first vertical power line PL1_V and the first sensing line SL1 may be located in the left direction relative to the first capacitor electrode CE1_O of the first subpixel SPX1_O, and the first data line D1 and the second vertical power line PL2_V may be located in the right direction relative to the first capacitor electrode CE1_O of the first subpixel SPX1_O.

[0099] The first vertical power line PL1_V, the sensing lines SL1, SL2, SL3, SL4, SL5 and SL6, the data lines D1, D2, D3, D4, D5 and D6, the second vertical power line PL2_V and the first capacitor electrode CE1_O may include the same material or similar materials and may be disposed on the same layer through the same process.

[0100] The second horizontal power line PL2_H, the first gate line SC_ODD, the second gate line SC_EVEN, and the first horizontal power line PL1_H may extend in the first direction (X-axis direction), and may be arranged in the second direction (Y-axis direction). The second horizontal power line PL2_H and the first gate line SC_ODD may be located in an upper direction relative to the second capacitor electrode CE2_O of the first subpixel SPX1_O, and the second gate line SC_EVEN and the first horizontal power line PL1_H may be located in a lower direction relative to the second capacitor electrode CE2_O of the first subpixel SPX1_O.

[0101] The second horizontal power line PL2_H, the first gate line SC_ODD, the second gate line SC_EVEN, the first horizontal power line PL1_H, and the second capacitor electrode CE2_O may include the same material or similar materials and may be disposed on the same layer through the same process.

[0102] The first capacitor electrode CE1_O and the second capacitor electrode CE2_O may overlap each other and form a storage capacitor Cst_O (refer to Figure 4 Cst).

[0103] The second horizontal power line PL2_H may cross the second vertical power line PL2_V and may be connected to the second vertical power line PL2_V through a contact hole in the crossing region. The second horizontal power line PL2_H and the second vertical power line PL2_V may completely form a mesh structure and may form a second power line (refer to Figure 4 PL2).

[0104] Similarly, the first horizontal power line PL1_H may cross the first vertical power line PL1_V and may be connected to the first vertical power line PL1_V through a contact hole in the crossing region. The first horizontal power line PL1_H and the first vertical power line PL1_V may completely form a mesh structure and may form a first power line (refer to Figure 4 The positions of the first horizontal power line PL1_H and the second horizontal power line PL2_H may be changed with each other.

[0105] The first transistor T1_O may be located in a downward direction relative to the first capacitor electrode CE1_O and the second capacitor electrode CE2_O, and may partially overlap the first capacitor electrode CE1_O and the second capacitor electrode CE2_O. The central portion of the semiconductor pattern overlapping the first capacitor electrode CE1_O and the second capacitor electrode CE2_O may form a channel of the first transistor T1_O, the second capacitor electrode CE2_O may form a gate of the first transistor T1_O, and the first capacitor electrode CE1_O may form a back gate electrode of the first transistor T1_O. The first portion of the semiconductor pattern of the first transistor T1_O may be electrically connected to the protruding portion of the first vertical power line PL1_V through the second bridge electrode BRP2_O. The first portion of the semiconductor pattern of the first transistor T1_O or the second bridge electrode BRP2_O may be the first electrode of the first transistor T1_O. The second portion of the semiconductor pattern of the first transistor T1_O may be electrically connected to the first capacitor electrode CE1_O at the opening portion of the second capacitor electrode CE2_O. The second portion of the semiconductor pattern of the first transistor T1_O may be the second electrode of the first transistor T1_O.

[0106] The second transistor T2_O may be located in an upper direction relative to the first capacitor electrode CE1_O and the second capacitor electrode CE2_O, and may partially overlap the first gate line SC_ODD. A central portion of the semiconductor pattern overlapping the first gate line SC_ODD may form a channel of the second transistor T2_O, and the first gate line SC_ODD may form a gate electrode of the second transistor T2_O. The first gate line SC_ODD may be used as a scan line of the first subpixel SPX1_O of the first pixel PXL_ODD (reference Figure 4Si in). The first portion of the semiconductor pattern of the second transistor T2_O may be electrically connected to the first data line D1 through the third bridge electrode BRP3_O. The first portion of the semiconductor pattern of the second transistor T2_O or the third bridge electrode BRP3_O may be the first electrode of the second transistor T2_O. The second portion of the semiconductor pattern of the second transistor T2_O may be electrically connected to the second capacitor electrode CE2_O through the fourth bridge electrode BRP4_O. The second portion of the semiconductor pattern of the second transistor T2_O or the fourth bridge electrode BRP4_O may be the second electrode of the second transistor T2_O.

[0107] The third transistor T3_O may be located in an upper direction relative to the first capacitor electrode CE1_O and the second capacitor electrode CE2_O, and may partially overlap the first gate line SC_ODD. A central portion of the semiconductor pattern overlapping the first gate line SC_ODD may form a channel of the third transistor T3_O, and the first gate line SC_ODD may form a gate electrode of the third transistor T3_O. The first gate line SC_ODD may be used as a sensing control line of the first subpixel SPX1_O of the first pixel PXL_ODD (reference Figure 4 The first portion of the semiconductor pattern of the third transistor T3_O may be electrically connected to the first sensing line SL1 through the fifth bridge electrode BRP5_O. The first portion of the semiconductor pattern of the third transistor T3_O or the fifth bridge electrode BRP5_O may be the first electrode of the third transistor T3_O. The second portion of the semiconductor pattern of the third transistor T3_O may be electrically connected to the first capacitor electrode CE1_O through the sixth bridge electrode BRP6_O. The second portion of the semiconductor pattern of the third transistor T3_O or the sixth bridge electrode BRP6_O may be the second electrode of the third transistor T3_O.

[0108] In the second pixel PXL_EVEN, the first vertical power line PL1_V and the fourth sensing line SL4 may be located in the left direction relative to the first capacitor electrode CE1_E of the first subpixel SPX1_E, and the second data line D2 and the second vertical power line PL2_V may be located in the right direction relative to the first capacitor electrode CE1_E of the first subpixel SPX1_E.

[0109] The second horizontal power line PL2_H and the first gate line SC_ODD may be located in an upper direction with respect to the second capacitor electrode CE2_E of the first subpixel SPX1_E, and the second gate line SC_EVEN and the first horizontal power line PL1_H may be disposed in a lower direction with respect to the second capacitor electrode CE2_E of the first subpixel SPX1_E.

[0110] The first capacitor electrode CE1_E and the second capacitor electrode CE2_E may overlap each other and form a storage capacitor Cst_E.

[0111] The first transistor T1_E may be located in an upper direction relative to the first capacitor electrode CE1_E and the second capacitor electrode CE2_E, and may partially overlap with the first capacitor electrode CE1_E and the second capacitor electrode CE2_E. The central portion of the semiconductor pattern overlapping with the first capacitor electrode CE1_E and the second capacitor electrode CE2_E may form a channel of the first transistor T1_E, the second capacitor electrode CE2_E forms a gate of the first transistor T1_E, and the first capacitor electrode CE1_E may form a back gate electrode of the first transistor T1_E. The first portion of the semiconductor pattern of the first transistor T1_E may be electrically connected to the protruding portion of the first vertical power line PL1_V through the second bridge electrode BRP2_E. The first portion of the semiconductor pattern of the first transistor T1_E or the second bridge electrode BRP2_E may be the first electrode of the first transistor T1_E. The second portion of the semiconductor pattern of the first transistor T1_E may be electrically connected to the first capacitor electrode CE1_E at the opening portion of the second capacitor electrode CE2_E. The second portion of the semiconductor pattern of the first transistor T1_E may be the second electrode of the first transistor T1_E.

[0112] The second transistor T2_E may be located in a downward direction relative to the first capacitor electrode CE1_E and the second capacitor electrode CE2_E, and may partially overlap the second gate line SC_EVEN. A central portion of the semiconductor pattern overlapping the second gate line SC_EVEN may form a channel of the second transistor T2_E, and the second gate line SC_EVEN may form a gate electrode of the second transistor T2_E. The second gate line SC_EVEN may be used as a scan line of the first subpixel SPX1_E of the second pixel PXL_EVEN (reference Figure 4 Si). The first portion of the semiconductor pattern of the second transistor T2_E may be electrically connected to the second data line D2 through the third bridge electrode BRP3_E. The first portion of the semiconductor pattern of the second transistor T2_E or the third bridge electrode BRP3_E may be the first electrode of the second transistor T2_E. The second portion of the semiconductor pattern of the second transistor T2_E may be electrically connected to the second capacitor electrode CE2_E through the fourth bridge electrode BRP4_E. The second portion of the semiconductor pattern of the second transistor T2_E or the fourth bridge electrode BRP4_E may be the second electrode of the second transistor T2_E.

[0113] The third transistor T3_E may be located in a downward direction relative to the first capacitor electrode CE1_E and the second capacitor electrode CE2_E, and may partially overlap the second gate line SC_EVEN. A central portion of the semiconductor pattern overlapping the second gate line SC_EVEN may form a channel of the third transistor T3_E, and the second gate line SC_EVEN may form a gate electrode of the third transistor T3_E. The second gate line SC_EVEN may be used as a sensing control line of the first subpixel SPX1_E of the second pixel PXL_EVEN (reference Figure 4 The first portion of the semiconductor pattern of the third transistor T3_E may be electrically connected to the fourth sensing line SL4 through the fifth bridge electrode BRP5_E. The first portion of the semiconductor pattern of the third transistor T3_E or the fifth bridge electrode BRP5_E may be the first electrode of the third transistor T3_E. The second portion of the semiconductor pattern of the third transistor T3_E may be electrically connected to the first capacitor electrode CE1_E through the sixth bridge electrode BRP6_E. The second portion of the semiconductor pattern of the third transistor T3_E or the sixth bridge electrode BRP6_E may be the second electrode of the third transistor T3_E.

[0114] The sub-pixels SPX1_O, SPX2_O, and SPX3_O of the first pixel PXL_ODD and the sub-pixels SPX1_E, SPX2_E, and SPX3_E of the second pixel PXL_EVEN may include the same light source unit LSU.

[0115] The first alignment electrode ELT1, the second alignment electrode ELT2, and the third alignment electrode ELT3 may extend in the second direction (Y-axis direction) and may be arranged along the first direction (X-axis direction). The first alignment electrode ELT1, the second alignment electrode ELT2, and the third alignment electrode ELT3 adjacent to each other may receive different signals during the alignment step of the light emitting element LD. For example, in the case where the first alignment electrode ELT1, the second alignment electrode ELT2, and the third alignment electrode ELT3 are sequentially arranged in the first direction (X-axis direction), the first alignment electrode ELT1 may receive a first alignment signal (or a first alignment voltage), the second alignment electrode ELT2 may receive a second alignment signal (or a second alignment voltage), and the third alignment electrode ELT3 may receive a first alignment signal (or a first alignment voltage), but the present disclosure is not limited thereto. After the light emitting element LD is aligned, the first alignment electrode ELT1, the second alignment electrode ELT2, and the third alignment electrode ELT3 may be used as driving electrodes for driving the light emitting element LD.

[0116] The first, second and third alignment electrodes ELT1, ELT2 and ELT3 may include the same material or similar material as the bridging electrodes BRP1_O, BRP1_E, BRP2_O, BRP2_E, BRP3_O, BRP3_E, BRP4_O, BRP4_E, BRP5_O, BRP5_E, BRP6_O and BRP6_E and may be disposed on the same layer by the same process.

[0117] According to an embodiment, the sub-pixel SPX may further include a bank pattern (refer to Figure 8 The bank patterns WL may extend along the second direction (Y-axis direction) and may be spaced apart from each other along the first direction (X-axis direction). The bank patterns WL may overlap the first alignment electrode ELT1, the second alignment electrode ELT2, and the third alignment electrode ELT3.

[0118] According to an embodiment, the bank pattern WL may include a reflective material. Since light emitted from the light emitting element LD is reflected by the bank pattern WL and emitted in an image display direction of the display device, light output efficiency of the display panel PNL may be improved.

[0119] The light emitting element LD may be disposed between the first alignment electrode ELT1, the second alignment electrode ELT2, and the third alignment electrode ELT3. The first light emitting element LD1 may be aligned between the first alignment electrode ELT1 and the second alignment electrode ELT2. For example, the first light emitting element LD1 may be aligned in a first region (e.g., an upper region) of the first alignment electrode ELT1 and the second alignment electrode ELT2. The first light emitting element LD1 may be electrically connected to the first electrode CNE1 and the first intermediate electrode IET1. A first end of the first light emitting element LD1 may be electrically connected to the first electrode CNE1, and a second end of the first light emitting element LD1 may be electrically connected to the first intermediate electrode IET1.

[0120] The second light emitting element LD2 may be aligned between the first alignment electrode ELT1 and the second alignment electrode ELT2. For example, the second light emitting element LD2 may be aligned in a second region (e.g., a lower region) of the first alignment electrode ELT1 and the second alignment electrode ELT2. The second light emitting element LD2 may be electrically connected to the first intermediate electrode IET1 and the second intermediate electrode IET2. A first end of the second light emitting element LD2 may be electrically connected to the first intermediate electrode IET1, and a second end of the second light emitting element LD2 may be electrically connected to the second intermediate electrode IET2.

[0121] The third light emitting element LD3 may be aligned between the second alignment electrode ELT2 and the third alignment electrode ELT3. For example, the third light emitting element LD3 may be aligned in the second region (e.g., the lower region) of the second alignment electrode ELT2 and the third alignment electrode ELT3. The third light emitting element LD3 may be electrically connected to the second intermediate electrode IET2 and the third intermediate electrode IET3. A first end of the third light emitting element LD3 may be electrically connected to the second intermediate electrode IET2, and a second end of the third light emitting element LD3 may be electrically connected to the third intermediate electrode IET3.

[0122] The fourth light emitting element LD4 may be aligned between the second alignment electrode ELT2 and the third alignment electrode ELT3. For example, the fourth light emitting element LD4 may be aligned in a first region (e.g., an upper region) of the second alignment electrode ELT2 and the third alignment electrode ELT3. The fourth light emitting element LD4 may be electrically connected to the third intermediate electrode IET3 and the second electrode CNE2. A first end of the fourth light emitting element LD4 may be electrically connected to the third intermediate electrode IET3, and a second end of the fourth light emitting element LD4 may be electrically connected to the second electrode CNE2.

[0123] The first electrode CNE1 and the second electrode CNE2 and the first intermediate electrode IET1, the second intermediate electrode IET2, and the third intermediate electrode IET3 may include the same material or similar materials and may be provided on the same layer by the same process. In the case where the first electrode CNE1 and the second electrode CNE2 and the first intermediate electrode IET1, the second intermediate electrode IET2, and the third intermediate electrode IET3 are formed by the same process, the number of masks may be reduced and the manufacturing process may be simplified. However, the present disclosure is not limited thereto, and according to an embodiment, the first electrode CNE1 and the second electrode CNE2 and the first intermediate electrode IET1, the second intermediate electrode IET2, and the third intermediate electrode IET3 may be formed of a plurality of conductive layers.

[0124] In the above-described method, the light emitting element LD aligned between the first electrode CNE1 and the second electrode CNE2 and the first intermediate electrode IET1, the second intermediate electrode IET2, and the third intermediate electrode IET3 may be connected in a desired shape. For example, the first light emitting element LD1, the second light emitting element LD2, the third light emitting element LD3, and the fourth light emitting element LD4 may be sequentially connected in series by using the first electrode CNE1 and the second electrode CNE2 and the first intermediate electrode IET1, the second intermediate electrode IET2, and the third intermediate electrode IET3.

[0125] The light emitting element LD can be electrically connected to the pixel circuit (refer to Figure 4 PXC), and can be electrically connected to the second power line (reference Figure 4 PL2).

[0126] In an embodiment, the first electrode CNE1_O of the first pixel PXL_ODD and the first electrode CNE1_E of the second pixel PXL_EVEN may be electrically connected to the pixel circuit PXC in different areas A1 and A2. For example, in the first pixel PXL_ODD, the first electrode CNE1_O of the first subpixel SPX1_O may be electrically connected to the pixel circuit PXC in the first area A1. For example, the first electrode CNE1_O of the first subpixel SPX1_O may be electrically connected to the pixel circuit PXC (or the first transistor T1_O) through the first bridge electrode BRP1_O in the first area A1. The first area A1 may be located at one side or on the side of the pixel circuit PXC (or the storage capacitors Cst_O and Cst_E), the first transistors T1_O and T1_E, the second transistors T2_O and T2_E, and / or the third transistors T3_O and T3_E. For example, the first area A1 may be located on lower sides of the pixel circuit PXC (or the storage capacitors Cst_O and Cst_E), the first transistors T1_O and T1_E, the second transistors T2_O and T2_E, and / or the third transistors T3_O and T3_E.

[0127] In the second pixel PXL_EVEN, the first electrode CNE1_E of the first subpixel SPX1_E may be electrically connected to the pixel circuit PXC in the second area A2. For example, the first electrode CNE1_E of the first subpixel SPX1_E may be electrically connected to the pixel circuit PXC (or the first transistor T1_E) through the first bridge electrode BRP1_E in the second area A2. The second area A2 may be located on the other side of the pixel circuit PXC (or the storage capacitors Cst_O and Cst_E), the first transistors T1_O and T1_E, the second transistors T2_O and T2_E, and / or the third transistors T3_O and T3_E. For example, the second area A2 may be located on the upper side of the pixel circuit PXC (or the storage capacitors Cst_O and Cst_E), the first transistors T1_O and T1_E, the second transistors T2_O and T2_E, and / or the third transistors T3_O and T3_E.

[0128] The first electrode CNE1_O of the first subpixel SPX1_O in the first pixel PXL_ODD may be formed at a position that is the same as or similar to that of the first electrode CNE1_E of the first subpixel SPX1_E in the second pixel PXL_EVEN. For example, the first electrode CNE1_O of the first subpixel SPX1_O in the first pixel PXL_ODD may have a shape that is the same as or similar to that of the first electrode CNE1_E of the first subpixel SPX1_E in the second pixel PXL_EVEN. The area of ​​the first electrode CNE1_O of the first subpixel SPX1_O in the first pixel PXL_ODD may be the same as or similar to that of the first electrode CNE1_E of the first subpixel SPX1_E in the second pixel PXL_EVEN. For example, the first electrode CNE1_O of the first subpixel SPX1_O in the first pixel PXL_ODD may include a first extension portion CNE1_O' overlapping the second area A2. The first extension portion CNE1_O' may extend from the first electrode CNE1_O of the first subpixel SPX1_O to the second area A2. The first electrode CNE1_E of the first subpixel SPX1_E in the second pixel PXL_EVEN may include a second extension portion CNE1_E' overlapping the first area A1. The second extension portion CNE1_E' may extend from the first electrode CNE1_E of the first subpixel SPX1_E to the first area A1. Therefore, even if the first electrode CNE1_O of the first subpixel SPX1_O in the first pixel PXL_ODD and the first electrode CNE1_E of the first subpixel SPX1_E in the second pixel PXL_EVEN are electrically connected to the pixel circuit PXC in different areas A1 and A2, the first electrodes CNE1_O and CNE1_E may be formed at the same or similar positions to each other in each of the pixels PXL_ODD and PXL_EVEN by including the extension portions CNE1_O' and CNE1_E' extending to the remaining portions of the areas A1 and A2. Therefore, a capacitance deviation with a lower electrode (eg, an electrode included in the pixel circuit layer PCL) according to a difference in electrode positions (or shapes) of the first pixel PXL_ODD and the second pixel PXL_EVEN may be minimized.

[0129] Fig. 9 is a schematic cross-sectional view showing a sub-pixel according to an embodiment. Fig. 9 In FIG. 1 , the sub-pixel SPX is shown based on the first light emitting element LD1 .

[0130] refer to Fig. 9 , the sub-pixel SPX may include a pixel circuit layer PCL and a display element layer DPL disposed on a substrate SUB. For ease of description, the pixel circuit layer PCL is described first, and then the display element layer DPL is described.

[0131] The pixel circuit layer PCL may include a first conductive layer (or a first metal layer), a first transistor T1, and a second conductive layer (or a second metal layer).

[0132] The first conductive layer may be disposed on the substrate SUB and may include a back gate electrode BGE and a second vertical power line PL2_V. The first conductive layer may be formed as a single layer using a material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and alloys thereof, alone or in combination, or may be formed as a double-layer structure or a multi-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag) as a low resistance material to reduce line resistance.

[0133] The buffer layer BFL may be disposed and / or formed on the substrate SUB and the first conductive layer, and may prevent impurities from diffusing into the first transistor T1. The buffer layer BFL may be an inorganic insulating layer including an inorganic material. The buffer layer BFL may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x ). The buffer layer BFL may be set as a single layer, but may be set as a multilayer of at least two layers or more. In the case where the buffer layer BFL is set as a multilayer, each layer may be formed of the same material, a similar material, or a different material. The buffer layer BFL may be omitted depending on the material of the substrate SUB, process conditions, etc.

[0134] The semiconductor pattern ACT of the first transistor T1 may be disposed and / or formed on the buffer layer BFL. The semiconductor pattern ACT may include a first contact region (or a first transistor electrode TE1), a second contact region (or a second transistor electrode TE2), and a channel region between the first contact region and the second contact region. The first contact region (or the first transistor electrode TE1) may contact the first bridge electrode BRP1. The channel region may overlap with the gate electrode GE of the first transistor T1. The semiconductor pattern ACT may be a semiconductor pattern formed of amorphous silicon, polycrystalline silicon, low temperature polycrystalline silicon, an oxide semiconductor, or an organic semiconductor. The channel region is, for example, a semiconductor pattern not doped with impurities, and may be an intrinsic semiconductor. The first contact region and the second contact region may be semiconductor patterns doped with impurities.

[0135] The gate insulating layer GI may be disposed on the semiconductor pattern ACT. The gate insulating layer GI may be an inorganic insulating layer including an inorganic material. For example, the gate insulating layer GI may include silicon nitride (SiN x ), silicon oxide (SiOx ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x ) at least one of. However, the material of the gate insulating layer GI is not limited to the above-described embodiments, and various materials that impart insulation to the gate insulating layer GI may be applied according to the embodiments. For example, the gate insulating layer GI may be formed of an organic insulating layer including an organic material. The gate insulating layer GI may be provided as a single layer, but may also be provided as a multilayer of at least two or more layers.

[0136] The second conductive layer may be disposed on the gate insulating layer GI and may include a gate electrode GE of the first transistor T1. The gate electrode GE may overlap with a channel region of the semiconductor pattern ACT. The second conductive layer may include the same material or a similar material as the first conductive layer, or may include one or more materials selected from materials that are configuration materials of the first conductive layer.

[0137] The interlayer insulating layer ILD may be disposed on the second conductive layer. The interlayer insulating layer ILD may be disposed in the form of an organic insulating layer, an inorganic insulating layer, or an organic insulating layer disposed on an inorganic insulating layer. The inorganic insulating layer may include, for example, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x The organic insulating layer may include, for example, at least one of polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin.

[0138] The via layer VIA may be disposed on the interlayer insulating layer ILD. The via layer VIA may be formed of an organic insulating layer. For example, the via layer VIA may include at least one of polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin, but is not limited thereto.

[0139] The display element layer DPL may be disposed on the via layer VIA.

[0140] The display element layer DPL may include first and second alignment electrodes ELT1 and ELT2 , a first bridge electrode BRP1 , a first insulating layer INS1 , a bank pattern WL, a first light emitting element LD1 (or light emitting element LD), a first electrode CNE1 , and a first intermediate electrode IET1 .

[0141] The first alignment electrode ELT1 and the second alignment electrode ELT2 may be disposed and / or formed on the via layer VIA.

[0142] The first alignment electrode ELT1 and the second alignment electrode ELT2 may be formed of a material having a constant reflectivity to allow light emitted from the light emitting element LD to travel in the image display direction of the display device. The first alignment electrode ELT1 and the second alignment electrode ELT2 may be formed of a conductive material having a constant reflectivity. For example, the first alignment electrode ELT1 and the second alignment electrode ELT2 may include a metal such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti) and alloys thereof as an opaque metal. According to an embodiment, the first alignment electrode ELT1 and the second alignment electrode ELT2 may include a transparent conductive material. Within the spirit and scope of the present disclosure, the transparent conductive material may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), conductive polymers (such as poly (3,4-ethylenedioxythiophene) (PEDOT)), etc.

[0143] In the case where the first alignment electrode ELT1 and the second alignment electrode ELT2 include a transparent conductive material, a separate conductive layer formed of an opaque metal for reflecting light emitted from the light emitting element LD in the image display direction of the display device may be added. However, the materials of the first alignment electrode ELT1 and the second alignment electrode ELT2 are not limited to the materials described above.

[0144] The first alignment electrode ELT1 and the second alignment electrode ELT2 may be provided and / or formed as a single layer, but are not limited thereto. According to an embodiment, the first alignment electrode ELT1 and the second alignment electrode ELT2 may be provided and / or formed as a multilayer in which at least two materials among metals, alloys, conductive oxides, and conductive polymers may be stacked on each other. The first alignment electrode ELT1 and the second alignment electrode ELT2 may be formed as a multilayer of at least two or more layers to minimize distortion due to signal delay when transmitting a signal (or voltage) to the light emitting element LD. For example, the first alignment electrode ELT1 and the second alignment electrode ELT2 may be formed as a plurality of layers sequentially stacked on each other in the order of indium tin oxide (ITO) / silver (Ag) / indium tin oxide (ITO).

[0145] The first alignment electrode ELT1 may be electrically connected to the second conductive layer (or gate electrode GE) through a contact hole passing through the via layer VIA and the interlayer insulating layer ILD. The second alignment electrode ELT2 may be electrically connected to the first conductive layer (or second vertical power line PL2_V) through a contact hole passing through the via layer VIA and the interlayer insulating layer ILD.

[0146] The first bridge electrode BRP1 may be electrically connected to the first transistor T1 through a contact hole passing through the via layer VIA and the interlayer insulating layer ILD. For example, the first bridge electrode BRP1 may be electrically connected to the back gate electrode BGE through a first contact hole passing through the via layer VIA and the interlayer insulating layer ILD, and may be electrically connected to the semiconductor pattern ACT (or the first transistor electrode TE1) through a second contact hole passing through the via layer VIA and the interlayer insulating layer ILD.

[0147] The first bridge electrode BRP1 may include the same material or a similar material as the first and second alignment electrodes ELT1 and ELT2 , and may be disposed on the same layer through the same process as the first and second alignment electrodes ELT1 and ELT2 .

[0148] The first insulating layer INS1 may be disposed and / or formed on the first alignment electrode ELT1, the second alignment electrode ELT2 and the first bridge electrode BRP1. The first insulating layer INS1 may include an inorganic insulating layer formed of an inorganic material or an organic insulating layer formed of an organic material. The first insulating layer INS1 may be formed of an inorganic insulating layer that is beneficial for protecting the light emitting element LD from the pixel circuit layer PCL. For example, the first insulating layer INS1 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x ), but is not limited thereto. According to an embodiment, the first insulating layer INS1 may be formed of an organic insulating layer that facilitates planarizing a support surface of the light emitting element LD.

[0149] The bank patterns WL may be disposed and / or formed on the first insulating layer INS1. The bank patterns WL may be spaced apart from each other. Fig. 9 The case where the bank pattern WL is disposed on the first insulating layer INS1 is shown, but the position of the bank pattern WL may be variously changed. For example, the bank pattern WL may be disposed between the via layer VIA and the first and second alignment electrodes ELT1 and ELT2.

[0150] The embankment pattern WL may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. According to an embodiment, the embankment pattern WL may include a single-layer organic insulating layer and / or a single-layer inorganic insulating layer, but the present disclosure is not limited thereto. According to an embodiment, the embankment pattern WL may be provided in the form of a multilayer in which at least one organic insulating layer and at least one inorganic insulating layer may be stacked on each other. However, the material of the embankment pattern WL is not limited to the above-described embodiments, and according to an embodiment, the embankment pattern WL may include a conductive material.

[0151] The embankment pattern WL may have a cross section of a trapezoidal shape whose width becomes narrower toward the upper portion in the third direction (Z-axis direction), but is not limited thereto. According to an embodiment, the embankment pattern WL may include a curved surface having a cross section of a semi-elliptical shape, a semicircular shape (or a hemispherical shape), etc. whose width becomes narrower toward the upper portion. When observed in a cross section, the shape of the embankment pattern WL is not limited to the above-described embodiment, and may be variously changed within a range capable of improving the efficiency of light emitted from each of the light emitting elements LD. The embankment pattern WL may have the same height (or thickness) in the third direction (Z-axis direction).

[0152] The first light emitting element LD1 (or the light emitting element LD) may be aligned between the first alignment electrode ELT1 and the second alignment electrode ELT2. The light emitting element LD may be disposed on the first insulating layer INS1 between the bank patterns WL.

[0153] The light emitting element LD may be an ultra-small size (for example, a size as small as nanometer to micrometer) light emitting diode using a material of an inorganic crystal structure. Fig.12 and Fig.13 A detailed description of the light emitting element LD is described.

[0154] The number of the light emitting elements LD provided in the sub-pixel SPX may be at least two to several tens. According to embodiments, the number of the light emitting elements LD provided in the sub-pixel SPX may be variously changed.

[0155] The light emitting element LD may emit any one of colored light and / or white light. In an embodiment, the light emitting element LD may emit blue light of a short wavelength band, but is not limited thereto.

[0156] The second insulating layer INS2 (or the second insulating pattern) may be disposed and / or formed on the light emitting element LD. The second insulating layer INS2 may be disposed and / or formed on the light emitting element LD to partially cover the peripheral surface (or surface) of the light emitting element LD. The active layer of the light emitting element LD may not contact the external conductive material through the second insulating layer INS2. The second insulating layer INS2 may cover only part of the peripheral surface (or surface) of the light emitting element LD to expose both ends of the light emitting element LD to the outside.

[0157] The second insulating layer INS2 may be a single layer or a multilayer, and may include an inorganic insulating layer including at least one inorganic material or an organic insulating layer including at least one organic material. The second insulating layer INS2 may be formed of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material according to design conditions of a display device to which the light emitting element LD is applied, etc. After the alignment of the light emitting element LD is completed, the light emitting element LD may be prevented from being separated from the aligned position by forming the second insulating layer INS2 on the light emitting element LD.

[0158] The first electrode CNE1 may be disposed on the first alignment electrode ELT1. The first electrode CNE1 may be disposed and / or formed on a first end of the first light emitting element LD1 and may be electrically connected to the first end of the first light emitting element LD1.

[0159] The first electrode CNE1 may be disposed on the first bridge electrode BRP1 and may be electrically connected to the first bridge electrode BRP1 through a contact hole passing through the first insulating layer INS1. Thus, the first electrode CNE1 may be electrically connected to the pixel circuit layer PCL (or the first transistor T1) through the first bridge electrode BRP1.

[0160] According to an embodiment, in the case where an opening exposing the first alignment electrode ELT1 is formed in the first insulating layer INS1 , the first electrode CNE1 may make contact with the first alignment electrode ELT1 through the opening to be electrically connected to the first alignment electrode ELT1 .

[0161] The first intermediate electrode IET1 may be disposed on the second alignment electrode ELT2. The first intermediate electrode IET1 may be disposed and / or formed on the second end of the first light emitting element LD1 and may be electrically connected to the second end of the first light emitting element LD1.

[0162] In order to allow light emitted from the light emitting element LD to travel in the image display direction of the display device, the first electrode CNE1 and the first intermediate electrode IET1 may be formed of various transparent conductive materials. The first electrode CNE1 and the first intermediate electrode IET1 may be transparent or translucent to satisfy the transmittance (or transmissivity). For example, the first electrode CNE1 and the first intermediate electrode IET1 may be transparently formed to have a transmittance of about 80% or more or a transmittance of about 90% or more.

[0163] The first electrode CNE1 and the first intermediate electrode IET1 may be spaced apart from each other. For example, the first electrode CNE1 and the first intermediate electrode IET1 may be spaced apart from each other, and the second insulating layer INS2 is interposed therebetween. The first electrode CNE1 and the first intermediate electrode IET1 may be formed on the same layer by the same process, but are not limited thereto. For example, the first electrode CNE1 and the first intermediate electrode IET1 may be disposed on different layers and formed by different processes.

[0164] According to an embodiment, the display element layer DPL may further include an optical layer. For example, the display element layer DPL may further include a color conversion layer including color conversion particles that convert light emitted from the light emitting element LD into light of a specific color or a given color. The display element layer DPL may further include a color filter layer that transmits only light of a specific wavelength band.

[0165] Fig.10 and Fig.11 is a schematic cross-sectional view showing a pixel according to an embodiment. Fig.10 and Fig.11 The individual configurations of the pixel circuit layer PCL and the display element layer DPL are briefly shown in FIG.

[0166] refer to Fig.10 , the light emitting element LD disposed in each of the sub-pixels SPX1, SPX2, and SPX3 may emit light of the same color. For example, the sub-pixels SPX1, SPX2, and SPX3 may include a light emitting element LD that emits light of a third color (e.g., blue light). The color conversion layer CCL and / or the color filter layer CFL may be disposed in the sub-pixels SPX1, SPX2, and SPX3 to display a full-color image. However, the present disclosure is not limited thereto, and the sub-pixels SPX1, SPX2, and SPX3 may include light emitting elements LD that emit light of different colors.

[0167] like Fig.10 As shown in , the color conversion layer CCL may be disposed on the same layer as the display element layer DPL. For example, the color conversion layer CCL may be disposed between the banks BNK.

[0168] The bank BNK may be located in the non-emission area NEA of the sub-pixels SPX1, SPX2, and SPX3. The bank BNK may be formed between the sub-pixels SPX1, SPX2, and SPX3 to surround each emission area EMA. The bank BNK may include an opening overlapping the emission area EMA of each of the sub-pixels SPX1, SPX2, and SPX3. The bank BNK may serve as a dam structure that prevents a solution for forming the color conversion layer CCL from flowing into the emission area EMA of adjacent sub-pixels SPX1, SPX2, and SPX3 or controls a constant amount of solution to be provided to each emission area EMA.

[0169] The bank BNK may include an organic material or an inorganic material, and according to an embodiment, the bank BNK may include a black matrix material (or a light blocking material).

[0170] The color conversion layer CCL may include a first color conversion layer WCP1, a second color conversion layer WCP2, a light transmitting layer LTP, and a first capping layer CAP1. WCP1 and WCP2 may be collectively referred to as a color conversion layer WCP.

[0171] The first color conversion layer WCP1 may be disposed to overlap with the emission area EMA of the first sub-pixel SPX1. The second color conversion layer WCP2 may be disposed to overlap with the emission area EMA of the second sub-pixel SPX2. The light transmission layer LTP may be disposed to overlap with the emission area EMA of the third sub-pixel SPX3. Each of the first color conversion layer WCP1, the second color conversion layer WCP2, and the light transmission layer LTP may be disposed in an opening of the bank BNK overlapping with the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3.

[0172] In an embodiment, the first color conversion layer WCP1 may include first color conversion particles that convert light of a third color emitted from the light emitting element LD into light of a first color. For example, when the light emitting element LD is a blue light emitting element that emits blue light and the first sub-pixel SPX1 is a red pixel, the first color conversion layer WCP1 may include first quantum dots that convert blue light emitted from the blue light emitting element into red light.

[0173] For example, the first color conversion layer WCP1 may include first quantum dots dispersed in a matrix material such as a base resin. The first quantum dots may absorb blue light and convert the wavelength according to energy conversion to emit red light. In the case where the first sub-pixel SPX1 is a pixel of another color, the first color conversion layer WCP1 may include first quantum dots corresponding to the color of the first sub-pixel SPX1.

[0174] In an embodiment, the second color conversion layer WCP2 may include second color conversion particles that convert light of a third color emitted from the light emitting element LD into light of a second color. For example, when the light emitting element LD is a blue light emitting element that emits blue light and the second sub-pixel SPX2 is a green pixel, the second color conversion layer WCP2 may include second quantum dots that convert blue light emitted from the blue light emitting element into green light.

[0175] For example, the second color conversion layer WCP2 may include second quantum dots dispersed in a matrix material such as a base resin. The second quantum dots may absorb blue light and convert the wavelength according to energy conversion to emit green light.

[0176] The first quantum dot and the second quantum dot may have the shape of spherical, pyramidal, multi-armed or cubic nanoparticles, nanotubes, nanowires, nanofibers, nanoplate particles, etc., but are not limited thereto, and the shapes of the first quantum dot and the second quantum dot may be variously changed.

[0177] In an embodiment, the absorption coefficient of the first quantum dot and the second quantum dot can be increased by causing blue light with a relatively short wavelength in the visible light region to be incident on the first quantum dot and the second quantum dot. Therefore, in the end, the efficiency of light emitted from the first sub-pixel SPX1 and the second sub-pixel SPX2 can be improved, and excellent color reproducibility can be ensured. By configuring the sub-pixels SPX using light-emitting elements LD of the same color (e.g., blue light-emitting elements), the manufacturing efficiency of the display device can be improved.

[0178] In an embodiment, the light transmission layer LTP may be configured to effectively use the light of the third color emitted from the light emitting element LD. For example, when the light emitting element LD is a blue light emitting element emitting blue light and the third sub-pixel SPX3 is a blue pixel, the light transmission layer LTP may include at least one type of light scattering particles to effectively use the light emitted from the light emitting element LD.

[0179] For example, the light transmission layer LTP may include light scattering particles dispersed in a matrix material such as a base resin. For example, the light transmission layer LTP may include light scattering particles such as silicon dioxide, but the configuration material of the light scattering particles is not limited thereto. According to an embodiment, the light scattering particles may also be included in the first color conversion layer WCP1 and / or the second color conversion layer WCP2.

[0180] The first capping layer CAP1 may seal (or cover) the first color conversion layer WCP1, the second color conversion layer WCP2, and the light transmission layer LTP. The first capping layer CAP1 may be disposed between the low refractive layer LRL and the display element layer DPL. The first capping layer CAP1 may be disposed throughout the sub-pixels SPX1, SPX2, and SPX3. The first capping layer CAP1 may prevent impurities such as moisture or air from penetrating from the outside and damaging or contaminating the color conversion layer CCL.

[0181] In an embodiment, the first capping layer CAP1 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ) and titanium oxide (TiO x ) or more than one insulating material, but not limited to these.

[0182] The optical layer OPL may include a low refractive layer LRL and a second capping layer CAP2. The optical layer OPL may be disposed on the color conversion layer CCL. The optical layer OPL may be disposed on the display element layer DPL.

[0183] The low refractive layer LRL may be disposed between the color conversion layer CCL and the color filter layer CFL. The low refractive layer LRL may be disposed between the first capping layer CAP1 and the second capping layer CAP2. The low refractive layer LRL may be disposed throughout the sub-pixels SPX1, SPX2, and SPX3.

[0184] The low refraction layer LRL may serve to improve light efficiency by recycling light provided from the color conversion layer CCL through total reflection. To this end, the low refraction layer LRL may have a refractive index relatively lower than that of the color conversion layer CCL.

[0185] In an embodiment, the low refractive layer LRL may include a base resin and hollow particles dispersed in the base resin. The hollow particles may include hollow silica particles. As an example, the hollow particles may be pores formed by a porogen, but are not limited thereto. The low refractive layer LRL may include zinc oxide (ZnO) particles, titanium dioxide (TiO 2 ) particles and nano-silicate particles, but not limited thereto.

[0186] The second capping layer CAP2 may be disposed on the low refractive layer LRL. The second capping layer CAP2 may be disposed between the color filter layer CFL and the low refractive layer LRL. The second capping layer CAP2 may be disposed throughout the sub-pixels SPX1, SPX2, and SPX3. The second capping layer CAP2 may prevent impurities such as moisture or air from penetrating from the outside and damaging or contaminating the low refractive layer LRL. The second capping layer CAP2 may include the same material or a similar material as the first capping layer CPA1, or may include one or more materials selected from the materials that are the configuration materials of the first capping layer CPA1. For example, the second capping layer CAP2 may be a material including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ) and titanium oxide (TiO x ) or more than one insulating material, but not limited to these.

[0187] The color filter layer CFL may be disposed on the second capping layer CAP2. The color filter layer CFL may be disposed throughout the sub-pixels SPX1, SPX2, and SPX3. The color filter layer CFL may include color filters CF1, CF2, and CF3, a planarization layer PLA, and an overcoat layer OC.

[0188] In an implementation, color filters CF1, CF2, and CF3 may be disposed on the second capping layer CAP2. The color filters CF1, CF2, and CF3 may overlap emission areas EMA of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3, respectively.

[0189] The first color filter CF1 may transmit light of the first color, and may not transmit light of the second color and light of the third color. The second color filter CF2 may transmit light of the second color, and may not transmit light of the first color and light of the third color. The third color filter CF3 may transmit light of the third color, and may not transmit light of the first color and light of the second color.

[0190] In an embodiment, a planarization layer PLA may be disposed on the color filters CF1, CF2, and CF3. The planarization layer PLA may cover the color filters CF1, CF2, and CF3. The planarization layer PLA may planarize the step difference generated by the color filters CF1, CF2, and CF3. The planarization layer PLA may be disposed throughout the sub-pixels SPX1, SPX2, and SPX3.

[0191] The planarization layer PLA may include an organic material such as an acrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, a polyester resin, a polyphenylene sulfide resin, or a benzocyclobutene (BCB). However, the present disclosure is not limited thereto, and the planarization layer PLA may include various types of inorganic materials, including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) or titanium oxide (TiO x ).

[0192] The overcoat layer OC may be disposed on the planarization layer PLA. The overcoat layer OC may be disposed between the upper film layer UFL and the planarization layer PLA. The overcoat layer OC may be disposed throughout the sub-pixels SPX1, SPX2, and SPX3. The overcoat layer OC may cover the lower component including the color filter layer CFL. The overcoat layer OC may prevent moisture or air from penetrating into the lower component described above. The overcoat layer OC may protect the lower component described above from foreign matter such as dust.

[0193] The overcoat layer OC may include an organic material or an inorganic material. For example, the overcoat layer OC may include one or more materials selected from materials that are configuration materials of the planarization layer PLA.

[0194] The upper film layer UFL may be disposed on the color filter layer CFL. The upper film layer UFL may be disposed outside the display device to reduce external influences on the display device. The upper film layer UFL may be disposed throughout the sub-pixels SPX1, SPX2 and SPX3.

[0195] In an embodiment, the upper film layer UFL may include an AR coating (anti-reflective coating). The AR coating may refer to a material having an anti-reflective function applied to a surface or a configuration of a surface of a specific configuration or a given configuration. Here, the applied material may have a low reflectivity. For example, the material for the AR coating may include silicon oxide (SiO x ), aluminum oxide (AlO x ) and titanium oxide (TiO x ), but not limited to.

[0196] In an embodiment, if Fig.11As shown in , the color conversion layer CCL may be disposed on the display element layer DPL. For example, the first capping layer CAP1 may seal (or cover) a region in which the light emitting element LD is disposed, and the color conversion layer CCL may be disposed on the first capping layer CAP1.

[0197] In an embodiment, the color conversion layer CCL may further include a light blocking layer LBL (or a light blocking pattern). The light blocking layer LBL may be disposed on the display element layer DPL. The light blocking layer LBL may be disposed between the first capping layer CAP1 and the second capping layer CAP2. The light blocking layer LBL may be disposed to surround the first color conversion layer WCP1, the second color conversion layer WCP2, and the light transmission layer LTP at the boundaries between the sub-pixels SPX1, SPX2, and SPX3.

[0198] The light blocking layer LBL may overlap the non-emission area NEA. The light blocking layer LBL may surround the emission area EMA of the sub-pixels SPX1, SPX2, and SPX3. The light blocking layer LBL may be formed of an organic material including at least any one of graphite, carbon black, a black pigment, or a black dye, or may be formed of a metal material including chromium (Cr), but is not limited thereto, as long as the light blocking layer LBL is a material capable of blocking and absorbing light.

[0199] The second capping layer CAP2 may seal (or cover) the first color conversion layer WCP1 , the second color conversion layer WCP2 , and the light transmission layer LTP.

[0200] The low refractive layer LRL may be disposed between the second capping layer CAP2 and the third capping layer CAP3. The third capping layer CAP3 may include the same material or a similar material as the first capping layer CPA1, or may include one or more materials selected from materials configured as the first capping layer CPA1.

[0201] Fig.12 is a schematic perspective view showing a light emitting element according to an embodiment. Fig.13 is a schematic cross-sectional view showing a light emitting element according to an embodiment. Fig.12 and Fig.13 A columnar-shaped light emitting element LD is shown, but the type and / or shape of the light emitting element LD is not limited thereto.

[0202] refer to Fig.12 and Fig.13, the light emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, in the case where the extension direction of the light emitting element LD is the length L direction, the light emitting element LD may include the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 sequentially stacked on each other along the length L direction.

[0203] The light emitting element LD may be provided in a columnar shape extending in one direction or in one direction. The light emitting element LD may have a first end EP1 and a second end EP2. One of the first semiconductor layer 11 and the second semiconductor layer 13 may be provided at the first end EP1 of the light emitting element LD. The other of the first semiconductor layer 11 and the second semiconductor layer 13 may be provided at the second end EP2 of the light emitting element LD.

[0204] According to the embodiment, within the spirit and scope of the present disclosure, the light emitting element LD may be a light emitting element manufactured into a columnar shape by an etching method or the like. In the present specification, the columnar shape may include a rod-like shape or a strip-like shape such as a circular column or a polygonal column that is long in the length L direction (for example, an aspect ratio greater than 1), and the shape of its cross section is not particularly limited. For example, the length L of the light emitting element LD may be greater than the diameter D (or the width of the cross section) of the light emitting element LD.

[0205] The light emitting element LD may have a size as small as nanometer to micrometer. For example, each light emitting element LD may have a diameter D (or width) and / or a length L ranging from nanometer to micrometer. However, the size of the light emitting element LD is not limited thereto, and the size of the light emitting element LD may be variously changed according to the design conditions of various devices (e.g., display devices) using the light emitting device using the light emitting element LD as a light source.

[0206] The first semiconductor layer 11 may be a semiconductor layer of the first conductivity type. For example, the first semiconductor layer 11 may include an n-type semiconductor layer. For example, the first semiconductor layer 11 may include any semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include an n-type semiconductor layer doped with a first conductivity type dopant such as Si, Ge, and Sn. However, the material configuring the first semiconductor layer 11 is not limited thereto, and various other materials may also form the first semiconductor layer 11.

[0207] The active layer 12 may be disposed on the first semiconductor layer 11 and may be formed in a single quantum well structure or a multi-quantum well structure. The position of the active layer 12 may be variously changed according to the type of the light emitting element LD.

[0208] An encapsulation layer (not shown) doped with a conductive dopant may be formed on the active layer 12, and / or may be formed under or below the active layer 12. For example, the encapsulation layer may be formed of AlGaN or InAlGaN. According to an embodiment, materials such as AlGaN, InAlGaN, etc. may be used to form the active layer 12, and various other materials may also form the active layer 12.

[0209] The second semiconductor layer 13 may be disposed on the active layer 12, and may include a semiconductor layer of a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include a p-type semiconductor layer. For example, the second semiconductor layer 13 may include at least one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor layer doped with a second conductive type dopant such as Mg. However, the material configuring the second semiconductor layer 13 is not limited thereto, and various other materials may form the second semiconductor layer 13.

[0210] When a voltage equal to or greater than the threshold voltage is applied to both ends of the light emitting element LD, electron-hole pairs are recombined in the active layer 12, and thus the light emitting element LD emits light. By controlling the light emission of the light emitting element LD using this principle, the light emitting element LD can be used as a light source for various light emitting devices including pixels of a display device.

[0211] The light emitting element LD may further include an insulating film INF disposed on the surface. The insulating film INF may be formed on the surface of the light emitting element LD to surround at least the outer peripheral surface of the active layer 12 and may also surround one region of the first semiconductor layer 11 and the second semiconductor layer 13 .

[0212] According to an embodiment, the insulating film INF may expose both ends of the light emitting element LD having different polarities. For example, the insulating film INF may expose one end or ends of each of the first semiconductor layer 11 and the second semiconductor layer 13 at the first end EP1 and the second end EP2 of the light emitting element LD. In an embodiment, the insulating film INF may expose side portions of the first semiconductor layer 11 and the second semiconductor layer 13 adjacent to the first end EP1 and the second end EP2 of the light emitting element LD having different polarities.

[0213] According to an embodiment, the insulating film INF may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ) and titanium oxide (TiO x) and may be a single layer or multiple layers (for example, aluminum oxide (AlO x ) and silicon oxide (SiO x ) formed of a double layer), but is not limited thereto. According to an embodiment, the insulating film INF may be omitted.

[0214] When the insulating film INF is provided to cover the surface of the light emitting element LD (e.g., the peripheral surface of the active layer 12), a short circuit between the active layer 12 and the first pixel electrode, the second pixel electrode, etc. to be described later can be prevented. Therefore, the electrical stability of the light emitting element LD can be ensured.

[0215] When the insulating film INF is provided on the surface of the light emitting element LD, surface defects of the light emitting element LD can be minimized, thereby improving life and efficiency. When the light emitting elements LD are provided in close contact with each other, undesirable short circuits between the light emitting elements LD can be prevented.

[0216] In an embodiment, in addition to the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13 and / or the insulating film INF surrounding them, the light emitting element LD may further include another component. For example, the light emitting element LD may further include at least one phosphor layer, an active layer, a semiconductor layer and / or an electrode layer disposed on one end side or end side of the first semiconductor layer 11, the active layer 12 and / or the second semiconductor layer 13. For example, a contact electrode layer may be disposed at each of the first end EP1 and the second end EP2 of the light emitting element LD.

[0217] The light-emitting device including the light-emitting element LD described above can be used in various types of equipment (including display devices) that require a light source. For example, the light-emitting element LD can be arranged in each sub-pixel SPX of the display panel PNL described above, and the light-emitting element LD can be used as a light source for each sub-pixel SPX. However, the application field of the light-emitting element LD is not limited to the example described above. For example, the light-emitting element LD can also be used in other types of equipment (such as lighting equipment) that require a light source.

[0218] Although the present disclosure has been described with reference to the embodiments, those skilled in the art will appreciate that various modifications and changes can be made to the present disclosure without departing from the spirit and scope of the present disclosure and as described in the appended claims.

[0219] Therefore, the scope of the present disclosure should not be limited to the contents described in the detailed description of the specification, but should also be defined by the claims.

Claims

1. Display equipment, including: a first pixel and a second pixel, each of the first pixel and the second pixel comprising a first sub-pixel, a second sub-pixel, and a third sub-pixel; a first data line electrically connected to the first sub-pixel of the first pixel; a second data line electrically connected to the first sub-pixel of the second pixel; as well as A first connecting line electrically connects the first data line and the second data line, wherein: Each of the first sub-pixel, the second sub-pixel, and the third sub-pixel includes: A first region is disposed at one side of the pixel circuit; A second region is disposed on the other side of the pixel circuit; a light emitting element electrically connected to the pixel circuit; and an electrode electrically connecting the light emitting element and the pixel circuit, The electrode of the first subpixel of the first pixel is electrically connected to the pixel circuit in the first region and includes a first extension portion overlapping the second region in a plan view, and The electrode of the first subpixel of the second pixel is electrically connected to the pixel circuit in the second region and includes a second extension portion overlapping the first region in a plan view.

2. The display device according to claim 1, wherein: The first pixel and the second pixel are adjacent to each other in the same pixel row.

3. The display device according to claim 1, wherein: The first sub-pixel, the second sub-pixel, and the third sub-pixel are sequentially disposed in a first direction.

4. The display device according to claim 3, wherein: The first data line and the second data line are disposed in the first direction and extend in a second direction.

5. The display device according to claim 1, wherein: The first data line is disposed between the first sub-pixel and the second sub-pixel of the first pixel, and The second data line is disposed between the first sub-pixel and the second sub-pixel of the second pixel.

6. The display device according to claim 1, wherein: The electrode of the first subpixel of the first pixel and the electrode of the first subpixel of the second pixel have the same shape.

7. The display device according to claim 1, wherein: The electrode of the first subpixel of the first pixel and the electrode of the first subpixel of the second pixel have the same area.

8. The display device according to claim 1, wherein: The first sub-pixel emits light of a first color, The second sub-pixel emits light of a second color, and The third sub-pixel emits light of a third color.

9. The display device according to claim 1, wherein: The light emitting element comprises: a first semiconductor layer; A second semiconductor layer is disposed on the first semiconductor layer; and The active layer is disposed between the first semiconductor layer and the second semiconductor layer.

10. The display device according to claim 1, further comprising: a third data line electrically connected to the second sub-pixel of the first pixel; a fourth data line electrically connected to the second sub-pixel of the second pixel; as well as The second connecting line electrically connects the third data line and the fourth data line.

11. The display device according to claim 1, further comprising: a fifth data line electrically connected to the third sub-pixel of the first pixel; a sixth data line electrically connected to the third sub-pixel of the second pixel; as well as The third connecting line electrically connects the fifth data line and the sixth data line.

12. Display equipment, including: a first pixel and a second pixel, each of the first pixel and the second pixel including sub-pixels emitting light of the same color; a first data line electrically connected to the sub-pixel of the first pixel; a second data line electrically connected to the sub-pixel of the second pixel; as well as A connecting line electrically connects the first data line and the second data line, wherein: The sub-pixel comprises: A first region is disposed at one side of the pixel circuit; A second region is disposed on the other side of the pixel circuit; a light emitting element electrically connected to the pixel circuit; and an electrode electrically connecting the pixel circuit and the light emitting element, The electrode of the sub-pixel of the first pixel is electrically connected to the pixel circuit in the first region and includes a first extension portion overlapping the second region in a plan view, and The electrode of the sub-pixel of the second pixel is electrically connected to the pixel circuit in the second region and includes a second extension portion overlapping the first region in a plan view.

13. The display device according to claim 12, wherein: The first pixel and the second pixel are adjacent to each other in a first direction in the same pixel row.

14. The display device according to claim 13, wherein: The first data line and the second data line are disposed in the first direction and extend in a second direction.

15. The display device according to claim 12, wherein: The electrode of the sub-pixel of the first pixel and the electrode of the sub-pixel of the second pixel have the same shape.

16. The display device according to claim 12, wherein: The electrode of the sub-pixel of the first pixel and the electrode of the sub-pixel of the second pixel have the same area.

17. The display device according to claim 12, wherein: The light emitting element comprises: a first semiconductor layer; A second semiconductor layer is disposed on the first semiconductor layer; and The active layer is disposed between the first semiconductor layer and the second semiconductor layer.

18. The display device according to claim 12, further comprising: Align the electrodes, space them apart from each other, Wherein, the light emitting element is arranged between the alignment electrodes.

19. The display device according to claim 18, further comprising: a bridge electrode, the bridge electrode and the alignment electrode being arranged on the same layer, Wherein, the electrode of the sub-pixel is electrically connected to the pixel circuit through the bridge electrode.

20. The display device according to claim 12, further comprising: A color conversion layer is disposed on the light emitting element; as well as The color filter layer is disposed on the color conversion layer.

Images