A control method and circuit for adapting to different valve openings of a steam control valve

Abstract

The present invention discloses a control method and its circuit adapted to different valve openings of a steam control valve, which includes a control unit and a processing unit. The control unit includes several resistors, several operational amplifiers, a digital potentiometer, a flip-flop, a counter, and an inverter. One end of resistor R15 among the several resistors is connected to the CS pin and the 1_1 end of digital potentiometer U8, and a low-level signal is input to 1_1 during valve control. The U / D pin of digital potentiometer U8 is connected to one end of resistor R12 and the output pin of inverter U7, the A1 pin is connected to the power supply, the W1 pin, the B1 pin, one end of resistor R13, the inverting end of operational amplifier U11, and the non-inverting end of operational amplifier U10 are connected. The inverting end of operational amplifier U10 is connected to the reference voltage and the 2_1 end. The non-inverting end of operational amplifier U11 is connected to the reference voltage and the 2_2 end. The output ends of operational amplifier U10 and operational amplifier U11 are connected to the 1CLK pin of flip-flop U9 and the CP pin of counter U5.

Description

Technical Field

[0001] The present invention relates to the technical field of automatic control, and particularly relates to a control method and its circuit for adapting to different valve openings of a steam control valve. Background Art

[0002] In a pipeline system, due to the limitation of the valve service life and the iteration and update of products, when damaged and replaced, there are errors in products of different models or different manufacturers, and it is impossible to ensure the same flow rate as other valves under the same control. This will lead to uneven distribution of pipeline flow. Some pipelines may be overloaded due to excessive flow, or unable to meet the usage requirements due to insufficient flow. In the long run, it will not only affect the operation efficiency of the system, but also may exacerbate pipeline wear. Moreover, in actual use, the problem faced is that for the valve models that have been put into use, it is often difficult to purchase products with the same specifications as before in the market after iteration, and only similar products can be selected as substitutes. This substitution scheme may further exacerbate the problem of uneven flow. Summary of the Invention

[0003] In view of the above technical problems, the object of the present invention is to provide a control circuit for adapting to different valve openings of a steam control valve, which includes a control unit and a processing unit. The control unit includes several resistors, several operational amplifiers, a digital potentiometer, a flip-flop, a counter, and an inverter. One end of resistor R15 among several resistors is connected to the CS pin and the 1_1 end of digital potentiometer U8, and 1_1 inputs a low-level signal during valve control; the U / D pin of digital potentiometer U8 is connected to one end of resistor R12 and the output pin of inverter U7, the A1 pin is connected to the power supply, the W1 pin, the B1 pin, one end of resistor R13, the inverting input end of operational amplifier U11, and the non-inverting input end of operational amplifier U10 are connected; the inverting input end of operational amplifier U10 is connected to the reference voltage and the 2_1 end; the non-inverting input end of operational amplifier U11 is connected to the reference voltage and the 2_2 end; the output ends of operational amplifier U10 and operational amplifier U11 are connected to the 1CLK pin of flip-flop U9 and the CP pin of counter U5; the 1D pin of flip-flop U9 is connected to the inverse of the 1Q pin, and the 1Q pin is connected to the input pin of inverter U7; the CE pin of counter U5 is connected to one end of resistor R5, the MR pin is connected to one end of resistor R6 and the 1_2 end, and except for the 0 pin at the output end, the 1 to 9 pins respectively correspond to the outputs of the 4_1_1 to 4_1_N ends, and 1_2 inputs a signal during reset; the other ends of resistor R15, resistor R12, resistor R13, resistor R6, and resistor R5 are connected to the ground terminal; the 2_1 end, the 2_2 end, the 2_3 end, and the 4_1_1 to 4_1_N ends are fed back to the processing unit to obtain asynchronous pulse signals.

[0004] Preferably, the processing unit includes a processor. The terminals 2_1, 2_2, 2_3, and 4_1_1 to 4_1_N are fed back to the processor. When the single-pin feedback signal is output from the output terminal of the counter U5, the processor obtains the positive voltage difference between the terminals 2_3 and 2_2. When the double-pin feedback signal is output, the processor obtains the positive voltage difference between the terminals 2_1 and 2_3, and generates a conversion signal based on the pins at the output terminal of the counter U5 and feeds it back to the voltage-controlled oscillator to output an asynchronous pulse signal to the servo motor.

[0005] Preferably, the processing unit includes several resistors, a selector, an operational amplifier. The AY pin of the selector U1 in the selector is connected to the terminal 2_1, the BX pin is connected to the terminal 2_2, the BY pin, the AX pin are connected to the terminal 2_3, the AX / AY pins are connected to one end of the resistor R1, the BX / BY pins are connected to one end of the resistor R2, and the A and B pins are connected to the input pins of the inverter U7; the non-inverting input terminal of the operational amplifier U2 is connected to the other end of the resistor R1 and one end of the resistor R4, the inverting input terminal of the operational amplifier U2 is connected to the other end of the resistor R2 and one end of the resistor R3, and the output terminal of the operational amplifier U2 is connected to one end of the resistor R3 and the terminal 3_1; the other end of the resistor R4 is connected to the ground terminal.

[0006] Preferably, the processing unit further includes an inverter, a multiplex flip-flop, and several transfer modules. Among the several transfer modules, there are several diodes and several resistors. The cathodes of the diodes D1 and D2 and one end of the resistor R19 are connected. One end of the resistor R11 is connected to one ends of the resistors R18 and R17. The other ends of the resistors R18 and R19 are connected to the ground terminal; the anodes of the D1 in each transfer module are respectively connected to the corresponding 4_1_1 to 4_1_N terminals corresponding to the 1 to 9 pins at the output terminal of the counter U5, the anode of the D2 is connected to the other end of the resistor R11 and the corresponding 4_3_1 to 4_3_N terminals corresponding to the 1Q to 8Q output terminals of the multiplex flip-flop U4, the cathode of the D2 is connected to the corresponding 4_2_1 to 4_2_N terminals corresponding to the 1D to 8D input terminals of the multiplex flip-flop U4, and the other end of the resistor R17 is connected to the corresponding 5_1_1 to 5_1_N terminals; the input terminal of the inverter U3 in the inverter is connected to the terminal 1_2, and the output terminal is connected to the CLR pin of the multiplex flip-flop U4.

[0007] Preferably, the processing unit further includes several resistors and an operational amplifier. The non-inverting input terminal of the operational amplifier U6 in the operational amplifier is connected to the 5_1_1 to 5_1_N terminals, and the inverting input terminal is connected to one ends of the resistors R7 and R8; the other end of the resistor R7 is connected to the output terminal of the operational amplifier U6 and the terminal 6_1, and the other end of the resistor R8 is connected to the ground terminal; the terminal 6_1 is connected to the voltage-controlled oscillator of the servo motor control system.

[0008] Preferably, the control unit further includes a plurality of resistors. Among the plurality of resistors, one end of resistor R10 is connected to the A1 pin of digital potentiometer U8, and the other end is connected to one end of resistor R14 and the inverting input terminal of operational amplifier U10; one end of resistor R9 is connected to the power supply, and the other end is connected to one end of resistor R16 and the non-inverting input terminal of operational amplifier U11; the other ends of resistor R16 and resistor R14 are connected to the ground terminal.

[0009] Preferably, resistor R11 and resistor R18 are adjustable resistors.

[0010] Preferably, a control method adapted to different valve openings of a steam control valve is provided, which is characterized by including the following steps:

[0011] S1. Set a reference signal as the reference signal for different valve gradings;

[0012] S2. Classify the flow rates corresponding to different valve openings;

[0013] S3. Generate asynchronous pulse signals according to valves of different levels;

[0014] S4. Feed back the signal to the servo motor corresponding to the valve to complete flow synchronization.

[0015] Compared with the prior art, when the present invention controls valves with different flow rates, it can always maintain a consistent flow rate, prevent overload and insufficient flow, and can adapt to most types of valves on the market. The control accuracy is high, and the final flow error can be controlled within the range of the motor step angle error corresponding to one pulse. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for use in the prior art and the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0017] Figure 1 It is a schematic diagram of the overall structure signal feedback provided by the present invention.

[0018] Figure 2 It is a schematic diagram of the overall structure of the control unit and the processing unit provided by the present invention.

[0019] Figure 3 It is a schematic diagram of the input structure of the trans-storage module in the processing unit provided by the present invention.

[0020] Figure 4 It is a schematic diagram of the output structure of the trans-storage module in the processing unit provided by the present invention.

[0021] Figure 5 Schematic diagram of the processing unit structure provided by the present invention. Detailed implementation manners

[0022] In order to make the objectives and advantages of the present invention more clear and understandable, the present invention will be specifically described below in conjunction with embodiments. It should be understood that the following text is only used to describe one or several specific implementation manners of the present invention, and does not strictly limit the scope of protection of the specific claims of the present invention.

[0023] Refer to Figure 1 and Figure 2 The present invention discloses a control circuit adapted to different valve openings of a steam control valve, which includes a control unit and a processing unit. The control unit includes several resistors, several operational amplifiers, a digital potentiometer, a flip-flop, a counter, and an inverter. One end of resistor R15 among several resistors is connected to the CS pin and the 1_1 terminal of digital potentiometer U8, and a low-level signal is input to 1_1 during valve control; the U / D pin of digital potentiometer U8 is connected to one end of resistor R12 and the output pin of inverter U7, the A1 pin is connected to the power supply, and the W1 pin, B1 pin, one end of resistor R13, the inverting terminal of operational amplifier U11, and the non-inverting terminal of operational amplifier U10 are connected; the inverting terminal of operational amplifier U10 is connected to the reference voltage and the 2_1 terminal; the non-inverting terminal of operational amplifier U11 is connected to the reference voltage and the 2_2 terminal; the output terminals of operational amplifiers U10 and U11 are connected to the 1CLK pin of flip-flop U9 and the CP pin of counter U5; the 1D pin of flip-flop U9 is connected to the 1Q inverse pin, and the 1Q pin is connected to the input pin of inverter U7; the CE pin of counter U5 is connected to one end of resistor R5, the MR pin is connected to one end of resistor R6 and the 1_2 terminal, and except for the 0 pin at the output terminal, the 1 to 9 pins respectively correspond to the 4_1_1 to 4_1_N terminals, and a signal is input to 1_2 during reset; the other ends of resistor R15, resistor R12, resistor R13, resistor R6, and resistor R5 are connected to the ground terminal; the 2_1 terminal, 2_2 terminal, 2_3 terminal, and 4_1_1 to 4_1_N terminals are fed back to the processing unit to obtain asynchronous pulse signals;

[0024] In order to adapt to common valve types on the market, we select the valve opening corresponding to a lower flow rate as the reference benchmark. The purpose is to ensure that the flow rates of valves with different flow rates are always synchronized when they are opened. Since the flow rates corresponding to the same opening range of different valves are different, to solve this problem, a reference signal is first set, and the flow rates corresponding to different valve openings are classified. Then, asynchronous pulse signals are generated according to different levels of valves and fed back to the servo motors corresponding to each valve to achieve flow synchronization. The specific control method is as follows: when a valve is selected and opened, a low-level signal is fed back to start the digital potentiometer U8 at 1_1. The U / D pin of the digital potentiometer U8 is in a high-impedance to low-impedance state by default in the initial state. As the CLK signal is input, the voltage at the connection end of the B1 pin of the digital potentiometer U8 and the resistor R13 is pulled up and fed back to the non-inverting input terminal of the operational amplifier U10 and the inverting input terminal of the operational amplifier U11 for detection. A reference voltage is set at the inverting input terminal of the operational amplifier U10. In the attached figure, it is assumed that the digital potentiometer U8 uses the attached figure model, with a resistance value of 10KΩ, 1024 tap numbers, and an output range of 5V. Then, the selection rules for the resistors R10 and R14 are the downward rounded value of the voltage at the voltage division point of the 1024 - 1 tap number and the resistor R13, and the selection rules for the resistors R9 and R16 are the upward rounded value of the voltage at the voltage division point of the 1024 - 1023 tap number and the resistor R13. Assuming based on the digital potentiometer U8 model and a power supply of 5V, the resistance values of the resistors R10, R14, R9, and R16 are selected as 300Ω, 4.7KΩ, 2.3KΩ, and 2.7KΩ respectively (for illustrative purposes only. For other spans, it can be set by yourself. When the resistors are non-standard, they can be connected in series). The voltage span is 2V per order, and the precision is 1024. The purpose of setting the order is to make the control precision consistent when valves with different opening ranges are converted into pulses asynchronously, and to reduce the error of the final opened flow rate to the error of one pulse step angle. When the voltage at the connection end of the B1 pin of the digital potentiometer U8 and the resistor R13 is pulled up to the reference voltage of the operational amplifier U10, the operational amplifier U10 outputs a signal to the 1CLK pin of the flip-flop U9. In the initial state of the flip-flop U9, the 1Q pin outputs (pins 5 and 6 are the inverse pins of 1Q). After the 1CLK receives the signal, the inverse pin of 1Q outputs, and the signal fed back by the pull-down of the 1Q pin is sent to the inverter U7. After inversion by the inverter U7, the output signal is sent to the U / D pin of the digital potentiometer U8, and the digital potentiometer U8 is changed from low impedance to high impedance until the operational amplifier U11 outputs and then the conversion is performed again. At the same time, the 1CLK signal of the flip-flop U9 is fed back to the CP pin of the counter U5, and the 0 to 9 pins of the counter U5 poll and output. The 1 - 9 pins of the counter U5 correspond to the connection ends from 4_1_1 to 4_1_N respectively. In this embodiment, 2_1 to 2_3 and 4_1_1 to 4_1_N are all fed back to the upper processor (not shown in the attached figure).

[0025] Refer to Figure 2, specifically, the processing unit includes a processor. The 2_1 terminal, 2_2 terminal, 2_3 terminal, and 4_1_1 to 4_1_N terminals are fed back to the processor. When the single-pin feedback signal is output at the output terminal of the counter U5, the processor obtains the positive voltage difference between the 2_3 terminal and the 2_2 terminal. When the double-pin feedback signal is output, the processor obtains the positive voltage difference between the 2_1 terminal and the 2_3 terminal, and generates a conversion signal based on the pins at the output terminal of the counter U5 and feeds it back to the voltage-controlled oscillator to output an asynchronous pulse signal to the servo motor;

[0026] The logic of the processor is that when any of the 1st, 3rd, 5th, 7th, and 9th single pins of the counter U5 is input, the voltage of the 2_3 terminal minus the voltage of the 2_2 terminal, and for the double pins, the voltage of the 2_1 terminal minus the voltage of the 2_3 terminal. This voltage is the voltage parameter value corresponding to the current order. The above example is 2V. Assuming it is the 3rd order, it corresponds to 3 * 2 + the voltage parameter value corresponding to the current order. This parameter is the final conversion parameter. After the flow rate conversion of each valve is completed in the above manner, the corresponding signal is fed back to the processor. The processor takes any one as the reference voltage signal of the valve, and when controlling, proportionally amplifies the voltage signals of the orders corresponding to the openings of other valves and feeds them back to the servo motor, or directly feeds the converted voltage signal back to the voltage-controlled oscillator (or external) in the servo motor control system to output an asynchronous pulse to the servo motor to complete the flow rate synchronization control.

[0027] See Figure 2 , specifically, the processing unit includes several resistors, a selector, an operational amplifier. The AY pin of the selector U1 in the selector is connected to the 2_1 terminal, the BX pin is connected to the 2_2 terminal, the BY pin, the AX pin are connected to the 2_3 terminal, the AX / AY pins are connected to one end of the resistor R1, the BX / BY pins are connected to one end of the resistor R2, and the A pin and the B pin are connected to the input pins of the inverter U7; the non-inverting terminal of the operational amplifier U2 is connected to the other end of the resistor R1 and one end of the resistor R4, the inverting terminal of the operational amplifier U2 is connected to the other end of the resistor R2 and one end of the resistor R3, the output terminal of the operational amplifier U2 is connected to one end of the resistor R3 and the 3_1 terminal; the other end of the resistor R4 is connected to the ground terminal;

[0028] See Figure 2, in one embodiment, based on the above solution, a more preferred control method is provided. Compared with the above method that requires secondary embedded development, the logic is simpler. It can partially or completely replace the development process and can also be used as an independent controller after encapsulation. In this embodiment, signals from 2_1 to 2_3 are connected to the selector U1. The A and B pins of the selector U1 are connected to the 1Q pin of the flip-flop U9. When the flip-flop U9 outputs, the selector U1 corresponds the outputs of AX / AY and BX / BY to AX or AY and BX or BY. Subsequently, the AX / AY pin is fed back to the non-inverting input terminal of the operational amplifier U2 after passing through the resistor R1 and the resistor R4 loop. After the BX / BY is input to the inverting input terminal of the operational amplifier U2 through the resistor R2, the output terminal is then output to the inverting input terminal of the operational amplifier U2 through the resistor R3 to form negative feedback. When the output pin of the counter U5 is an odd-numbered pin, the A and B pins of the selector U1 are pulled down, the output signal of AX / AY is AX, and the output signal of BX / BY is BX. At the same time, the digital potentiometer U8 inverts the signal output by the flip-flop U9 and inputs it to the U / D pin of the digital potentiometer U8. When 1_1 is cut off, the voltage of 3_1 corresponds to the difference between the voltage of the 2_3 terminal and the voltage of the 2_2 terminal; when the output pin of the counter U5 is an even number, the A and B pins of the selector U1 are pulled up, the output signal of AX / AY is AY, and the output signal of BX / BY is BY. At the same time, the digital potentiometer U8 inverts the signal output by the flip-flop U9 and inputs it to the U / D pin of the digital potentiometer U8. When 1_1 is cut off, the voltage of 3_1 corresponds to the difference between the voltage of the 2_1 terminal and the voltage of the 2_3 terminal.

[0029] Refer to Figure 3 and Figure 4 , specifically, the processing unit further includes an inverter, a multiplex flip-flop, and several transfer modules. Among the several transfer modules, there are several diodes and several resistors. The cathodes of D1 and D2 among the several diodes are connected to one end of the resistor R19, one end of the resistor R11 is connected to one ends of the resistor R18 and the resistor R17, and the other ends of the resistor R18 and the resistor R19 are connected to the ground terminal; the anodes of D1 in each transfer module are respectively connected to the 4_1_1 to 4_1_N terminals corresponding to the output terminals 1 to 9 of the counter U5, the anode of D2 is connected to the other end of the resistor R11 and the 4_3_1 to 4_3_N terminals corresponding to the output terminals 1Q to 8Q of the multiplex flip-flop U4, the cathode of D2 is connected to the 4_2_1 to 4_2_N terminals corresponding to the input terminals 1D to 8D of the multiplex flip-flop U4, and the other end of the resistor R17 is connected to the corresponding 5_1_1 to 5_1_N terminals; the input terminal of the inverter U3 in the inverter is connected to the 1_2 terminal, and the output terminal is connected to the CLR pin of the multiplex flip-flop U4;

[0030] For the replacement of the order, the output pins of the counter U5 except the divide-by-zero pin are fed back to the corresponding D1s, and a multiplex flip-flop U4 is added to make up for the polling method of the output of the counter U5. The connection terminal voltage of D1 and D2 is pulled up by the resistor R19 and then input from 4_2_1 to the 1D to 8D input terminals of the multiplex flip-flop U4. When the output pins 0 to 9 of the counter U5 are output in sequence, the output pins 1Q to 8Q of the multiplex flip-flop U4 are input to D2 through 4_3_1 to 4_3_N in sequence and then fed back to the input pins of the multiplex flip-flop U4, so that the multiplex flip-flop U4 does not need to be set when the CLK signal is input.

[0031] Refer to Figure 5 , specifically, the processing unit further includes several resistors and operational amplifiers. The non-inverting input terminal of the operational amplifier U6 in the operational amplifier is connected to the 5_1_1 to 5_1_N terminals, and the inverting input terminal is connected to one end of the resistor R7 and the resistor R8; the other end of the resistor R7 is connected to the output terminal of the operational amplifier U6 and the 6_1 terminal, and the other end of the resistor R8 is connected to the ground terminal; the 6_1 terminal is connected to the voltage-controlled oscillator of the servo motor control system;

[0032] The final conversion parameters are obtained by feeding back 4_3_1 to 4_3_N to the corresponding resistor R11. The resistor R11 and the resistor R18 are used to divide the fixed parameter voltage output by the multiplex flip-flop U4 into the corresponding first-order voltage. The resistor R17 is used for impedance matching and is fed back to the non-inverting input terminal of the operational amplifier U6. The resistor R17 can also be replaced by an isolation circuit and input to the non-inverting input terminal of the operational amplifier U6. At the same time, 3_1 is also fed back to the non-inverting input terminal of the operational amplifier U6. After the operational amplifier U6 superimposes and outputs 6_1, the final conversion parameters are output. The signal is fed back to the voltage-controlled oscillator and directly outputs asynchronous pulses to control the servo motor (the voltage-controlled oscillator is not shown in the figure), and 1_2 is used to reset the counter U5 and the multiplex flip-flop U4.

[0033] Refer to Figure 2 , specifically, the control unit further includes several resistors. Among the several resistors, one end of the resistor R10 is connected to the A1 pin of the digital potentiometer U8, and the other end is connected to one end of the resistor R14 and the inverting input terminal of the operational amplifier U10; one end of the resistor R9 is connected to the power supply, and the other end is connected to one end of the resistor R16 and the non-inverting input terminal of the operational amplifier U11; the other ends of the resistor R16 and the resistor R14 are connected to the ground terminal;

[0034] The voltage signals fed back by the resistor R10, the resistor R14, the resistor R9, and the resistor R16 can also be directly input to the corresponding voltage by the upper processor.

[0035] Refer to Figure 4 , specifically, the resistor R11 and the resistor R18 are adjustable resistors.

[0036] Specifically, a control method adapted to different valve openings of a steam control valve is also provided, which is characterized by including the following steps:

[0037] S1. Set a reference signal as the reference signal for different valve gradings;

[0038] S2. Classify the flow rates corresponding to different valve openings;

[0039] S3. Generate asynchronous pulse signals according to valves of different levels;

[0040] S4. Feed the signal back to the servo motor corresponding to the valve to complete flow synchronization.

[0041] Refer to Figure 1 and Figure 2, in order to adapt to common valve types on the market, we choose the valve with an opening corresponding to a lower flow rate as the reference benchmark. The purpose is to ensure that the flow rates of valves with different flow rates are always synchronized when they are opened. Since the flow rates corresponding to the same opening range of different valves are different, to solve this problem, a reference signal is first set, and the flow rates corresponding to different valve openings are classified. Then, asynchronous pulse signals are generated according to different levels of valves and fed back to the servo motors corresponding to each valve to achieve flow synchronization. The specific control method is as follows: when a valve is selected and opened, a low-level signal is fed back to start the digital potentiometer U8 at 1_1. The U / D pin of the digital potentiometer U8 is in a high-impedance to low-impedance state by default in the initial state. With the input of the CLK signal, the voltage at the connection end of the B1 pin of the digital potentiometer U8 and the resistor R13 is pulled up and fed back to the non-inverting input terminal of the operational amplifier U10 and the inverting input terminal of the operational amplifier U11 for detection. The reference voltage is set at the inverting input terminal of the operational amplifier U10. In the attached figure, it is assumed that the digital potentiometer U8 uses the signal in the attached figure, its resistance value is 10KΩ, the number of taps is 1024, and the output range is 5V. Then the selection rules for the resistors R10 and R14 are the downward rounded value of the voltage at the voltage division point of the number of taps 1024 - 1 and the resistor R13, and the selection rules for the resistors R9 and R16 are the upward rounded value of the voltage at the voltage division point of the number of taps 1024 - 1023 and the resistor R13. Assuming based on the model of the digital potentiometer U8 and the power supply voltage is 5V, then the resistance values of the resistors R10, R14, R9, and R16 are selected as 300Ω, 4.7KΩ, 2.3KΩ, 2.7KΩ (for illustrative purposes only, it can be set by yourself for other spans. When the resistance is non-standard, it can be connected in series). Its voltage span is 2V per order, and the accuracy is 1024. The purpose of setting the order is to make the control accuracy consistent when valves with different opening ranges are asynchronously converted into pulses, so that the error of the final opening flow rate is reduced to the error of one pulse step angle. When the voltage at the B1 pin of the digital potentiometer U8 and the resistor R13 terminal is pulled up to the reference voltage of the operational amplifier U10, the operational amplifier U10 outputs a signal to the 1CLK pin of the flip-flop U9. When the flip-flop U9 is in the initial state, the 1Q pin outputs (pins 5 and 6 are the inverse pins of 1Q). After the 1CLK receives the signal, the inverse pin of 1Q outputs, and the signal fed back by the pull-down of the 1Q pin goes to the inverter U7. After the inverter U7 inverts, it outputs a signal to the U / D pin of the digital potentiometer U8. The digital potentiometer U8 is changed from low resistance to high resistance until the operational amplifier U11 outputs and then the conversion is performed again. At the same time, the 1CLK signal of the flip-flop U9 is fed back to the CP pin of the counter U5. The 0 to 9 pins of the counter U5 poll and output. The 1-9 pins of the counter U5 respectively correspond to the 4_1_1 to 4_1_N connection terminals. In this embodiment, 2_1 to 2_3 and 4_1_1 to 4_1_N are all fed back to the upper processor (not shown in the figure). The logic of the processor is that when any of the odd pins 1, 3, 5, 7, 9 of the counter U5 inputs, the voltage at the 2_3 terminal minus the voltage at the 2_2 terminal, and for the even pins, the voltage at the 2_1 terminal minus the voltage at the 2_3 terminal. This voltage is the voltage parameter value corresponding to the current order. The above example is 2V. Assuming it is 3 orders, it corresponds to 3*2 + the voltage parameter value corresponding to the current order. This parameter is the final conversion parameter. After the flow rate conversion of each valve is completed through the above method, the corresponding signal is fed back to the processor. The processor takes any one as the valve reference voltage signal, and when controlling, it proportionally amplifies the voltage signals of the orders corresponding to the opening degrees of other corresponding valves and then feeds them back to the servo motor, or directly feeds the converted voltage signal to the voltage-controlled oscillator (or external) in the servo motor control system to output asynchronous pulses to the servo motor to complete the flow rate synchronization control.

[0042] Refer to Figure 3 , Figure 4 and Figure 5, in one embodiment, based on the above solution, a more preferred control method is provided. Compared with the above method that requires secondary embedding and development, the logic is simpler, and it can partially or completely replace the secondary embedding process. When it is put into a used system, after the control system of the servo motor feeds back the opening control signal of the valve, the above process can be completed to replace the original motor control signal, and it can also be used as an independent controller after encapsulation.In this embodiment, signals 2_1 to 2_3 are connected to the selector U1. The A and B pins of the selector U1 are connected to the 1Q pin of the flip-flop U9. When the flip-flop U9 outputs, the selector U1 corresponds the outputs of AX / AY and BX / BY to AX or AY, and BX or BY. Subsequently, the AX / AY pin is fed back to the non-inverting input terminal of the operational amplifier U2 after passing through the resistor R1 and the resistor R4 loop. After the BX / BY is input to the inverting input terminal of the operational amplifier U2 through the resistor R2, the output terminal is output to the inverting input terminal of the operational amplifier U2 through the resistor R3 to form negative feedback. When the output pin of the counter U5 is an odd-numbered pin, the A and B pins of the selector U1 are pulled down, the output signal of AX / AY is AX, and the output signal of BX / BY is BX. At the same time, the digital potentiometer U8 inverts the signal output by the flip-flop U9 and inputs it to the U / D pin of the digital potentiometer U8. When 1_1 is cut off, the voltage of 3_1 will correspond to the difference between the voltage of the 2_3 terminal and the voltage of the 2_2 terminal; when the output pin of the counter U5 is an even number, the A and B pins of the selector U1 are pulled up, the output signal of AX / AY is AY, and the output signal of BX / BY is BY. At the same time, the digital potentiometer U8 inverts the signal output by the flip-flop U9 and inputs it to the U / D pin of the digital potentiometer U8. When 1_1 is cut off, the voltage of 3_1 will correspond to the difference between the voltage of the 2_1 terminal and the voltage of the 2_3 terminal; for the replacement of the order, the output pins of the counter U5 except the 0 pin are fed back to the corresponding D1 respectively, and a multiplex flip-flop U4 is added to make up for the polling method of the output of the counter U5. The connection terminal voltage of D1 and D2 is pulled up by the resistor R19 and then input to the 1D to 8D input terminals of the multiplex flip-flop U4 through 4_2_1. When the output pins 0 to 9 of the counter U5 are output in sequence, the output pins 1Q to 8Q of the multiplex flip-flop U4 are input to D2 through 4_3_1 to 4_3_N in sequence and then fed back to the input pins of the multiplex flip-flop U4, so that the CLK signal of the multiplex flip-flop U4 can be input without being set; the final conversion parameter is obtained by feeding back 4_3_1 to 4_3_N to the corresponding resistor R11. The resistor R11 and the resistor R18 are used to divide the fixed parameter voltage output by the multiplex flip-flop U4 into the corresponding first-order voltage. The resistor R17 is used for impedance matching and is fed back to the non-inverting input terminal of the operational amplifier U6. The resistor R17 can also be replaced by an isolation circuit and input to the non-inverting input terminal of the operational amplifier U6. At the same time, 3_1 is also fed back to the non-inverting input terminal of the operational amplifier U6. After the operational amplifier U6 superimposes, it outputs 6_1 to complete the output of the final conversion parameter. The signal is fed back to the voltage-controlled oscillator to directly output asynchronous pulses to control the servo motor (the voltage-controlled oscillator is not shown in the figure). 1_2 is used to reset the counter U5 and the multiplex flip-flop U4. The voltage signals fed back by the resistors R10, R14, R9, and R16 can also be directly input to the corresponding voltage by the upper processor.

[0043] It is obvious to those skilled in the art that the present invention is not limited to the details of the above-described exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention. Therefore, in all respects, the embodiments should be regarded as exemplary and non-restrictive. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be embraced within the present invention. Any reference signs in the claims should not be construed as limiting the claim concerned.

Claims

1. A control circuit adapted to different valve openings of a steam regulating valve, characterized in that The invention comprises a control unit and a processing unit, wherein the control unit comprises a plurality of resistors, a plurality of operational amplifiers, a digital potentiometer, a trigger, a counter, and an inverter. One end of a resistor R15 among the plurality of resistors is connected to the CS pin and the 1_1 end of the digital potentiometer U8, and 1_1 inputs a low-level signal during valve control; the U / D pin of the digital potentiometer U8 is connected to one end of a resistor R12 and the output pin of the inverter U7, the A1 pin is connected to a power supply, the W1 pin, the B1 pin, one end of a resistor R13, the reverse end of the operational amplifier U11, and the in-phase end of the operational amplifier U10 are connected; the reverse end of the operational amplifier U10 is connected to the reference voltage and the 2_1 end; the in-phase end of the operational amplifier U11 is connected to the reference voltage and the 2_2 end; the operational amplifier U10 and the operational amplifier The output end of U11 is connected to the 1CLK pin of the trigger U9 and the CP pin of the counter U5; the 1D pin of the trigger U9 is connected to the 1Q inverting pin, and the 1Q pin is connected to the input pin of the inverter U7; the CE pin of the counter U5 is connected to one end of the resistor R5, the MR pin is connected to one end of the resistor R6 and the 1_2 end, the output end is except the 0 pin, and the 1 to 9 pins correspond to the output 4_1_1 to 4_1_N ends respectively, and 1_2 inputs the signal during reset; the other ends of the resistors R15, R12, R13, R6, and R5 are connected to the ground end; the 2_1 end, the 2_2 end, the 2_3 end, and the 4_1_1 to 4_1_N ends are fed back to the processing unit to obtain asynchronous pulse signals.

2. The control circuit for adapting steam regulating valves to different valve openings according to claim 1, characterized in that: The processing unit includes a processor, and the 2_1 terminal, 2_2 terminal, 2_3 terminal, and 4_1_1 to 4_1_N terminals are fed back to the processor. When the odd-numbered pins at the output end of the counter U5 feedback a signal, the processor obtains the positive voltage difference between the 2_3 terminal and the 2_2 terminal, and the even-numbered pins obtain the positive voltage difference between the 2_1 terminal and the 2_3 terminal, and generates a conversion signal based on the pin at the output end of the counter U5 and feeds it back to the voltage-controlled oscillator to output an asynchronous pulse signal to the servo motor.

3. The control circuit for adapting steam regulating valves to different valve openings according to claim 1, characterized in that: The processing unit includes a plurality of resistors, a gate, and an operational amplifier. The AY pin of the gate U1 is connected to the 2_1 end, the BX pin is connected to the 2_2 end, the BY pin is connected to the AX pin and the 2_3 end, the AX / AY pin is connected to one end of the resistor R1, the BX / BY pin is connected to one end of the resistor R2, the A pin, the B pin are connected to the input pin of the inverter U7; the in-phase end of the operational amplifier U2 is connected to the other end of the resistor R1 and one end of the resistor R4, the inverting end of the operational amplifier U2 is connected to the other end of the resistor R2 and one end of the resistor R3, the output end of the operational amplifier U2 is connected to one end of the resistor R3 and the 3_1 end; the other end of the resistor R4 is connected to the ground end.

4. The control circuit for adapting steam regulating valves to different valve openings according to claim 3, characterized in that: The processing unit also includes an inverter, a multi-way trigger, and several transfer modules. The several transfer modules include several diodes and several resistors. The cathode of D1 in the several diodes is connected to the cathode of D2 and one end of the resistor R19, one end of the resistor R11 is connected to one end of the resistor R18 and the resistor R17, and the other end of the resistor R18 and the resistor R19 is connected to the ground end; the anode of D1 in each transfer module is respectively connected to the 4_1_1 to 4_1_N ends corresponding to the output ends 1 to 9 of the counter U5, the anode of D2 is connected to the other end of the resistor R11 and the 4_3_1 to 4_3_N ends corresponding to the output ends 1Q to 8Q of the multi-way trigger U4, the cathode of D2 is connected to the 4_2_1 to 4_2_N ends corresponding to the input ends 1D to 8D of the multi-way trigger U4, and the other end of the resistor R17 is connected to the corresponding 5_1_1 to 5_1_N ends; the input end of the inverter U3 in the inverter is connected to the 1_2 end, and the output end is connected to the CLR pin of the multi-way trigger U4.

5. The control circuit for adapting steam regulating valves to different valve openings according to claim 4, characterized in that: The processing unit also includes a plurality of resistors and operational amplifiers, wherein the in-phase end of the operational amplifier U6 is connected to the ends 5_1_1 to 5_1_N, and the inverting end is connected to one end of the resistor R7 and the resistor R8; the other end of the resistor R7 is connected to the output end of the operational amplifier U6 and the end 6_1, and the other end of the resistor R8 is connected to the ground end; the end 6_1 is connected to the voltage-controlled oscillator of the servo motor control system.

6. The control circuit for adapting steam regulating valves to different valve openings according to claim 1, characterized in that: The control unit also includes a plurality of resistors, among which one end of resistor R10 is connected to the A1 pin of the digital potentiometer U8, and the other end is connected to one end of resistor R14 and the inverting end of the operational amplifier U10; one end of resistor R9 is connected to the power supply, and the other end is connected to one end of resistor R16 and the non-inverting end of the operational amplifier U11; the other ends of resistor R16 and resistor R14 are connected to the ground.

7. The control circuit for adapting steam regulating valves to different valve openings according to claim 4, characterized in that: The resistor R11 and the resistor R18 are adjustable resistors.

8. A control method, used for the control circuit adapted to different valve openings of a steam regulating valve as described in any one of claims 1 to 7, characterized in that: The following steps are involved: S1. Set a reference signal as a reference signal for different valve classifications; S2 classifies the flow rates corresponding to different valve openings; S3. Generate asynchronous pulse signals according to valves of different levels; S4. Feedback the signal to the servo motor corresponding to the valve to complete flow synchronization.

Images