Chip under-hanging equipment testing method and device, equipment and storage medium

Abstract

The invention discloses an under-hanging device testing method and device of a chip, equipment and a storage medium, and relates to the technical field of computers, and the method comprises the following steps: reading under-hanging device information of a preset chip; determining one or more ports connected with the lower-mounted device in the preset chip according to the lower-mounted device information; in response to a selection operation of a user on one or more ports, determining each to-be-tested port; testing a lower device of each to-be-tested port to generate a corresponding test folder; extracting corresponding test data from each test folder, and generating a test report according to the test data; according to the method and the device, the test reports corresponding to the under-hanging devices are output, the under-hanging devices of the to-be-tested ports are automatically tested by selecting the to-be-tested ports, the corresponding under-hanging devices do not need to be manually switched, and the test efficiency of the under-hanging devices is improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method, device, equipment and storage medium for testing a device mounted on a chip. Background Art

[0002] With the development of high-speed serial computer expansion bus technology, its importance in high-performance computing, data centers, AI and other fields has become increasingly prominent. Eye diagram testing is an important part of this. The oscilloscope accumulates and superimposes digital signals into an eye-shaped graph, and analyzes the signal quality based on this to ensure that the downstream equipment will not make mistakes when running at high speed.

[0003] In the related art, after the chip is connected to multiple hanging devices through a serial port tool, it is necessary to manually set and switch the corresponding hanging devices one by one for testing. However, in the related art, by manually setting and switching the corresponding hanging devices one by one, it is easy to cause the hanging devices to be switched untimely, resulting in low testing efficiency of the hanging devices. Summary of the invention

[0004] The present application provides a chip's downstream device testing method, apparatus, equipment and storage medium, in order to at least solve the problem in the related art that manually setting and switching corresponding downstream devices one by one may easily lead to untimely switching of downstream devices, resulting in low testing efficiency of the downstream devices.

[0005] The present application provides a method for testing a device mounted on a chip, comprising:

[0006] Reading the downstream device information of the preset chip, wherein the preset chip at least includes a plurality of ports, each port being used to connect to the downstream device;

[0007] Determine one or more ports connected to the downstream device according to the downstream device information;

[0008] In response to a user's selection operation on the one or more ports, determining each port to be tested;

[0009] Testing the devices connected to the ports to be tested to generate corresponding test folders;

[0010] Extracting corresponding test data from each test folder, and generating a test report based on the test data;

[0011] Output the test report corresponding to each downstream device.

[0012] The present application also provides a chip-mounted device testing device, comprising:

[0013] A first reading module is used to read the downstream device information of the preset chip, wherein the preset chip at least includes a plurality of ports, each port being used to connect to the downstream device;

[0014] A first determining module, configured to determine one or more ports connected to the downstream device according to the downstream device information;

[0015] A second determination module, configured to determine the ports to be tested in response to a user's selection operation on the one or more ports;

[0016] The first test module is used to test the devices connected to the ports to be tested to generate corresponding test folders;

[0017] An extraction module, used to extract corresponding test data from each test folder and generate a test report based on the test data;

[0018] The first output module is used to output the test report corresponding to each downstream device.

[0019] The present application also provides a computer device, including: a memory for storing a computer program; a processor for implementing the steps of the method for testing a device hanging down of any of the above chips when executing the computer program.

[0020] The present application also provides a computer-readable storage medium, in which a computer program is stored, wherein when the computer program is executed by a processor, the steps of the method for testing a device hanging down of any of the above-mentioned chips are implemented.

[0021] The chip downstream device testing method, apparatus, equipment and storage medium provided in the present application read the downstream device information of the preset chip; determine each port to be tested in response to the user's selection operation on one or more ports of the preset chip; test the downstream device of each port to be tested to generate a corresponding test folder; extract the corresponding test data from each test folder, and generate a test report based on the test data; output the test report corresponding to each downstream device, and only need to select each port to be tested to automatically test the downstream device of each port to be tested, without the need to manually switch the corresponding downstream device, thereby improving the testing efficiency of the downstream device. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1A schematic diagram of an application scenario of a method for testing a device mounted on a chip provided in an embodiment of the present application;

[0024] Figure 2 Schematic diagram of the process of the chip hanging device testing method provided in the embodiment of the present application Figure 1 ;

[0025] Figure 3 Schematic diagram of the process of the chip hanging device testing method provided in the embodiment of the present application Figure 2 ;

[0026] Figure 4 Schematic diagram of the process of the chip hanging device testing method provided in the embodiment of the present application Figure 3 ;

[0027] Figure 5 A schematic diagram of the structure of a chip-mounted device testing device provided in an embodiment of the present application;

[0028] Figure 6 A schematic diagram of the hardware structure of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0030] It should be noted that, in the description of this application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0031] With the development of high-speed serial computer expansion bus technology, its importance in high-performance computing, data centers, AI and other fields has become increasingly prominent. Among them, eye diagram testing is an important part. Through the oscilloscope, digital signals are accumulated and superimposed to display a graph similar to the shape of an eye, which can intuitively show the quality of the signal. Through the eye diagram, we can quickly judge the signal quality and find out the problems that may occur during signal transmission, such as whether the signal is deformed, whether the jitter is too large, and whether it is interfered with, so as to optimize the system performance and ensure that the hanging device will not make mistakes when running at high speed. In the related art, after the chip is connected to multiple hanging devices through the serial port tool, it is necessary to manually set and switch the corresponding hanging devices one by one for testing. However, in the related art, by manually setting and switching the corresponding hanging devices one by one, it is easy for the hanging devices to switch untimely, which makes the test efficiency of the hanging devices low.

[0032] In order to solve the above-mentioned technical problems, the embodiments of the present application propose the following technical concept: the inventor takes into account the downstream device information of the preset chip that is read, determines one or more ports in the preset chip that are connected to the downstream device based on the downstream device information, and obtains each port to be tested after selecting one or more ports, and uses each port to be tested to test the corresponding downstream device to generate a corresponding test report, thereby improving the testing efficiency of the downstream device.

[0033] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0034] In combination with the specific application environment architecture or specific hardware architecture on which the execution of the chip's downstream device testing method depends, the specific application environment architecture or specific hardware architecture is described herein. Figure 1 , Figure 1 This is a schematic diagram of an application scenario of a chip downstream device testing method.

[0035] like Figure 1 As shown, the scene includes: a preset chip 10, a hanging device 20, a computer device 30 and a display terminal 40.

[0036] The preset chip 10 includes a plurality of ports 101 and a standard interface 102 .

[0037] The downstream device 20 may be a single downstream device 20 or a cluster of multiple downstream devices 20, each of which is connected to a corresponding port 101. Figure 1 This is only for illustration, and not necessarily all ports 101 are connected to corresponding downstream devices 20 .

[0038] The computer device 30 may be an independent device or a cluster consisting of multiple devices.

[0039] The display terminal 40 may be a mobile phone terminal or a mobile computer terminal.

[0040] The computer device 30 reads the downstream device information of the preset chip 10 through the standard interface 102, determines one or more ports 101 connected to the downstream device 20 according to the downstream device information, and determines each port 101 to be tested in response to the user's selection operation on one or more ports 101 on the display terminal 40, tests the downstream device 20 of each port 101 to be tested to generate a corresponding test folder, extracts corresponding test data from each test folder, generates a test report according to the test data, and outputs the test report corresponding to each downstream device 20 to the display terminal 40.

[0041] Figure 2 Schematic diagram of the process of the chip hanging device testing method provided in the embodiment of the present application Figure 1 ,like Figure 2 As shown, the embodiment of the present application provides a method for testing a device mounted on a chip, and the method is described in detail as follows:

[0042] S201: Reading the downstream device information of the preset chip, wherein the preset chip at least includes a plurality of ports, each port being used to connect to the downstream device.

[0043] In this embodiment, the preset chip also includes a standard interface; accordingly, step S201 specifically includes: reading the downstream device information of the preset chip through the standard interface.

[0044] The standard interface may be an SDB interface or other interfaces; the SDB interface is an auxiliary data bus.

[0045] The preset chip may be a Switch chip or other chips; the Switch chip is a switching chip.

[0046] The downstream device information is used to indicate that one or more ports of the chip are connected to normal downstream devices.

[0047] In addition, before step S201, it also includes: generating a preset screening threshold, a preset reading number threshold, a preset file quantity threshold, a preset time interval and a cycle number in response to a setting operation of the user in the test interface.

[0048] Specifically, in response to the user's setting operation of test parameter-n in the test interface, a preset screening threshold is generated; in response to the user's setting operation of test parameter-m in the test interface, a preset reading number threshold is generated; in response to the user's setting operation of test parameter-k in the test interface, a preset file quantity threshold is generated; in response to the user's setting operation of test parameter-Wait time in the test interface, a preset time interval is generated; in response to the user's setting operation of test parameter-Times in the test interface, the number of loops is generated.

[0049] The number of cycles is used to determine the overall number of cycles for testing each downstream device.

[0050] The test interface also includes: information about the port connected to the downstream device, the speed is Gen5, and the virtual button corresponding to the test device - run.

[0051] S202: Determine one or more ports connected to the downstream device according to the downstream device information.

[0052] For example, reference Figure 1 , according to the downstream device information, determine that one or more ports connected to the downstream device are S2, S3, S5 and S6.

[0053] S203: In response to the user's selection operation on one or more ports, determine the ports to be tested.

[0054] Exemplarily, in response to the user's selection operation on S2, S3, S5 and S6 in the test interface, the ports to be tested are determined to be S2, S3, S5 and S6.

[0055] In addition, you can also select only any one port among S2, S3, S5 or S6, or you can select any two ports among S2, S3, S5 and S6. This needs to be determined based on specific needs, and there are no excessive restrictions on this.

[0056] S204: Testing the devices connected to each port to be tested to generate a corresponding test folder.

[0057] Exemplarily, the devices mounted under S2, S3, S5 and S6 are tested to generate corresponding test folders.

[0058] Among them, the downstream devices are the corresponding D2, D3, D5 and D6.

[0059] The test folder is the "s1_test1_Results" folder.

[0060] S205: extracting corresponding test data from each test folder, and generating a test report according to the test data.

[0061] In this embodiment, the test data may be data on signal transmission quality or other data.

[0062] In this embodiment, the test report may be a report in a document, table, or other text format.

[0063] S206: Output the test report corresponding to each downstream device.

[0064] Exemplarily, the test reports corresponding to D2, D3, D5 and D6 are output.

[0065] In summary, the chip downstream device testing method provided in this embodiment reads the downstream device information of the preset chip; determines each port to be tested in response to the user's selection operation on one or more ports of the preset chip; tests the downstream device of each port to be tested to generate a corresponding test folder; extracts corresponding test data from each test folder, and generates a test report based on the test data; outputs the test report corresponding to each downstream device, and only needs to select each port to be tested to automatically test the downstream device of each port to be tested, without the need to manually switch the corresponding downstream device, thereby improving the testing efficiency of the downstream device.

[0066] Figure 3 Schematic diagram of the process of the chip hanging device testing method provided in the embodiment of the present application Figure 2 In the embodiment of the present application, Figure 2 Based on the embodiment provided, the specific implementation method of testing the devices connected to each port to be tested in step S204 to generate a corresponding test folder is described in detail. Figure 3 As shown, the method includes:

[0067] S301: Obtain numbers corresponding to multiple ports.

[0068] In this embodiment, reference Figure 1 When SN is set to S9, the numbers corresponding to the S0, S1, S2, S3, S4, S5, S6, S7, S8 and S9 ports are obtained as 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9.

[0069] S302: Obtain the target number corresponding to each port to be tested.

[0070] For example, in Figure 2 Based on the corresponding embodiment, the target numbers corresponding to S2, S3, S5 and S6 are 2, 3, 5 and 6.

[0071] S303: Filter multiple numbers according to a preset sequence rule until any target number is found.

[0072] In this embodiment, the preset sequence rule is N+1, and N starts from 0, that is, the screening starts from number 0 and accumulates 1 by 1.

[0073] Exemplarily, 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9 are screened according to a preset order rule until any target number 2 is screened out.

[0074] S304: Testing the downstream device corresponding to the target number to obtain a test folder.

[0075] Specifically, step S304 includes:

[0076] S3041: In response to the user's triggering operation on the test device, the downstream device is tested and the following steps are performed:

[0077] In this embodiment, the discussion on the testing device has been described in detail in step S201 and will not be repeated here.

[0078] S3042: Determine a plurality of lines to be tested corresponding to the downstream device according to a preset file quantity threshold.

[0079] In this embodiment, the preset file quantity threshold may be any number among 11, 22, or 33, or may be another number.

[0080] In this embodiment, the calculation formula for determining the multiple lines to be tested corresponding to the downstream device according to the preset file quantity threshold includes:

[0081]

[0082] In the formula, is the number of lines to be tested; The preset file quantity threshold.

[0083] Exemplarily, 16 lines to be tested corresponding to the downstream devices are determined according to a preset file quantity threshold 33 .

[0084] S3043: Testing each circuit to be tested by using a preset test tool to obtain a corresponding image file and an image size file.

[0085] In this embodiment, the preset test tool is an eye diagram test tool; the image is an eye diagram image; and the image size is the eye height and eye width of the eye diagram image.

[0086] In addition, the eye diagram test tool can be configured to test bit error rate and measure step length.

[0087] Specifically, each circuit to be tested is tested by an eye diagram test tool, so as to obtain a corresponding eye diagram image file according to a drawing tool, and to obtain a corresponding eye diagram image size file according to a measuring tool.

[0088] Among them, the drawing tool is a digital plotter, namely iplot; the measuring tool is a measurement instruction, namely meas instruction.

[0089] S3044: Store each image file and each corresponding image size file into a test folder.

[0090] In this embodiment, the discussion about the test folder has been described in detail in step S204 and will not be repeated here.

[0091] S3045: Integrate the image files and image size files corresponding to each test line into the statistical file.

[0092] In this embodiment, the statistical file may be a statistical table, a statistical document or other statistical files.

[0093] S3046: Store the statistical file in the test folder.

[0094] In addition, after step S3046, steps a and b are also included:

[0095] Step a: Format the preset test tool to obtain a formatted test tool.

[0096] Step b: Use the formatted test tool to test the downstream device corresponding to the next target number.

[0097] In addition, after step S304, steps c to e are also included:

[0098] Step c: Obtain a preset screening threshold.

[0099] Exemplarily, since the maximum number is 9 and the maximum target number is 6, the preset screening threshold is set to 9 or 6 for screening each target number.

[0100] Step d: Continuously screen multiple numbers according to the preset screening threshold until each target number is screened.

[0101] Specifically, multiple numbers are continuously screened according to a preset screening threshold and a preset sequence rule until each target number is screened.

[0102] Step e: Test the downstream devices corresponding to each target number to obtain the corresponding test folder.

[0103] In summary, the chip downstream device testing method provided in this embodiment obtains numbers corresponding to multiple ports; obtains target numbers corresponding to each port to be tested; filters multiple numbers according to preset sequence rules until any target number is filtered out; tests the downstream device corresponding to the target number to obtain a test folder, so that the downstream device to be tested can be accurately located to detect the downstream device.

[0104] In addition, the chip downstream device testing method provided in this embodiment continuously screens multiple numbers according to a preset screening threshold until each target number is screened; the downstream devices corresponding to each target number are tested to obtain the corresponding test folder, thereby avoiding the error of manual switching of the downstream devices and improving the accuracy of the downstream device testing.

[0105] Figure 4 Schematic diagram of the process of the chip hanging device testing method provided in the embodiment of the present application Figure 3 In the embodiment of the present application, Figure 3 Based on the embodiment provided, a specific implementation method for detecting the number of files in the test folder after step S304 is described in detail. Figure 4 As shown, the method includes:

[0106] S401: Obtain numbers corresponding to multiple ports.

[0107] In this embodiment, the discussion on numbering has been described in detail in step S301 and will not be repeated here.

[0108] S402: Obtain the target number corresponding to each port to be tested.

[0109] In this embodiment, the discussion on the target number has been described in detail in step S302 and will not be repeated here.

[0110] S403: Filter the multiple numbers according to a preset sequence rule until any target number is found.

[0111] In this embodiment, the discussion on the preset sequence rule has been described in detail in step S303 and will not be repeated here.

[0112] S404: Testing the downstream device corresponding to the target number to obtain a test folder.

[0113] In this embodiment, the discussion about the test folder has been described in detail in step S204 and will not be repeated here.

[0114] S405: Read the number of files in the test folder at a preset time interval and perform a read count.

[0115] In this embodiment, the preset time interval may be 0.5 hours, 1 hour, or 2 hours, or may be other time periods.

[0116] S406: Determine whether the number of files is equal to a preset file number threshold.

[0117] In this embodiment, the discussion on the preset file quantity threshold has been described in detail in step S304 and will not be repeated here.

[0118] S407: If the number of files is equal to the preset file number threshold, output a first test result.

[0119] In this embodiment, the first test result is a test completion result.

[0120] S408: If the number of files is not equal to the preset file number threshold, repeatedly read the number of files in the test folder at a preset time interval until the number of files is equal to the preset file number threshold and / or the read count reaches the preset read count threshold to obtain a corresponding second test result.

[0121] In this embodiment, the second test result is a test completion result or a test termination result. Accordingly, step S408 specifically includes:

[0122] S4081: If the number of files is not equal to the file number threshold, repeatedly read the number of files in the test folder at a preset time interval until the number of files is equal to the preset file number threshold, so as to obtain a test completion result, wherein the read count is less than the preset read count threshold.

[0123] In this embodiment, the subsequent preset time interval can be modified as required.

[0124] In this embodiment, the preset reading times threshold may be any value among 2, 4 or 6, or other values.

[0125] S4082: If the number of files is not equal to the file number threshold, repeatedly read the number of files in the test folder at a preset time interval until the number of files is equal to the preset file number threshold and the read count reaches the preset read count threshold, so as to obtain a test completion result, wherein the read count is equal to the preset read count threshold.

[0126] S4083: If the number of files is not equal to the file number threshold, repeatedly reading the number of files in the test folder at a preset time interval until the read count reaches a preset read count threshold to obtain a test termination result, wherein the number of files is less than the file number threshold.

[0127] In this embodiment, the test termination result is used to indicate that the test program is stuck or the test ends abnormally.

[0128] S409: Output the second test result.

[0129] Specifically, step S409 is specifically: outputting a test completion result or a test termination result.

[0130] In summary, the chip downstream device testing method provided in this embodiment reads the number of files in the test folder at a preset time interval and performs a read count; determines whether the number of files is equal to the preset file number threshold; if the number of files is equal to the preset file number threshold, outputs a first test result; if the number of files is not equal to the preset file number threshold, repeatedly reads the number of files in the test folder at a preset time interval until the number of files is equal to the preset file number threshold, and / or the read count reaches the preset read count threshold, so as to obtain the corresponding second test result; outputs the second test result, so that the user can intuitively understand whether the downstream device has been tested normally, so that the user can subsequently handle the downstream device with test termination problems.

[0131] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method.

[0132] Figure 5 This is a schematic diagram of the structure of the chip hanging device testing device provided in the embodiment of the present application. Figure 5 As shown, an embodiment of the present application also provides a chip downstream device testing device, including: a first reading module 501, a first determination module 502, a second determination module 503, a first testing module 504, an extraction module 505 and a first output module 506.

[0133] A first reading module 501 is used to read the downstream device information of a preset chip, wherein the preset chip at least includes a plurality of ports, each port being used to connect to the downstream device;

[0134] A first determining module 502, configured to determine one or more ports connected to the downstream device according to the downstream device information;

[0135] A second determination module 503, configured to determine the ports to be tested in response to a user's selection operation on the one or more ports;

[0136] The first test module 504 is used to test the devices connected to the ports to be tested to generate corresponding test folders;

[0137] The extraction module 505 is used to extract the corresponding test data from each test folder and generate a test report according to the test data;

[0138] The first output module 506 is used to output the test report corresponding to each downstream device.

[0139] In a possible implementation, the testing module 504 specifically includes:

[0140] A first obtaining unit, used to obtain serial numbers corresponding to the multiple ports;

[0141] A second acquisition unit, used to acquire the target number corresponding to each port to be tested;

[0142] A screening unit, used for screening multiple numbers according to a preset sequence rule until any target number is screened;

[0143] The testing unit is used to test the downstream device corresponding to the target number to obtain a test folder.

[0144] In a possible implementation, the testing unit specifically includes:

[0145] The first testing unit is used to test the hanging device in response to the user's triggering operation on the testing device, and execute the following steps:

[0146] A determination unit, configured to determine a plurality of lines to be tested corresponding to the downstream device according to a preset file quantity threshold;

[0147] The second testing unit is used to test each circuit to be tested by using a preset testing tool to obtain a corresponding image file and an image size file;

[0148] A first storage unit, used for storing each image file and each corresponding image size file in a test folder;

[0149] An integration unit, used for integrating the image files and image size files corresponding to each test line into a statistical file;

[0150] The second storage unit is used to store the statistical file in the test folder.

[0151] In a possible implementation manner, the device further includes:

[0152] A formatting module, used for formatting the preset test tool to obtain a formatted test tool;

[0153] The second test module is used to test the downstream device corresponding to the next target number through the formatted test tool.

[0154] In a possible implementation manner, the device further includes:

[0155] A second reading module is used to read the number of files in the test folder at a preset time interval and perform a reading count;

[0156] A judging module, used to judge whether the number of files is equal to a preset file number threshold;

[0157] A second output module, configured to output a first test result if the number of files is equal to the preset file number threshold;

[0158] A third reading module is used for repeatedly reading the number of files in the test folder at the preset time interval if the number of files is not equal to the preset file number threshold, until the number of files is equal to the preset file number threshold and / or the read count reaches the preset read count threshold, so as to obtain a corresponding second test result;

[0159] The third output module is used to output the second test result.

[0160] In a possible implementation, the second test result is a test completion result or a test termination result; accordingly, the third reading module specifically includes:

[0161] A first reading unit, configured to repeatedly read the number of files in the test folder at the preset time interval if the number of files is not equal to the file number threshold, until the number of files is equal to the preset file number threshold, so as to obtain a test completion result, wherein the read count is less than the preset read count threshold;

[0162] A second reading unit is used for repeatedly reading the number of files in the test folder at the preset time interval if the number of files is not equal to the file number threshold, until the number of files is equal to the preset file number threshold and the read count reaches the preset read count threshold, so as to obtain a test completion result, wherein the read count is equal to the preset read count threshold;

[0163] The third reading unit is used to repeatedly read the number of files in the test folder at the preset time interval until the read count reaches the preset read count threshold if the number of files is not equal to the file number threshold, so as to obtain a test termination result, wherein the number of files is less than the file number threshold; accordingly, the third output module is specifically used to output the test completion result or the test termination result.

[0164] In a possible implementation, the preset chip further includes a standard interface; accordingly, the first reading module 501 is specifically configured to read the downstream device information of the preset chip through the standard interface.

[0165] For the description of the features in the embodiment corresponding to the chip-mounted device testing apparatus, reference may be made to the relevant description of the embodiment corresponding to the chip-mounted device testing method, which will not be described in detail here.

[0166] Figure 6 This is a schematic diagram of the structure of the computer device provided in this application. Figure 6 As shown, the computer device provided in this embodiment includes: at least one processor 601 and a memory 602. Optionally, the computer device also includes a communication component 603. The processor 601, the memory 602 and the communication component 603 are connected via a bus.

[0167] In a specific implementation process, at least one processor 601 executes the computer execution instructions stored in the memory 602, so that at least one processor 601 executes the above-mentioned chip downstream device testing method embodiment.

[0168] The specific implementation process of the processor 601 can be found in the above method embodiment, and its implementation principle and technical effect are similar, so this embodiment will not be repeated here.

[0169] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the method disclosed in the application may be directly implemented as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor.

[0170] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (NVM), such as at least one disk storage.

[0171] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of this application is not limited to only one bus or one type of bus.

[0172] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps in any of the above-mentioned chip-hook device testing method embodiments when running.

[0173] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0174] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in the embodiment of the method for testing a device hanging down from any of the above chips are implemented.

[0175] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, the non-volatile computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, the steps in the embodiment of the method for testing a downstream device of any of the above-mentioned chips are implemented.

[0176] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0177] The above is a detailed introduction to the chip-mounted device testing method, device, equipment and storage medium provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A method for testing a device mounted on a chip, characterized in that: include: Reading the downstream device information of the preset chip, wherein the preset chip at least includes a plurality of ports, each port being used to connect to the downstream device; Determine one or more ports connected to the downstream device according to the downstream device information; In response to a user's selection operation on the one or more ports, determining each port to be tested; Testing the devices connected to the ports to be tested to generate corresponding test folders; Extracting corresponding test data from each test folder, and generating a test report based on the test data; Output the test report corresponding to each downstream device.

2. The chip-mounted device testing method according to claim 1, characterized in that: The step of testing the downstream device of the port to be tested to generate a corresponding test folder includes: Obtaining numbers corresponding to the multiple ports; Obtaining the target number corresponding to each port to be tested; Filter multiple numbers according to the preset order rules until any target number is found; The downstream device corresponding to the target number is tested to obtain a test folder.

3. The chip-mounted device testing method according to claim 2, characterized in that: The testing of the downstream device corresponding to the target number to obtain a test folder includes: In response to the user's triggering operation on the test device, the hanging device is tested and the following steps are performed: Determine a plurality of lines to be tested corresponding to the downstream device according to a preset file quantity threshold; Test each circuit to be tested by using a preset test tool to obtain a corresponding image file and image size file; Store each image file and the corresponding image size file in a test folder; Integrate the image files and image size files corresponding to each test line into a statistical file; The statistical file is stored in the test folder.

4. The method for testing a device mounted on a chip according to claim 3, characterized in that: After storing the statistical file in the test folder, the method further includes: Formatting the preset test tool to obtain a formatted test tool; The formatted test tool is used to test the downstream device corresponding to the latter target number.

5. The method for testing a device mounted on a chip according to claim 2, characterized in that: After testing the downstream device corresponding to the target number to obtain a test folder, the method further includes: Read the number of files in the test folder at a preset time interval and perform a reading count; Determining whether the number of files is equal to a preset file number threshold; If the number of files is equal to the preset file number threshold, outputting a first test result; If the number of files is not equal to the preset file number threshold, repeatedly reading the number of files in the test folder at the preset time interval until the number of files is equal to the preset file number threshold and / or the read count reaches the preset read count threshold, so as to obtain a corresponding second test result; The second test result is outputted.

6. The chip-mounted device testing method according to claim 5, characterized in that: The second test result is a test completion result or a test termination result; Correspondingly, if the number of files is not equal to the file number threshold, the number of files in the test folder is repeatedly read at the preset time interval until the number of files is equal to the preset file number threshold, and / or the read count reaches the preset read count threshold, to obtain the corresponding test result, including: If the number of files is not equal to the file number threshold, repeatedly reading the number of files in the test folder at the preset time interval until the number of files is equal to the preset file number threshold, so as to obtain a test completion result, wherein the read count is less than the preset read count threshold; If the number of files is not equal to the file number threshold, repeatedly reading the number of files in the test folder at the preset time interval until the number of files is equal to the preset file number threshold and the read count reaches the preset read count threshold, so as to obtain a test completion result, wherein the read count is equal to the preset read count threshold; If the number of files is not equal to the file number threshold, repeatedly reading the number of files in the test folder at the preset time interval until the read count reaches the preset read count threshold, so as to obtain a test termination result, wherein the number of files is less than the file number threshold; Accordingly, outputting the second test result includes: Output the test completion result or the test termination result.

7. The method for testing a device mounted on a chip according to any one of claims 1 to 6, characterized in that: The preset chip also includes a standard interface; Accordingly, the reading of the device information of the preset chip includes: The device information of the preset chip is read through the standard interface.

8. A chip hanging device testing device, characterized in that: include: A first reading module is used to read the downstream device information of the preset chip, wherein the preset chip at least includes a plurality of ports, each port being used to connect to the downstream device; A first determining module, configured to determine one or more ports connected to the downstream device according to the downstream device information; A second determination module, configured to determine the ports to be tested in response to a user's selection operation on the one or more ports; The first test module is used to test the devices connected to the ports to be tested to generate corresponding test folders; An extraction module, used to extract corresponding test data from each test folder and generate a test report based on the test data; The first output module is used to output the test report corresponding to each downstream device.

9. A computer device, characterized in that: include: Memory for storing computer programs; A processor, used to implement the steps of the method for testing a device hanging down the chip as claimed in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method for testing a device hanging down from a chip as claimed in any one of claims 1 to 7.

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