Testing Method, Device and Storage Medium for Wafer

Abstract

The present invention provides a method, device and storage medium for testing a wafer, including: obtaining a test data file, obtaining a test data file of a wafer to be tested, testing the die to be tested of the wafer to be tested to obtain an initial test result of the wafer to be tested; determining a retest area of the wafer to be tested according to the initial test result; the retest area is determined according to the offset of the die to be tested that fails the test, and the retest area includes at least one untested die; testing the wafer to be tested according to the die information in the retest area to obtain a retest result of the wafer to be tested. During the testing process, there is no need to replace the test data file, and cyclic testing is supported. Moreover, different test die coordinates can be dynamically obtained each time, thereby shortening the testing time, reducing the hardware usage loss, and improving the accuracy of the yield rate.

Description

Technical Field

[0001] The present invention relates to the technical field of wafer testing, and in particular, to a method, device, and storage medium for testing a wafer. Background Art

[0002] At present, the semiconductor industry is developing rapidly, and the output is increasing. More and more attention is paid to the testing time, cost, and yield rate of wafers. Most of the testing methods applied in the existing technologies are single-step process testing methods. After the current test file is completed, if the test needs to be adjusted, the test file needs to be modified each time before the test operation. One set of data is obtained for each test, and the process is repeated.

[0003] However, the single-step process testing method has defects such as the immutability of the test file for each test and the need to manually modify the test file to retest. Therefore, on this premise, how to shorten the testing time, reduce the hardware usage loss, and improve the yield rate at the same time is a problem worthy of attention. Therefore, a method that can save testing time, reduce the operation process, and improve the die coverage and accuracy of wafer testing is imperative. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a method, device, and storage medium for testing a wafer, so as to shorten the testing time, reduce the hardware usage loss, and improve the accuracy of the yield rate.

[0005] In a first aspect, an embodiment of the present invention provides a method for testing a wafer. The method includes: obtaining a test data file of the wafer to be tested, testing the die to be tested of the wafer to be tested to obtain an initial test result of the wafer to be tested; determining a retest area of the wafer to be tested according to the initial test result; the retest area is determined according to the offset of the die that fails the test, and the retest area includes at least one untested die; testing the wafer to be tested according to the die information in the retest area to obtain a retest result of the wafer to be tested.

[0006] In an optional embodiment of the present application, the wafer to be tested is divided into multiple test areas, and the initial test result includes the first pass rate of the wafer to be tested and multiple second pass rates corresponding to the multiple test areas; determining the retest area of the wafer to be tested according to the initial test result includes: determining the wafer to be tested or the test area as the retest object according to the first pass rate and the multiple second pass rates; determining the retest area according to the die to be tested that fails the test in the retest object.

[0007] In an alternative embodiment of the present application, the above method for determining the retest area of the wafer to be tested based on the initial test results further includes: if the first pass rate meets the requirements and there is a retest pass rate that does not meet the requirements among multiple second pass rates, determining the test area corresponding to the retest pass rate as the retest object; determining the retest area based on the untested die to be tested in the retest object; if the first pass rate does not meet the requirements, determining the wafer to be tested as the retest object; and determining the retest area based on all the die to be tested in the retest object.

[0008] In an alternative embodiment of the present application, the above method for determining the retest area based on the untested die to be tested in the retest object includes: determining the coordinates, height, width, and offset value of the untested die to be tested based on the test data file; and determining the coordinates of the retest area based on the coordinates, height, width, and offset value of the die to be tested.

[0009] In an alternative embodiment of the present application, the above method for testing the wafer to be tested based on the die information in the retest area to obtain the retest result of the wafer to be tested further includes: judging whether to update the retest area in the retest object according to the retest result; if the retest area is updated, retesting the wafer to be tested based on the updated retest area to obtain a new retest result.

[0010] In an alternative embodiment of the present application, the above method for updating the retest area further includes: setting the retest area to be updated as the current retest area, judging whether a new retest area can be obtained by offsetting according to the current retest area, if a new retest area cannot be obtained, updating the offset parameter of the current retest area and re-judging whether a new retest area can be obtained; if a new retest area cannot be obtained according to the current retest area, updating the offset parameter of the previous retest area, and re-determining a new retest area by offsetting according to the previous retest area.

[0011] In an alternative embodiment of the present application, the above method for judging whether a new retest area can be obtained by offsetting according to the current retest area includes:

[0012] Obtaining the position information within a retest area according to the current offset parameter, and judging whether it is at the edge of the wafer and / or there is an area overlap with other retest areas.

[0013] In an alternative embodiment of the present application, the above method for judging whether to update the retest area in the retest object according to the retest result further includes: judging whether the number of die in the retest area meets the individual judgment requirement; if the number of die meets the individual judgment requirement, judging whether to update the retest area in the retest object according to the retest result of a single retest area; if the number of die does not meet the individual judgment requirement, judging whether to update the retest area in the retest object according to all the retest results in the retest object.

[0014] In an alternative embodiment of the present application, testing the wafer to be tested according to the die information of the retest area to obtain the retest result of the wafer to be tested includes: obtaining the die information of the retest area, updating the die information to the configuration file, and the die information includes at least die coordinate information; obtaining the die information of the configuration file, setting the die to be tested based on the die information, completing the retest of the wafer to be tested, and obtaining the retest result of the wafer to be tested.

[0015] In an alternative embodiment of the present application, determining the coordinates of the retest area based on the coordinates of the die to be tested, the height and width of the die, and the offset value includes: determining the coordinates of the retest area based on the coordinates of the die to be tested, the height and width of the die, and the offset value through the following formula: ; ; where and are the x coordinate and y coordinate of the lower left corner of the die in the retest area respectively, and are the offset values in the x direction and y direction respectively, and are the height and width of the die respectively, and are the x coordinate and y coordinate of the die to be tested respectively, is the step function.

[0016] In a second aspect, an embodiment of the present invention further provides a wafer testing device, including: a wafer initial testing module, configured to obtain a test data file of the wafer to be tested, test the die to be tested of the wafer to be tested, and obtain an initial test result of the wafer to be tested; a retest area determination module, configured to determine a retest area of the wafer to be tested according to the initial test result; the retest area is determined according to the offset of the die that fails the test, and the retest area includes at least one untested die; a wafer retest module, configured to test the wafer to be tested according to the die information of the retest area, and obtain a retest result of the wafer to be tested.

[0017] In a third aspect, an embodiment of the present invention further provides a computer-readable storage medium, which stores computer-executable instructions, and when the computer-executable instructions are called and executed by a processor, the computer-executable instructions cause the processor to implement the above-mentioned wafer testing method.

[0018] The embodiments of the present invention bring the following beneficial effects:

[0019] An embodiment of the present invention provides a method, apparatus, and storage medium for testing a wafer. Obtain a test data file, obtain the test data file of the wafer to be tested, test the die to be tested on the wafer to be tested, and obtain the initial test result of the wafer to be tested; determine the retest area of the wafer to be tested according to the initial test result, and the retest area includes at least one untested die; test the wafer to be tested according to the die information in the retest area to obtain the retest result of the wafer to be tested. In this way, during the testing process, it is possible to support loop testing without replacing the test data file, and different test die coordinates can be dynamically obtained each time, thereby shortening the testing time, reducing the hardware usage loss, and improving the accuracy of the yield rate.

[0020] Other features and advantages of the present disclosure will be described in the following description, or some features and advantages can be inferred from the description or determined without doubt, or can be learned by implementing the above technologies of the present disclosure.

[0021] To make the above objects, features, and advantages of the present disclosure more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, is described in detail as follows. Description of the Drawings

[0022] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0023] Figure 1 A flowchart of a method for testing a wafer provided by an embodiment of the present invention;

[0024] Figure 2 A flowchart of another method for testing a wafer provided by an embodiment of the present invention;

[0025] Figure 3 A schematic diagram of dividing a wafer to be tested into several test areas provided by an embodiment of the present invention;

[0026] Figure 4 A schematic diagram of retesting area 1 provided by an embodiment of the present invention;

[0027] Figure 5 A schematic diagram of a method for testing a wafer provided by an embodiment of the present invention;

[0028] Figure 6 A schematic structural diagram of a wafer testing apparatus provided by an embodiment of the present invention;

[0029] Figure 7 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. Detailed implementation manners

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Apparently, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0031] Currently, the semiconductor industry is developing rapidly, with increasing production. More and more attention is paid to the test time, cost, and yield of wafers. Most of the test methods applied in the prior art are single-step process test methods. After the current test file is tested, if the test needs to be adjusted, the test file needs to be modified each time before the test operation. One set of data is obtained for each test, and the process is repeated. Or only the untested dies that fail the test can be repeatedly tested. However, when the wafer fab generally obtains unsatisfactory first test results, it needs to test other untested wafers to increase the data sample size for analyzing more problems. At this time, the test file needs to be modified each time before the test operation. Under such circumstances, how to shorten the test time, reduce the hardware usage loss, and improve the yield is a problem worthy of attention. Therefore, a method that can save test time, reduce the operation process, and at the same time improve the die coverage and accuracy of wafer testing is imperative.

[0032] However, the prior art has the following defects:

[0033] 1) Based on most current wafer test processes, the test file for each test remains immutable, which is not flexible enough, and the obtained data results are also relatively single. To obtain flexible data results for comparative observation or general conclusions, the test file needs to be replaced in a timely manner and compared with a certain correct standard.

[0034] 2) In the prior art, the retest function needs to be enabled under certain specific conditions (only the previously set dies can be retested, and un-set dies cannot be covered for testing). However, this method is too customized, and retesting is not allowed if the specific conditions are not met. At the same time, it increases the code complexity and requires the introduction of complex code logic.

[0035] 3) In the prior art, if you want to dynamically obtain the test DIE coordinates for testing, you need to stop the current test and manually modify the test file to achieve the purpose of modifying the test area, and the operation is still not flexible enough.

[0036] Based on this, a wafer testing method, device, and storage medium provided by embodiments of the present invention can support loop testing without the need to replace the test data file during the testing process, and different test DIE coordinates can be dynamically obtained for each test, thereby shortening the testing time, reducing the wear and tear of hardware usage, and improving the accuracy of the yield rate.

[0037] To facilitate the understanding of this embodiment, a wafer testing method disclosed by embodiments of the present invention will be introduced in detail first.

[0038] Embodiment 1:

[0039] Embodiments of the present invention provide a wafer testing method. Refer to Figure 1 the flowchart of a wafer testing method shown. The wafer testing method includes the following steps:

[0040] Step S102, obtain the test data file of the wafer to be tested, test the bare die of the wafer to be tested, and obtain the initial test result of the wafer to be tested.

[0041] In this embodiment, the test data file of the wafer to be tested can be obtained. The attributes of the wafer to be tested are preset in the test data file, including numerical values such as wafer size, quadrant, center coordinates, width and height of the bare die, offset value, etc. After obtaining the test data file, the software and hardware test environments for testing can be deployed in this embodiment.

[0042] Step S104, determine the retest area of the wafer to be tested according to the initial test result. The retest area includes at least one untested bare die.

[0043] In this embodiment, it can be determined whether the requirements are met according to the initial test result of the wafer to be tested. If the initial test result does not meet the requirements, other bare dies need to be selected for retesting, that is, retesting. If retesting is required, in this embodiment, the retest area of the wafer to be tested can be determined according to the initial test result first, and then untested bare dies are selected from the retest area for retesting.

[0044] Specifically, the retest area is determined according to the offset of the untested bare die to be tested, and untested bare dies are re-obtained and tested around the untested bare die to be tested.

[0045] Step S106, test the wafer to be tested according to the bare die information in the retest area, and obtain the retest result of the wafer to be tested.

[0046] This embodiment can perform re - testing on the wafer to be tested based on the die information in the re - testing area, and use the pass rate of the untested dies in the re - testing area as the re - testing result. If the re - testing result still does not meet the requirements, this embodiment can re - select the re - testing area for another re - testing, and loop multiple times until the re - testing result meets the requirements or no re - testing area can be obtained.

[0047] If the re - testing result meets the requirements, it indicates that the testing is completed. In this embodiment, more diverse sampling test data can be obtained based on the initial test result and the re - testing result. Therefore, this embodiment supports dynamically obtaining die coordinates for re - testing, and there is no need to replace the test data file during the testing process. At the same time, it saves part of the operation time at both the software and hardware levels, increases the diversity of test data, and greatly improves the accuracy of the yield rate.

[0048] An embodiment of the present invention provides a method for testing a wafer, which includes obtaining a test data file, obtaining the test data file of the wafer to be tested, testing the dies to be tested on the wafer to be tested to obtain the initial test result of the wafer to be tested; determining the re - testing area of the wafer to be tested according to the initial test result, where the re - testing area includes at least one untested die; and testing the wafer to be tested according to the die information in the re - testing area to obtain the re - testing result of the wafer to be tested. In this way, during the testing process, it is possible to support loop testing without replacing the test data file, and different test die coordinates can be dynamically obtained each time, thereby shortening the testing time, reducing the hardware usage loss, and improving the accuracy of the yield rate.

[0049] Embodiment Two:

[0050] This embodiment provides another method for testing a wafer, which is implemented based on the above - mentioned embodiment. Refer to Figure 2 the flowchart of another method for testing a wafer shown in

[0051] Step S202: Obtain the test data file of the wafer to be tested, test the dies to be tested on the wafer to be tested, and obtain the initial test result of the wafer to be tested.

[0052] Among them, the above - mentioned test data file includes the wafer attributes of the wafer to be tested and the information of the test dies; the wafer attributes include at least one of the following: wafer size, number of regions, height and width of the die, coordinates of the central die of the wafer, coordinates of the dies to be tested on the wafer; the information of the test dies includes offset values.

[0053] In this embodiment, the wafer attributes of the wafer to be tested and the information of related test dies can be preset in the test data file. This setting can be used as the data for the initial test during the test process. Once set, the preset information does not need to be changed during subsequent retesting. After this embodiment, the test environment can be prepared, and the software and hardware test environments can be deployed.

[0054] In this embodiment, the test data file can be used for testing. Among them, corresponding parameters can be set, and after the deployment is completed, the test is started. Among them, the number of regions can be determined to be n based on the test data file. Where n is a positive integer greater than or equal to 1; the wafer is divided into n test regions, and dies are selected from each region for testing based on the test data file and the test environment to determine the test data for this time.

[0055] Reference can be made to Figure 3 the schematic diagram showing a method of dividing the wafer to be tested into several test regions as shown in Figure 3 in which the wafer to be tested is divided into 4 test regions (i.e., n = 4). In subsequent tests, dies can be randomly selected for testing in each test region to prevent the selection of test dies from being too concentrated.

[0056] Step S204, determining the retest region of the wafer to be tested according to the initial test result; the retest region is determined according to the offset of the dies that fail the test, and the retest region includes at least one untested die.

[0057] In some embodiments, the wafer to be tested is divided into multiple test regions, and the initial test result includes the first pass rate of the wafer to be tested and multiple second pass rates corresponding to the multiple test regions; based on the first pass rate and the multiple second pass rates, determining the wafer to be tested or the test region as the retest object; determining the retest region according to the dies that fail the test in the retest object.

[0058] The initial test result in this embodiment can include the first pass rate of the entire wafer to be tested and multiple second pass rates corresponding to each test region of the wafer to be tested. By dividing the wafer into multiple test regions, only the test regions that do not meet the requirements can be retested separately; the division mode of the test regions is determined according to the test requirements. For example, it can also be divided into five rings, and the offset rule is determined according to the division mode. The division mode can be selected by the user or automatically determined according to the test content.

[0059] Among them, standard test data can be obtained; based on the initial test data and the standard test data, it is determined whether the dies in this test are qualified, so as to determine the second pass rate of the dies in each test region and the first pass rate of the entire wafer to be tested.

[0060] This embodiment can obtain initial test data after executing test cases (the test data file may include test cases, and the test cases include information about relevant test dies and information on how to conduct the tests), and compare the initial test data with the standard test data to determine whether each die is qualified.

[0061] Among them, before the test, this embodiment can first test the data of all dies on a standard wafer to obtain a standard correct data file, that is, the above-mentioned standard test data. During the test, this embodiment can test the dies in different test areas to obtain initial test data, and compare the initial test data with the standard test data to determine whether the dies in each area are qualified.

[0062] After determining whether each die is qualified, this embodiment can further determine the retest object. Among them, the retest object can be the entire wafer to be tested, or one or several test areas of the wafer to be tested.

[0063] In some embodiments, if the first pass rate meets the requirements and there is a retest pass rate that does not meet the requirements among multiple second pass rates, then determine the test area corresponding to the retest pass rate as the retest object; according to the unqualified dies to be tested in the retest object, determine the retest area; if the first pass rate does not meet the requirements, then determine the wafer to be tested as the retest object; according to all the dies to be tested in the retest object, determine the retest area.

[0064] For example, after determining whether each die is qualified, this embodiment can further determine the first pass rate of all test areas of the wafer to be tested. If the first pass rate does not meet the requirements, it means that all test areas of the wafer to be tested need to be retested. The retest object at this time can be all test areas of the wafer to be tested.

[0065] Or, if the first pass rate meets the requirements, this embodiment can further determine the second pass rate of each test area of the wafer to be tested. If the second pass rate of the test object and / or the target area does not meet the requirements, it means that the target area needs to be retested. The retest object at this time can be the target area.

[0066] After determining the retest object, this embodiment can further determine the retest area of the retest object. In this embodiment, the retest area can be selected around the unqualified dies of the retest object, and a specified number of dies in the retest area are retested, and then the retest test data is compared with the standard test data to determine whether the dies in the retest area to be tested are qualified. It should be noted that if the wafer to be tested is the retest object, the retest area may only include one untested die offset according to the wafer to be tested.

[0067] In some embodiments, the coordinates of the die under test that fails the test, the height and width of the die, and the offset value can be determined based on the test data file; the coordinates of the retest area can be determined based on the coordinates of the die under test, the height and width of the die, and the offset value.

[0068] Among them, taking a certain area under test as an example of the test object. In this embodiment, the number of dies to be retested (assumed to be 9) can be determined first, and the size of the area under test (3×3) can be determined based on the number of dies to be retested. According to the visual contrast analysis function, the non-conforming dies in the area under test can be determined, and the above-mentioned size (3×3) anchor box can be set around the non-conforming dies, and the new die coordinates within the anchor box can be obtained for retesting (i.e., re-testing). If the qualified rate of the re-testing is still less than the threshold, the position of the anchor box can be cyclically moved to re-test again until the range of the anchor box exceeds the wafer under test. At this time, the part of the anchor box that exceeds the wafer under test is not tested, and the part of the anchor box that does not exceed the wafer is tested.

[0069] For example, referring to Figure 4 a schematic diagram of re-testing area 1 as shown. Assume that 10 dies are selected for testing in area 1, and 2 dies are found to be unqualified in the first test (the threshold of the qualified rate is defined as 90%, and the qualified rate of the first test is 80% < threshold 90%). When re-testing, it is necessary to first determine the size of the anchor box ( Figure 4 which is 2×3 in the figure), and re-test the 6 dies in the re-testing anchor box. If only 2 dies are qualified among the 6 dies re-tested, the qualified rate of the re-testing is 33.33% < threshold 90%, and it is still necessary to re-select the anchor box for re-testing.

[0070] Among them, the coordinates of the retest area can be determined based on the coordinates of the die under test, the height and width of the die, and the offset value through the following formula:

[0071] ;

[0072] ;

[0073] Among them, and are the x coordinate and y coordinate of the lower left corner of the die in the retest area respectively, and are the offset values in the x direction and y direction respectively, and are the height and width of the die respectively, and are the x coordinate and y coordinate of the die under test respectively, is the step function.

[0074] Among them, the x coordinate of the lower left corner of the anchor box needs to be re-determined every time of re-testing and the y coordinate . The first time the retest and The x-coordinate and y-coordinate of the lower left corner of the die to be tested can be used for retesting after the second time. and They can be the x-coordinate and y-coordinate of the lower left corner of the anchor box during the previous remeasurement.

[0075] In some embodiments, it can also be determined whether to update the retest area in the retest object based on the retest result; if the retest area is updated, the wafer to be tested is tested again based on the updated retest area to obtain a new retest result.

[0076] If the retest results of the wafer to be tested (which can be the qualified rate of a single retest area or all retest areas) still do not meet the requirements, retesting is required. At this time, the retest area needs to be updated in the retest object; the wafer to be tested is tested again based on the updated retest area to obtain a new retest result.

[0077] See also Figure 5 The schematic diagram of a wafer testing method shown in the figure shows that if the qualified rate is less than the threshold value after the initial test, retesting is required. Each retesting requires moving the anchor frame to determine the qualified rate of the bare die in the anchor frame until the qualified rate of the bare die in the retested anchor frame is greater than or equal to the threshold value, then the cyclic retesting ends, and the final test result of the wafer can be determined based on the initial test result and the retest result. At the same time, the present embodiment can also mark the retest result in the final test result.

[0078] In some embodiments, updating the resurvey area may be performed as follows: the resurvey area to be updated is set as the current resurvey area, and it is determined whether a new resurvey area can be obtained by offsetting based on the current resurvey area; if a new resurvey area cannot be obtained, the offset parameters of the current resurvey area are updated to re-determine whether a new resurvey area can be obtained; if a new resurvey area cannot be obtained based on the current resurvey area, the offset parameters of the previous resurvey area are updated, and the new resurvey area is determined by re-offsetting based on the previous resurvey area.

[0079] Among them, the current retest area is obtained based on the offset parameter of the previous retest area. When the current retest area needs to be updated, in the case where there is a new retest area at the edge or overlapping with other retest areas, to ensure the quality of the acquired data, it will first be determined whether a retest area that meets the requirements can be obtained. If not, the offset parameter will be updated (for example, the offset direction will be updated. For example, if the four corners are set as the offset directions, different angular offset parameters can be obtained and updated in sequence clockwise or counterclockwise; of course, the offset parameter can be a combination of one or both of the offset direction and the offset amount). If a retest area that meets the requirements cannot be obtained around the current retest area, a new retest area can also be obtained by updating the offset parameter of the previous retest area.

[0080] In some embodiments, determining whether a new retest area can be offset based on the current retest area includes: obtaining the position information within a retest area according to the current offset parameter, and determining whether it is at the edge of the wafer and / or there is an area overlap with other retest areas.

[0081] In some embodiments, when determining whether to update the retest area in the retest object according to the retest result, it can be simply determined according to the yield rate of the retest result, or it can be comprehensively determined in combination with the die data within the retest area. For example: it can be determined whether the number of dies within the retest area meets the individual judgment requirements; if the number of dies meets the individual judgment requirements, it is determined whether to update the retest area in the retest object according to the retest result of a single retest area; if the number of dies does not meet the individual judgment requirements, it is determined whether to update the retest area in the retest object according to all the retest results in the retest object.

[0082] After updating the retest area, this embodiment can also determine whether the number of dies within the retest area meets the individual judgment requirements. For example, the judgment requirement can be that there are 10 untested dies within the retest area for each retest.

[0083] If the number of untested dies within the retest area is greater than or equal to 10, it is considered that the retest area at this time meets the judgment requirements, and it can be determined whether to update the retest area in the retest object according to the retest result of a single retest area. If the number of untested dies within the retest area is less than 10, it is considered that the retest area at this time does not meet the judgment requirements, and it can be determined whether to update the retest area in the retest object according to all the retest results in the retest object.

[0084] Step S206, obtain the die information of the retest area, update the die information to the configuration file, and the die information includes at least die coordinate information; obtain the die information of the configuration file, set the die to be tested based on the die information, complete the retest of the wafer to be tested and obtain the retest result of the wafer to be tested.

[0085] When performing re - testing, the die information of the re - testing area can be obtained and updated to the configuration file. The die information includes at least die coordinate information; obtain the die information in the configuration file, set it as the die to be tested, complete the re - testing of the wafer to be tested, and thus obtain the re - testing result of the wafer to be tested.

[0086] The above - mentioned wafer testing method provided by the embodiments of the present invention has the following advantages:

[0087] 1) Reduce time cost: In previous tests, if different test dies need to be tested or re - tested in a specified scenario, the test needs to be aborted, the test data needs to be manually changed, and the machine operation needs to be stopped. This will consume a large amount of test time during mass production and the operation is also relatively cumbersome. The above - mentioned method provided by the embodiments of the present invention can support multiple loop tests without changing the test data file, and different test dies can be selected for each test, thus reducing the time cost in operation.

[0088] 2) Improve the accuracy of the good product rate: In traditional sampling tests, the test data is relatively single, the test data is too concentrated, and the coverage rate is small. The above - mentioned method provided by the embodiments of the present invention can diversify the test samples, make the test data richer, and improve the accuracy of the good product rate.

[0089] 3) Wide range of applicable scenarios: The rule of using a moving anchor box for loop re - testing in this invention is not only applied to WAT (Wafer Acceptance Test) testers and WLR (Wafer Level Reliability Testing) testers, but also supports various types of wafer tests, with a wide range of applicable scenarios.

[0090] Embodiment Three:

[0091] Corresponding to the above - mentioned method embodiment, the embodiments of the present invention provide a wafer testing device. Refer to Figure 6 the structural schematic diagram of a wafer testing device shown. The wafer testing device includes:

[0092] A wafer initial testing module 61, configured to obtain a test data file of the wafer to be tested, test the die to be tested of the wafer to be tested, and obtain an initial test result of the wafer to be tested;

[0093] A re - testing area determination module 62, configured to determine the re - testing area of the wafer to be tested according to the initial test result; the re - testing area is determined according to the offset of the die that fails the test, and the re - testing area includes at least one untested die;

[0094] A wafer re - testing module 63, configured to test the wafer to be tested according to the die information in the re - testing area, and obtain a re - testing result of the wafer to be tested.

[0095] An embodiment of the present invention provides a test device for a wafer, which obtains a test data file, obtains a test data file of a wafer to be tested, tests the die to be tested on the wafer to be tested, and obtains an initial test result of the wafer to be tested; determines a retest area of the wafer to be tested according to the initial test result, where the retest area includes at least one untested die; and tests the wafer to be tested according to the die information in the retest area, and obtains a retest result of the wafer to be tested. In this way, during the test process, it is possible to support cyclic testing without replacing the test data file, and different test die coordinates can be dynamically obtained each time, thereby shortening the test time, reducing the hardware usage loss, and improving the accuracy of the yield rate.

[0096] The above-mentioned wafer to be tested is divided into multiple test areas, and the initial test result includes the first pass rate of the wafer to be tested and multiple second pass rates corresponding to the multiple test areas; the above-mentioned retest area determination module is used to determine the wafer to be tested or the test area as the retest object according to the first pass rate and the multiple second pass rates; and determine the retest area according to the die to be tested that fails the test in the retest object.

[0097] The above-mentioned retest area determination module is further used to, if the first pass rate meets the requirements and there is a retest pass rate that does not meet the requirements among the multiple second pass rates, determine the test area corresponding to the retest pass rate as the retest object; determine the retest area according to the die to be tested that fails the test in the retest object; if the first pass rate does not meet the requirements, determine the wafer to be tested as the retest object; and determine the retest area according to all the die to be tested in the retest object.

[0098] The above-mentioned retest area determination module is used to determine the coordinates, height and width, and offset value of the die to be tested that fails the test based on the test data file; and determine the coordinates of the retest area based on the coordinates, height and width, and offset value of the die to be tested.

[0099] The above-mentioned retest area determination module is further used to judge whether to update the retest area in the retest object according to the retest result; if the retest area is updated, the wafer to be tested is tested again based on the updated retest area, and a new retest result is obtained.

[0100] The above-mentioned retest area determination module is further used to set the retest area to be updated as the current retest area, judge whether a new retest area can be obtained by offsetting according to the current retest area, if a new retest area cannot be obtained, update the offset parameter of the current retest area and judge again whether a new retest area can be obtained; if a new retest area cannot be obtained according to the current retest area, update the offset parameter of the previous retest area, and re-offset according to the previous retest area to determine a new retest area.

[0101] The above re - measurement area determination module is further configured to obtain the position information within a re - measurement area according to the current offset parameter, and determine whether it is at the wafer edge and / or there is an area overlap with other re - measurement areas.

[0102] The above re - measurement area determination module is configured to determine whether the number of dies within the re - measurement area meets the individual judgment requirement; if the number of dies meets the individual judgment requirement, then determine whether to update the re - measurement area in the re - measurement object according to the re - measurement result of a single re - measurement area; if the number of dies does not meet the individual judgment requirement, then determine whether to update the re - measurement area in the re - measurement object according to all the re - measurement results in the re - measurement object.

[0103] The above re - measurement area determination module is configured to obtain the die information of the re - measurement area, update the die information to the configuration file, and the die information at least includes die coordinate information; obtain the die information of the configuration file, set the die to be measured based on the die information, complete the re - measurement of the wafer to be measured and obtain the re - measurement result of the wafer to be measured.

[0104] The above re - measurement area determination module is configured to determine the coordinates of the re - measurement area based on the coordinates of the die to be measured, the height and width of the die, and the offset value through the following arithmetic formula: ; ; where and are respectively the x - coordinate and y - coordinate of the lower - left corner of the die in the re - measurement area, and are respectively the offset values in the x - direction and y - direction, and are respectively the height and width of the die, and are respectively the x - coordinate and y - coordinate of the die to be measured, is the step function.

[0105] Those skilled in the art can clearly understand that for the convenience and conciseness of description, the specific working process of the above - described wafer testing device can refer to the corresponding process in the embodiment of the wafer testing method described above, and will not be elaborated here.

[0106] Embodiment Four:

[0107] The embodiment of the present invention further provides an electronic device for running the above - described wafer testing method; refer to Figure 7 the structural schematic diagram of an electronic device shown. The electronic device includes a memory 100 and a processor 101. Among them, the memory 100 is used to store one or more computer instructions, and the one or more computer instructions are executed by the processor 101 to implement the above - described wafer testing method.

[0108] Furthermore, Figure 7The electronic device shown also includes a bus 102 and a communication interface 103. The processor 101, the communication interface 103, and the memory 100 are connected via the bus 102.

[0109] Among them, the memory 100 may include high-speed random access memory (RAM), and may also include non-volatile memory, such as at least one disk memory. The communication connection between this system network element and at least one other network element is realized through at least one communication interface 103 (which can be wired or wireless). The Internet, wide area network, local area network, metropolitan area network, etc. can be used. The bus 102 can be an ISA bus, a PCI bus, an EISA bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of simplicity of representation, Figure 7 only a bidirectional arrow is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0110] The processor 101 may be an integrated circuit chip with signal processing capabilities. In the implementation process, the steps of the above method can be completed by the integrated logic circuit in the hardware of the processor 101 or instructions in software form. The above-mentioned processor 101 can be a general-purpose processor, including a central processing unit (CPU for short), a network processor (NP for short), etc.; it can also be a digital signal processor (DSP for short), an application specific integrated circuit (ASIC for short), a field-programmable gate array (FPGA for short), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in combination with the embodiments of the present invention can be directly embodied as being executed and completed by a hardware decoding processor, or executed and completed by a combination of hardware and software modules in the decoding processor. The software module can be located in a mature storage medium in the art such as random access memory, flash memory, read-only memory, programmable read-only memory, or electrically erasable programmable memory, registers, etc. This storage medium is located in the memory 100, and the processor 101 reads the information in the memory 100 and combines its hardware to complete the steps of the method in the foregoing embodiments.

[0111] An embodiment of the present invention also provides a computer-readable storage medium storing computer-executable instructions, which, when called and executed by a processor, cause the processor to implement the above-mentioned wafer testing method. For specific implementation, reference may be made to the method embodiment and will not be elaborated herein.

[0112] The computer program product of the wafer testing method, device, and storage medium provided by the embodiments of the present invention includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the methods in the foregoing method embodiments. For specific implementation, reference may be made to the method embodiments and will not be elaborated herein.

[0113] Those skilled in the art can clearly understand that for the convenience and conciseness of description, the specific working processes of the above-described system and / or device can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0114] In addition, in the description of the embodiments of the present invention, unless otherwise clearly specified and limited, the terms "installation", "connection", and "coupling" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0115] If a function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program code.

[0116] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present invention. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0117] Finally, it should be noted that the above-described embodiments are only specific embodiments of the present invention, used to illustrate the technical solutions of the present invention, rather than limiting it. The protection scope of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: any person skilled in the art within the technical scope disclosed by the present invention can still modify the technical solutions recorded in the foregoing embodiments or can easily think of changes, or perform equivalent replacements on some of the technical features; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A method for testing a wafer, characterized in that, The method includes: Obtaining a test data file of a wafer to be tested, testing die to be tested on the wafer to be tested, and obtaining an initial test result of the wafer to be tested; Determining a retest area of the wafer to be tested according to the initial test result; the retest area is determined according to the offset of the die to be tested that fails the test, and the retest area includes at least one untested die; Testing the wafer to be tested according to the die information in the retest area, and obtaining a retest result of the wafer to be tested; The wafer to be tested is divided into multiple test areas, and the initial test result includes the first pass rate of the wafer to be tested and multiple second pass rates corresponding to the multiple test areas; determining the retest area of the wafer to be tested according to the initial test result includes: determining the wafer to be tested or the test area as a retest object according to the first pass rate and the multiple second pass rates; determining the retest area according to the die to be tested that fails the test in the retest object; Determining the retest area of the wafer to be tested according to the initial test result includes: if the first pass rate meets the requirements and there is a retest pass rate that does not meet the requirements among the multiple second pass rates, determining the test area corresponding to the retest pass rate as the retest object; determining the retest area according to the die to be tested that fails the test in the retest object; if the first pass rate does not meet the requirements, determining the wafer to be tested as the retest object; determining the retest area according to all the die to be tested in the retest object.

2. The test method according to claim 1, wherein Determining the retest area according to the die to be tested that fails the test in the retest object includes: Based on the test data file, determining the coordinates, height and width, and offset value of the die to be tested that fails the test; Based on the coordinates of the die to be tested, the height and width of the die, and the offset value, determining the coordinates of the retest area.

3. The test method according to claim 1, characterized in that, Testing the wafer to be tested according to the die information in the retest area, and obtaining a retest result of the wafer to be tested, further includes: Judging whether to update the retest area in the retest object according to the retest result; If the retest area is updated, testing the wafer to be tested again based on the updated retest area, and obtaining a new retest result.

4. The test method according to claim 3, wherein If the retest area is updated, it further includes: Setting the retest area to be updated as the current retest area, judging whether a new retest area can be obtained by offset according to the current retest area, if a new retest area cannot be obtained, updating the offset parameter of the current retest area and re-judging whether a new retest area can be obtained; If a new retest area cannot be obtained according to the current retest area, updating the offset parameter of the previous retest area, and re-determining a new retest area by offset according to the previous retest area.

5. The testing method according to claim 3, characterized in that Judging whether a new retest area can be obtained by offset according to the current retest area includes: Obtaining the position information in a retest area according to the current offset parameter, and judging whether it is at the edge of the wafer and / or there is an area overlap with other retest areas.

6. The test method according to claim 3, characterized in that, Judging whether to update the retest area in the retest object according to the retest result, further includes: Judging whether the number of die in the retest area meets the requirement for separate judgment; If the number of dies meets the individual judgment requirement, determine whether to update the retest area in the retest object according to the retest result of a single retest area; If the number of dies does not meet the individual judgment requirement, determine whether to update the retest area in the retest object according to all the retest results in the retest object.

7. The testing method according to claim 1, characterized in that, Test the to-be-tested wafer according to the die information of the retest area to obtain the retest result of the to-be-tested wafer, including: Obtain the die information of the retest area, and update the die information to the configuration file. The die information includes at least die coordinate information; Obtain the die information of the configuration file, set the to-be-tested die based on the die information, complete the retest of the to-be-tested wafer, and obtain the retest result of the to-be-tested wafer.

8. The method according to claim 2, wherein Determine the coordinates of the retest area based on the coordinates of the to-be-tested die, the height and width of the die, and the offset value, including: Determine the coordinates of the retest area through the following formula based on the coordinates of the to-be-tested die, the height and width of the die, and the offset value: ； ； in, and are the x-coordinate and y-coordinate of the lower left corner of the die in the retest area, and are the offset values ​​in the x and y directions respectively, and are the height and width of the die, respectively, and are the x-coordinate and y-coordinate of the die to be tested, is a step function.

9. A test device for a wafer, characterized in that, The device includes: A wafer initial test module, configured to obtain a test data file of a to-be-tested wafer, test the to-be-tested die of the to-be-tested wafer, and obtain the initial test result of the to-be-tested wafer; A retest area determination module, configured to determine the retest area of the to-be-tested wafer according to the initial test result; the retest area is determined according to the offset of the to-be-tested die that fails the test, and the retest area includes at least one untested die; A wafer retest module, configured to test the to-be-tested wafer according to the die information of the retest area to obtain the retest result of the to-be-tested wafer; The to-be-tested wafer is divided into multiple test areas. The initial test result includes the first pass rate of the to-be-tested wafer and multiple second pass rates corresponding to the multiple test areas; the retest area determination module is configured to determine the to-be-tested wafer or the test area as the retest object according to the first pass rate and the multiple second pass rates; determine the retest area according to the to-be-tested die that fails the test in the retest object; The retest area determination module is configured to, if the first pass rate meets the requirement and there is a retest pass rate that does not meet the requirement among the multiple second pass rates, determine the test area corresponding to the retest pass rate as the retest object; determine the retest area according to the to-be-tested die that fails the test in the retest object; if the first pass rate does not meet the requirement, determine the to-be-tested wafer as the retest object; determine the retest area according to all the to-be-tested dies in the retest object.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions. When the computer-executable instructions are called and executed by a processor, the computer-executable instructions cause the processor to implement the wafer test method according to any one of claims 1 to 8.

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