Ultrasonic signal processing circuit and electronic equipment

Abstract

The invention provides an ultrasonic signal processing circuit and electronic equipment, and relates to the technical field of electronics. An ultrasonic signal processing circuit includes: an amplitude limiting circuit for controlling a voltage of an input signal within a first threshold; the first amplification circuit is used for amplifying the input signal processed by the amplitude limiting circuit based on a preset first gain; the first filter circuit is used for filtering the input signal processed by the first amplification circuit; the second amplification circuit is used for determining a second gain based on the received first digital control signal and amplifying the input signal processed by the first filter circuit based on the second gain; the second filter circuit is used for filtering the input signal processed by the second amplification circuit; and the analog-to-digital conversion circuit is used for converting the input signal processed by the second filter circuit into a digital signal. The ultrasonic signal processing circuit disclosed by the invention can meet the requirements of an ultrasonic radar on performance indexes such as low noise, high gain and wide frequency band.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic technology, and in particular to an ultrasonic signal processing circuit and an electronic device. Background Art

[0002] Ultrasonic radar is widely used in many fields such as automobiles, scientific research instruments, industrial automation, etc. Its core component is ultrasonic sensor. The ultrasonic signal output by ultrasonic sensor is usually weak and easily interfered by noise, so it needs to be amplified and filtered. Traditional ultrasonic signal processing circuits are difficult to meet the requirements of ultrasonic radar for low noise, high gain, wide bandwidth and other performance indicators. Specifically: the noise performance is poor and it is difficult to meet the needs of low-frequency ultrasonic signal reception; the gain control accuracy is not high and accurate gain adjustment cannot be achieved; the gain jump transient response time is long, which affects the processing speed of ultrasonic signals. Summary of the invention

[0003] The present disclosure provides an ultrasonic signal processing circuit and an electronic device to at least solve the above technical problems existing in the prior art.

[0004] According to a first aspect of the present disclosure, an ultrasonic signal processing circuit is provided, the circuit comprising: a limiter circuit, for controlling the voltage of an input signal within a first threshold value, the input end of the limiter circuit being used to receive the input signal, and the output end of the limiter circuit being connected to the input end of a first amplifier circuit; a first amplifier circuit, for amplifying the input signal processed by the limiter circuit based on a first gain set in advance, and the output end of the first amplifier circuit being connected to the input end of a first filter circuit; a first filter circuit, for filtering the input signal processed by the first amplifier circuit, and the output end of the first filter circuit being connected to the input end of a second amplifier circuit; a second amplifier circuit, for determining a second gain based on a received first digital control signal, and amplifying the input signal processed by the first filter circuit based on the second gain, and the output end of the second amplifier circuit being connected to the input end of the second filter circuit; a second filter circuit, for filtering the input signal processed by the second amplifier circuit, and the output end of the second filter circuit being connected to the input end of an analog-to-digital conversion circuit; an analog-to-digital conversion circuit, for converting the input signal processed by the second filter circuit into a digital signal, and the output end of the analog-to-digital conversion circuit being used to output the digital signal.

[0005] In one possible implementation, the limiting circuit includes a clamping diode, and the limiting circuit is further used to: if the voltage of the input signal is greater than the first threshold, control the clamping diode to conduct so that the voltage of the input signal flows to the target component through the clamping diode, and the target component does not belong to the ultrasonic signal processing circuit.

[0006] In one possible implementation manner, the first amplification circuit includes: a level conversion circuit, which is used to convert the received second digital control signal into a control voltage, and the control voltage is used to drive the first common-mode voltage driving circuit and the second common-mode voltage driving circuit, and the two output terminals of the level conversion circuit are respectively connected to the input terminals of the first common-mode voltage driving circuit and the second common-mode voltage driving circuit; a first common-mode voltage driving circuit, which is used to determine the first common-mode voltage based on the control voltage, and the output terminal of the first common-mode voltage driving circuit is connected to the first input terminal of the cascade amplifier; a second common-mode voltage driving circuit, which is used to determine the second common-mode voltage based on the control voltage, and the output terminal of the second common-mode voltage driving circuit is connected to the second input terminal of the cascade amplifier; a cascade amplifier, which is used to amplify the input signal processed by the limiting circuit based on the first common-mode voltage and the second common-mode voltage, and the third input terminal of the cascade amplifier is used to receive the input signal processed by the limiting circuit, and the output terminal of the cascade amplifier is connected to the input terminal of the first filtering circuit.

[0007] In one possible implementation manner, the analog-to-digital conversion circuit includes: a holding circuit, used to keep the voltage of the input signal processed by the second filtering circuit within a second threshold value, the output end of the holding circuit is connected to the first input end of the comparison voltage generating circuit; a reference circuit, used to generate a first reference voltage, the output end of the reference circuit is connected to the second input end of the comparison voltage generating circuit; a comparison voltage generating circuit, used to adjust the input signal processed by the holding circuit based on the first reference voltage to obtain a comparison voltage, the output end of the comparison voltage generating circuit is connected to the input end of the comparison circuit; a comparison circuit, used to compare the comparison voltage with a second reference voltage inside the comparison circuit, and output the comparison result to a calibration circuit; a calibration circuit, used to perform smoothing calculation on the comparison result, and determine the smoothing calculation result as the digital signal.

[0008] In one possible implementation manner, the clamping diode in the amplitude limiting circuit is a silicon-controlled rectifier diode or a bidirectional trigger diode, and the amplitude limiting circuit is used to control the voltage of the input signal within 2.1V.

[0009] In one possible implementation manner, the first gain is 22 dB; the second gain ranges from 2 dB to 32 dB, with a step of 1 dB, and a gain jump time of 1 μs.

[0010] In one possible implementation manner, the cutoff frequencies of the first filter circuit and the second filter circuit are between 5 kHz and 400 kHz.

[0011] In one possible implementation manner, the bandwidth of the first amplifier circuit and the second amplifier circuit is 300 kHz.

[0012] In one possible implementation manner, the resolution of the analog-to-digital conversion circuit is 16 bits.

[0013] According to a second aspect of the present disclosure, an electronic device is provided, comprising: an ultrasonic signal processing circuit according to the present disclosure.

[0014] The present invention discloses an ultrasonic signal processing circuit and an electronic device, wherein the ultrasonic signal processing circuit includes a limiting circuit, a first amplifying circuit, a first filtering circuit, a second amplifying circuit, a second filtering circuit and an analog-to-digital conversion circuit, wherein the first amplifying circuit can reduce noise while amplifying the input signal, the second amplifying circuit can adjust the gain of the input signal as required to achieve dynamic gain control of the input signal, and the analog-to-digital conversion circuit can protect the input signal from distortion under strong interference. Thus, the input signal is limited, amplified, filtered, amplified again, filtered again and converted in the ultrasonic signal processing circuit, and finally outputs a digital signal. Through multi-stage amplification, filtering and gain control, low-noise, high-gain and programmable processing functions are achieved, and low-frequency modulated signals can be effectively received and amplified, and converted into signals that are easy to process.

[0015] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, in which:

[0017] In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.

[0018] Figure 1 A schematic diagram of the structure of an ultrasonic signal processing circuit according to an embodiment of the present disclosure is shown;

[0019] Figure 2 A schematic diagram showing the structure of a first amplifier circuit according to an embodiment of the present disclosure is shown;

[0020] Figure 3 A schematic diagram of the structure of the analog-to-digital conversion circuit according to an embodiment of the present disclosure is shown;

[0021] Figure 4 A schematic structural diagram of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0022] In order to make the purpose, features, and advantages of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0023] Figure 1 FIG. 4 shows a schematic diagram of the structure of an ultrasonic signal processing circuit according to an embodiment of the present disclosure. Figure 1 As shown, an ultrasonic signal processing circuit includes:

[0024] A limiter circuit 101 is used to control the voltage of an input signal within a first threshold value, an input end of the limiter circuit 101 is used to receive the input signal, and an output end of the limiter circuit 101 is connected to an input end of the first amplifier circuit 102;

[0025] A first amplifier circuit 102 is used to amplify the input signal processed by the limiter circuit 101 based on a first gain set in advance, and the output end of the first amplifier circuit 102 is connected to the input end of the first filter circuit 201;

[0026] The first filter circuit 201 is used to filter the input signal processed by the first amplifier circuit 102, and the output end of the first filter circuit 201 is connected to the input end of the second amplifier circuit 103;

[0027] The second amplifier circuit 103 is used to determine a second gain based on the received first digital control signal, and amplify the input signal processed by the first filter circuit 201 based on the second gain, and the output end of the second amplifier circuit 103 is connected to the input end of the second filter circuit 202;

[0028] The second filter circuit 202 is used to filter the input signal processed by the second amplifying circuit 103, and the output end of the second filter circuit 202 is connected to the input end of the analog-to-digital conversion circuit 104;

[0029] The analog-to-digital conversion circuit 104 is used to convert the input signal processed by the second filtering circuit 202 into a digital signal, and the output end of the analog-to-digital conversion circuit 104 is used to output the digital signal.

[0030] In this embodiment, the limiter circuit 101 is an electrostatic discharge (ESD) protection circuit, which is used to control the voltage of the input signal within a first threshold value so as to protect the first amplifier circuit 102 connected to the limiter circuit 101 from being damaged by a high voltage signal.

[0031] The first amplifier circuit 102 is a low noise amplifier (LNA) for amplifying the input signal processed by the limiter circuit 101 based on a first gain set in advance. The first amplifier circuit 102 mainly focuses on amplifying the input signal in a manner with the lowest noise without changing its characteristics. In one example, the first gain can be 22 dB (decibel); the first amplifier circuit 102 adopts a fully differential structure, and amplifies the amplitude of the input signal by 22 dB through multi-stage amplification; the bandwidth of the first amplifier circuit 102 can be 300 kHz (kilohertz).

[0032] The first filter circuit 201 is a band pass filter (BPF) for filtering the input signal processed by the first amplifier circuit 102. The cutoff frequency of the first filter circuit 201 may be 5 kHz to 400 kHz, thereby filtering noise of other frequencies and improving the signal-to-noise ratio of the signal.

[0033] The second amplifier circuit 103 is a digitally controlled amplifier (PGA, Programmable Gain Amplifier), which is used to determine the second gain based on the received first digital control signal, and amplify the input signal processed by the first filter circuit 201 based on the second gain, that is, the second amplifier circuit 103 can adjust the gain of the input signal as needed to achieve dynamic control of the gain of the input signal, and the second amplifier circuit 103 includes a three-stage amplifier circuit. In an example, the first digital control signal can be PWD_1P8 or Gain<5:1>, etc. PWD_1P8 is Power Down 1.8V, indicating a power down control signal related to a 1.8V power supply, Gain<5:1> indicates a gain control signal, <5:1> specifies a multi-bit bus or signal group for setting the gain level of the amplifier; the second gain ranges from 2dB to 32dB, the step is 1dB, and the gain jump time is 1μs (microseconds); the bandwidth of the second amplifier circuit 103 can be 300kHz (kilohertz).

[0034] The second filter circuit 202 is a band pass filter (BPF) for filtering the input signal processed by the second amplifier circuit 102. The cutoff frequency of the second filter circuit 202 may be 5 kHz to 400 kHz, thereby filtering noise of other frequencies and improving the signal-to-noise ratio of the signal.

[0035] The analog-to-digital conversion circuit 104 is an analog-to-digital converter (ADC) for converting the input signal processed by the second filter circuit 202 into a digital signal. In one example, the resolution of the analog-to-digital conversion circuit 104 is 16 bits. Compared with the commonly used analog-to-digital conversion circuit, the analog-to-digital conversion circuit 104 with a high dynamic range in the present disclosure can protect the useful signal from distortion under strong interference.

[0036] In the present disclosure, the ultrasonic signal processing circuit includes a limiting circuit, a first amplifier circuit, a first filter circuit, a second amplifier circuit, a second filter circuit and an analog-to-digital conversion circuit, wherein the limiting circuit can protect the first amplifier circuit from being damaged by a high voltage signal and improve the reliability of the circuit, the first amplifier circuit can reduce noise while amplifying the input signal, the second amplifier circuit can adjust the gain of the input signal as needed to achieve dynamic gain control of the input signal, and the analog-to-digital conversion circuit can protect the input signal from distortion in the case of strong interference. Therefore, the ultrasonic signal processing circuit of the present disclosure has the following advantages: excellent noise performance, which can meet the needs of low-frequency signal reception; high gain control accuracy, which can achieve accurate gain adjustment; short gain jump transient response time, fast signal processing speed; high circuit reliability.

[0037] In another embodiment, the limiting circuit 101 includes a clamping diode, and the limiting circuit 101 is also used to: if the voltage of the input signal is greater than the first threshold, control the clamping diode to conduct so that the voltage of the input signal flows to the target component through the clamping diode, and the target component does not belong to the ultrasonic signal processing circuit.

[0038] In this embodiment, the limiter circuit 101 further includes a clamping diode. If the voltage of the input signal is greater than the first threshold, the clamping diode in the limiter circuit 101 will be turned on, so that the excess voltage flows through the clamping diode to the target component, such as the ground wire or the power supply, which is not a component of the ultrasonic signal processing circuit, thereby clamping the overvoltage at a safe level, thereby protecting the subsequent circuit from the harm of high voltage. In one example, the clamping diode can be a silicon-controlled rectifier diode or a bidirectional trigger diode, which can provide protection for the subsequent circuit in both positive and negative directions; the first threshold can be 2.1V, that is, the limiter circuit 101 is used to control the voltage of the input signal within 2.1V.

[0039] Figure 2 FIG. 4 shows a schematic diagram of the structure of the first amplifier circuit according to an embodiment of the present disclosure. Figure 2 As shown, the first amplifier circuit 102 includes:

[0040] The level conversion circuit 301 is used to convert the received second digital control signal into a control voltage, and the control voltage is used to drive the first common-mode voltage driving circuit 302 and the second common-mode voltage driving circuit 303. The two output ends of the level conversion circuit 301 are respectively connected to the input ends of the first common-mode voltage driving circuit 302 and the second common-mode voltage driving circuit 303;

[0041] A first common-mode voltage driving circuit 302, used for determining a first common-mode voltage based on a control voltage, wherein an output terminal of the first common-mode voltage driving circuit 302 is connected to a first input terminal of a cascade amplifier 304;

[0042] A second common-mode voltage driving circuit 303, used for determining a second common-mode voltage based on the control voltage, wherein an output terminal of the second common-mode voltage driving circuit 303 is connected to a second input terminal of the cascade amplifier 304;

[0043] The cascade amplifier 304 is used to amplify the input signal processed by the limiting circuit 101 based on the first common-mode voltage and the second common-mode voltage. The third input terminal of the cascade amplifier 304 is used to receive the input signal processed by the limiting circuit 101. The output terminal of the cascade amplifier 304 is connected to the input terminal of the first filter circuit 201.

[0044] In this embodiment, the level conversion circuit 301 is used to convert the received second digital control signal into a control voltage, and the control voltage is used to drive the first common-mode voltage driving circuit 302 and the second common-mode voltage driving circuit 303. The second digital control signal can be a parallel port control signal of a complementary metal oxide semiconductor (CMOS) standard level. The level conversion circuit 301 can convert the second digital control signal into a control voltage suitable for the internal analog circuit of the first amplifier circuit 102, thereby driving the first common-mode voltage driving circuit 302 and the second common-mode voltage driving circuit 303.

[0045] The first common-mode voltage driving circuit 302 is used to determine the first common-mode voltage based on the control voltage. The first common-mode voltage driving circuit 302 is close to the input end of the first amplifier circuit 102, thereby providing a first common-mode voltage for the input stage amplifier of the first amplifier circuit 102. The first common-mode voltage ensures that the input stage amplifier of the cascade amplifier 304 operates under optimal bias conditions to avoid entering the saturation region or the cut-off region, and provides a stable DC offset for the input signal so that the input signal can correctly enter the amplification link.

[0046] The second common-mode voltage driving circuit 303 is used to determine the second common-mode voltage based on the control voltage. The second common-mode voltage driving circuit 303 is farther away from the input end of the first amplifier circuit 102 than the first common-mode voltage driving circuit 302, thereby providing a second common-mode voltage for the intermediate stage amplifier of the first amplifier circuit 102. The second common-mode voltage can ensure that the subsequent stages of the input stage amplifier in the cascade amplifier 304 can operate under optimal bias conditions, avoiding performance degradation due to common-mode voltage fluctuations, and providing a stable DC offset for the intermediate stage signal to ensure that the signal will not be distorted during transmission.

[0047] The cascade amplifier 304 is used to amplify the input signal processed by the limiting circuit 101 based on the first common-mode voltage and the second common-mode voltage. The cascade amplifier 304 includes multiple amplifiers, such as an input stage amplifier and an intermediate stage amplifier. Each amplifier can amplify the input signal based on the corresponding first common-mode voltage and second common-mode voltage. In addition, the cascade amplifier 304 adopts a differential structure, which can suppress common-mode noise and flicker noise and improve the signal-to-noise ratio.

[0048] Figure 3 The schematic diagram of the structure of the analog-to-digital conversion circuit of the embodiment of the present disclosure is shown as follows: Figure 3 As shown, the analog-to-digital conversion circuit 104 includes:

[0049] A holding circuit 401, used to keep the voltage of the input signal processed by the second filtering circuit 202 within a second threshold, and the output terminal of the holding circuit 401 is connected to the first input terminal of the comparison voltage generating circuit 402;

[0050] A reference circuit 404, used for generating a first reference voltage, wherein an output terminal of the reference circuit 404 is connected to a second input terminal of the comparison voltage generating circuit 402;

[0051] A comparison voltage generating circuit 402 is used to adjust the input signal processed by the holding circuit 401 based on the first reference voltage to obtain a comparison voltage, and the output end of the comparison voltage generating circuit 402 is connected to the input end of the comparison circuit 403;

[0052] The comparison circuit 403 is used to compare the comparison voltage with a second reference voltage inside the comparison circuit 403 and output the comparison result to the calibration circuit 405;

[0053] The calibration circuit 405 is used to perform smoothing calculation on the comparison result and determine the smoothing calculation result as a digital signal.

[0054] In this embodiment, the holding circuit 401 is used to sample the input signal and keep the voltage of the input signal unchanged in each sampling cycle, that is, to keep the voltage of the input signal within the second threshold until the conversion is completed, thereby ensuring that the input signal does not change during the conversion process and improving the conversion accuracy. In one example, the holding circuit 401 includes a switch and a capacitor. In the sampling phase, the switch is in a closed state, allowing the input signal to pass directly and charge onto the capacitor. The capacitor will quickly charge to the voltage level of the current input signal. Since the capacitor can store charge, it can "remember" this voltage value; when the sampling cycle ends, the switch will be disconnected to isolate the capacitor from the input signal so that the voltage on the capacitor is fixed. Even if the input signal changes, the voltage on the capacitor will not be affected. Therefore, even if the input signal changes during the conversion, the analog-to-digital conversion circuit 104 can perform accurate conversion based on the voltage on the capacitor; in addition, in order to ensure that the output terminal can provide a sufficiently low impedance, the input holding circuit usually also includes a buffer amplifier, which can copy the voltage on the capacitor to the output terminal without discharging the capacitor.

[0055] The reference circuit 404 is used to provide a stable and accurate first reference voltage, and the first reference voltage is used to determine the full-scale input voltage range when converting the analog signal into a digital signal. For example, if the reference voltage is 3.3V, the input signal of 0 to 3.3V will be mapped into the output codeword range of the analog-to-digital conversion circuit 104.

[0056] The comparison voltage generating circuit 402 is used to dynamically adjust the input signal processed by the holding circuit 401 based on the first reference voltage to obtain the comparison voltage. That is, the comparison voltage generating circuit 402 will adjust the output comparison voltage on the fixed first reference voltage according to the characteristics of the input signal.

[0057] The comparison circuit 403 is used to compare the comparison voltage with the second reference voltage inside the comparison circuit 403, and output the comparison result to the calibration circuit 405, wherein the second reference voltage is a fixed reference voltage set in advance, and the second reference voltage can be the same as or different from the first reference voltage. In one example, if the input comparison voltage is higher than the second reference voltage, the comparator outputs a high-level signal; conversely, if the comparison voltage is lower than the second reference voltage, a low-level signal is output, and the high-low level output results are transmitted to the calibration circuit 405 for subsequent processing and conversion, and finally form the digital output of the analog-to-digital conversion circuit 104.

[0058] The calibration circuit 405 processes the comparison result output by the comparison circuit 403, performs necessary smoothing calculations to eliminate possible quantization errors, and generates a final digital signal. This part is also responsible for managing the format and timing control of the output digital signal.

[0059] Figure 4 A schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure is shown. Figure 4 As shown, the electronic device 500 includes the ultrasonic signal processing circuit 100 of the present disclosure. In one example, the electronic device 500 may be a device that needs to use ultrasonic signals, such as a reversing radar, a sonar device, an ultrasonic rangefinder, a medical ultrasonic device, and a flow monitoring device.

[0060] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0061] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0062] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. An ultrasonic signal processing circuit, characterized in that: The circuit comprises: A limiter circuit (101) is used to control the voltage of an input signal within a first threshold value, the input end of the limiter circuit (101) is used to receive the input signal, and the output end of the limiter circuit (101) is connected to the input end of a first amplifier circuit (102); A first amplifier circuit (102) is used to amplify the input signal processed by the limiter circuit (101) based on a first gain set in advance, and the output end of the first amplifier circuit (102) is connected to the input end of the first filter circuit (201); A first filtering circuit (201) is used to filter the input signal processed by the first amplifying circuit (102), the output end of the first filtering circuit (201) being connected to the input end of the second amplifying circuit (103); a second amplifier circuit (103), used for determining a second gain based on the received first digital control signal, and amplifying the input signal processed by the first filter circuit (201) based on the second gain, wherein the output end of the second amplifier circuit (103) is connected to the input end of the second filter circuit (202); A second filtering circuit (202) is used to filter the input signal processed by the second amplifying circuit (103), and the output end of the second filtering circuit (202) is connected to the input end of the analog-to-digital conversion circuit (104); The analog-to-digital conversion circuit (104) is used to convert the input signal processed by the second filtering circuit (202) into a digital signal, and the output end of the analog-to-digital conversion circuit (104) is used to output the digital signal.

2. The circuit according to claim 1, characterized in that The amplitude limiting circuit (101) comprises a clamping diode, and the amplitude limiting circuit (101) is further used for: If the voltage of the input signal is greater than the first threshold, the clamping diode is controlled to be turned on so that the voltage of the input signal flows to the target component through the clamping diode, and the target component does not belong to the ultrasonic signal processing circuit.

3. The circuit according to claim 1, characterized in that The first amplifying circuit (102) comprises: A level conversion circuit (301) is used for converting a received second digital control signal into a control voltage, wherein the control voltage is used for driving a first common-mode voltage driving circuit (302) and a second common-mode voltage driving circuit (303), wherein two output ends of the level conversion circuit (301) are respectively connected to input ends of the first common-mode voltage driving circuit (302) and the second common-mode voltage driving circuit (303); A first common-mode voltage driving circuit (302) is used to determine a first common-mode voltage based on the control voltage, wherein an output terminal of the first common-mode voltage driving circuit (302) is connected to a first input terminal of a cascade amplifier (304); A second common-mode voltage driving circuit (303) is used to determine a second common-mode voltage based on the control voltage, wherein an output end of the second common-mode voltage driving circuit (303) is connected to a second input end of the cascade amplifier (304); A cascade amplifier (304) is used to amplify the input signal processed by the limiting circuit (101) based on the first common-mode voltage and the second common-mode voltage, the third input end of the cascade amplifier (304) is used to receive the input signal processed by the limiting circuit (101), and the output end of the cascade amplifier (304) is connected to the input end of the first filter circuit (201).

4. The circuit according to claim 1, characterized in that The analog-to-digital conversion circuit (104) comprises: A holding circuit (401), used for keeping the voltage of the input signal processed by the second filtering circuit (202) within a second threshold, the output end of the holding circuit (401) being connected to the first input end of the comparison voltage generating circuit (402); A reference circuit (404) for generating a first reference voltage, wherein an output terminal of the reference circuit (404) is connected to a second input terminal of the comparison voltage generating circuit (402); A comparison voltage generating circuit (402) is used to adjust the input signal processed by the holding circuit (401) based on the first reference voltage to obtain a comparison voltage, wherein the output end of the comparison voltage generating circuit (402) is connected to the input end of the comparison circuit (403); A comparison circuit (403) for comparing the comparison voltage with a second reference voltage inside the comparison circuit (403), and outputting the comparison result to a calibration circuit (405); The calibration circuit (405) is used to perform smoothing calculation on the comparison result and determine the smoothing calculation result as the digital signal.

5. The circuit according to claim 2, characterized in that The clamping diode in the amplitude limiting circuit (101) is a silicon-controlled rectifier diode or a bidirectional trigger diode, and the amplitude limiting circuit (101) is used to control the voltage of the input signal within 2.1V.

6. The circuit according to claim 1, characterized in that The first gain is 22 dB; the second gain ranges from 2 dB to 32 dB, with a step of 1 dB and a gain jump time of 1 μs.

7. The circuit according to claim 1, characterized in that The cut-off frequencies of the first filter circuit (201) and the second filter circuit (202) are between 5 kHz and 400 kHz.

8. The circuit according to claim 1, characterized in that The bandwidth of the first amplifier circuit (102) and the second amplifier circuit (103) is 300 kHz.

9. The circuit according to claim 1, characterized in that The resolution of the analog-to-digital conversion circuit (104) is 16 bits.

10. An electronic device, characterized in that: include: An ultrasonic signal processing circuit according to claims 1-9.

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