Power-on and power-off time sequence control circuit and method for multi-path power supply

Abstract

The invention provides a multipath power supply power-on and power-off time sequence control circuit and method. The circuit comprises a multi-path power supply loop, a system power supply voltage detection loop, a reset loop, a power-on and power-off state selection loop and a multi-path power supply time sequence control loop. According to the power-on and power-off time sequence control circuit of the multi-path power supply, the power supply state of the system power supply of the processor device can be obtained through the system power supply voltage detection loop, and the restart state of the processor device can be obtained through the reset loop. The actual power-on and power-off states of the processor device can be determined by combining the power supply state of the system power supply and the restart state of the processor device. On the basis of the actual power-on and power-off states of the processor device, the power-on and power-off time sequence of the processor device can be more accurately controlled, normal work of the processor device can be guaranteed, and the reliability of the processor device is improved.

Description

Technical Field

[0001] The present application relates to the field of electronic circuit design, and in particular to a multi-channel power supply power-on and power-off timing control circuit and method. Background Art

[0002] With the rapid development of semiconductor manufacturing technology and electronic technology, various industries have higher and higher requirements for chip processor devices such as central processing unit (CPU) and field-programmable gate array (FPGA). These devices have strict requirements for power-on and power-off timing. If the power-on and power-off timing does not meet the requirements, the normal working life of these devices will be shortened. In severe cases, the chip will fail directly, which restricts the application and development of these devices. Usually, the power-on and power-off timing of these devices can be controlled by complex programmable logic devices (CPLD). However, CPLD does not always meet the requirements for power-on and power-off timing. In addition, CPLD devices involve CPLD software programming, which will increase the complexity of the entire system architecture. Summary of the invention

[0003] The embodiments of the present application provide a circuit and method for controlling power-on and power-off timing of multiple power supplies.

[0004] In a first aspect, an embodiment of the present application provides a multi-power supply power-on and power-off timing control circuit, including a multi-power supply circuit, a system power supply voltage detection circuit, a reset circuit, a power-on and power-off state selection circuit, and a multi-power supply timing control circuit;

[0005] Multiple power supply loops are used to enable processor devices;

[0006] The system power supply voltage detection circuit is used to determine whether the voltage of the system power supply of the processor device is greater than a first threshold value, the input end of the system power supply voltage detection circuit is connected to the system power supply, and the output end of the system power supply voltage detection circuit is connected to the first input end of the power-on and power-off state selection circuit;

[0007] The reset loop is used to control the restart of the processor device, the input end of the reset loop is connected to the output end of the processor device, and the output end of the reset loop is connected to the second input end of the power-up and power-down state selection loop;

[0008] The power-on and power-off state selection circuit is used to determine the power-on and power-off state of the processor device. When the voltage is greater than the first threshold and the reset circuit does not control the processor device to restart, the processor device is in the power-on state. When the voltage is not greater than the first threshold or the reset circuit controls the processor device to restart, the processor device is in the power-off state. The output end of the power-on and power-off state selection circuit is connected to the input end of the multi-channel power supply timing control circuit.

[0009] The multi-way power supply timing control circuit is used to control the power-on and power-off timing of the multi-way power supply circuit according to the power-on and power-off status. In the power-on state, the multi-way power supply timing control circuit controls the multi-way power supply circuit to power on in a predetermined sequence. Conversely, the multi-way power supply timing control circuit controls the multi-way power supply circuit to power off in a predetermined sequence. The output end of the multi-way power supply timing control circuit is connected to the input end of the multi-way power supply circuit.

[0010] Optionally, the system power supply voltage detection circuit includes a comparator and a reference voltage circuit, the first input terminal of the comparator is connected to the reference voltage circuit, the second input terminal of the comparator is connected to the system power supply, the output terminal of the comparator is connected to the first input terminal of the power-on and power-off state selection circuit, the first threshold is determined based on the reference voltage of the reference voltage circuit, and the comparator outputs a high level when the voltage of the system power supply is greater than the first threshold, otherwise it outputs a low level.

[0011] Optionally, the hysteresis band of the comparator is smaller than the second threshold, the operating voltage of the comparator is smaller than the third threshold, and the operating voltage of the reference voltage circuit is smaller than the fourth threshold.

[0012] Optionally, the reset loop includes a watchdog circuit, which outputs a low level when the control processor device is restarted, and outputs a high level when the control processor device is not restarted.

[0013] Optionally, the power-on / power-off state selection loop includes an AND gate circuit, and the AND gate circuit outputs a high level when both the comparator and the watchdog circuit output a high level, and outputs a low level otherwise.

[0014] Optionally, the multi-power supply timing control loop includes a bidirectional buffer, which outputs an enable signal to control the multi-power supply loops to power on in a predetermined sequence when the AND gate circuit outputs a high level, and conversely, the bidirectional buffer outputs an enable signal to control the multi-power supply loops to power off in a predetermined sequence when the AND gate circuit outputs a low level.

[0015] Optionally, the multi-channel power supply timing control loop includes a bidirectional buffer.

[0016] Optionally, the multi-channel power supply timing control loop includes two bidirectional buffers, and the power-on and power-off timings of the two bidirectional buffers are independent of each other.

[0017] Optionally, the time required for the multiple power supply circuits to enable the processor device is less than the time during which the multiple power supply circuits can work normally during power-off of the system power supply.

[0018] In a second aspect, an embodiment of the present application provides a power supply system, which includes a multi-power supply power-on and power-off timing control circuit as described in any one of the first aspects.

[0019] In a third aspect, an embodiment of the present application provides a method for controlling power-on and power-off timings of multiple power supplies, which controls the power-on and power-off timings of a processor device through a multiple power-on and power-off timing control circuit as described in any one of the first aspects.

[0020] According to a fourth aspect, an electronic device is provided, which may include at least one unit or module that can be used to execute any method according to the third aspect.

[0021] In a fifth aspect, an electronic device is provided, which may include at least one processor coupled to at least one memory, and the at least one memory may be used to store computer programs or instructions. When the computer program or instructions are executed by the at least one processor, the electronic device implements any method as described in the third aspect above.

[0022] In a sixth aspect, a computer-readable storage medium is provided, which stores a computer program or instruction. When the computer program or instruction runs on a computer, the method as described in any one of the third aspects above is executed.

[0023] In the multi-power power on and off timing control circuit of the present application, the power supply status of the system power supply of the processor device can be obtained through the system power supply voltage detection circuit, and the restart status of the processor device can be obtained through the reset circuit. In combination with the power supply status of the system power supply and the restart status of the processor device, the actual power on and off status of the processor device can be clarified. Based on the actual power on and off status of the processor device, the power on and off timing of the processor device can be controlled more accurately, which helps to ensure the normal operation of the processor device and improve the reliability of the processor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for describing the embodiments are briefly introduced below.

[0025] Figure 1 It is a structural schematic diagram of a multi-power supply power-on and power-off timing control circuit provided in an embodiment of the present application.

[0026] Figure 2 This is an example diagram of a multi-power supply power-on and power-off timing control circuit provided in an embodiment of the present application.

[0027] Figure 3 This is an example diagram of another multi-power supply power-on and power-off timing control circuit provided in an embodiment of the present application.

[0028] Figure 4 It is a schematic diagram of the structure of the electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The technical solution of the embodiment of the present application will be described below in conjunction with the drawings in the embodiment of the present application.

[0030] With the rapid development of semiconductor manufacturing technology and electronic technology, various industries have higher and higher requirements for chip processor devices such as CPU and FPGA. For example, in the industrial, automotive and consumer industries, the complexity of devices such as CPU and FPGA is getting higher and higher.

[0031] These devices have strict requirements for power-on and power-off timing. If the power-on and power-off timing does not meet the requirements, the normal working life of these devices will be shortened. In severe cases, the chip will fail directly, which restricts the application and development of these devices. For example, if the power-on and power-off timing does not meet the requirements, it may cause the electronic fuse (electronic fuse, EFUSE) function of the CPU, FPGA and other devices to malfunction or the input / output (IO) status of the power-on and power-off control to be uncertain, which may lead to the risk of false triggering or the direct burning of the CPU, FPGA and other devices.

[0032] Usually, the power-on and power-off timing of these devices can be controlled by CPLD. However, CPLD cannot always meet the power-on and power-off timing requirements. For example, when the chip system is powered off, the power supply voltage of CPLD also starts to power off, which may cause the CPLD to stop working, but the power supply of devices such as CPU and FPGA has not been completely powered off. Moreover, if the IO of the CPLD device fails, the power supply of devices such as CPU or FPGA cannot be supplied normally, which will cause the CPU, FPGA and other devices to fail to start normally or never start. In addition, CPLD devices involve CPLD software programming, which will increase the complexity of the entire system architecture.

[0033] Based on this, Figure 1 As shown in the embodiment of the present application, a multi-power supply power-on and power-off timing control circuit is provided, which can be used for power-on and power-off timing control of processor devices such as CPU, FPGA, etc.

[0034] like Figure 1As shown, the circuit 100 may include a multi-way power supply circuit 110 , a system power supply voltage detection circuit 120 , a reset circuit 130 , a power-up and power-down state selection circuit 140 and a multi-way power supply timing control circuit 150 .

[0035] Among them, the multi-way power supply circuit 110 can be used to enable the processor device. The multi-way power supply circuit 110 may include multiple power supply circuits, and the multiple power supply circuits can be used to enable different modules in the processor device. Each power supply circuit in the multiple power supply circuits may include a direct current-direct current converter (DCDC) or a low dropout voltage regulator (LDO), and the type of DCDC or LDO is not limited.

[0036] The system power supply voltage detection circuit 120 can be used to determine whether the voltage of the system power supply of the processor device is greater than a first threshold value. The input end of the system power supply voltage detection circuit 120 is connected to the system power supply, and the output end of the system power supply voltage detection circuit 120 is connected to the first input end of the power-on and power-off state selection circuit 140.

[0037] The first threshold value may be a threshold value for judging whether the system power supply can supply power normally. When the voltage of the system power supply is greater than the first threshold value, it indicates that the system power supply can supply power normally, and it can be determined that the circuit 100 is in a power-on state. Otherwise, when the voltage of the system power supply is less than or equal to the first threshold value, it indicates that the system power supply cannot supply power normally, and it can be determined that the circuit 100 is in a power-off state.

[0038] It should be noted that when it is determined that the circuit 100 is in the power-on state, it cannot be determined that the processor device is also in the power-on state. For example, when the processor device is restarted, the circuit 100 is in the power-on state, but the processor device is in the power-off state. However, when it is determined that the circuit 100 is in the power-off state, it can be determined that the processor device is also in the power-off state.

[0039] The system power supply voltage detection circuit 120 can compare the voltage of the system power supply with the first threshold value, and determine the output result according to the comparison result. For example, when the voltage of the system power supply is greater than the first threshold value, the system power supply voltage detection circuit 120 can output a high level, otherwise the system power supply voltage detection circuit 120 can output a low level.

[0040] The reset loop 130 can be used to control the restart of the processor device, the input end of the reset loop 130 is connected to the output end of the processor device, and the output end of the reset loop 130 is connected to the second input end of the power-up and power-down state selection loop 140. Exemplarily, the reset loop 130 can control the restart of the processor device when the processor device runs dead or the processor device needs to be remotely upgraded.

[0041] In the present application, restarting the processor device refers to restarting the enable power supply of the processor device. When the reset loop 130 controls the processor device to restart, the processor device needs to be powered off, that is, the processor device is in a power-off state. When the reset loop 130 controls the processor device to restart, the system power supply is usually still powered normally, that is, the circuit 100 is in a power-on state.

[0042] The reset loop 130 may determine the output result according to whether the control processor device is restarted. For example, when the reset loop 130 controls the processor device to restart, it may output a low level, otherwise it may output a high level.

[0043] The power-on and power-off state selection circuit 140 can be used to determine the power-on and power-off states of the processor device. When the voltage of the system power supply is greater than the first threshold and the reset circuit 130 does not control the processor device to restart, the processor device is in the power-on state. When the voltage of the system power supply is not greater than the first threshold or the reset circuit 130 controls the processor device to restart, the processor device is in the power-off state. The output end of the power-on and power-off state selection circuit 140 is connected to the input end of the multi-power supply timing control circuit 150.

[0044] When the voltage of the system power supply is greater than the first threshold and the reset loop 130 does not control the processor device to restart, the circuit 100 is in the power-on state, and the processor does not need to be powered off, so the processor device is in the power-on state. When the voltage of the system power supply is less than or equal to the first threshold, the circuit 100 is in the power-off state, so the processor device is in the power-off state. When the reset loop 130 controls the processor device to restart, the circuit 100 is in the power-on state, but the processor needs to be powered off, so the processor device is in the power-off state.

[0045] The power-up and power-down state selection circuit 140 can determine the output result according to the power-up and power-down state of the processor device. For example, when the processor device is in the power-up state, the power-up and power-down state selection circuit 140 can output a high level, otherwise it can output a low level.

[0046] The multi-power supply timing control circuit 150 can be used to control the power-on and power-off timing of the multi-power supply circuit 110 according to the power-on and power-off states. In the power-on state, the multi-power supply timing control circuit 150 controls the multi-power supply circuit 110 to power on in a predetermined sequence. Conversely, the multi-power supply timing control circuit 150 controls the multi-power supply circuit 110 to power off in a predetermined sequence. The output end of the multi-power supply timing control circuit 150 is connected to the input end of the multi-power supply circuit 110.

[0047] The multi-way power supply timing control circuit 150 can control the power-on and power-off sequence of multiple power supply circuits in the multi-way power supply circuit 110 according to the power-on and power-off states. The power-on and power-off sequence of the multiple power supply circuits determines the power-on and power-off sequence of different modules in the processor device. The power-on and power-off sequence of different modules in the processor device may be opposite, or may not be opposite but independent of each other. Accordingly, the power-on and power-off sequence of the multiple power supply circuits may be opposite, or may be independent of each other.

[0048] In the multi-power power on and off timing control circuit of the present application, the power supply status of the system power supply of the processor device can be obtained through the system power supply voltage detection circuit, and the restart status of the processor device can be obtained through the reset circuit. In combination with the power supply status of the system power supply and the restart status of the processor device, the actual power on and off status of the processor device can be clarified. Based on the actual power on and off status of the processor device, the power on and off timing of the processor device can be controlled more accurately, which helps to ensure the normal operation of the processor device and improve the reliability of the processor device.

[0049] Optionally, the system power supply voltage detection circuit 120 may include a comparator and a reference voltage circuit, wherein a first input terminal of the comparator is connected to the reference voltage circuit, a second input terminal of the comparator is connected to the system power supply, an output terminal of the comparator is connected to a first input terminal of the power-up and power-down state selection circuit 140, a first threshold value may be determined based on a reference voltage of the reference voltage circuit, and the comparator may output a high level when the voltage of the system power supply is greater than the first threshold value, and vice versa, a low level is output. Based on the comparator and the reference voltage circuit, the comparison between the voltage of the system power supply and the first threshold value may be simply realized.

[0050] The model of the comparator is not limited. Optionally, the hysteresis of the comparator can be less than the second threshold. For example, the second threshold can be 0.05, that is, the hysteresis of the comparator can be less than 0.05. A comparator with a smaller hysteresis is more sensitive. Optionally, the operating voltage of the comparator can be less than the third threshold. For example, the third threshold can be 2V, that is, the operating voltage of the comparator can be less than 2V. The low operating voltage of the comparator can ensure that when the system power supply is powered off, the comparator works longer, and no separate power supply is required to power the comparator. Exemplarily, the model of the comparator can be TLV3691.

[0051] The model of the reference voltage circuit is also not limited. Optionally, the operating voltage of the reference voltage circuit may be less than the fourth threshold. For example, the fourth threshold may be 2V, that is, the operating voltage of the reference voltage circuit may be less than 2V. The low operating voltage of the reference voltage circuit can ensure that when the system power supply is powered off, the reference voltage circuit works longer, and no separate power supply is required to power the reference voltage circuit. Exemplarily, the model of the reference voltage circuit may be TPR3312.

[0052] Alternatively, the system power supply voltage detection circuit 120 may also include a power supply monitoring circuit with a reference. The power supply monitoring circuit with a reference may also compare the voltage of the system power supply with the first threshold, and the model of the power supply monitoring circuit with a reference is not limited.

[0053] Optionally, the reset loop 130 may include a watchdog (WD) circuit, which outputs a low level when the control processor device is restarted, and outputs a high level when the control processor device is not restarted. The watchdog circuit can control the processor device to restart when the processor device is dead or the processor device needs to be remotely upgraded. The model of the watchdog circuit is not limited, for example, the model of the watchdog may be SGM706.

[0054] Optionally, the power-up and power-down state selection circuit 140 may include an AND gate circuit, which outputs a high level when both the comparator and the watchdog circuit output a high level, otherwise outputs a low level. When both the comparator and the watchdog circuit output a high level, the processor device is in a power-on state. When the comparator or the watchdog circuit outputs a low level, the processor device is in a power-down state. In other words, the AND gate circuit may output a high level when the processor device is in a power-on state, and output a low level when the processor device is in a power-down state. The model of the AND gate circuit is not limited, for example, the model of the AND gate circuit may be SN74LVC1G08. Based on the AND gate circuit, it is possible to simultaneously determine the power-up and power-down state of the processor device based on the output results of the comparator and the watchdog circuit.

[0055] Optionally, the multi-way power supply timing control loop 150 may include a bidirectional buffer, and the output of the watchdog circuit may be used as the input of the bidirectional buffer. When the AND gate circuit outputs a high level, the bidirectional buffer outputs an enable signal to control the multi-way power supply loop 110 to power on in a predetermined order. Conversely, when the AND gate circuit outputs a low level, the bidirectional buffer outputs an enable signal to control the multi-way power supply loop 110 to power off in a predetermined order. The bidirectional buffer can control the current transmission direction between the two circuits. When the inputs of the bidirectional buffer are high and low levels respectively, the current transmission directions controlled by the bidirectional buffer are opposite.

[0056] As mentioned above, the power-on and power-off sequences of the multiple power supply circuits in the system power supply voltage detection circuit 120 may be opposite, so the multi-channel power supply timing control circuit 150 may include a bidirectional buffer.

[0057] Alternatively, the power-on and power-off sequences of the multiple power supply circuits in the system power supply voltage detection circuit 120 may also be independent of each other, so the multi-way power supply timing control circuit 150 may also include two bidirectional buffers. The power-on and power-off timing sequences of the two bidirectional buffers are independent of each other, one of which is used to control power-on, and the other is used to control power-off.

[0058] The model of the bidirectional buffer is not limited, for example, the model of the bidirectional buffer may be SN74LVCR2245A.

[0059] Based on the bidirectional buffer, the power-on and power-off sequence of the multi-way power supply loop 110 can be conveniently controlled, thereby controlling the power-on and power-off sequence of the processor device.

[0060] Optionally, the time required for the multi-way power supply circuit to enable the processor device is less than the time during which the multi-way power supply circuit can work normally during the power-off process of the system power supply. That is to say, during the power-off process of the system power supply, the multi-way power supply circuit can complete the enabling of the processor device. Based on this, it helps to avoid the situation in which the processor device has not yet completed the power-off process during the power-off process of the system power supply, but the multi-way power supply circuit has already failed to work.

[0061] Optionally, the multi-channel power supply circuit 110 may include an enable pin, and the enable signal output by the multi-channel power supply timing control circuit 150 may be input into the multi-channel power supply circuit 110 through the enable pin.

[0062] Combine the following Figure 2 , the multi-power supply power-on and power-off timing control circuit of the present application is introduced by example.

[0063] For example, Figure 2 In the circuit shown, the processor device is a CPU / FPGA. The system power supply voltage detection circuit includes a TLV3691 comparator and a TPR3312 reference voltage circuit, the reset circuit includes an SGM706 watchdog circuit, the power-up and power-down state selection circuit includes an SN74LVC1G08 AND gate circuit, the multi-channel power supply timing control circuit includes an SN74LVCR2245A bidirectional buffer, and the multi-channel power supply circuit includes 6 power supply circuits (respectively controlled by DCDC1, DCDC2, DCDC3, LDO1, LDO2, and LDO3).

[0064] exist Figure 2In the circuit shown, the watchdog circuit is connected to the general-purpose input / output (GPIO) pin of the CPU / FPGA through the watchdog input pin (WDI) to determine whether to control the restart of the CPU / FPGA. The watchdog circuit outputs a low level when controlling the restart of the CPU / FPGA, and outputs a high level otherwise. The output of the watchdog circuit is connected to the second input terminal of the AND gate circuit through the reset (RESET, RST) pin.

[0065] The first input terminal of the comparator is connected to the reference voltage (V ref ), and the second input terminal is connected to the voltage of the system power supply. The voltage threshold of the system power supply (i.e., the first threshold) can be calculated by the reference voltage and the resistors R1 and R2. The comparator outputs a high level when the voltage of the system power supply is greater than the first threshold, otherwise it outputs a low level, and the output of the comparator is connected to the first input terminal of the AND gate circuit through the power fail output (PFO) pin.

[0066] The AND gate circuit outputs a high level when both the first input terminal and the second input terminal are input with a high level, indicating that the power of the multiple power supply circuits is turned on (i.e., PWP-UP). Otherwise, the AND gate circuit outputs a low level, indicating that the power of the multiple power supply circuits is turned off (i.e., PWP-DOWN). The output of the AND gate circuit is connected to the input terminal of the bidirectional buffer. The output of the bidirectional buffer includes 6 enable (EN) terminals (EN[1:6]), which respectively enable the 6 power supply circuits. The output voltages (VOUT)[1:6] of the 6 power supply circuits respectively enable different modules in the CPU / FPGA.

[0067] When the AND gate circuit outputs a high level (i.e., PWP-UP), the bidirectional buffer A controls the direction of B (not shown in the figure) as the power-on control timing; when the AND gate circuit outputs a low level (i.e., PWP-DOWN), the bidirectional buffer B controls the direction of A (not shown in the figure) as the power-off control timing, enabling LDOs or DCDCs of different voltage levels to meet the power-on and power-off timing requirements of the CPU / FPGA.

[0068] Figure 2 The working process of the circuit shown can be: after the circuit is powered on, the system power supply starts to work. When the voltage of the system power supply reaches a preset threshold, the AND gate loop determines that the CPU / FPGA is in a power-on state, and the bidirectional buffer outputs an enable control signal to successively enable multiple DCDCs or LDOs according to the timing requirements, so that the multiple DCDCs or LDOs can be powered on according to the timing requirements.

[0069] When the system power supply starts to lose power so that the voltage is less than or equal to a preset threshold, or when the reset loop starts to reset (i.e., controls the CPU / FPGA to restart), the AND gate loop determines that the CPU / FPGA is in a power-off state, and the bidirectional buffer outputs an enable control signal to successively turn off the enable of multiple DCDCs or LDOs according to the timing requirements, so that the multiple DCDCs or LDOs can be powered off according to the timing requirements.

[0070] When the reset loop is reset, since the system power supply is still working, the AND gate loop determines that the CPU / FPGA is in the power-on state, and the bidirectional buffer outputs the enable control signal to enable multiple power supplies DCDC or LDO one by one according to the timing requirements, so that the DCDC or LDO can be powered on according to the timing requirements.

[0071] Combine the following Figure 3 , the circuit design of the multi-power supply power-on and power-off timing control circuit of the present application is introduced by example.

[0072] like Figure 3 As shown, U1 is an AND gate circuit, U2 is a watchdog circuit, U3 is a bidirectional buffer, U4A is a comparator circuit, and U5 is a reference voltage circuit.

[0073] Figure 3 The meanings of some terms in the specification are as follows: Vcc represents the power supply voltage pin of the AND gate circuit, PFI represents the input terminal of the threshold detector of the watchdog circuit, IN represents the input terminal of the reference voltage circuit, OUT represents the output terminal of the reference voltage circuit, DIR represents the direction control pin of the bidirectional buffer, OE represents the enable control pin of the bidirectional buffer, and VCC represents the power supply voltage pin of the bidirectional buffer. Figure 3 The meanings of the remaining terms are explained in the context and will not be repeated here.

[0074] Among them, U2's 1st and 8th pins are short-circuited, and a pull-up resistor R1 is required to connect to the system power supply (VDD can be used to represent the system power supply voltage), 2nd pin is connected to VDD, 3rd pin is grounded (ground, GND), 4th and 5th pins are in a floating state (normally close, NC). U2's 6th pin is connected to the FPGA or CPU's GPIO pin for feeding the dog, with a pull-up resistor, 7th pin is the reset pin, with a pull-up resistor, and 7th pin is connected to U1's 1st pin.

[0075] Pin 1 of U5 is connected to VDD, pin 3 is connected to GND, and pin 2 is connected to the load capacitor to stabilize the reference voltage (VREF). At the same time, pin 2 is connected to pin 2 of U4A. Pin 3 of U4A is connected to resistors R5 and R16, and pin 1 is connected to U1. The calculation formula for the system power supply voltage threshold (i.e., the first threshold) is: VT=(R5+R16) / R16*VREF. When the VDD voltage>VT, pin 1 of U4A outputs a high level, indicating that the power supply is in the power-on state; when the VDD voltage≤VT, pin 1 of U4A outputs a low level, indicating that the power supply is in the power-off state.

[0076] Pin 1 of U1 is connected to pin 7 of U2, pin 2 of U1 is connected to pin 1 of U4A, pin 3 is GND pin, pin 5 is power supply VDD pin, and pin 4 is PWR_STAUS power status pin, which needs to be connected to pull-down resistor R2. When pin 4 outputs high level, it means the power is powered on, and when pin 4 outputs low level, it means the power is powered off.

[0077] Pin 1 of U3 is the direction control pin. When the input is high level, the control data is from A to B. When the input is low level, the control data is from B to A. Pins 2 to 9 of U3 are A direction data signals, pins 11 to 18 are B direction data signals, pin 10 is the GND pin, pin 20 is the power supply VDD pin, and pin 19 is the enable pin. It is directly short-circuited to ground and works normally. EN[1:6] enables LDO or DCDC, so that its output voltage is VOUT[1:6] to FPGA or CPU.

[0078] When the PWR_STAUS signal is high, the CPU / FPGA is in power-on mode, U3 is transferring data from A to B, and R7 and C12 form a resistor-capacitance circuit (RC) charging loop. By controlling the resistance value of R7 and the capacitance value of C12, after U3 starts to be enabled, EN1 is delayed to start, and the EN1 delay start time (time constant) is: R7*C12 (1 time constant is 0.663*VDD, which is high at this time). By analogy, the EN2 delay EN1 start time is: R10*C10, the EN3 delay EN2 start time is: R13*C8, the EN4 delay EN3 start time is: R17*C6, the EN5 delay EN4 start time is: R20*C4, and the EN6 delay EN5 start time is: R23*C2.

[0079] When the PWR_STAUS signal is low, the CPU / FPGA is in power-off mode, and U3 is transferring data from B to A. Therefore, the capacitance of C3 needs to be very small, and the capacitance of C3 is discharged through R24 and R25. When the PWR_STAUS signal is low, EN6 delays power-off, and the EN6 delay power-off time is: 2.3*(R24+R25)*C3 (2.3 time constants are 0.9*VDD, which is low at this time). C3 can be quickly powered off by selecting pF level, and the EN5 delay EN6 power-off time is: 2.3*(R21+R23)*C5. The reason is: the resistors R9, R12, R15, R19, and R22 provide EN power-on The voltage level is determined, the resistance value is at the 10K level, and the resistors R7, R8, R10, R11, R13, R14, R17, R18, R20, R21, R23, and R24 act as series resistance with a resistance value of 100Ω. When the capacitance of C3 is at a low level, the output of pin 7 of U3 is at a low level. At this time, the discharge circuit of C5 passes through R21 and then connects R23 and R22 in parallel. Since the resistance value of R23 is much smaller than that of R22, the discharge time of R22 is ignored. By analogy, the time that EN4 delays EN5 power-off is: 2.3*(R18+R20)*C7, the time that EN3 delays EN4 power-off is: 2.3*(R14+R17)*C9, the time that EN2 delays EN3 power-off is: 2.3*(R11+R13)*C11, and the time that EN1 delays EN2 power-off is: 2.3*(R8+R10)*C13. It should be noted that the sum of all EN signal intervals must be less than the time that U3 can work normally during the VDD power-off process.

[0080] Figure 3 The circuit shown is designed with pure hardware circuits, without involving programmable devices such as CPLD. Therefore, the circuit has low cost, high reliability, flexible configuration parameters, and is suitable for all devices with complex timing requirements such as CPU and FPGA.

[0081] The present application also provides a power supply system, which may include a multi-power supply power-on and power-off timing control circuit as described in any one of the above texts.

[0082] The present application also provides a method for controlling power-on and power-off timing of multiple power supplies, which can control the power-on and power-off timing of a processor device through a multiple power-on and power-off timing control circuit as described in any one of the above.

[0083] An embodiment of the present application further provides an electronic device, which may include at least one unit or module that can be used to execute the above-mentioned method for controlling power-on and power-off timing of multiple power supplies.

[0084] The present application also provides an electronic device. Figure 4As shown, the electronic device 400 includes: at least one processor 401, a memory 402, and a computer program 403 stored in the memory 402 and executable on the at least one processor 401. When the processor 401 executes the computer program 403, the method provided in the present application is implemented.

[0085] Exemplarily, the computer program 403 may be divided into one or more modules / units, one or more modules / units are stored in the memory 402, and executed by the processor 401 to complete the present application. One or more modules / units may be a series of computer program instruction segments capable of completing specific functions, and the instruction segments are used to describe the execution process of the computer program in the electronic device 400.

[0086] Those skilled in the art will understand that Figure 4 It is only an example of the electronic device 400 and does not constitute a limitation of the electronic device. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the electronic device 400 may also include input and output devices, network access devices, buses, etc.

[0087] The processor 401 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0088] The memory 402 may be an internal storage unit of the electronic device 400, such as a hard disk or memory of the electronic device 400. The memory 402 may also be an external storage device of the electronic device 400, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the electronic device 400. Further, the memory 402 may also include both an internal storage unit of the electronic device 400 and an external storage device. The memory 402 is used to store computer programs and other programs and data required by the electronic device 400. The memory 402 may also be used to temporarily store data that has been output or is to be output.

[0089] The electronic device 400 provided in this embodiment can execute the above method embodiment, and its implementation principle and technical effect are similar, which will not be repeated here.

[0090] The embodiment of the present application also provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps in the above-mentioned multi-power supply power-on and power-off timing control method can be implemented.

[0091] The embodiment of the present application also provides a computer program product. When the computer program product is run on an electronic device, the electronic device can implement the steps in the above-mentioned multi-power supply power-on and power-off timing control method when executing the computer program product.

[0092] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above method embodiments, which can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the steps of the above method embodiments can be implemented. Among them, the computer program includes computer program code, which can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device that can carry the computer program code to the camera / electronic device, recording medium, computer memory, ROM (read-only memory), RAM (random access memory), CD-ROM (compact disc read-only memory), magnetic tape, floppy disk and optical data storage device. The computer-readable storage medium mentioned in the present application can be a non-volatile storage medium, in other words, a non-transient storage medium.

[0093] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0094] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0095] In the embodiments provided in the present application, it should be understood that the disclosed devices / equipment and methods can be implemented in other ways. For example, the device / equipment embodiments described above are only schematic, for example, the division of modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0096] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0097] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0098] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0099] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0100] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A multi-power supply power-on and power-off timing control circuit, characterized in that: It includes a multi-way power supply circuit, a system power supply voltage detection circuit, a reset circuit, a power-on and power-off state selection circuit, and a multi-way power supply timing control circuit; The multi-channel power supply circuit is used to enable the processor device; The system power supply voltage detection circuit is used to determine whether the voltage of the system power supply of the processor device is greater than a first threshold value, the input end of the system power supply voltage detection circuit is connected to the system power supply, and the output end of the system power supply voltage detection circuit is connected to the first input end of the power-up and power-down state selection circuit; The reset loop is used to control the restart of the processor device, the input end of the reset loop is connected to the output end of the processor device, and the output end of the reset loop is connected to the second input end of the power-up and power-down state selection loop; The power-up and power-down state selection circuit is used to determine the power-up and power-down state of the processor device. When the voltage is greater than the first threshold and the reset circuit does not control the processor device to restart, the processor device is in the power-up state. When the voltage is not greater than the first threshold or the reset circuit controls the processor device to restart, the processor device is in the power-down state. The output end of the power-up and power-down state selection circuit is connected to the input end of the multi-way power supply timing control circuit. The multi-way power supply timing control circuit is used to control the power-on and power-off timing of the multi-way power supply circuit according to the power-on and power-off states. In the power-on state, the multi-way power supply timing control circuit controls the multi-way power supply circuit to power on in a predetermined sequence. Conversely, the multi-way power supply timing control circuit controls the multi-way power supply circuit to power off in a predetermined sequence. The output end of the multi-way power supply timing control circuit is connected to the input end of the multi-way power supply circuit.

2. The circuit according to claim 1, characterized in that The system power supply voltage detection circuit includes a comparator and a reference voltage circuit, the first input end of the comparator is connected to the reference voltage circuit, the second input end of the comparator is connected to the system power supply, the output end of the comparator is connected to the first input end of the power-on and power-off state selection circuit, the first threshold is determined based on the reference voltage of the reference voltage circuit, and the comparator outputs a high level when the voltage of the system power supply is greater than the first threshold, otherwise it outputs a low level.

3. The circuit according to claim 2, characterized in that The hysteresis band of the comparator is smaller than the second threshold, the operating voltage of the comparator is smaller than the third threshold, and the operating voltage of the reference voltage circuit is smaller than the fourth threshold.

4. The circuit according to claim 3, characterized in that The reset loop includes a watchdog circuit, which outputs a low level when controlling the processor device to restart, and outputs a high level when not controlling the processor device to restart.

5. The circuit according to claim 4, characterized in that The power-up and power-down state selection loop includes an AND gate circuit, and the AND gate circuit outputs a high level when both the comparator and the watchdog circuit output a high level, and otherwise outputs a low level.

6. The circuit according to claim 5, characterized in that The multi-way power supply timing control loop includes a bidirectional buffer, which outputs an enable signal to control the multi-way power supply loop to power on in a predetermined order when the AND gate circuit outputs a high level, and vice versa, the bidirectional buffer outputs an enable signal to control the multi-way power supply loop to power off in a predetermined order when the AND gate circuit outputs a low level.

7. The circuit according to claim 6, characterized in that The multi-channel power supply timing control loop includes a bidirectional buffer.

8. The circuit according to claim 6, characterized in that The multi-channel power supply timing control loop includes two bidirectional buffers, and the power-on and power-off timings of the two bidirectional buffers are independent of each other.

9. The circuit according to claim 7 or 8, characterized in that The time required for the multi-way power supply circuit to enable the processor device is less than the time during which the multi-way power supply circuit can operate normally during the power-off process of the system power supply.

10. A method for controlling the power-on and power-off timing of multiple power supplies, characterized in that: The power-on and power-off timing sequence of the processor device is controlled by the multi-power supply power-on and power-off timing sequence control circuit according to any one of claims 1 to 9.

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