A circuit for improving the high power supply rejection ratio of an LDO

Abstract

The present invention discloses a circuit for improving the high power supply rejection ratio of an LDO, belonging to the technical field of LDO circuits. It mainly includes a feedback control amplifier module opa1 and a power transistor module. The power transistor module includes a power transistor MP1 and a power transistor MP2. The drain of the power transistor MP1 is connected to the source of the power transistor MP2. The non-inverting input terminal of the feedback control amplifier module opa1 is connected to the source of the power transistor MP1. The inverting input terminal of the feedback control amplifier module opa1 is respectively connected to the drain of the power transistor MP1 and the source of the power transistor MP2. The output terminal of the feedback control amplifier module opa1 is connected to the substrate potential of the power transistor MP1. Through special design, the feedback control amplifier module opa1 has a lower gain in the low-frequency band and an increased gain in the high-frequency band. At high frequencies, by raising the substrate potential of MP1, the impedance of the MP1 transistor is increased, thereby improving the power supply rejection ratio psrr in the high-frequency band and effectively suppressing the influence of high-frequency noise in the power supply on the output voltage, meeting the requirements for the power supply rejection ratio in high-precision fields.

Description

Technical Field

[0001] The invention relates to the technical field of LDO circuits, and in particular to a circuit for improving a high power supply rejection ratio of an LDO. Background Art

[0002] As a core component of high-efficiency power management, low-dropout linear regulators (LDOs) are widely used in electronic systems with limited input / output voltage differences. With the rapid development of portable devices, IoT terminals, and wearable technologies, the defects of traditional switching power supplies, such as large electromagnetic interference and complex peripheral circuits, have become increasingly prominent. LDOs, with their low voltage difference, low noise, and fast dynamic response characteristics, have shown significant advantages in lithium battery-powered scenarios, especially in the fields of high-precision analog circuits (such as sensors, RF modules), medical electronics, and automotive-grade chips, which have high requirements for LDO power supply rejection ratio.

[0003] However, in the fields of high-precision analog circuits (such as sensors, RF modules), medical electronics and automotive-grade chips, these fields have extremely high requirements for the purity of the power supply. The noise and fluctuations in the power supply may cause inaccurate signal acquisition, unstable operation of medical equipment, and failure of automotive-grade chips. The traditional LDO architecture has an unsatisfactory power supply rejection ratio (PSRR) in the high-frequency range and cannot effectively suppress the high-frequency noise in the power supply, resulting in fluctuations and noise in the output voltage, which cannot meet the application requirements of these high-precision fields.

[0004] Therefore, it is necessary to provide a circuit for improving the high power supply rejection ratio of LDO to solve the above problems.

[0005] It should be noted that the above information disclosed in this background technology section is only for understanding the background technology of the present inventive concept, and therefore, it may contain information that does not constitute the prior art. Summary of the invention

[0006] The object of the present invention is to provide a circuit for improving the high power supply rejection ratio of an LDO, so as to solve the problems raised in the above background technology.

[0007] The technical solution adopted by the present invention to solve the technical problem is:

[0008] A circuit for improving the high power supply rejection ratio of an LDO, comprising a feedback control amplifier module opa1 and a power tube module;

[0009] The power transistor module includes power transistors MP1 and MP2. The drain of power transistor MP1 is connected to the source of power transistor MP2. The non-inverting input terminal of the feedback control amplifier module opa1 is connected to the source of power transistor MP1. The inverting input terminal of the feedback control amplifier module opa1 is respectively connected to the drain of power transistor MP1 and the source of power transistor MP2. The output terminal of the feedback control amplifier module opa1 is connected to the substrate potential of power transistor MP1;

[0010] After the feedback control amplifier module opa1 detects the signals of the source and drain of power transistor MP1, the output terminal vout0 of the feedback control amplifier module opa1 controls the substrate potential of power transistor MP1.

[0011] Preferably, it further includes an error amplifier opa0 and a feedback resistor module. The non-inverting input terminal of the error amplifier opa0 receives a reference signal Vref. The inverting input terminal of the error amplifier opa0 is electrically connected to the feedback resistor module. The output control terminal G of the error amplifier opa0 is respectively connected to the gates of power transistors MP1 and MP2;

[0012] After the error amplifier opa0 compares the feedback signal input by the feedback resistor module with the reference signal Vref, the output control terminal G of the error amplifier opa0 outputs a control signal to power transistors MP1 and MP2.

[0013] Preferably, the feedback resistor module includes resistors R1 and R2. Resistors R1 and R2 are connected in series. The series-connected resistor R1 is connected to the drain of power transistor MP2, and the drain of power transistor MP2 is the output voltage Vout. Resistor R2 is grounded. The inverting input terminal of the error amplifier opa0 is connected to the common terminal of resistors R1 and R2.

[0014] Preferably, the feedback control amplifier module opa1 includes an input stage unit, a frequency compensation unit, and an output stage unit;

[0015] The input stage unit includes power transistors NM9, NM7, NM8, NM1, and NM2. The drain of power transistor NM9 is connected to current source Ib1. The drain of power transistor NM9 is connected to the gate of power transistor NM8. The gate of power transistor NM9 is connected to the gate of power transistor NM7. The drain of power transistor NM9 is also connected to its own gate. The sources of power transistors NM9, NM7, and NM8 are grounded. The drains of power transistors NM7 and NM8 are respectively connected to the sources of power transistors NM1 and NM2. The gates of power transistors NM1 and NM2 are respectively connected to differential input signals Vinp and Vinn;

[0016] The frequency compensation unit includes resistor R1 and capacitor C1. The two ends of resistor R1 and capacitor C1 are respectively connected in parallel to the sources of power transistors NM1 and NM2;

[0017] The output stage unit includes power transistors NM3, NM4, NM5, NM6, PM3, PM4, PM5, PM6, and PM7. Power transistors NM3, NM4, NM5, and NM6 together form a current mirror;

[0018] The gates of power transistors PM3 and PM4 are commonly connected and connected to bias voltage Vbias. The sources of power transistors PM3 and PM4 are respectively connected to the sources of power transistors PM5 and PM6. And the drains of power transistors NM1 and NM2 are respectively connected to the common connection terminals of power transistors PM3, PM5 and power transistors PM4, PM6. The drains of power transistors PM5 and PM6 are grounded. The gates of power transistors PM5 and PM6 are commonly connected and connected to the gate and source of power transistor PM7. The drain of power transistor PM7 is grounded. The drain of power transistor PM7 is connected to current source Ib1;

[0019] The drain of power transistor PM3 is connected to the drain of power transistor NM3. The drain of power transistor PM4 is connected to the drain of power transistor NM4. The gates of power transistors NM3 and NM4 are connected. The gates of power transistors NM5 and NM6 are connected. The drain of power transistor PM3 is also commonly connected to the gates of power transistors NM3, NM4, NM5, and NM6. The drain of power transistor PM4 is the output voltage Vout. The sources of power transistors NM5 and NM6 are grounded.

[0020] Preferably, the feedback control amplifier module opa1 includes an input stage unit, a frequency compensation unit, and an output stage unit;

[0021] The input stage unit includes power transistors NM9, NM7, NM8, NM1, and NM2. The drain of power transistor NM9 is connected to current source Ib1. The drain of power transistor NM9 is connected to the gate of power transistor NM8. The gate of power transistor NM9 is connected to the gate of power transistor NM7. The drain of power transistor NM9 is also connected to the gate of power transistor NM9. The sources of power transistors NM9, NM7, and NM8 are grounded. The drains of power transistors NM7 and NM8 are respectively connected to the sources of power transistors NM1 and NM2. The gates of power transistors NM1 and NM2 are respectively connected to differential input signals Vinp and Vinn;

[0022] The frequency compensation unit includes capacitors C21, C22, resistors R21 and R22, and a bias circuit. Capacitor C21 is in parallel with resistor R21. Capacitor C22 is in parallel with resistor R22. One ends of resistors R21 and R22 are grounded. The other end of resistor R21 is connected to the substrate bias potential Vsub1 of power transistor NM1. The other end of resistor R22 is connected to the substrate bias potential Vsub2 of power transistor NM2;

[0023] The bias circuit includes power transistors PM8, PM9, and PM10. The gate of power transistor PM8 is connected to the gates of power transistors PM9 and PM10. The source of power transistor PM8 is connected to current source Ib3. The source of power transistor PM8 is connected to the gate of power transistor PM8. The drains of power transistors PM8, PM9, and PM10 are grounded. The source of power transistor PM9 is connected to substrate bias potential Vsub1. The source of power transistor PM10 is connected to substrate bias potential Vsub2;

[0024] The output stage unit includes power transistors NM3, NM4, NM5, NM6, PM3, PM4, PM5, PM6, and PM7. Power transistors NM3, NM4, NM5, and NM6 together form a current mirror;

[0025] The gates of the power transistors PM3 and PM4 are commonly connected and are connected to a bias voltage Vbias. The sources of the power transistors PM3 and PM4 are respectively connected to the sources of the power transistors PM5 and PM6. The drains of the power transistors NM1 and NM2 are respectively connected to the common connection terminals of the power transistors PM3 and PM5 and the common connection terminals of the power transistors PM4 and PM6. The drains of the power transistors PM5 and PM6 are grounded. The gates of the power transistors PM5 and PM6 are commonly connected and are connected to the gate and source of the power transistor PM7. The drain of the power transistor PM7 is grounded, and a current source Ib1 is connected to the drain of the power transistor PM7;

[0026] The drain of the power transistor PM3 is connected to the drain of the power transistor NM3. The drain of the power transistor PM4 is connected to the drain of the power transistor NM4. The gates of the power transistors NM3 and NM4 are connected. The gates of the power transistors NM5 and NM6 are connected. The drain of the power transistor PM3 is also commonly connected to the gates of the power transistors NM3, NM4, NM5, and NM6. The drain of the power transistor PM4 is the output voltage Vout. The sources of the power transistors NM5 and NM6 are grounded.

[0027] Preferably, the feedback control amplifier module opa1 includes an input stage unit, a frequency compensation unit, and an output stage unit;

[0028] The input stage unit includes the power transistors NM9, NM7, NM8, NM1, and NM2. The drain of the power transistor NM9 is connected to a current source Ib1. The drain of the power transistor NM9 is connected to the gate of the power transistor NM8. The gates of the power transistors NM9 and NM7 are connected. The drain of the power transistor NM9 is also connected to its own gate. The sources of the power transistors NM9, NM7, and NM8 are grounded. The drains of the power transistors NM7 and NM8 are respectively connected to the sources of the power transistors NM1 and NM2. The gates of the power transistors NM1 and NM2 are respectively connected to differential input signals Vinp and Vinn;

[0029] The frequency compensation unit includes a capacitor C21 and a resistor R21. The capacitor C21 is in parallel with the resistor R21. One end of the resistor R21 is grounded, and the other end of the resistor R21 is connected to the substrate bias potential Vsub1 of the power transistors NM1 and NM2;

[0030] The bias circuit includes power transistors PM8 and PM9. The gates of power transistor PM8 and power transistor PM9 are connected. The source of power transistor PM8 is connected to current source Ib3. The source of power transistor PM8 is connected to the gate of power transistor PM8. The drains of power transistor PM8 and power transistor PM9 are grounded. The source of power transistor PM9 is connected to substrate bias potential Vsub1;

[0031] The output stage unit includes power transistors NM3, NM4, NM5, NM6, PM3, PM4, PM5, PM6 and PM7. Power transistors NM3, NM4, NM5 and NM6 together form a current mirror;

[0032] The gates of power transistors PM3 and PM4 are commonly connected and connected to bias voltage Vbias. The sources of power transistors PM3 and PM4 are respectively connected to the sources of power transistors PM5 and PM6. The drains of power transistors NM1 and NM2 are respectively connected to the common connection ends of power transistors PM3 and PM5 and the common connection ends of power transistors PM4 and PM6. The drains of power transistors PM5 and PM6 are grounded. The gates of power transistors PM5 and PM6 are commonly connected and connected to the gate and source of power transistor PM7. The drain of power transistor PM7 is grounded. The drain of power transistor PM7 is connected to current source Ib1;

[0033] The drain of power transistor PM3 is connected to the drain of power transistor NM3. The drain of power transistor PM4 is connected to the drain of power transistor NM4. The gates of power transistor NM3 and power transistor NM4 are connected. The gates of power transistor NM5 and power transistor NM6 are connected. The drain of power transistor PM3 is also commonly connected to the gates of power transistors NM3, NM4, NM5 and NM6. The drain of power transistor PM4 is the output voltage Vout. The sources of power transistors NM5 and NM6 are grounded.

[0034] Preferably, the drain of power transistor MP2 is also connected to one end of resistor Rload and capacitor CL. The other ends of resistor Rload and capacitor CL are grounded.

[0035] The beneficial effects of the present invention are:

[0036] 1. Through special design, the feedback control amplifier module opa1 in this circuit has a lower gain in the low-frequency band and an increased gain in the high-frequency band. At high frequencies, by raising the substrate potential of MP1, the impedance of the MP1 transistor is increased, thereby improving the power supply rejection ratio (PSRR) in the high-frequency band and effectively suppressing the influence of high-frequency noise in the power supply on the output voltage, meeting the requirements for the power supply rejection ratio in high-precision fields.

[0037] 2. Different designs of the feedback control amplifier module opa1, especially the settings of the frequency compensation unit, such as different combinations of capacitors and resistors, have different effects on signals at different frequencies, achieving frequency compensation and enabling the circuit to operate stably in a specific frequency band, further optimizing the circuit performance and enhancing the ability to suppress power supply noise.

[0038] In addition to the purposes, features, and advantages described above, the present invention has other purposes, features, and advantages. The following will refer to the drawings to further elaborate on the present invention in detail. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The specification drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0040] Figure 1 is a system block diagram of a circuit for improving the high power supply rejection ratio of an LDO according to the present invention;

[0041] Figure 2 is a circuit diagram of a circuit for improving the high power supply rejection ratio of an LDO according to the present invention;

[0042] Figure 3 is a circuit diagram of the first feedback control amplifier according to the present invention;

[0043] Figure 4 is a circuit diagram of the second feedback control amplifier according to the present invention;

[0044] Figure 5 is a circuit diagram of the third feedback control amplifier according to the present invention;

[0045] Figure 6 is a comparison diagram of the PSRR waveform (dashed line) of the present invention and the PSRR waveform (solid line) of the traditional architecture. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0046] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other. The following will refer to the drawings and combine with the embodiments to elaborate on the present invention in detail.

[0047] To enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present invention.

[0048] Please refer to Figure 1-6 , the embodiments provided by the present invention:

[0049] As Figure 1 and Figure 2 shown, a circuit for improving the high power supply rejection ratio of an LDO includes a feedback control amplifier module opa1 and a power transistor module;

[0050] The power transistor module includes a power transistor MP1 and a power transistor MP2. The drain of the power transistor MP1 is connected to the source of the power transistor MP2. The non-inverting input terminal of the feedback control amplifier module opa1 is connected to the source of the power transistor MP1. The inverting input terminal of the feedback control amplifier module opa1 is respectively connected to the drain of the power transistor MP1 and the source of the power transistor MP2. The output terminal of the feedback control amplifier module opa1 is connected to the substrate potential of the power transistor MP1;

[0051] The feedback resistor module includes a resistor R1 and a resistor R2. The resistor R1 and the resistor R2 are connected in series. The series-connected resistor R1 is connected to the drain of the power transistor MP2, and the drain of the power transistor MP2 is the output voltage Vout. The resistor R2 is grounded. The inverting input terminal of the error amplifier opa0 is connected to the common terminal of the resistor R1 and the resistor R2. The resistor R1 and R2 detect the LDO output voltage Vout and feedback it to the error amplifier opa0.

[0052] The non-inverting input terminal of the error amplifier opa0 is connected to the reference signal Vref. The inverting input terminal of the error amplifier opa0 is electrically connected to the feedback resistor module. The output control terminal G of the error amplifier opa0 is respectively connected to the gates of the power transistor MP1 and the power transistor MP2;

[0053] After the error amplifier opa0 compares the feedback signal input by the feedback resistor module with the reference signal Vref, the output control terminal G of the error amplifier opa0 outputs a control signal to the power transistor MP1 and the power transistor MP2.

[0054] After the feedback control amplifier module opa1 detects the signals of the source and drain of the power transistor MP1, the output terminal vout0 of the feedback control amplifier module opa1 controls the substrate potential of the power transistor MP1. Through circuit design, the gain of this amplifier will only increase in the high-frequency band.

[0055] The working principle is:

[0056] The reference signal Vref is connected to the non-inverting input terminal of the error amplifier opa0. At the same time, the output voltage Vout is divided by the feedback resistor module, resistors R1 and R2 are connected in series, and the feedback signal FB is input to the inverting input terminal of the error amplifier opa0. The error amplifier opa0 compares the two signals to determine the deviation between the output voltage Vout and the reference signal Vref.

[0057] The error amplifier opa0 outputs a control signal from the output control terminal G to the gates of the power tubes MP1 and MP2 according to the comparison result. When the output voltage Vout deviates from the reference signal Vref, the control signal adjusts the conduction degree of the power tubes MP1 and MP2, thereby adjusting the output voltage Vout. For example, if Vout is lower than Vref, the control signal will increase the conduction degree of the power tube to increase Vout; conversely, if Vout is higher than Vref, the conduction degree of the power tube will be reduced to reduce Vout, thereby achieving a stable output voltage.

[0058] The in-phase input of the feedback control amplifier module opa1 is connected to the source of the power tube MP1, and the inverting input is connected to the drain of the power tube MP1, that is, the source of the power tube MP2. Under normal circumstances, the source voltage of MP1 is higher than the drain voltage, and the voltage difference between the two is v1=Vin-Vs2. The feedback control amplifier module opa1 processes the detected source and drain signals, and its output vout0=Gain*v1 (Gain is the auxiliary amplifier gain).

[0059] The feedback control amplifier is specially designed to have a low gain in the low frequency band, so the output Vout0 voltage is low, making the substrate voltage of MP1 low; when the frequency increases, the amplifier gain increases, Vout0 increases, and the MP1 substrate potential increases accordingly. Since the increase in the MP1 substrate potential will increase the impedance of the MP1 tube, the power supply rejection ratio (PSRR) in the high frequency band is improved, effectively suppressing the impact of high-frequency noise in the power supply on the output voltage.

[0060] Furthermore, the drain of the power tube MP2 is also connected to the resistor Rload and one end of the capacitor CL, and the other ends of the resistor Rload and the capacitor CL are grounded. The drain of the power tube MP2 outputs a stable voltage Vout to power the load. At the same time, the capacitor CL plays a filtering role, smoothing the output voltage, reducing voltage fluctuations and high-frequency ripples, and ensuring the stability and purity of the output voltage.

[0061] The specific circuit design of the feedback control amplifier module is as follows:

[0062] like Figure 3As shown, the feedback control amplifier module opa1 includes an input stage unit, a frequency compensation unit, and an output stage unit;

[0063] The input stage unit includes power transistors NM9, NM7, NM8, NM1, and NM2. The drain of power transistor NM9 is connected to current source Ib1. The drain of power transistor NM9 is connected to the gate of power transistor NM8. The gate of power transistor NM9 is connected to the gate of power transistor NM7. The drain of power transistor NM9 is also connected to its own gate. The sources of power transistors NM9, NM7, and NM8 are grounded. The drains of power transistors NM7 and NM8 are respectively connected to the sources of power transistors NM1 and NM2. The gates of power transistors NM1 and NM2 are respectively connected to differential input signals Vinp and Vinn. Power transistors NM1 and NM2 form a differential input pair transistor. Power transistors NM9, NM7, and NM8 provide bias current for the input stage, and a suitable static operating point is determined through current source Ib1.

[0064] The frequency compensation unit includes resistor R1 and capacitor C1. The two ends of resistor R1 and capacitor C1 are respectively connected in parallel to the sources of power transistors NM1 and NM2. Resistor R1 and capacitor C1 form a frequency compensation network;

[0065] The output stage unit includes power transistors NM3, NM4, NM5, NM6, PM3, PM4, PM5, PM6, and PM7. Power transistors NM3, NM4, NM5, and NM6 together form a current mirror for current replication;

[0066] The gates of power transistors PM3 and PM4 are commonly connected and connected to bias voltage Vbias. The sources of power transistors PM3 and PM4 are respectively connected to the sources of power transistors PM5 and PM6. And the drains of power transistors NM1 and NM2 are respectively connected to the common connection terminals of power transistors PM3, PM5 and power transistors PM4, PM6. The drains of power transistors PM5 and PM6 are grounded. The gates of power transistors PM5 and PM6 are commonly connected and connected to the gate and source of power transistor PM7. The drain of power transistor PM7 is grounded. The drain of power transistor PM7 is connected to current source Ib1;

[0067] The drain of power transistor PM3 is connected to the drain of power transistor NM3, the drain of power transistor PM4 is connected to the drain of power transistor NM4, the gates of power transistors NM3 and NM4 are connected, the gates of power transistors NM5 and NM6 are connected, the drain of power transistor PM3 is also commonly connected to the gates of power transistors NM3, NM4, NM5, and NM6, the drain of power transistor PM4 is the output voltage Vout, and the sources of power transistors NM5 and NM6 are grounded.

[0068] In the low-frequency range, the capacitive reactance of capacitor C1 is large, equivalent to an open circuit. At this time, resistor R1 is connected to the sources of power transistors NM1 and NM2, introducing negative feedback and causing the gain of the input stage to decrease.

[0069] As the frequency increases, the capacitive reactance of capacitor C1 decreases, showing a high-pass characteristic, making the source terminal approximately short-circuited and weakening the negative feedback effect. As a result, the gain of the input stage increases. In this way, the entire amplifier circuit achieves the characteristic of having different gains at different frequencies. At the same time, the current mirror structure ensures the current distribution and signal transmission between stages, and finally the output terminal Vout outputs the amplified signal.

[0070] The feedback control amplifier module opa1 can also be replaced with the following design:

[0071] As Figure 4 shown, the feedback control amplifier module opa1 includes an input stage unit, a frequency compensation unit, and an output stage unit; the input stage unit includes power transistors NM9, NM7, NM8, NM1, and NM2. The drain of power transistor NM9 is connected to current source Ib1, the drain of power transistor NM9 is connected to the gate of power transistor NM8, the gates of power transistors NM9 and NM7 are connected, the drain of power transistor NM9 is also connected to its own gate, the sources of power transistors NM9, NM7, and NM8 are grounded, the drains of power transistors NM7 and NM8 are respectively connected to the sources of power transistors NM1 and NM2, and the gates of power transistors NM1 and NM2 are respectively connected to differential input signals Vinp and Vinn.

[0072] Power transistors NM1 and NM2 form a differential input pair for receiving differential input signals Vinp and Vinn. Power transistors NM9, NM7, and NM8 provide bias current for the input stage, and current source Ib1 is used to determine the appropriate quiescent operating point to ensure that power transistors NM1 and NM2 operate in the appropriate region.

[0073] The frequency compensation unit includes capacitor C21, capacitor C22, resistor R21, resistor R22 and a bias circuit. Capacitor C21 is in parallel with resistor R21, and capacitor C22 is in parallel with resistor R22. One end of resistor R21 and resistor R22 is grounded. The other end of resistor R21 is connected to the substrate bias potential Vsub1 of power transistor NM1, and the other end of resistor R22 is connected to the substrate bias potential Vsub2 of power transistor NM2. Capacitor C21, capacitor C22, resistor R21 and resistor R22 adjust the characteristics of the circuit at different frequencies. The network formed by capacitor C21, capacitor C22, resistor R21 and resistor R22 has different effects on signals at different frequencies, achieving frequency compensation and enabling the circuit to operate stably in a specific frequency band. For example, when the frequency is high, the capacitive reactance of the capacitor becomes smaller, the signal path changes, and the amplification characteristics are affected.

[0074] The bias circuit includes power transistors PM8, PM9 and PM10. The gates of power transistor PM8, power transistor PM9 and power transistor PM10 are connected. The source of power transistor PM8 is connected to current source Ib3, and the source of power transistor PM8 is connected to its gate. The drains of power transistor PM8, power transistor PM9 and power transistor PM10 are grounded. The source of power transistor PM9 is connected to substrate bias potential Vsub1, and the source of power transistor PM10 is connected to substrate bias potential Vsub2;

[0075] The output stage unit includes power transistors NM3, NM4, NM5, NM6, power transistors PM3, PM4, PM5, PM6 and power transistor PM7. Power transistors NM3, NM4, NM5, NM6 together form a current mirror to copy and transmit current, and transfer the processed signal current to the output stage;

[0076] The gates of power transistor PM3 and power transistor PM4 are commonly connected and connected to bias voltage Vbias. The sources of power transistor PM3 and power transistor PM4 are respectively connected to the sources of power transistor PM5 and power transistor PM6. And the drains of power transistor NM1 and power transistor NM2 are respectively connected to the common connection terminals of power transistor PM3, power transistor PM5 and the common connection terminals of power transistor PM4, power transistor PM6. The drains of power transistor PM5 and power transistor PM6 are grounded. The gates of power transistor PM5 and power transistor PM6 are commonly connected and connected to the gate and source of power transistor PM7. The drain of power transistor PM7 is grounded, and the drain of power transistor PM7 is connected to current source Ib1;

[0077] The drain of power transistor PM3 is connected to the drain of power transistor NM3, the drain of power transistor PM4 is connected to the drain of power transistor NM4, the gates of power transistors NM3 and NM4 are connected, the gates of power transistors NM5 and NM6 are connected, the drain of power transistor PM3 is also commonly connected to the gates of power transistors NM3, NM4, NM5, and NM6, the drain of power transistor PM4 is the output voltage Vout, and the sources of power transistors NM5 and NM6 are grounded.

[0078] The output stage unit converts the current signal into the voltage signal Vout for output under the bias of current source Ib2. The bias voltage Vbias and the bias circuit ensure that each stage of transistors is at an appropriate operating point to maintain the normal operation of the circuit.

[0079] The feedback control amplifier module opa1 can also be replaced with the following design: The feedback control amplifier module opa1 includes an input stage unit, a frequency compensation unit, and an output stage unit;

[0080] As Figure 5 shown, the input stage unit includes power transistors NM9, NM7, NM8, NM1, and NM2. The drain of power transistor NM9 is connected to current source Ib1, the drain of power transistor NM9 is connected to the gate of power transistor NM8, the gates of power transistors NM9 and NM7 are connected, the drain of power transistor NM9 is also connected to its own gate, the sources of power transistors NM9, NM7, and NM8 are grounded, the drains of power transistors NM7 and NM8 are respectively connected to the sources of power transistors NM1 and NM2, and the gates of power transistors NM1 and NM2 are respectively connected to the differential input signals Vinp and Vinn;

[0081] The frequency compensation unit includes capacitor C21 and resistor R21. Capacitor C21 is in parallel with resistor R21. One end of resistor R21 is grounded, and the other end of resistor R21 is connected to the substrate bias potential Vsub1 of power transistors NM1 and NM2. The network composed of resistor R21 and capacitor C21 generates different impedances for signals at different frequencies. At high frequencies, the capacitive reactance of C21 decreases, which will bypass part of the signal, thereby adjusting the high-frequency gain of the circuit, avoiding high-frequency self-oscillation, and enabling the circuit to operate stably;

[0082] The bias circuit includes power transistors PM8 and PM9. The gates of power transistor PM8 and power transistor PM9 are connected. The source of power transistor PM8 is connected to current source Ib3. The source of power transistor PM8 is connected to its gate. The drains of power transistor PM8 and power transistor PM9 are grounded. The source of power transistor PM9 is connected to substrate bias potential Vsub1 to provide appropriate bias voltages for each stage of transistors, ensure that they operate in the best state, and maintain the stable operation of the entire circuit;

[0083] The output stage unit includes power transistors NM3, NM4, NM5, NM6, PM3, PM4, PM5, PM6 and PM7. Power transistors NM3, NM4, NM5, NM6 together form a current mirror;

[0084] The gates of power transistors PM3 and PM4 are commonly connected and connected to bias voltage Vbias. The sources of power transistors PM3 and PM4 are respectively connected to the sources of power transistors PM5 and PM6. And the drains of power transistors NM1 and NM2 are respectively connected to the common connection terminals of power transistors PM3, PM5 and power transistors PM4, PM6. The drains of power transistors PM5 and PM6 are grounded. The gates of power transistors PM5 and PM6 are commonly connected and connected to the gate and source of power transistor PM7. The drain of power transistor PM7 is grounded. The drain of power transistor PM7 is connected to current source Ib1;

[0085] The drain of power transistor PM3 is connected to the drain of power transistor NM3. The drain of power transistor PM4 is connected to the drain of power transistor NM4. The gates of power transistor NM3 and power transistor NM4 are connected. The gates of power transistor NM5 and power transistor NM6 are connected. The drain of power transistor PM3 is also commonly connected to the gates of power transistors NM3, NM4, NM5, NM6. The drain of power transistor PM4 is the output voltage Vout. The sources of power transistors NM5 and NM6 are grounded.

[0086] As Figure 6 shown, after comparing the novel high power supply rejection LDO architecture circuit with the traditional LDO architecture, the dotted line in the figure is the PSRR waveform of the novel high power supply rejection LDO architecture, and the solid line is the PSRR waveform of the traditional LDO architecture. In the high frequency range, the PSRR of the novel high power supply rejection LDO architecture is improved compared with the traditional LDO architecture. Figure 6 In it, A_LG: open-loop gain of the error amplifier; β: loop gain coefficient; β*A_LG: loop gain; f: represents the frequency represented by the abscissa in the figure;

[0087] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A circuit for improving the power supply rejection ratio of an LDO, characterized in that: Including feedback control amplifier module opa1 and power tube module; The power tube module includes a power tube MP1 and a power tube MP2, the drain of the power tube MP1 is connected to the source of the power tube MP2, the in-phase input end of the feedback control amplifier module opa1 is connected to the source of the power tube MP1, the inverting input end of the feedback control amplifier module opa1 is respectively connected to the drain of the power tube MP1 and the source of the power tube MP2, and the output end of the feedback control amplifier module opa1 is connected to the substrate potential of the power tube MP1; After the feedback control amplifier module opa1 detects the signals of the source and drain of the power tube MP1, the output terminal vout0 of the feedback control amplifier module opa1 controls the substrate potential of the power tube MP1; It also includes an error amplifier opa0 and a feedback resistor module, wherein the in-phase input terminal of the error amplifier opa0 is connected to a reference signal Vref, the inverting input terminal of the error amplifier opa0 is electrically connected to the feedback resistor module, and the output control terminal G of the error amplifier opa0 is respectively connected to the gates of the power tube MP1 and the power tube MP2; After the error amplifier opa0 compares the feedback signal input by the feedback resistor module with the reference signal Vref, the output control terminal G of the error amplifier opa0 outputs a control signal to the power tube MP1 and the power tube MP2; The feedback resistor module includes a resistor R1 and a resistor R2, the resistor R1 and the resistor R2 are connected in series, the series resistor R1 is connected to the drain of the power tube MP2, and the drain of the power tube MP2 is the output voltage Vout, the resistor R2 is grounded, and the inverting input terminal of the error amplifier opa0 is connected to the common terminal of the resistor R1 and the resistor R2.

2. A circuit for improving the high power supply rejection ratio of an LDO according to claim 1, characterized in that: The feedback control amplifier module opa1 includes an input stage unit, a frequency compensation unit and an output stage unit; The input stage unit includes a power tube NM9, a power tube NM7, a power tube NM8, a power tube NM1 and a power tube NM2, the drain of the power tube NM9 is connected to the current source Ib1, the drain of the power tube NM9 is connected to the gate of the power tube NM8, the gate of the power tube NM9 is connected to the gate of the power tube NM7, the drain of the power tube NM9 is also connected to the gate of the power tube NM9, the source electrodes of the power tubes NM9, NM7 and NM8 are grounded, the drain of the power tube NM7 and the drain of the power tube NM8 are respectively connected to the source electrodes of the power tube NM1 and the power tube NM2, and the gate electrodes of the power tubes NM1 and NM2 are respectively connected to the differential input signals Vinp and Vinn; The frequency compensation unit includes a resistor R1 and a capacitor C1, and both ends of the resistor R1 and the capacitor C1 are connected in parallel to the source electrodes of the power tube NM1 and the power tube NM2 respectively; The output stage unit includes power tube NM3, power tube NM4, power tube NM5, power tube NM6, power tube PM3, power tube PM4, power tube PM5, power tube PM6 and power tube PM7, and the power tube NM3, power tube NM4, power tube NM5 and power tube NM6 together form a current mirror; The gates of the power tubes PM3 and PM4 are connected in common and are connected to a bias voltage Vbias. The sources of the power tubes PM3 and PM4 are connected to the sources of the power tubes PM5 and PM6 respectively. The drains of the power tubes NM1 and NM2 are connected to the common terminals of the power tubes PM3 and PM5 and the common terminals of the power tubes PM4 and PM6 respectively. The drains of the power tubes PM5 and PM6 are grounded. The gates of the power tubes PM5 and PM6 are connected in common and are connected to the gate and source of the power tube PM7. The drain of the power tube PM7 is grounded. The drain of the power tube PM7 is connected to a current source Ib1. The drain of the power tube PM3 is connected to the drain of the power tube NM3, the drain of the power tube PM4 is connected to the drain of the power tube NM4, the gate of the power tube NM3 is connected to the gate of the power tube NM4, the gate of the power tube NM5 is connected to the gate of the power tube NM6, the drain of the power tube PM3 is also connected to the gates of the power tubes NM3, NM4, NM5 and NM6, the drain of the power tube PM4 is the output voltage Vout, and the sources of the power tubes NM5 and NM6 are grounded.

3. The circuit for improving the power supply rejection ratio of an LDO according to claim 1, characterized in that: The feedback control amplifier module opa1 includes an input stage unit, a frequency compensation unit and an output stage unit; The input stage unit includes a power tube NM9, a power tube NM7, a power tube NM8, a power tube NM1 and a power tube NM2, the drain of the power tube NM9 is connected to the current source Ib1, the drain of the power tube NM9 is connected to the gate of the power tube NM8, the gate of the power tube NM9 is connected to the gate of the power tube NM7, the drain of the power tube NM9 is also connected to the gate of the power tube NM9, the source electrodes of the power tubes NM9, NM7 and NM8 are grounded, the drain of the power tube NM7 and the drain of the power tube NM8 are respectively connected to the source electrodes of the power tube NM1 and the power tube NM2, and the gate electrodes of the power tubes NM1 and NM2 are respectively connected to the differential input signals Vinp and Vinn; The frequency compensation unit includes a capacitor C21, a capacitor C22, a resistor R21, a resistor R22 and a bias circuit, the capacitor C21 is connected in parallel with the resistor R21, the capacitor C22 is connected in parallel with the resistor R22, one end of the resistor R21 and the resistor R22 is grounded, the other end of the resistor R21 is connected to the substrate bias potential Vsub1 of the power tube NM1, and the other end of the resistor R22 is connected to the substrate bias potential Vsub2 of the power tube NM2; The bias circuit includes a power tube PM8, a power tube PM9 and a power tube PM10, the gate of the power tube PM8 is connected to the gate of the power tube PM9 and the gate of the power tube PM10, the source of the power tube PM8 is connected to the current source Ib3, the source of the power tube PM8 is connected to the gate of the power tube PM8, the drains of the power tube PM8, the power tube PM9 and the power tube PM10 are grounded, the source of the power tube PM9 is connected to the substrate bias potential Vsub1, and the source of the power tube PM10 is connected to the substrate bias potential Vsub2; The output stage unit includes power tube NM3, power tube NM4, power tube NM5, power tube NM6, power tube PM3, power tube PM4, power tube PM5, power tube PM6 and power tube PM7, and the power tube NM3, power tube NM4, power tube NM5 and power tube NM6 together form a current mirror; The gates of the power tubes PM3 and PM4 are connected in common and are connected to a bias voltage Vbias. The sources of the power tubes PM3 and PM4 are connected to the sources of the power tubes PM5 and PM6 respectively. The drains of the power tubes NM1 and NM2 are connected to the common terminals of the power tubes PM3 and PM5 and the common terminals of the power tubes PM4 and PM6 respectively. The drains of the power tubes PM5 and PM6 are grounded. The gates of the power tubes PM5 and PM6 are connected in common and are connected to the gate and source of the power tube PM7. The drain of the power tube PM7 is grounded. The drain of the power tube PM7 is connected to a current source Ib1. The drain of the power tube PM3 is connected to the drain of the power tube NM3, the drain of the power tube PM4 is connected to the drain of the power tube NM4, the gate of the power tube NM3 is connected to the gate of the power tube NM4, the gate of the power tube NM5 is connected to the gate of the power tube NM6, the drain of the power tube PM3 is also connected to the gates of the power tubes NM3, NM4, NM5 and NM6, the drain of the power tube PM4 is the output voltage Vout, and the sources of the power tubes NM5 and NM6 are grounded.

4. The circuit for improving the power supply rejection ratio of an LDO according to claim 1, characterized in that: The feedback control amplifier module opa1 includes an input stage unit, a frequency compensation unit and an output stage unit; The input stage unit includes a power tube NM9, a power tube NM7, a power tube NM8, a power tube NM1 and a power tube NM2, the drain of the power tube NM9 is connected to the current source Ib1, the drain of the power tube NM9 is connected to the gate of the power tube NM8, the gate of the power tube NM9 is connected to the gate of the power tube NM7, the drain of the power tube NM9 is also connected to the gate of the power tube NM9, the source electrodes of the power tubes NM9, NM7 and NM8 are grounded, the drain of the power tube NM7 and the drain of the power tube NM8 are respectively connected to the source electrodes of the power tube NM1 and the power tube NM2, and the gate electrodes of the power tubes NM1 and NM2 are respectively connected to the differential input signals Vinp and Vinn; The frequency compensation unit includes a bias circuit, a capacitor C21 and a resistor R21, wherein the capacitor C21 is connected in parallel with the resistor R21, one end of the resistor R21 is grounded, and the other end of the resistor R21 is connected to the substrate bias potential Vsub1 of the power tube NM1 and the power tube NM2; The bias circuit includes a power tube PM8 and a power tube PM9, the gate of the power tube PM8 is connected to the gate of the power tube PM9, the source of the power tube PM8 is connected to the current source Ib3, the source of the power tube PM8 is connected to the gate of the power tube PM8, the drains of the power tube PM8 and the power tube PM9 are grounded, and the source of the power tube PM9 is connected to the substrate bias potential Vsub1; The output stage unit includes power tube NM3, power tube NM4, power tube NM5, power tube NM6, power tube PM3, power tube PM4, power tube PM5, power tube PM6 and power tube PM7, and the power tube NM3, power tube NM4, power tube NM5 and power tube NM6 together form a current mirror; The gates of the power tubes PM3 and PM4 are connected in common and are connected to a bias voltage Vbias. The sources of the power tubes PM3 and PM4 are connected to the sources of the power tubes PM5 and PM6 respectively. The drains of the power tubes NM1 and NM2 are connected to the common terminals of the power tubes PM3 and PM5 and the common terminals of the power tubes PM4 and PM6 respectively. The drains of the power tubes PM5 and PM6 are grounded. The gates of the power tubes PM5 and PM6 are connected in common and are connected to the gate and source of the power tube PM7. The drain of the power tube PM7 is grounded. The drain of the power tube PM7 is connected to a current source Ib1. The drain of the power tube PM3 is connected to the drain of the power tube NM3, the drain of the power tube PM4 is connected to the drain of the power tube NM4, the gate of the power tube NM3 is connected to the gate of the power tube NM4, the gate of the power tube NM5 is connected to the gate of the power tube NM6, the drain of the power tube PM3 is also connected to the gates of the power tubes NM3, NM4, NM5 and NM6, the drain of the power tube PM4 is the output voltage Vout, and the sources of the power tubes NM5 and NM6 are grounded.

5. The circuit for improving the power supply rejection ratio of an LDO according to claim 1, characterized in that: The drain of the power tube MP2 is also connected to the resistor Rload and one end of the capacitor CL, and the other ends of the resistor Rload and the capacitor CL are grounded.

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