Iic communication slave low power consumption sleep digital implementation method

Abstract

The application discloses a kind of IIC communication slave low-power sleep digital implementation methods, specific steps include: S1: host sends control instruction by IIC communication bus;S2: IIC decoding unit is by parsing the data of IIC communication bus;Confirm data type, if it is sleep instruction, then data is sent to IIC sleep \ wake-up control unit;If it is application control instruction, then data is sent to system application control unit;While 1 high level output control wake-up decoding unit and total control unit;The small circuit module of the application has good interference, prevents mis-triggering wake-up work when normal working, the method used in the application is when normal working, so that wake-up small circuit does not participate in decoding work, in reset state;Can maximum limit reduce the sleep power consumption of chip digital module, while there is good anti-interference and good applicability, can effectively make system sleep or wake up.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuits, and particularly relates to a low-power sleep digital implementation method for an IIC communication slave. BACKGROUND

[0002] With the popularity of mobile devices, more and more devices are powered by batteries. In order to provide the use time and service life of the battery, the power consumption requirement for the chip is higher and higher. The low-power design of the chip puts forward higher requirements, and the low-power design is a difficulty for the digital design of the chip. Therefore, the application provides a low-power sleep digital implementation method for an IIC communication slave, which can make the chip consume extremely low power consumption after entering the low-power sleep, thereby improving the use time and service life of the battery. SUMMARY

[0003] The application aims to provide a low-power sleep digital implementation method for an IIC communication slave to solve the problems in the background.

[0004] To achieve the above-mentioned purpose, the application provides the following technical scheme: a low-power sleep digital implementation method for an IIC communication slave, and the specific steps include: S1: the host sends a control instruction through an IIC communication bus;

[0005] S2: the IIC decoding unit analyzes the data of the IIC communication bus; if the data is a sleep instruction, the data is sent to an IIC sleep\wake-up control unit; if the data is an application control instruction, the data is sent to a system application control unit;

[0006] S3: after receiving the sleep instruction, the IIC sleep\wake-up control unit notifies the system application control unit to exit the application control to prevent the disorder of the application control; and simultaneously outputs a high level to control the wake-up decoding unit and the total control unit;

[0007] S4: the output control signal of the IIC sleep\wake-up control unit is the reset control signal of the wake-up decoding unit; when the output control signal is at a low level, the sleep control unit is always in a reset state; when the system is in a normal working state, the wake-up decoding unit is in a reset state; when the system enters sleep, the reset signal is at a high level, and at this time, the wake-up decoding unit is enabled; therefore, it is indicated that the wake-up unit circuit is enabled only after entering sleep; in this way, the interference of the system can be effectively reduced;

[0008] S5: when the wake-up decoding unit is reset, the wake-up control unit outputs a high level; when the chip is in a normal working state and is not in sleep, the wake-up control unit outputs a high level; and the high level output is maintained; only when the wake-up decoding unit is in an active working state and receives a wake-up working instruction, the wake-up control unit outputs a low level;

[0009] S6: Since the wake-up control unit outputs a high level at this time, the IIC sleep / wake-up control unit outputs a high level, and the total control unit outputs a high level, when the total control unit is at a high level, the total control unit outputs an enable signal of the RC system clock, and the RC system clock is disabled at a high level, and the clock is turned off; since there is no clock driving at this time, the flip rate is at a low level, and the system power consumption is reduced; when the host IIC communication bus does not need to wake up the slave, the IIC communication bus communication signal is also not flipped at this time, and the wake-up decoding unit is also not clock driven;

[0010] S7: When wake-up is needed, the host sends data, and at this time, since the wake-up decoding unit is driven by the IIC communication bus, other units are not clock driven, and only the wake-up decoding unit participates in the decoding work, when the wake-up decoding unit analyzes the wake-up instruction, the wake-up control unit is controlled to be at a low level;

[0011] S8: The total control unit of the AND gate controller is at a low level due to the output of the wake-up control unit, and the total control unit is at a low level, and at this time, the RC system clock starts to work;

[0012] S9: Since the RC system clock starts to work at this time, the IIC decoding unit is clock driven, and the wake-up instruction sent by the host through the IIC communication bus can be analyzed; after receiving the wake-up instruction, the IIC sleep / wake-up control unit is controlled to output a low level, the wake-up decoding unit is reset, and a low level is output to control the total control unit to output a low level, and when the total control unit outputs a low level, the RC system clock is enabled, so that the entire system can work normally.

[0013] Preferably, the total control unit is an AND gate controller, which means that when the inputs are all at a high level, the output is at a high level.

[0014] Preferably, the RC system clock is a driving clock for the entire application system, which drives the IIC decoding unit to decode data and interact with the host, and drives the IIC sleep / wake-up control unit to control sleep or wake-up, and can also drive the system application control unit to control the application.

[0015] Preferably, the wake-up decoding unit is only driven by the IIC communication bus signal.

[0016] Preferably, the system module used in the method includes an RC system clock, an IIC communication bus, an IIC decoding unit, an IIC sleep / wake-up control unit, a wake-up decoding unit, a wake-up control unit, a system application control unit, a total control unit, and a host.

[0017] Compared with the prior art, the present application has the advantages that: the present application adopts a simple small circuit module as a clock wake-up module of a complex circuit, monitors host signals in real time, wakes up the clock of the system with the simple small circuit module, and adopts a communication signal as a driving clock; the frequency of the communication signal is less than the system frequency, and the power consumption is smaller, and the module only works when the system is in sleep, in addition, after the slave enters sleep, the host has a long time without communication with the slave, so the communication signal as the driving clock can be turned off, so that the driving frequency of the simple small circuit module is 0Hz, so that the whole system has no clock driving, and the power consumption of the system in sleep can be greatly reduced.

[0018] In addition, the small circuit module of the present application has good anti-interference performance, prevents false triggering of wake-up work in normal work, and the method adopted by the present application is that the wake-up small circuit does not participate in decoding work in normal work and is in a reset state; the sleep power consumption of the chip digital module can be maximally reduced, and the system can be effectively put into sleep or wake-up. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 The flowchart of the present application is shown. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0021] Embodiment 1

[0022] Please refer to Figure 1 The first embodiment of the present application provides a technical solution: a low-power sleep digital implementation method of an IIC communication slave, and the specific steps include: S1: the host sends a control instruction through an IIC communication bus;

[0023] S2: the IIC decoding unit analyzes the data of the IIC communication bus; confirms the data type, and if it is a sleep instruction, sends the data to the IIC sleep\wake-up control unit; if it is an application control instruction, sends the data to the system application control unit;

[0024] S3: after the IIC sleep\wake-up control unit receives the sleep instruction, informs the system application control unit to exit the application control to prevent the disorder of the application control; at the same time, sets 1 (high level) to output control wake-up decoding unit and total control unit;

[0025] S4: the output control signal of the IIC sleep / wakeup control unit is the reset control signal of the wakeup decoding unit; when the output control signal is 0 (low level), the sleep control unit is always in the reset state; then, when the system is in the normal working state, the wakeup decoding unit is in the reset state; when the system enters sleep, the reset signal is set to 1 (high level), at this time, the wakeup decoding unit is enabled; then, it is explained that only after entering sleep, the wakeup unit circuit is enabled; in this way, the system interference can be effectively reduced;

[0026] S5: when the wakeup decoding unit is reset, the wakeup control unit outputs 1 (high level); when the chip is normally working and not in sleep, the wakeup control unit outputs 1 (high level); and remains 1 (high level) output, only when the wakeup decoding unit is in the active working state and receives the wakeup working instruction, the output is set to 0 (low level);

[0027] S6: since the wakeup control unit outputs 1 (high level) and the IIC sleep / wakeup control unit outputs 1 (high level) at this time, the total control unit outputs 1 (high level); when the total control unit is 1 (high level), the RC system clock is invalid, and the clock is turned off; since there is no clock driving at this time, the flip rate is 0 (low level), thereby reducing the system power consumption; when the host IIC communication bus does not need to wake up the slave, the IIC communication bus communication signal is also not flipped at this time, and the wakeup decoding unit is also not clock driven;

[0028] S7: when the wakeup is needed, the host sends data; at this time, since the wakeup decoding unit is driven by the IIC communication bus, other units are not clock driven, only the wakeup decoding unit participates in the decoding work; when the wakeup decoding unit analyzes the wakeup instruction, the wakeup control unit is set to 0 (low level);

[0029] S8: the total control unit of the AND gate controller; since the wakeup control unit outputs 0 (low level), the total control unit outputs 0 (low level), at this time, the RC system clock starts to work;

[0030] S9: since the RC system clock starts to work at this time, the IIC decoding unit has clock driving, and the wakeup instruction sent by the host through the IIC communication bus can be analyzed; after receiving the wakeup instruction, the IIC sleep / wakeup control unit outputs 0 (low level), the wakeup decoding unit is reset, and 0 (low level) is output to control the total control unit to output low level; when the total control unit outputs 0 (low level), the RC system clock is enabled, and the whole system can work normally.

[0031] In the embodiment, preferably, the total control unit is an AND gate controller, which means that when all inputs are 1 (high level), the output is 1 (high level).

[0032] In the embodiment, preferably, the RC system clock provides a driving clock for the whole application system, drives the IIC decoding unit to decode data and interact with the host, and drives the IIC sleep / wake control unit to control sleep or wake up, and can also drive the system application control unit to control application.

[0033] In the embodiment, preferably, the wake-up decoding unit is only driven by the IIC communication bus signal.

[0034] In the embodiment, preferably, the system module used in the method includes an RC system clock, an IIC communication bus, an IIC decoding unit, an IIC sleep / wake control unit, a wake-up decoding unit, a wake-up control unit, a system application control unit, a total control unit, and a host.

[0035] Although the embodiments of the present application have been shown and described (in detail) above, it should be understood by those ordinary skilled in the art that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present application, and the scope of the present application is defined by the appended claims and their equivalents.

Claims

1. A low-power sleep mode digital implementation method for IIC communication slave devices, characterized in that: The specific steps include: S1: The host sends control commands through the IIC communication bus; S2: The IIC decoding unit parses the data on the IIC communication bus; confirms the data type; if it is a sleep command, it sends the data to the IIC sleep / wake-up control unit; if it is an application control command, it sends the data to the system application control unit. S3: After receiving the hibernation command, the IIC sleep / wake-up control unit notifies the system application control unit to exit application control; at the same time, it sets a high-level output to control the wake-up decoding unit and the main control unit. S4: The output control signal of the IIC sleep / wake-up control unit is the reset control signal of the wake-up decoding unit; when the output control signal is low, the sleep control unit is always in the reset state; when the system is in normal working state, the wake-up decoding unit is in the reset state; when the system enters sleep mode, the reset signal is set to high level, and the wake-up decoding unit is then enabled. S5: When the wake-up decoding unit is reset, the wake-up control unit outputs a high level. This means that when the chip is working normally and not in sleep mode, the wake-up control unit outputs a high level and maintains a high level output. Only after the wake-up decoding unit is in an active working state and receives a wake-up command will the output be set to a low level. S6: Since the wake-up control unit outputs a high level and the IIC sleep / wake-up control unit outputs a high level, the main control unit outputs a high level. When the main control unit of the AND gate controller is high, the output signal of the main control unit is the enable signal of the RC system clock. When the signal is high, the RC system clock is disabled and the clock is turned off. Since there is no clock drive at this time, the toggle rate is low, which reduces the system power consumption. When the slave is in sleep mode, when the master IIC communication bus does not need to wake up the slave, the IIC communication bus communication signal does not toggle, so the wake-up decoding unit also has no clock drive. S7: When wake-up is required, the host sends data. At this time, since the wake-up decoding unit is driven by the IIC communication bus, and other units are not driven by the clock, only the wake-up decoding unit participates in the decoding work. When the wake-up decoding unit parses the wake-up command, it controls the wake-up control unit to set to low level. S8: This is the main control unit of the AND gate controller. Since the wake-up control unit outputs a low level, the main control unit outputs a low level, and the RC system clock starts working at this time. S9: Since the RC system clock starts working at this time, the IIC decoding unit has a clock drive, so it can parse the wake-up command sent by the host through the IIC communication bus; when the wake-up command is received, the IIC sleep / wake-up control unit is controlled to output a low level to reset the wake-up decoding unit. At the same time, the output low level controls the main control unit to output a low level. When the main control unit outputs a low level, the RC system clock is enabled, and the whole system can work normally.

2. The method for implementing low-power sleep mode in IIC communication slave devices according to claim 1, characterized in that: The main control unit is an AND gate controller, which means that when all inputs are high, the output is high.

3. The method for implementing low-power sleep mode in IIC communication slave according to claim 1, characterized in that: The RC system clock provides the driving clock for the entire application system, drives the IIC decoding unit to decode data and interact with the host, drives the IIC sleep / wake-up control unit to perform sleep or wake-up control, and can also drive the system application control unit to perform application control.

4. The method for implementing low-power sleep mode in IIC communication slave according to claim 3, characterized in that: The wake-up decoding unit is driven only by the IIC communication bus signal.

5. The method for implementing low-power sleep mode in IIC communication slave according to claim 4, characterized in that: The system modules used in the method include an RC system clock, an IIC communication bus, an IIC decoding unit, an IIC sleep / wake-up control unit, a wake-up decoding unit, a wake-up control unit, a system application control unit, a main control unit, and a host.

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