Signed number multiply-accumulate operation circuit, CIM chip and electronic equipment

Abstract

The invention relates to a signed number multiply-accumulate operation circuit, a CIM chip and electronic equipment, the signed number multiply-accumulate operation circuit comprises a weight storage array, the weight storage array comprises a plurality of storage modules distributed in rows and columns, each storage module comprises a storage unit and NMOS tubes N5 and N6, the grid electrode and the drain electrode of the N5 are connected with the storage node QB of the storage unit and the source electrode of the N6 respectively, and the storage node QB of the storage unit and the source electrode of the N6 are connected with the storage node QB of the storage unit; the source electrodes of the N5 in the same column are connected with the same bit line BL, the grid electrodes of the N6 in the same row are connected with the same calculation word line IWL, the drain electrodes of the N6 in the same column are connected with the same bit line SL, the bit line BL is further connected with a reference voltage, the bit line SL is further connected with a ground end VSS, and the multi-bit weight W is coded to form w = 2W + 1 and then is stored in the weight storage array in rows. The circuit realizes MAC in-memory calculation of signed data under lower time, area and power consumption overhead, and solves the problem that the multiply-accumulate calculation efficiency of the conventional multiply-accumulate operation circuit with signed numbers is lower.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a signed number multiplication and accumulation operation circuit, a CIM chip and an electronic device. Background Art

[0002] In iterative computing scenarios such as deep neural networks, unsigned numbers need to perform offset compensation (such as +128 zero offset) when processing negative weights, which causes the offset to be amplified multiple times during the accumulation process, and ultimately requires additional subtraction operations for correction. Signed numbers directly retain the weight sign information, eliminating systematic bias at the algorithm level and reducing reasoning errors.

[0003] Data processing based on deep learning algorithms includes a large number of multiply-accumulate (MAC) tasks. Taking convolutional neural networks as an example, the sliding window calculation when generating feature maps involves dense multiplication and accumulation of positive and negative weights and activation values. The use of a signed number architecture can directly handle the retention of negative values ​​after ReLU activation (such as the h-swish function of MobileNet V3), while the unsigned solution requires the introduction of absolute value conversion and sign bit separation, resulting in an increase in the complexity of the calculation graph. This advantage is more prominent in the in-memory computing architecture.

[0004] Existing various types of CIM circuits with MAC functions based on SRAM are highly efficient in integer operations. However, when performing signed data operations, traditional CIM circuits need to introduce a large number of cross switches in the computing unit or require more computing cycles in order to achieve complete convolution operations, which greatly increases the circuit overhead and reduces the efficiency of executing signed multiplication and accumulation operations.

[0005] There is no effective solution to the problem of low multiplication and accumulation efficiency of the current signed multiplication and accumulation circuit. Summary of the invention

[0006] The present invention provides a signed number multiplication-accumulation operation circuit, a CIM chip and an electronic device to solve the problem of low multiplication-accumulation calculation efficiency of the current signed number multiplication-accumulation operation circuit.

[0007] In a first aspect, the present invention provides a signed number multiplication and accumulation operation circuit, comprising: The weight storage array includes a plurality of storage modules distributed in rows and columns, each storage module includes a storage unit and NMOS tubes N5 and N6, the gate and drain of N5 are respectively connected to the storage node QB of the storage unit and the source of N6, the source of N5 in the same column is connected to the same bit line BL, the gate of N6 in the same row is connected to the same calculation word line IWL, the drain of N6 in the same column is connected to the same bit line SL, the bit line BL is also connected to the reference voltage Vref, the bit line SL is also connected to the ground terminal VSS, and the weight of multiple bits is calculated. W Encoding w =2 W After +1, they are stored row by row in the weight storage array; Multiple input coding circuits corresponding to each row of storage modules, the output of each input coding circuit is fed into the calculation word line IWL of the corresponding row, the input coding circuit encodes each bit of the n-bit input in turn and feeds the encoding result into the calculation word line IWL, the encoding method is:

[0008] in, a i represents the output of the i-th encoding of the input encoding circuit, A n-1 ...A 2 A 1 A 0 means n-bit input, A n-1 is the sign bit, A n-2 ...A 2 A 1 A 0 is the digital position; A plurality of voltage clamping current mirror circuits respectively corresponding to each column storage module, each voltage clamping current mirror circuit comprises a first voltage clamping circuit and two first current mirror circuits, the output of the first voltage clamping circuit is the input of the two current mirror circuits, the outputs of the two first current mirror circuits are respectively grounded through a first capacitor and a second capacitor, the input of the first voltage clamping circuit is a bit line BL of the corresponding column, and the capacitance difference between the first capacitor and the second capacitor is used to characterize the multiplication and accumulation result.

[0009] In a second aspect, the present invention provides a CIM chip, which integrates the signed number multiplication and accumulation operation circuit described in the first aspect.

[0010] In a third aspect, the present invention provides an electronic device, which has the CIM chip described in the second aspect built in, and implements convolution operations for deep learning through the CIM chip.

[0011] Compared with the related art, the present invention provides a new circuit architecture and operation logic of a signed number fast operation circuit. A new weight mapping scheme, signed number XNOR operation and bit counting calculation scheme are applied in the circuit scheme, which can divide the multiplication and accumulation calculation results of positive and negative numbers into four parts, so that each part can be accumulated separately during the calculation process, and finally the difference between two calculation capacitors is quantized to calculate the final result, thereby reducing the introduction of a large number of cross switches in the calculation unit of traditional analog signed numbers, saving calculation cycles, and further realizing MAC in-memory calculation of signed data with lower time, area and power consumption overhead, solving the problem of low multiplication and accumulation calculation efficiency of the current signed number multiplication and accumulation operation circuit.

[0012] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a schematic diagram of a signed multiplication-accumulation operation circuit provided in this embodiment; Figure 2 is a structural diagram of an input coding circuit provided in this embodiment; Figure 3 Schematic diagram of XNOR operation of the weight storage array provided in this embodiment; Figure 4 is a circuit diagram of a 6T memory cell provided in this embodiment; Figure 5 is a circuit diagram of a voltage clamp current mirror circuit and a compensation circuit provided in this embodiment; Figure 6 is a schematic diagram of charging the calculation capacitor during the multiplication and accumulation calculation process of this embodiment; Figure 7 is a timing diagram of the multiplication-accumulation calculation process of this embodiment; Figure 8 is a schematic diagram of the calculation result quantization process of this embodiment; Fig. 9 It is an overall timing diagram of the signed multiplication and accumulation operation circuit provided in this embodiment. DETAILED DESCRIPTION

[0014] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0015] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meaning understood by people with general skills in the technical field to which this application belongs. The words "one", "a", "the", "these" and the like in this application do not indicate a quantitative limitation, and they may be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, "A and / or B" may mean: A exists alone, A and B exist at the same time, and B exists alone. Generally, the character " / " indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", "third", etc. in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0016] In this embodiment, a signed multiplication and accumulation operation circuit is provided. Figure 1 is a schematic diagram of a signed multiplication and accumulation circuit provided in this embodiment. Figure 1 As shown, the signed multiplication and accumulation operation circuit includes a weight storage array, a plurality of input encoding circuits corresponding to each row storage module, and a plurality of voltage clamping current mirror circuits corresponding to each column storage module.

[0017] The weight storage array includes a number of storage modules distributed in rows and columns, each storage module includes a storage unit and NMOS tubes N5 and N6, the gate and drain of N5 are respectively connected to the storage node QB of the storage unit and the source of N6, the source of N5 in the same column is connected to the same bit line BL, the gate of N6 in the same row is connected to the same calculation word line IWL, the drain of N6 in the same column is connected to the same bit line SL, the bit line BL is also connected to the reference voltage Vref, and the bit line SL is also connected to the ground terminal VSS, for multi-bit weights W Encoding w =2 W After +1, they are stored row by row in the weight storage array.

[0018] Specifically, the weight storage array can be divided into multiple banks (a bank includes multiple rows of storage modules), each bank stores a set of multi-bit weights, each storage module in the same row is used to store one bit of the multi-bit weight, and the number of columns in each bank is reasonably allocated according to the number of signed numbers that need to be calculated in the actual operation process. An n-bit signed number weight requires n columns of SRAM units.

[0019] In this embodiment, in order to satisfy the multiplication and accumulation calculation, each multi-bit weight needs to be encoded and stored in a row of storage modules. The specific encoding method is: w =2 W +1. W is the multi-bit weight before encoding, w is the encoded multi-bit weight. For example, for a four-bit weight w Each of them needs to meet the following requirements:

[0020] in, w j express w The jth position in .

[0021] For the storage unit used to store the j-th weight, when its storage value is 1 (Q=1, QB=0), it means w j =1; when its storage value is 0 (Q=0, QB=1), it means w j =-1. Multi-bit weights are encoded into multi-column storage modules of the weight storage array. Taking 4 columns as an example, for the weight "0010" (+2), it is mapped from MSB (most significant bit) to LSB (least significant bit), and the encoding is: "1 0 1 0"; for "1010" (-2), the encoding is: "0 1 1 0". The truth table of the four-bit weight of a four-bit signed number is as follows: Table 1 Truth table of four-bit weights of four-bit signed numbers

[0022] Furthermore, for each storage module, the storage unit therein may be a 6T storage unit. Figure 4 In this embodiment, the 6T storage unit includes PMOS transistors P1 and P2 and NMOS transistors N1, N2, N3 and N4. The specific connection relationship of each device in each storage module is as follows: The sources of P1 and P2 are connected to VDD; the drain of P1 is connected to the gates of P2 and N2 and the drains of N1 and N3, and serves as the storage node QB; the drain of P2 is connected to the gates of P1, N1, N5 and the drains of N2 and N4, and serves as the inverted storage node Q; the sources of N3 and N5 are connected to the bit line BL; the source of N4 is connected to the bit line BLB; the gates of N3 and N4 are connected to the word line WL; the drain of N5 is connected to the source of N6; the gate of N6 is connected to IWL, and the drain of N6 is connected to the bit line SL. Among them, the P1-P2 and N1-N4 parts in the storage module constitute a 6T storage unit, and the 6T storage unit in the storage module is used to realize the data storage function in the storage mode, and is used to pre-store one of the weights in the calculation module.

[0023] The input encoding circuit encodes each bit of the n-bit input in turn and feeds the encoding result into the calculation word line IWL. The encoding method is:

[0024] in, a i represents the output of the i-th encoding of the input encoding circuit (the encoding result of the i-th bit in the n-bit input), A n-1 ...A 2 A 1 A 0 indicates n-bit input, where A n-1 For the sign bit.

[0025] During the calculation, the n-bit input A n-1 ...A 2 A 1 A 0 is encoded as n-1 inputs: a n-2 , …, a 1 and a 0. Each input waveform a k All based on the sign bit A n-1 Each input waveform a k can be serially fed into the corresponding calculation word line IWL in n-1 cycles. a 0 is fed into the calculation word line IWL to realize the multiplication calculation with the corresponding weight bit, and then the higher one bit is a 1 is fed into the calculation word line IWL to realize the multiplication calculation with the corresponding weight, and so on, and finally the highest bit is a n-2The input is fed into the calculation word line IWL to realize the multiplication calculation with the corresponding weight. The feeding order is the same as the encoding order of each bit in the n-bit input by the input encoding circuit.

[0026] For example, a 4-bit input A 3 A 2 A 1 A 0 is encoded as 3 inputs (3 outputs of the input encoding circuit): a 2. a 1 and a 0. Each input waveform a k All based on the sign bit A 3 Encoding obtained, input waveform a k It can be fed serially within 3 cycles. The specific encoding rules are as follows: Table 2 Input encoding truth table

[0027] Specifically, n-bit input A n-1 ...A 2 A 1 A 0 is divided into n-1 cycles as input. The sign bit is encoded into each bit of the input, and the encoding results '1', '0' and '-1' are directed to the corresponding input encoding circuit, which generates a biphase pulse signal (input signal) of "low_high", "low_low" and "high_low" for the input word line IWL according to the input data, and the encoding values ​​are 01 / 00 / 10 respectively. If the input value is +1, the first stage of the input signal is high and the second stage is low (high_low). If the input value is -1, the first stage is low and the second stage is high (low_high). If the input value is 0, the first and second stages of the input signal are both low (low_low). For example, for the positive input "+2", the three outputs of the input encoding circuit (low to high) are: "low_low low_highlow_low"; for "-2", the three outputs of the input encoding circuit (low to high) are: "low_low high_lowlow_low". The output of the input encoding circuit is input into the 8T-SRAM (storage module) as IWL. The input encoding circuit is used to encode the signed input into a bidirectional pulse signal bit by bit, thereby dividing the calculation into two steps, which is conducive to separating the several partial results of the convolution in the later calculation process.

[0028] Reference Figure 2Each input encoding circuit consists of an inverter, two AND gates and a multiplexer. The input signal X ( A n-2 ...A 2 A 1 A 0) and the clock signal CLK are connected to the multiplexer through one of the AND gates. At the same time, the inverted signal of the input signal X (obtained by inverting the inverter) and the clock signal CLK are connected to the multiplexer through another AND gate. The control end of the multiplexer is connected to the sign bit A n-1 The result of the multiplexer depends on the sign bit. A n-1 and input data X. If X is high and the sign bit A n-1 is 1, IWL is activated when CLK is in the high state. A n-1 When X is 0, IWL is activated when CLK is in the low state; when X is low, IWL is always in the deactivated state.

[0029] Through the above-mentioned information about the weight storage array and the input encoding circuit, it can be known that for a certain storage unit, if its storage node QB=1, the N5 controlled by it is turned on. At this time, if the corresponding IWL is activated, the corresponding N6 is turned on, and the bit line BL and the bit line SL are turned on, and then there is current from the bit line BL to SL. When the storage node QB=0 of the storage unit or IWL is not activated, the bit line BL and the bit line SL are not turned on, and then there is no current from the bit line BL to SL. Therefore, the calculation result between the single-bit input and the corresponding bit weight can be characterized by the current size of the bit line BL. Furthermore, the multiplication result of the multi-bit input and the multi-bit weight can be obtained based on the current of each bit line BL. Further, it can be realized by the voltage clamped current mirror circuit in this embodiment.

[0030] The operation logic of the storage unit cooperating with N5 and N6 to realize the multiplication operation is as follows: 1. The encoded weight is pre-stored in the storage unit: when Q is high and QB is low, it means that the corresponding bit of the encoded weight part is "1"; when Q is low and QB is high, it means that the corresponding bit of the encoded weight part is "0".

[0031] 2. Precharge the bit line BL to a high level, and then receive the input double pulse signal through the calculation word line IWL: when IWL is "low_high", it indicates that the corresponding bit of the mantissa of the input operand is "-1", when IWL is "high_low", it indicates that the corresponding bit of the mantissa of the input operand is "+1", and when IWL is "low_low", it indicates that the corresponding bit of the mantissa of the input operand is "0".

[0032] 3. Output the final XNOR operation and bit count based on the current change on BL (detailed introduction later).

[0033] Reference Figure 5 Each voltage clamp current mirror circuit VCCM includes a first voltage clamp circuit VC1 and two first current mirror circuits CM1. The output of the first voltage clamp circuit VC1 is the input of the two first current mirror circuits CM1. The outputs VOUT1 and VOUT2 of the two first current mirror circuits CM1 are grounded through the first capacitor C1 and the second capacitor C2 respectively. The input of the first voltage clamp circuit VC1 is the bit line BL of the corresponding column. The capacitance difference between the first capacitor C1 and the second capacitor C2 is used to characterize the multiplication and accumulation result. Among them, the first capacitor C1 and the second capacitor C2 constitute a group of calculation capacitors. When there is current on the bit line BL, charges will be accumulated on the two calculation capacitors (accumulating two different parts of the convolution calculation respectively), so the calculation capacitor has the function of accumulating the current of each bit line BL.

[0034] In this embodiment, there is a column of storage modules in the weight storage array whose storage node QB is always 1, which is defined as a redundant column; the signed number multiplication and addition operation circuit also includes: a plurality of compensation circuits corresponding to each column of storage modules, including two second current mirror circuits CM2, the outputs of the two second current mirror circuits CM2 respectively corresponding to the outputs VOUT1 and VOUT2 of the two first current mirror circuits CM1; and also includes a second voltage clamping circuit VC2, which outputs the inputs of the two second current mirror circuits CM2, and whose inputs are the bit lines BL of the redundant column.

[0035] like Figure 5As shown, VC1 and VC2 have the same structure, both consisting of two PMOS tubes connected in series (source-drain connection) and an amplifier, the positive end of the amplifier is connected to the bit line BL and the power supply voltage is connected through the two PMOS tubes connected in series, and the negative end is connected to the reference voltage Vref, the gate of the PMOS tube connected to the power supply is connected to the output end of the amplifier and provides a clamping voltage Vf (output of the voltage clamping circuit), and the gate of the other PMOS tube is connected to the control signal VCM; CM1 and CM2 have the same structure, both consisting of two PMOS tubes connected in series (source-drain connection), the source of one PMOS tube is connected to the power supply and the gate is used as the input end of the current mirror circuit, the source of the other PMOS tube is used as the output end of the current mirror circuit and the gate is connected to the control signal, the control signals of the two CM1s are SAMP1 and SAMP2, and the control signals of the two CM2s are PRE1 and PRE2.

[0036] Furthermore, in order to realize the discharge of the two calculation capacitors, an NMOS transistor is connected in parallel to the first capacitor and the second capacitor, and the gate control signals of the two NMOS transistors are CLR1 and CLR2 respectively.

[0037] It should be noted that the above-mentioned multiple voltage-clamped current mirror circuits and multiple compensation circuits correspond to multiple columns of storage modules respectively, and thus constitute a row of voltage-clamped current mirror circuits and compensation circuits. A row of voltage-clamped current mirror circuits and compensation circuits are commonly connected to a group of calculation capacitors, which can only support one row of storage modules (storing a multi-bit weight) for calculation at the same time. If you want to realize parallel calculation of multiple rows of storage modules, that is, support multiplication calculations of multiple multi-bit inputs and multiple multi-bit weights respectively, you need to set up multiple rows of voltage-clamped current mirror circuits and compensation circuits. The same group of calculation capacitors commonly connected to each row of voltage-clamped current mirror circuits and compensation circuits are used to output the corresponding multiplication calculation results of the multi-bit input and the multi-bit weight.

[0038] Furthermore, the first capacitor and the second capacitor are both connected in parallel with a plurality of auxiliary capacitors. The size of the auxiliary capacitor is the same as the calculation capacitor. The encoding results of different bits are fed into the calculation word line IWL, and the number of auxiliary capacitors turned on is different, so that the accumulated charge of the first capacitor and the second capacitor during the feeding cycle has a weight corresponding to the number of bits of the encoding result. Specifically, the number of auxiliary capacitors is determined by the number of bits of the input operand (multibit input). The input operand of n bits requires (2^ (n-2) -1) auxiliary capacitors. The auxiliary capacitors are turned on and shared with the computing capacitors in different calculation cycles to distribute the weight of the input data. Specifically, an n-bit input operand is fed in (n-1) cycles, with the lowest bit fed in the first cycle, requiring (2^ (n-2) -1) auxiliary capacitors and the calculation capacitor share charge, indicating that the weight of the lowest bit of the input is (2^ 0), and so on, the highest bit of the input is fed in the (n-1)th cycle, and all auxiliary capacitors are turned off, indicating that the weight of the highest bit of the input is (2^ (n-1) ).

[0039] Specifically, in this embodiment, if the input operand is 4 bits, each calculation capacitor needs to be equipped with 3 auxiliary capacitors, and the input needs to be fed in three cycles. The size of the auxiliary capacitor is equal to the calculation capacitor. The lowest bit is input in the first cycle, and all auxiliary capacitors are turned on. The cumulative value of the calculation capacitor corresponds to the input weight 2^ 0 ;In the second cycle, input the second lowest bit, share the charge calculation with an auxiliary capacitor, and calculate the weight of the input corresponding to the accumulated value of the capacitor 2^ 1 ; Input the highest bit in the third cycle, no need to share with the auxiliary capacitor, calculate the capacitor cumulative value corresponding to the input weight 2^ 2 .

[0040] As described above, the specific structure of the signed multiplication and accumulation operation circuit provided by this embodiment and the encoding description of the n-bit input and the n-bit weight are described. As follows, the calculation process of the signed multiplication and accumulation operation circuit is described.

[0041] The signed multiplication and accumulation circuit divides the convolution operation into four parts, starting with the first input a 0 and the lowest weight w 0 as an example.

[0042] The convolution operation is divided into: m: the part where the input is +1 multiplied by the weight of +1; n: the part where the input is +1 multiplied by the weight of -1; p: the part where the input is -1 multiplied by the weight of +1; q: the part where the input is -1 multiplied by the weight of -1; m+n is the part where the input is +1, and p+q is the part where the input is -1. The following equation is satisfied:

[0043] After deduction, we can get:

[0044] Therefore, the convolution operation is converted to ∑ q (-1)×(-1) and |∑ n (+1)×(-1)|and I +1 and I -1 Calculation.

[0045] Calculate ∑ q (-1)×(-1) and |∑ n (+1)×(-1)| is obtained by XNOR operation and bit counting, see Figure 3, the specific steps of XNOR operation and bit counting in the weight storage array are as follows: Preparation stage: precharge the bit line BL to a stable voltage ( V ref , a reference voltage to stabilize the BL voltage), and set the bit line SL to a low voltage, and CLR1 / CLR2 gives a high pulse to clear the charge in the calculation capacitor.

[0046] Phase 1: The input encoding circuit sets all IWLs corresponding to the input signal of -1 to high level. If the weight in the storage cell is -1, that is, the storage value in the storage cell is 0, that is, Q=0, QB=1, the storage cell forms a discharge path and generates I H If the value stored in the memory cell is 1, that is, Q=1, QB=0, the memory cell will not form a discharge path. At this stage, the BL current is q×I H Given, after charge sharing, ∑ q Calculation of (-1)×(-1).

[0047] The second stage: The input coding circuit activates the IWL corresponding to the +1 weight. Only when the storage value in the storage unit is 0, that is, Q=0, QB=1, can a discharge path be formed. At this time, the BL current is approximately n×I H , after charge sharing, ∣∑ n Calculation of (+1)×(-1)|.

[0048] After these two calculation stages, the convolution ∑ q (-1)×(-1) and |∑ n Partial results of (+1)×(-1)|.

[0049] A voltage clamped current mirror circuit (VCCM) is used to ensure the linearity of the calculation and convert the calculated current signal into voltage. The voltage clamped current mirror circuit consists of a first voltage clamp circuit and two current mirror circuits, and the outputs of the two current mirror circuits are connected to the first capacitor C1 and the second capacitor C2 (described in detail in the previous article). The VCCM circuit is divided into a group of n columns (the VCCM circuits in the same row are a group), which configures the current current mirror for the storage module. The ratio of MSB to LSB is (2^ n :…:4:2:1). The calculation process of the voltage clamp current mirror circuit is as follows: The second voltage clamp circuit VC2 can stabilize the bit line BL voltage according to the preset reference voltage Vref. During the calculation process, the PRE signal is set to a low value to connect BL to VC2; in addition, to turn on VC2, VCM is set to a lower value. The feedback signal from the amplifier is used to dynamically adjust the BL voltage to keep it stable. Figure 6 , SAMP1 and SAMP2 are low in the first and second stages respectively to activate the current replication path. The voltage of C1 is represented in the convolution result as ∑ q (-1)×(-1). The corresponding amount of electricity is expressed as Q 1. The voltage of C2 is represented in the convolution result as |∑ n (+1)×(-1)|. The amount of electricity in C2 is Q 2. Convert the convolution result into a form represented by the charge S:

[0050] in, Q - and Q + Respectively I -1 and I +1 The amount of charge.

[0051] Furthermore, the binary compensation circuit in this embodiment can obtain the charge S .Right now I -1 and I +1 part, charge Q - and Q + This can be achieved through a compensation circuit.

[0052] The compensation circuit allows each of the calculation capacitors C1 and C2 to have two current accumulation paths: one for the first current mirror circuit and the other for the second current mirror circuit. The current generated by the second current mirror circuit is copied from the redundant column, and the size of the PMOS tube in the first current mirror circuit is twice the size of the PMOS tube in the second current mirror circuit.

[0053] Continue to refer to Figure 6 as well as Figure 7 , the operation of the compensation circuit is as follows: Phase 1: After the "-1" signal is input to the calculation word line IWL of the weight storage array, SAMP1 and PRE2 are set to low voltage, thereby forming a calculation current path connected to capacitor C1 and a compensation current path connected to capacitor C2 to generate charges on capacitors C1 and C2Q 1 and ( Q - / 2).

[0054] Second stage: After the "+1" signal is input to the calculation word line IWL of the weight storage array, SAMP2 and PRE1 are set to low voltage, thereby forming a compensation current path connected to capacitor C1 and a calculation current path connected to capacitor C2 to generate a current on capacitors C1 and C2. Q 1+( Q + / 2) and ( Q - / 2)+ Q The charge of 2.

[0055] According to the previous formula, the final convolution result only needs to be quantized Q 1+( Q + / 2) and ( Q - / 2)+ Q 2. In order to obtain an n-bit quantization result, the multiplexing compensation circuit performs charge compensation, feeds the voltages of C1 and C2 into the sense amplifier SA for comparison, and generates an n-bit result after n comparison steps.

[0056] Reference Figure 8 In the first step, the sign bit is determined: if C1>C2, the sign bit is set to positive, and the subsequent output result is taken from OUT+ (that is, the level of OUT+ represents the calculation result). On the contrary, if C1≤C2, the sign bit is negative, and the subsequent output result is taken from OUT- (that is, the level of OUT+ represents the calculation result); in the second step, all redundant rows are activated, and the charge ( Q max / 2) is transferred to the capacitor with less charge between C1 and C2. A comparison is then performed in the sense amplifier SA. In the third step, half of the redundant rows are activated and the charge ( Q max / 4) is transferred to the capacitor with less charge, and then another comparison is made in the sense amplifier SA. In the fourth step, one quarter of the redundant rows are activated, and the charge ( Q max / 8) is transferred to the capacitor with less charge, and the final comparison is performed in the sense amplifier SA. By repeating the operation in this way, an n-bit calculation result can be obtained. Among them, the positive plate of the calculation capacitor C1 is connected to the positive input terminal of the sense amplifier SA, and the positive plate of the calculation capacitor C2 is connected to the negative input terminal of the sense amplifier SA. The positive terminal of the sense amplifier SA outputs OUT+. When the voltage of the positive input terminal is greater than the voltage of the negative input terminal, OUT+ is a high level (1). When the voltage of the positive input terminal is less than the voltage of the negative input terminal, OUT+ is a low level (0). The positive terminal of the sense amplifier SA outputs OUT-. When the voltage of the positive input terminal is greater than the voltage of the negative input terminal, OUT- is a high level (0). When the voltage of the positive input terminal is less than the voltage of the negative input terminal, OUT- is a high level (1). Among them, the redundant row refers to the storage module row in the weight storage array that does not participate in the signed number multiplication and accumulation operation.

[0057] Reference Fig. 9 , which is the overall timing diagram. The overall timing is described below using a 4-bit signed number and a 4-bit signed number weight as an example.

[0058] Calculation phase: The 4-bit signed input encoded input value is input in 3 cycles, each cycle is divided into two stages, The input of the storage cell is , -1, IWL is set high, and C1 is charged with the calculated charge of Q1. At the same time, C2 is charged with Q - / 2 compensation charge.

[0059] Phase 2: For the row where the memory cell has a +1 input, IWL is set high and C2 is charged with the calculated charge of Q2. At the same time, C1 is charged with a compensation charge of Q+ / 2.

[0060] After 3 cycles, the calculation result can be obtained.

[0061] Quantification stage: To obtain a 4-bit quantized result, the voltages of C1 and C2 are fed into a sense amplifier for comparison and a 4-bit result is generated after 4 comparison steps.

[0062] Phase 1: Determine the sign bit: If C1>C2, the sign bit is set to positive, and OUT+ is the output result. On the contrary, if C1≤C2, the sign bit is negative, and OUT- is the output result.

[0063] Phase 2: All redundant rows are activated, and the charge (Q max / 2) is transferred to the capacitor with less charge between C1 and C2. A comparison is then performed in the sense amplifier.

[0064] In the third stage, half of the redundant rows are activated, and the charge (Q max / 4) is transferred to the capacitor with less charge and then another comparison is made in the sense amplifier.

[0065] In the fourth stage, one quarter of the redundant rows are activated, and the charge (Q max / 8) is transferred to the capacitor with less charge and the final comparison is made in the sense amplifier.

[0066] When the comparison is completed, all multiplication and accumulation work is completed.

[0067] In summary, this embodiment provides a fast operation circuit for multiplying and adding a signed number based on SRAM, which is designed based on an SRAM array, VCCM, BCC, calculation capacitors and auxiliary capacitors, and peripheral circuits, and is used to implement multiplication and addition operations between multiple groups of multi-bit signed number operands and multi-bit signed number weights. The fast operation circuit for multiplying and adding a signed number in this embodiment has two working modes, storage and calculation, and controls the function switching of the circuit through a mode switching module. Among them, the peripheral circuit of the SRAM array refers to the related circuits and modules related to the use of the SRAM array to realize data reading, writing and saving.

[0068] like Figure 1 As shown, in order to realize the operation function, in the scheme of this embodiment, the operation circuit architecture is composed of a weight array, an input encoding circuit, a voltage clamping current mirror array, SA, two calculation capacitors and auxiliary capacitors and a memory control circuit.

[0069] The weight array can be divided into multiple banks, each bank stores a set of weights (a set of weights includes multiple cells), and the number of columns in each bank is reasonably allocated by the number of signed numbers that need to be calculated in the actual operation process. An n-bit signed number weight requires n columns of SRAM cells; for example, for a 4-bit signed number, each bank has 4 columns.

[0070] In practical applications, the encoded operand weights are input bit by bit into the same row of the array, and the same unit in the array stores one of the bits. Different rows are used to store different multi-bit weights. On this basis, the maximum number of groups of operands or weights for signed multiplication and accumulation that can be supported by the signed number fast operation circuit provided in this embodiment is determined by the number of rows of the SRAM array. For example, in a circuit with a weight array size of 64×4×16, it can support a maximum of 64×16 signed operands and 64×16 signed weights.

[0071] As described above, this is the signed number multiplication and accumulation operation circuit and its calculation process provided in this embodiment. It can be seen from the above description that the present invention provides a new circuit architecture and operation logic of a signed number fast operation circuit. A new weight mapping scheme, signed number XNOR operation and bit counting calculation scheme are applied in the circuit scheme, which can divide the multiplication and accumulation calculation results of positive and negative numbers into four parts, so that each part can be accumulated separately during the calculation process, and finally the difference between the two calculation capacitors is quantized to calculate the final result, which reduces the introduction of a large number of cross switches in the calculation unit of the traditional analog signed number, saves the calculation cycle, and then realizes the MAC memory calculation of signed data with lower time, area and power consumption overhead, and solves the problem of low multiplication and accumulation calculation efficiency of the current signed number multiplication and accumulation operation circuit.

[0072] In this embodiment, a CIM chip is also provided, which integrates the signed number multiplication and accumulation operation circuit provided in this embodiment.

[0073] In this embodiment, an electronic device is also provided, which has the CIM chip provided in this embodiment built in, and implements convolution operations for deep learning through the CIM chip.

[0074] It should be understood that the specific embodiments described herein are only used to explain the application, rather than to limit it. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of this application.

[0075] Obviously, the drawings are only some examples or embodiments of the present application. For ordinary technicians in the field, the present application can also be applied to other similar situations based on these drawings without creative work. In addition, it is understandable that although the work done in this development process may be complicated and lengthy, for ordinary technicians in the field, certain changes in design, manufacturing or production based on the technical content disclosed in this application are only conventional technical means and should not be regarded as insufficient content disclosed in this application.

Claims

1. A signed multiplication and accumulation circuit, characterized in that: include: The weight storage array includes a plurality of storage modules distributed in rows and columns, each storage module includes a storage unit and NMOS tubes N5 and N6, the gate and drain of N5 are respectively connected to the storage node QB of the storage unit and the source of N6, the source of N5 in the same column is connected to the same bit line BL, the gate of N6 in the same row is connected to the same calculation word line IWL, the drain of N6 in the same column is connected to the same bit line SL, the bit line BL is also connected to the reference voltage, the bit line SL is also connected to the ground terminal VSS, and the weight of multiple bits is calculated. W Encoding w =2 W After +1, they are stored row by row in the weight storage array; Multiple input coding circuits corresponding to each row of storage modules, the output of each input coding circuit is fed into the calculation word line IWL of the corresponding row, the input coding circuit encodes each bit of the n-bit input in turn and feeds the encoding result into the calculation word line IWL, the encoding method is: ， in, a i represents the output of the i-th encoding of the input encoding circuit, A n-1 ...A 2 A 1 A 0 means n-bit input, A n-1 is the sign bit, A n-2 ...A 2 A 1 A 0 is the digital position; A plurality of voltage clamping current mirror circuits respectively corresponding to each column storage module, each voltage clamping current mirror circuit comprises a first voltage clamping circuit and two first current mirror circuits, the output of the first voltage clamping circuit is the input of the two current mirror circuits, the outputs of the two first current mirror circuits are respectively grounded through a first capacitor and a second capacitor, the input of the first voltage clamping circuit is a bit line BL of the corresponding column, and the capacitance difference between the first capacitor and the second capacitor is used to characterize the multiplication and accumulation result.

2. The signed multiplication-accumulation operation circuit according to claim 1, characterized in that: There is a column of storage modules in the weight storage array whose storage node QB is always 1, which is defined as a redundant column; The signed multiplication and accumulation operation circuit also includes: A plurality of compensation circuits corresponding to each column storage module, including two second current mirror circuits, the outputs of the two second current mirror circuits correspondingly coupled to the outputs of the two first current mirror circuits; The output of the second voltage clamp circuit is the input of two second current mirror circuits, and the input of the second current mirror circuits is the bit line BL of the redundant column.

3. The signed multiplication-accumulation operation circuit according to claim 2, characterized in that: The first current mirror circuit and the second current mirror circuit are both composed of two PMOS tubes, and the size of the PMOS tube in the first current mirror circuit is twice the size of the PMOS tube in the second current mirror circuit.

4. The signed multiplication-accumulation operation circuit according to claim 1, characterized in that: The storage unit is a 6T storage unit, which includes PMOS tubes P1 and P2 and NMOS tubes N1, N2, N3 and N4; The sources of P1 and P2 are connected to VDD; the drain of P1 is connected to the gates of P2 and N2 and the drains of N1 and N3, and serves as the storage node QB; the drain of P2 is connected to the gates of P1, N1, N5 and the drains of N2 and N4, and serves as the inverted storage node Q; the sources of N3 and N5 are connected to the bit line BL; the source of N4 is connected to the bit line BLB; the gates of N3 and N4 are connected to the word line WL; the drain of N5 is connected to the source of N6; the gate of N6 is connected to IWL, and the drain of N6 is connected to the bit line SL.

5. The signed multiplication and accumulation circuit according to claim 1, characterized in that: The output of the input encoding circuit is a bidirectional pulse signal; When the first stage of the bidirectional pulse signal is high level and the second stage is low level, it represents +1; When the first stage of the bidirectional pulse signal is low level and the second stage is high level, it represents -1; When the first phase and the second phase of the bidirectional pulse signal are both at a low level, it represents 0.

6. The signed multiplication-accumulation operation circuit according to claim 1, characterized in that: The input encoding circuit includes an inverter, two AND gates and a multiplexer; The input signal X and the clock signal CLK are connected to the multiplexer through one of the AND gates, and the inverse signal of the input signal X and the clock signal CLK are connected to the multiplexer through another AND gate. The control end of the multiplexer is connected to the sign bit A n-1 , the input signal X is A n-2 ...A 2 A 1 A 0, the inverse signal of the input signal X is obtained by inverting it through the inverter.

7. The signed multiplication and accumulation circuit according to claim 1, characterized in that: The first capacitor and the second capacitor are both connected in parallel with a plurality of auxiliary capacitors, and the size of the auxiliary capacitors is the same as the calculated capacitor; When different bits of the encoding results are fed into the calculation word line IWL, the number of auxiliary capacitors turned on is different, so that the charges accumulated by the first capacitor and the second capacitor during the feeding period have weights corresponding to the number of bits of the encoding results.

8. The signed multiplication-accumulation operation circuit according to claim 1, characterized in that: The multiplication and accumulation result is obtained by feeding the voltages of the first capacitor and the second capacitor into a sense amplifier for comparison.

9. A CIM chip, characterized in that: The invention integrates the signed number multiplication and accumulation operation circuit described in any one of claims 1 to 8.

10. An electronic device, characterized in that: The CIM chip according to claim 9 is built in, and the convolution operation of deep learning is realized through the CIM chip.

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