Fixed-point complex number high-speed division method for radix-2 programmable circuit
By adopting fixed-point complex high-speed division method in the base 2 programmable circuit, the problems of long periods, low accuracy, slow speed and high power consumption are solved, and high precision and high speed calculations are achieved, while reducing power consumption.
Patent Information
- Application Number
- CN202411890033.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-20
- Publication Date
- 2025-05-02
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
In the prior art, the complex division method has problems such as long operation period, low calculation accuracy, slow calculation speed and high power consumption.
The fixed-point complex high-speed division method of the base 2 programmable circuit is adopted. By receiving the input of two complex numbers to be calculated, the denominator is determined whether the denominator is zero, the complex division operation is performed, the calculation is performed using a multiplier and a divider, and the accuracy range of the result is expanded.
The calculation accuracy and significant improvement of calculation speed are achieved. The calculation speed can be achieved several times at the same operating frequency, reducing power consumption and improving the computing efficiency of the system.
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Figure CN119917062A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of digital signal processing, and in particular to a radix-2 programmable circuit fixed-point complex number high-speed division method. Background Art
[0002] In the application development of programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs), fixed-point complex division operations have always been one of the key technologies for implementing high-performance digital signal processing (DSP) algorithms. However, the traditional implementation of radix-2 fixed-point complex division faces many challenges and limitations, especially in terms of computing speed, resource consumption, precision loss, and power consumption control.
[0003] First, complex number division involves complex operations on the real and imaginary parts, which increases the difficulty and complexity of implementation. In fixed-point representation, due to the limitations of accuracy and range, traditional base-2 fixed-point complex number division methods often have difficulty in achieving high-speed operations while ensuring calculation accuracy.
[0004] Secondly, some existing solutions, such as IP cores that come with the software (such as the Cordic IP core in Vivado), although they provide division functions, lack computational flexibility and consume a lot of resources. These IP cores are usually designed as general computing modules and lack optimization for specific application scenarios. Therefore, when processing fixed-point complex division, they may not be able to fully exert their performance advantages.
[0005] In addition, power consumption is also one of the important challenges facing the current field of digital signal processing. With the continuous improvement of processor integration, power consumption issues are becoming increasingly prominent. When processing high-frequency signals, the traditional radix-2 fixed-point complex division method consumes a lot of computing resources and time, so it is often accompanied by high power consumption. This not only increases the operating cost of the system, but may also have a negative impact on the stability and reliability of the system.
[0006] In summary, the existing complex number division method has the problems of long operation cycle, low calculation accuracy, slow calculation speed and high power consumption when it is actually used. Summary of the invention
[0007] The purpose of the present invention is to provide a radix 2 programmable circuit fixed-point complex high-speed division method, aiming to solve the technical problems of the complex number division method in the prior art in actual use, such as long operation cycle, low calculation accuracy, slow calculation speed and high power consumption.
[0008] To achieve the above object, the present invention adopts a radix-2 programmable circuit fixed-point complex number high-speed division method, comprising the following steps:
[0009] Step 1, receiving input of two complex numbers to be calculated;
[0010] Step 2: Determine whether the complex number used as the denominator is zero. If it is zero, the division operation cannot be performed and an error state or a specific value is returned. If it is not zero, proceed to the next step.
[0011] Step 3: Execute complex number division operation: first, clearly define the real part and imaginary part of the two complex numbers, and calculate the conjugate complex number of the denominator. Use the multiplier to multiply both the numerator and the denominator by the conjugate complex number of the denominator to obtain a new numerator and real denominator. The divider divides the obtained numerator by the real denominator to obtain the calculation result of the division operation.
[0012] Step 4: Expand the accuracy range of the calculation results.
[0013] Wherein, in step 1, two complex numbers to be calculated are received as input:
[0014] Use fixed-point input to input the real and imaginary numbers of the two complex numbers to be calculated, and the output parameter result is a signed binary number.
[0015] Among them, the two complex numbers to be calculated are defined as x and y, x=a+bj, y=c+dj;
[0016] Among them, a, b, c, and d are fixed-point values of the real part and imaginary part respectively, and each has a sign bit located at the highest bit of the value to indicate positive or negative.
[0017] In step 2, it is determined whether the complex number y as the denominator is zero. If the complex number y is zero, the division operation cannot be performed and an error state or a specific value is returned. If the complex number y is not zero, the specific method of continuing to perform the next step is:
[0018] Determine whether the complex number y is zero. If the complex number y is zero, the division operation cannot be performed, and the high impedance state is directly returned to end the division operation.
[0019] Determine whether the complex number y is zero. If the complex number y is not zero, perform a complex division operation.
[0020] Among them, in step three, the multiplier is used to multiply both the numerator and the denominator by the conjugate complex number of the denominator to obtain a new numerator and a real denominator, and the divider divides the obtained numerator by the real denominator to obtain the calculation result of the division operation. The specific method is:
[0021] First, calculate the conjugate complex number y' of the complex number y. If y = c + dj, then y' = c - dj;
[0022] In subroutines U4, U5, U6, and U7, the products of the complex numerator x and the conjugate complex number y' of the complex denominator y are calculated in parallel by using multipliers to obtain four product terms ac, bd, bc, and ad. The intermediate values of the real and imaginary parts of the results are calculated using the four product terms through addition and subtraction operations.
[0023] Use the middle value as the new numerator and the square of the modulus of the complex denominator as the real denominator;
[0024] Use the divider to divide the new numerator by the real denominator to obtain the calculation result of the division operation;
[0025] The specific formula is as follows:
[0026]
[0027] Where a and b are the real and imaginary parts of the numerator complex number x, c and d are the real part of the denominator complex number y and the imaginary part of its conjugate complex number, and c-dj is the conjugate complex number of c+dj.
[0028] Among them, in step 4, the specific method of expanding the accuracy range of the calculation result is:
[0029] A calculation result obtained by performing the complex number division operation is multiplied by a predetermined power of 2 to expand the precision range.
[0030] Before executing the division algorithm, the real and imaginary parts of the input numerator complex number x and the denominator complex number y are processed as follows:
[0031] Check the sign bits of the real and imaginary parts. If the values themselves are positive, no processing is done.
[0032] If the value is negative, convert it to its opposite, that is, take its complement or perform the corresponding inversion operation for subsequent calculations.
[0033] Among them, after completing the division calculation of two complex numbers to be calculated, professional numerical calculation software Matlab is used for comparative verification.
[0034] The invention discloses a method for high-speed complex number division using a radix-2 programmable circuit fixed-point, which receives inputs of two complex numbers to be calculated; determines whether the complex number as the denominator is zero, if it is zero, the division operation cannot be performed and an error state or a specific value is returned, and if it is not zero, the next step is continued; performs complex number division operation: firstly, the real part and the imaginary part of the two complex numbers are clearly defined, and the conjugate complex number of the denominator is calculated, and a multiplier is used to multiply both the numerator and the denominator by the conjugate complex number of the denominator to obtain a new numerator and a real denominator, and a divider is used to divide the obtained numerator by the real denominator to obtain a calculation result of the division operation; and the accuracy range of the calculation result is expanded;
[0035] The use of the present invention not only improves the accuracy, but also significantly improves the calculation speed. At the same operating frequency, the operation speed can be several times higher, thereby reducing the operating frequency and reducing power consumption. The improvement in accuracy not only means that the calculation results are more accurate, but also better reflects the characteristics of actual physical quantities or mathematical models. Especially in application scenarios that require high-precision calculations (such as signal processing, image processing, scientific computing and other fields), in scientific computing, the improvement in accuracy is particularly important. The reduction in operation cycles means that more computing tasks can be completed per unit time. In application scenarios that require high-speed processing (such as real-time signal processing, high-speed data transmission, etc.), shortening the operation cycle is particularly important. The reduction in operation cycles helps to reduce the power consumption of the system and increase the service life of the processor;
[0036] This method can complete an operation in 1 clock. Compared with the traditional VIVADO IP complex division (9 clocks are required to complete a complex division calculation), the data operation speed is greatly improved. At the same time, the accuracy of the calculation result of this method is not only not reduced, but also improved. The calculation is performed using the base 2 fixed-point complex division method. Under the premise of ensuring the speed, the accuracy of the result obtained by the operation is quite accurate, which will greatly improve the calculation efficiency of the system, thereby solving the technical problems of the complex division method in the prior art in actual use, such as long operation cycle, low calculation accuracy, slow calculation speed and high power consumption. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0038] Figure 1 It is a flow chart of the steps of the radix-2 programmable circuit fixed-point complex high-speed division method of the present invention.
[0039] Figure 2 It is a schematic diagram of simulation results of the radix-2 programmable circuit fixed-point complex high-speed division method of the present invention.
[0040] Figure 3 It is a schematic diagram of the existing complex division simulation results. DETAILED DESCRIPTION
[0041] Embodiments of the present invention are described in detail below. Examples of the embodiments are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, but should not be construed as limiting the present invention.
[0042] See also Figure 1 to Figure 3 ,in Figure 1 It is a flow chart of the steps of the radix-2 programmable circuit fixed-point complex high-speed division method of the present invention. Figure 2 It is a schematic diagram of simulation results of the radix-2 programmable circuit fixed-point complex high-speed division method of the present invention. Figure 3 It is a schematic diagram of the existing complex division simulation results.
[0043] The present invention provides a radix-2 programmable circuit fixed-point complex number high-speed division method, comprising the following steps:
[0044] Step 1, receiving input of two complex numbers to be calculated;
[0045] For this specific implementation, fixed-point input is used, and the real number and imaginary number of two complex numbers to be calculated are input respectively, and the output parameter result is a signed binary number;
[0046] Among them, the two complex numbers to be calculated are defined as x and y, x=a+bj, y=c+dj;
[0047] Among them, a, b, c, and d are fixed-point values of the real part and imaginary part respectively, and each has a sign bit located at the highest bit of the value to indicate positive or negative.
[0048] Step 2: Determine whether the complex number used as the denominator is zero. If it is zero, the division operation cannot be performed and an error state or a specific value is returned. If it is not zero, proceed to the next step.
[0049] According to this specific implementation, it is determined whether the complex number y is zero. If the complex number y is zero, the division operation cannot be performed, and the high impedance state is directly returned to terminate the division operation.
[0050] Determine whether the complex number y is zero. If the complex number y is not zero, perform a complex division operation.
[0051] Step 3: Execute complex number division operation: first, clearly define the real part and imaginary part of the two complex numbers, and calculate the conjugate complex number of the denominator. Use the multiplier to multiply both the numerator and the denominator by the conjugate complex number of the denominator to obtain a new numerator and real denominator. The divider divides the obtained numerator by the real denominator to obtain the calculation result of the division operation.
[0052] For this specific implementation, firstly, the conjugate complex number y' of the complex number y is calculated. If y=c+dj, then y'=c-dj;
[0053] In subroutines U4, U5, U6, and U7, the products of the complex numerator x and the conjugate complex number y' of the complex denominator y are calculated in parallel by using multipliers to obtain four product terms ac, bd, bc, and ad. The intermediate values of the real and imaginary parts of the results are calculated using the four product terms through addition and subtraction operations.
[0054] Use the middle value as the new numerator and the square of the modulus of the complex denominator as the real denominator;
[0055] Use the divider to divide the new numerator by the real denominator to obtain the calculation result of the division operation;
[0056] The specific formula is as follows:
[0057]
[0058] Where a and b are the real and imaginary parts of the numerator complex number x, c and d are the real part of the denominator complex number y and the imaginary part of its conjugate complex number, and c-dj is the conjugate complex number of c+dj.
[0059] Step 4: Expand the accuracy range of the calculation results.
[0060] According to this specific implementation, the calculation result obtained by performing the complex number division operation is multiplied by a predetermined power of 2 to expand the precision range.
[0061] Before executing the division algorithm, the real and imaginary parts of the input numerator complex number x and denominator complex number y are processed as follows:
[0062] Check the sign bits of the real and imaginary parts. If the values themselves are positive, no processing is done.
[0063] If the value is negative, convert it to its opposite, that is, take its complement or perform the corresponding inversion operation for subsequent calculations.
[0064] Among them, after completing the division calculation of two complex numbers to be calculated, professional numerical calculation software Matlab is used for comparative verification.
[0065] Example:
[0066] In an embodiment, the specific process of signed integer processing and algorithm is as follows:
[0067] a_reg=(A[width-1]==0)? A:{1'b0,~A[width-2:0]+1'b1};
[0068] b_reg=(B[(width / 2)-1]==0)? B:{1'b0,~B[(width / 2)-2:0]+1'b1};
[0069] Signed integer processing, division is performed directly on signed integers, and the positive and negative cases are handled by adjusting the signs of the dividend and divisor. Check if the highest bit of A is 0. If it is 0, it means that A is a non-negative number, so it is directly assigned to a_reg. If the highest bit of A is 1, then {1'b0,~A[width-2:0]+1'b1} is executed. Here, ~A[width-2:0] bitwise inverts the sign bit of A. Then, 1 (+1'b1) is added to this inverted number, which is the way two's complement represents negative numbers. The same is true for B. Direct support for signed integer division is provided by converting the dividend and divisor to the appropriate positive or negative form and restoring the correct sign in the final result.
[0070] In this subroutine, divisors of different multiples (temp_b array) are dynamically constructed through loops and shift operations. The required multiples are dynamically generated in each iteration through shift and addition operations, which reduces the storage space occupied and improves flexibility. In addition, the remainder is restored by repeatedly shifting the dividend and remainder and trying different multiples one by one to find the multiple closest to but not less than the original remainder. This strategy may be more efficient than directly searching for each possible multiple in some cases. After the division operation is completed, the sign of the final result is determined based on the signs of the original dividend and divisor. This is a key step in processing signed integer division and an important part of ensuring the correctness of the result.
[0071] In terms of cycle improvement, complex division uses parallel processing. Parallel algorithms are designed by taking advantage of the parallel computing capabilities of multi-core processors, and multi-threading or vectorization technology is combined to accelerate execution. At the same time, dedicated hardware accelerators such as FPGA and ASIC are explored to optimize resource utilization and reduce latency and power consumption. In addition, complex division is integrated with other complex operations through compound operations to reduce intermediate storage and conversion, and achieve efficient execution of compound operations.
[0072] 1. When a=1, b=2, c=0, d=0;
[0073] At this time, the second complex number (i.e., the divisor) = 0, and the complex number division calculation cannot be performed;
[0074] overflow=1; / / Return to high impedance state;
[0075] 2. When a=1,b=2,c=3,d=4 / / For ease of understanding, this calculation is an example of a detailed calculation process;
[0076] First, we must make sure that the divisor is 3+4j, which is not 0, so it makes sense to perform complex division;
[0077] From the above calculation results, it is necessary to calculate ac, bd, bc, ad, ac + bd, bc - ad, c 2 + d 2 ;
[0078] According to subroutine U1,
[0079] According to instantiation, we know that
[0080] Initialize a > 0, b > 0,
[0081] shift_a[0] = a = 3 (binary: 00000011), shift_b[0] = a = 3 (binary: 00000011)
[0082] shift_a[1] = b = 4 (binary: 00000100), shift_b[1] = b = 4 (binary: 00000100)
[0083] sum_temp[0] = 0, sum_temp[1] = 0, p_temp = 0
[0084] Enter the loop:
[0085] The least significant bit of 3 is 1, so sum_temp[0] += (a << 0), which actually just adds 3 to sum_temp[0].
[0086] Since a = 3 has only two bits that are 1 and they are both in the least significant bit. The same is true for b.
[0087] sum_temp[0] = 9; sum_temp[1] = 16;
[0088] p_temp = sum_temp[0] + sum_temp[1] = 25;
[0089] Subroutine U2, according to instantiation, in U4, A = 11, B = 25;
[0090] Since A > 0, B > 0, a_reg = A = 11; b_reg = B = 25;
[0091] Enter the loop:
[0092] temp_a < temp_b, temp_b will not be subtracted in the first loop.
[0093] In multiple loops, since temp_a is always less than temp_b, temp_a will remain unchanged, that is, all zeros
[0094] sign = 0; result = 0000000000000000.
[0095] Subroutine U3, according to instantiation, in U4, A = 11, B = 25;
[0096] Since A > 0, B > 0, a_reg = A = 2; b_reg = B = 25;
[0097] Enter the loop:
[0098] temp_a < temp_b, temp_b will not be subtracted in the first loop.
[0099] In multiple loops, since temp_a is always less than temp_b, temp_a will remain unchanged, i.e., all zeros
[0100] sign = 0; result = 0.
[0101] U4 program, can first calculate ac, according to instantiation, in U4, a = 1, b = 3;
[0102] result = 0, temp = 0;
[0103] Since they are all positive numbers;
[0104] sign = 0, a_reg = a = 1, b_reg = b = 3;
[0105] Enter the loop:
[0106] i = 0, b_reg[0] = 1, temp = 1; i = 1, b_reg[1] = 1, temp = 3;
[0107] Since sign = 0, then result = temp = 3;
[0108] U5 program, can first calculate bd, according to instantiation, in U5, a = 2, b = 4;
[0109] result = 0, temp = 0;
[0110] Since they are all positive numbers;
[0111] sign = 0, a_reg = a = 2, b_reg = b = 4;
[0112] Enter the loop:
[0113] i = 2, b_reg[2] = 1, temp = 8;
[0114] Since sign = 0, then result = temp = 8;
[0115] U6 program can first calculate bc. According to the instantiation, a=2, b=3 in U6;
[0116] result=0, temp=0;
[0117] Since they are all positive numbers;
[0118] sign=0, a_reg=a=2, b_reg=b=3;
[0119] Enter the loop:
[0120] i=0, b_reg[0]=1, temp=2; i=1, b_reg[1]=1, temp=6;
[0121] Since sign = 0, result = temp = 6;
[0122] U7 program can first calculate ad. According to the instantiation, a=1, b=4 in U7;
[0123] result=0, temp=0;
[0124] Since they are all positive numbers;
[0125] sign=0, a_reg=a=1, b_reg=b=4;
[0126] Enter the loop:
[0127] i=0, b_reg[2]=1, temp=4;
[0128] Since sign = 0, result = temp = 4;
[0129] 3. When a=3, b=4, c=7, d=5; / / the calculation process is the same as 2.
[0130] 4. When a=8, b=3, c=9, d=5; / / the calculation process is the same as 2.
[0131] In the same environment, the Cordic IP core provided by Vivado is used to perform complex number division operations. Here, the present invention gives several sets of integer complex numbers as examples and explains how to use the Vivado IP core to perform complex number division.
[0132] The first set of data: x=3+4j; y=1+2j;
[0133] The second set of data: x = 5-6j; y = 2-3j;
[0134] The first set of results: z = x / y = 2.2 + 0.4j, magnified 2^16 times: 143360 + 26214.4j;
[0135] The second set of results: z = x / y = 1 + 6 / 13j, magnified 2^16 times: 65536 + 30972j;
[0136] In order to verify the accuracy of this algorithm, we can refer to the complex number division calculation results of Matlab (special numerical calculation software, known for its high calculation accuracy) for comparison as follows:
[0137] x=1+2j; y=3+4j; z=x / y; the final result multiplied by 2^16 is (2.8836e+04)+(5.2429e+03)j, and the corresponding simulation result of the program is 28835+5254j;
[0138] x=3+4j; y=7+5j; z=x / y; the final result multiplied by 2^16 is (3.6310e+04)+(1.1513e+04)j, and the corresponding simulation result of the program is 36310+11513j;
[0139] x=8+3j; y=9+5j; z=x / y; the final result multiplied by 2^16 is (5.3789e+04)-(8.0374e+03)j, and the corresponding simulation result of the program is 53788-8037j;
[0140] x=3+4j; y=1+2j; z=x / y; the final result multiplied by 2^16 is (1.4418e+05)-(2.6214e+04)j, and the corresponding simulation result of the program is 143360+26214.4j;
[0141] x=8+3j; y=9+5j; z=x / y; the final result multiplied by 2^16 is (1.4115e+05)-(1.5124e+04)j, and the corresponding simulation result of the program is 65536+30972j;
[0142] Through verification, it was found that the complex division operation using Vivado's built-in Cordic IP is accurate, but the precision is still not enough, and the calculation is not very accurate; the calculation accuracy is very sensitive to the bit width and precision setting of the input data, the calculation results have significant deviations, and the sign processing and overflow problems are relatively complicated and require additional logic to handle, affecting the calculation efficiency of the entire system; while the calculation accuracy of the radix 2 complex operation method of the present invention is very high, the time required for each calculation is relatively low, and the accuracy of the complex division is higher.
[0143] A radix 2 programmable circuit fixed-point complex high-speed division method of the present invention is used to receive inputs of two complex numbers to be calculated; determine whether the complex number used as the denominator is zero, if it is zero, the division operation cannot be performed and an error state or a specific value is returned, if it is not zero, continue to execute the next step; perform complex number division operation: first clearly define the real part and imaginary part of the two complex numbers, and calculate the conjugate complex number of the denominator, use a multiplier to multiply both the numerator and the denominator by the conjugate complex number of the denominator to obtain a new numerator and real denominator, and a divider divides the obtained numerator by the real denominator to obtain a calculation result of the division operation; and the accuracy range of the calculation result is expanded;
[0144] The use of the present invention not only improves the accuracy, but also significantly improves the calculation speed. At the same operating frequency, the operation speed can be several times higher, thereby reducing the operating frequency and reducing power consumption. The improvement in accuracy not only means that the calculation results are more accurate, but also better reflects the characteristics of actual physical quantities or mathematical models. Especially in application scenarios that require high-precision calculations (such as signal processing, image processing, scientific computing and other fields), in scientific computing, the improvement in accuracy is particularly important. The reduction in operation cycles means that more computing tasks can be completed per unit time. In application scenarios that require high-speed processing (such as real-time signal processing, high-speed data transmission, etc.), shortening the operation cycle is particularly important. The reduction in operation cycles helps to reduce the power consumption of the system and increase the service life of the processor;
[0145] based on Figure 2 It can be seen that this method can complete an operation in 1 clock. Compared with the traditional VIVADO IP complex division (9 clocks are required to complete a complex division calculation), the data operation speed is greatly improved. At the same time, the accuracy of the calculation result of this method is not only not reduced, but also improved. The calculation using the base 2 fixed-point complex division method is quite accurate while ensuring the speed. This will greatly improve the calculation efficiency of the system, thereby solving the technical problems of the complex division method in the prior art in actual use, such as long operation cycle, low calculation accuracy, slow calculation speed and high power consumption.
[0146] What is disclosed above is only a preferred embodiment of the present invention, and it certainly cannot be used to limit the scope of rights of the present invention. Ordinary technicians in this field can understand that all or part of the processes of the above embodiment and equivalent changes made according to the claims of the present invention still fall within the scope of the invention.
Claims
1. A method for high-speed fixed-point complex number division using a radix-2 programmable circuit, characterized in that: The steps include: Step 1, receiving input of two complex numbers to be calculated; Step 2: Determine whether the complex number used as the denominator is zero. If it is zero, the division operation cannot be performed and an error state or a specific value is returned. If it is not zero, proceed to the next step. Step 3: Execute complex number division operation: first, clearly define the real part and imaginary part of the two complex numbers, and calculate the conjugate complex number of the denominator. Use the multiplier to multiply both the numerator and the denominator by the conjugate complex number of the denominator to obtain a new numerator and real denominator. The divider divides the obtained numerator by the real denominator to obtain the calculation result of the division operation. Step 4: Expand the accuracy range of the calculation results.
2. The method for high-speed fixed-point complex number division using a radix-2 programmable circuit as claimed in claim 1, wherein: In step 1, two complex numbers to be calculated are received as input: Use fixed-point input to input the real and imaginary numbers of the two complex numbers to be calculated, and the output parameter result is a signed binary number. Among them, the two complex numbers to be calculated are defined as x and y, x=a+bj, y=c+dj; Among them, a, b, c, and d are fixed-point values of the real part and imaginary part respectively, and each has a sign bit located at the highest bit of the value to indicate positive or negative.
3. The method for high-speed fixed-point complex number division using a radix-2 programmable circuit as claimed in claim 2, wherein: In step 2, it is determined whether the complex number y as the denominator is zero. If the complex number y is zero, the division operation cannot be performed and an error state or a specific value is returned. If the complex number y is not zero, the specific method of continuing to execute the next step is as follows: Determine whether the complex number y is zero. If the complex number y is zero, the division operation cannot be performed, and the high impedance state is directly returned to end the division operation. Determine whether the complex number y is zero. If the complex number y is not zero, perform a complex division operation.
4. The method for high-speed fixed-point complex number division using a radix-2 programmable circuit as claimed in claim 3, wherein: In step 3, a multiplier is used to multiply both the numerator and the denominator by the conjugate complex number of the denominator to obtain a new numerator and a real denominator, and a divider is used to divide the obtained numerator by the real denominator to obtain the calculation result of the division operation. The specific method is: First, calculate the conjugate complex number y' of the complex number y. If y = c + dj, then y' = c - dj; In subroutines U4, U5, U6, and U7, the products of the complex numerator x and the conjugate complex number y' of the complex denominator y are calculated in parallel by using multipliers to obtain four product terms ac, bd, bc, and ad. The intermediate values of the real and imaginary parts of the results are calculated using the four product terms through addition and subtraction operations. Use the middle value as the new numerator and the square of the modulus of the complex denominator as the real denominator; Use the divider to divide the new numerator by the real denominator to obtain the calculation result of the division operation; The specific formula is as follows: Where a and b are the real and imaginary parts of the numerator complex number x, respectively, and c and d are the real part of the denominator complex number y and the imaginary part of its conjugate complex number, respectively.
5. The method for high-speed fixed-point complex number division using a radix-2 programmable circuit as claimed in claim 4, wherein: In step 4, the specific method of expanding the accuracy range of the calculation results is: A calculation result obtained by performing the complex number division operation is multiplied by a predetermined power of 2 to expand the precision range.
6. The method for high-speed fixed-point complex number division using a radix-2 programmable circuit as claimed in claim 5, wherein: Before executing the division algorithm, the real and imaginary parts of the input numerator complex number x and denominator complex number y are processed as follows: Check the sign bits of the real and imaginary parts. If the values themselves are positive, no processing is done. If the value is negative, convert it to its opposite, that is, take its complement or perform the corresponding inversion operation for subsequent calculations.
7. The method for high-speed fixed-point complex number division using a radix-2 programmable circuit as claimed in claim 6, wherein: After completing the division calculation of two complex numbers to be calculated, professional numerical calculation software Matlab is used for comparative verification.