Matrix transposition processing method and computing device

Abstract

The embodiment of the invention provides a matrix transposition processing method and computing equipment. The method comprises the following steps: in response to a received first transpose instruction for partial data of a first matrix, an instruction recording unit records the current state of the instruction as a to-be-transmitted state; the instruction transmitting unit performs intra-core instruction transmitting state checking on the instruction, and when the checking result is that an intra-core instruction transmitting condition is met, the instruction recording unit is notified to change the current state of the instruction into a synchronization waiting state; the instruction recording unit performs inter-core instruction emission state check on the instruction, and when the plurality of processor cores all the instruction of the first matrix is in a synchronization waiting state, the current state of the instruction is changed into an operation waiting state; and the instruction transmitting unit transmits the instruction in the operation waiting state to the transposition execution unit, and the transposition execution unit carries out transposition operation on partial data of the first matrix to obtain local transposition result data.

Description

Technical Field

[0001] One or more embodiments of the present specification relate to the computer field, and more particularly, to a matrix transposition processing method and a computing device. Background Art

[0002] Currently, matrix transposition processing is involved in many scenarios. For example, in fully homomorphic encryption (FHE), which is often used in privacy protection, the data object is a polynomial of length N. Generally, the length of the polynomial is flexibly set to 1024, 2048, 4096, ..., 65536 and other values ​​in the application. For the number-theoretic transform (NTT) and automorphism (automorph isms) operations required for fully homomorphic encryption, it is difficult to directly implement parallel calculations of polynomials of the above lengths. There is a problem that the permutation network interconnection between polynomial coefficients is too large to be implemented. Therefore, when implementing in hardware, NTT and automorphism operations are usually implemented according to the 2D algorithm. Taking the 65536-point NTT as an example, two matrix transposition operations are introduced in the 2D algorithm, and the size of the matrix is ​​256x256.

[0003] In the prior art, since matrix transposition is a global data replacement operation, it has natural synchronization requirements and data consistency requirements, and is difficult to implement in a multi-core architecture. Therefore, a single processor core is used to process a matrix, resulting in low execution efficiency of the transposition processing. Summary of the invention

[0004] One or more embodiments of the present specification describe a matrix transposition processing method and computing device, which can implement multi-core parallel computing of transposition processing and improve its execution efficiency.

[0005] In a first aspect, a matrix transposition processing method is provided, which is executed by any target processor core among a plurality of processor cores, wherein the target processor core includes an instruction issuing unit, an instruction recording unit, and a transposition execution unit, and the method includes:

[0006] In response to receiving a first transposition instruction for a portion of data of the first matrix, the instruction recording unit records a current state of the first transposition instruction as a waiting-to-transmit state;

[0007] The instruction issuing unit checks the instruction issuing state in the core for the first transposition instruction, and when the checking result shows that the instruction issuing condition in the core is met, notifies the instruction recording unit to change the current state of the first transposition instruction to a waiting synchronization state;

[0008] The instruction recording unit performs an inter-core instruction issuance status check on the first transposition instruction, and when the first transposition instructions of the first matrix of the multiple processor cores are all in a waiting synchronization state, changes the current state of the first transposition instruction to a waiting operation state;

[0009] The instruction issuing unit issues the first transposition instruction in a waiting state to the transposition executing unit, and the transposition executing unit performs a transposition operation on part of the data of the first matrix to obtain local transposition result data.

[0010] In a possible implementation, the target processor core further includes a data exchange unit, and the method further includes:

[0011] The data interaction unit determines that the local transposition result data corresponds to partial result data in each processor core respectively, and distributes it to each processor core so that other processor cores determine a part of the global transposition result data for performing a transposition operation on the first matrix according to it.

[0012] In a possible implementation, the target processor core further includes a data exchange unit, and the method further includes:

[0013] Receive partial result data of the local transposition result data allocated to itself from other processor cores through the data exchange unit;

[0014] The partial result data allocated according to its own local transposition result data and the allocated partial result data received from other processor cores are combined into a part of the global transposition result data for performing the transposition operation on the first matrix.

[0015] In one possible implementation, the multiple processor cores are used to execute the same fully homomorphic encryption computing task in parallel, which involves multiple transposition instructions, and the order in which the transposition instructions enter the processor core remains the same for the multiple processor cores.

[0016] In a possible implementation manner, the first matrix is ​​formed by polynomial coefficients of a first polynomial.

[0017] In a possible implementation, the instruction recording unit includes an instruction catalog table and a state machine control module, the instruction catalog table includes an instruction field and a status field, and the state machine control module is used to update the status field of each instruction.

[0018] Further, recording the current state of the first transposition instruction as a waiting-to-transmit state includes:

[0019] A first entry in an idle state is determined in the instruction catalog table, the first transposition instruction is recorded in an instruction field of the first entry, and a state field of the first entry is recorded as waiting to be issued.

[0020] In a possible implementation, the instruction issuing unit includes a scoring board module, and the instruction issuing status check in the core includes: performing data conflict check and resource conflict check using the scoring board module.

[0021] In a possible implementation, the method further includes:

[0022] After the instruction issuing unit issues the first transposition instruction to the transposition executing unit, the instruction recording unit changes the current state of the first transposition instruction to the operation state.

[0023] Furthermore, the method further comprises:

[0024] After the transposition execution unit completes executing the first transposition instruction, the instruction recording unit changes the current state of the first transposition instruction to an end state.

[0025] Furthermore, the method further comprises:

[0026] When the first transpose instruction is retired, the first entry in the instruction directory table is changed to an idle state.

[0027] In a second aspect, a computing device is provided, comprising a plurality of processor cores, wherein any target processor core comprises: an instruction issuing unit, an instruction recording unit, and a transposition execution unit;

[0028] The instruction recording unit is used to record the current state of the first transposition instruction as a waiting-to-transmit state in response to receiving the first transposition instruction for part of the data of the first matrix;

[0029] The instruction issuing unit is used to check the instruction issuing state in the core for the first transposition instruction, and when the checking result shows that the instruction issuing condition in the core is met, notify the instruction recording unit to change the current state of the first transposition instruction to the waiting synchronization state;

[0030] The instruction recording unit is further used to perform an inter-core instruction emission status check on the first transposition instruction, and when the first transposition instructions of the first matrix of the multiple processor cores are all in a waiting synchronization state, change the current state of the first transposition instruction to a waiting operation state;

[0031] The instruction issuing unit is further used to issue the first transposition instruction in a waiting operation state to the transposition executing unit, and the transposition executing unit performs a transposition operation on part of the data of the first matrix to obtain local transposition result data.

[0032] According to a third aspect, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed in a computer, the computer is caused to execute the method of the first aspect.

[0033] According to a fourth aspect, a computing device is provided, including a memory and a processor, wherein the memory stores executable code, and when the processor executes the executable code, the method of the first aspect is implemented.

[0034] Through the method and computing device provided by the embodiments of this specification, an instruction recording unit is included in each of the multiple processor cores, and the instruction recording unit records the status of the transposition instruction in the processor core. Based on the status, the emission condition check of the transposition instruction in the core and the data consistency check of the same transposition instruction between cores are completed, and the synchronization requirements and data consistency requirements of multi-core transposition are solved by hardware, and asynchronous processing of multi-core parallel computing is realized. It is possible to realize multi-core parallel computing of transposition processing and improve its execution efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0036] Figure 1 A schematic diagram of an implementation scenario of an embodiment disclosed in this specification;

[0037] Figure 2 A schematic diagram of a column NTT operation of an embodiment disclosed in this specification;

[0038] Figure 3 A schematic diagram of an implementation scenario of another embodiment disclosed in this specification;

[0039] Figure 4 A schematic diagram of NTT operation of an embodiment disclosed in this specification;

[0040] Figure 5 A schematic diagram of multi-core asynchronous computing according to an embodiment disclosed in this specification;

[0041] Figure 6 A flow chart of a matrix transposition processing method according to an embodiment is shown;

[0042] Figure 7 A schematic block diagram showing a computing device according to another embodiment;

[0043] Figure 8 A schematic diagram of a matrix transposition hardware architecture according to an embodiment is shown;

[0044] Fig. 9 An instruction catalog table and a state transition diagram according to an embodiment are shown. DETAILED DESCRIPTION

[0045] The solution provided in this specification is described below in conjunction with the accompanying drawings.

[0046] Figure 1 This is a schematic diagram of an implementation scenario of an embodiment disclosed in this specification. The implementation scenario involves a matrix transposition process, which is specifically a matrix transposition process in FHE calculation. It can be understood that the matrix transposition process can be an intermediate processing sub-process of a processing process. Typically, FHE calculations need to complete a large number of NTT operations and automorphism operations. The operation data object is a polynomial of 1024 points to 65536 points. When multiple computing units are used for parallel calculation, there are a large number of data paths in the permutation network. Taking the 65536-point NTT as an example, the number of data paths is 16x65536, which is impossible to achieve in hardware design. Therefore, a 2D algorithm is usually used to implement NTT operations and automorphism operations. Taking 65536-point NTT as an example, a 65536-point polynomial is split into 256 256-point sub-polynomials for NTT operation. The calculation process of the 2D NTT algorithm includes: treating 65536 points as a 256x256 matrix and performing a 256x256 matrix transpose operation; performing 256 column NTT operations, and the sub-polynomial for each operation is 1 column of 256-point NTT data; performing a 256x256 matrix transpose operation; performing 256 row NTT operations, and the sub-polynomial for each operation is 1 row of 256-point NTT data.

[0047] Reference Figure 1 For a 256x256 matrix, its row index can be numbered from 0 to 255, and its column index can be numbered from 0 to 255. The row index and column index can be used to identify the position of the element in the matrix. For example, "0,0" represents the element at row 0 and column 0, "0,1" represents the element at row 0 and column 1, and "1,0" represents the element at row 1 and column 0. Matrix transposition means swapping the rows and columns of the matrix, that is, the rows of the original matrix become columns, and the columns of the original matrix become rows. The 0th row of the original matrix becomes the 0th column of the transposed matrix. For the transposed matrix, "1,0 T " represents the element in the 1st row and 0th column of the matrix, which corresponds to "0,1" in the original matrix. That is to say, the element in the 1st row and 0th column of the transposed matrix has the same element value as the element in the 0th row and 1st column of the original matrix.

[0048] Figure 2 FIG. 1 is a schematic diagram of a column NTT operation of an embodiment disclosed in this specification. It can be understood that the column NTT operation is a calculation subprocess of the aforementioned 2D NTT algorithm, which depends on Figure 1 The transposed matrix is ​​obtained. Figure 2 , 256-point NTT is performed on each row of the transposed matrix. Since a row of the transposed matrix corresponds to a column of the original matrix, the column NTT operation is implemented.

[0049] Figure 3 1 is a schematic diagram of an implementation scenario of another embodiment disclosed in this specification. The implementation scenario involves a matrix transposition process, which is specifically another matrix transposition process in FHE calculation. It can be understood that the matrix transposition process is a calculation subprocess of the aforementioned 2D NTT algorithm, which can be Figure 2 The NTT operation is performed after the column. Figure 3 ,against Figure 1 The obtained transposed matrix is ​​further subjected to matrix transposition operation to obtain the original matrix. It can be understood that matrix transposition satisfies the following basic properties, that is, the original matrix is ​​obtained by performing two transposition operations on the original matrix.

[0050] Figure 4 FIG. 1 is a schematic diagram of a row NTT operation of an embodiment disclosed in this specification. It can be understood that the row NTT operation is a calculation subprocess of the aforementioned 2D NTT algorithm, which depends on Figure 3 Refer to Figure 4 , 256-point NTT is performed on each row of the original matrix to achieve row NTT operation.

[0051] Above Figures 1 to 4 The processing of the 2D NTT algorithm is shown, which involves two matrix transposition operations. The calculation process for the 2D automorphism operation is similar and will not be described in detail here.

[0052] Generally, in FHE calculation, under the 2D algorithm, the permutation network becomes 8x256, which is 512 times lower than the original 16x65536, greatly reducing the hardware implementation cost. Among them, the 2D algorithm will introduce 2 times of 256x256 matrix transposition operation, and this matrix transposition operation requires all parallel computing units to be performed simultaneously. Whether it is a multi-core architecture based on single instruction multi-thread (single instruction multi threads, SIMT) or a multi-core architecture based on multiple instruction streams and multiple data streams (multi instruction multi data, MIMD), due to its synchronization requirements and data consistency requirements, this global matrix transposition operation is difficult to implement, and will limit the performance improvement of multi-core asynchronous computing. The embodiment of this specification implements the global permutation operation by designing an efficient hardware solution, thereby realizing the acceleration of multi-core parallel computing for FHE.

[0053] It should be noted that matrix transposition processing has a wide range of application scenarios, which can be but is not limited to matrix transposition processing in FHE calculations.

[0054] Figure 5 This is a schematic diagram of multi-core asynchronous computing according to an embodiment disclosed in this specification. Figure 5 The essence of transposition is data replacement. When multiple processor cores perform transposition of a polynomial at the same time, the amount of source data and destination data of each processor core remains unchanged, but the data in each processor core will be distributed to all processor cores. For example, four processor cores are recorded as Core0, Core1, Core2 and Core3. When the four processor cores perform transposition operation on a polynomial, each processor core obtains a quarter of the partial data of the polynomial assigned to itself, performs transposition operation on the partial data, and obtains local transposition result data. The local transposition result data obtained by one processor core is distributed to each processor core, so that each processor core obtains a part of the global transposition result data according to the combination of the allocated partial result data.

[0055] In the embodiments of the present specification, multiple processor cores perform transposition operations on a polynomial in parallel, which is equivalent to each processor core executing the same instruction at the same time. After executing the instruction, data between the multiple processor cores are exchanged with each other. Therefore, before executing the instruction, it is necessary to consider the problem of data consistency between multiple cores and provide corresponding solutions.

[0056] Figure 6 A flow chart of a matrix transposition processing method according to an embodiment is shown. The method can be based on Figure 1 or Figure 3The implementation scenario shown is executed by any target processor core among multiple processor cores, and the target processor core includes an instruction issuing unit, an instruction recording unit, and a transposition execution unit. Figure 6 As shown, the matrix transposition processing method in this embodiment includes the following steps: Step 61, in response to receiving the first transposition instruction for part of the data of the first matrix, the instruction recording unit records the current state of the first transposition instruction as the waiting state for emission; Step 62, the instruction emission unit performs an instruction emission state check in the core for the first transposition instruction, and when the check result satisfies the instruction emission condition in the core, notifies the instruction recording unit to change the current state of the first transposition instruction to the waiting state for synchronization; Step 63, the instruction recording unit performs an inter-core instruction emission state check for the first transposition instruction, and when the first transposition instructions of the first matrix of the multiple processor cores are all in the waiting state for synchronization, the current state of the first transposition instruction is changed to the waiting state for operation; Step 64, the instruction emission unit transmits the first transposition instruction in the waiting state for operation to the transposition execution unit, and the transposition execution unit performs the transposition operation on part of the data of the first matrix to obtain the local transposition result data. The specific execution method of each of the above steps is described below.

[0057] First, in step 61, in response to receiving a first transposition instruction for partial data of the first matrix, the instruction recording unit records the current state of the first transposition instruction as a waiting-to-issue state. It can be understood that the first matrix is ​​assigned to multiple processor cores to perform transposition operations in parallel, and each processor core obtains partial data of the first matrix.

[0058] For example, the first matrix is ​​a data with 256 rows and 256 columns. It can be divided by rows, and the first matrix can be evenly distributed to the four processor cores, with rows 1 to 64 allocated to processor core A, rows 65 to 128 allocated to processor core B, rows 129 to 192 allocated to processor core C, and rows 193 to 256 allocated to processor core D; or, it can be divided by columns, and the first matrix can be evenly distributed to the four processor cores, with columns 1 to 64 allocated to processor core A, columns 65 to 128 allocated to processor core B, columns 129 to 192 allocated to processor core C, and columns 193 to 256 allocated to processor core D.

[0059] It should be noted that the data of the matrix may be evenly distributed to each processor core, or may not be evenly distributed. For example, the data may be distributed according to the processing capability of each processor core, with more data being distributed to processor cores with strong processing capabilities and less data being distributed to processor cores with weak processing capabilities.

[0060] In one example, the multiple processor cores are used to execute the same fully homomorphic encryption computing task in parallel, which involves multiple transposition instructions, and the order in which the transposition instructions enter the processor core remains the same for the multiple processor cores.

[0061] In this example, each transposition instruction is usually directed to different objects, for example, transposition instruction A performs transposition processing on the first matrix, and transposition instruction B performs transposition processing on the second matrix. Different transposition instructions can be distinguished according to the time required to be executed in the program.

[0062] In one example, the first matrix is ​​composed of polynomial coefficients of a first polynomial.

[0063] In this example, it can correspond to the NTT operation scenario, and a 65536-point polynomial can be regarded as a 256×256 matrix.

[0064] In one example, the instruction recording unit includes an instruction catalog table and a state machine control module, the instruction catalog table includes an instruction field and a status field, and the state machine control module is used to update the status field of each instruction.

[0065] In this example, the state machine control module may update the state field based on a mathematical model such as a finite state machine (FSM).

[0066] Further, recording the current state of the first transposition instruction as a waiting-to-transmit state includes:

[0067] A first entry in an idle state is determined in the instruction catalog table, the first transposition instruction is recorded in an instruction field of the first entry, and a state field of the first entry is recorded as waiting to be issued.

[0068] In this example, when an entry in the instruction directory table is not used, its status field is in an idle state.

[0069] Then, in step 62, the instruction emission unit performs an instruction emission status check in the core for the first transposition instruction, and when the check result satisfies the instruction emission condition in the core, the instruction recording unit is notified to change the current state of the first transposition instruction to the waiting synchronization state. It can be understood that the above-mentioned instruction emission status check in the core only needs to be completed independently by a single processor core, without the cooperation of other processor cores.

[0070] In one example, the instruction issuing unit includes a scoring board module, and the instruction issuing status check in the core includes: performing data conflict check and resource conflict check using the scoring board module.

[0071] In this example, the scoring board module can be used for dynamic scheduling in pipeline processing to avoid data conflicts and resource conflicts.

[0072] Then, in step 63, the instruction recording unit performs an inter-core instruction emission status check on the first transposition instruction, and when the first transposition instructions of the first matrix of the multiple processor cores are all in a waiting synchronization state, the current state of the first transposition instruction is changed to a waiting operation state. It can be understood that the above inter-core instruction emission status check requires the cooperation of other processor cores.

[0073] The embodiments of this specification can ensure that the transpose instruction can reach the emission state in all processor cores before being emitted for execution through inter-core instruction emission status checking, thereby ensuring the correctness of the execution of the transpose instruction through hardware means.

[0074] Finally, in step 64, the instruction issuing unit issues the first transposition instruction in the waiting state to the transposition executing unit, and the transposition executing unit performs a transposition operation on part of the data of the first matrix to obtain local transposition result data. It can be understood that the above transposition operation is executed by a single processor core and can be processed in a common manner.

[0075] In one example, the target processor core further includes a data exchange unit, and the method further includes:

[0076] The data interaction unit determines that the local transposition result data corresponds to partial result data in each processor core respectively, and distributes it to each processor core so that other processor cores determine a part of the global transposition result data for performing a transposition operation on the first matrix according to it.

[0077] In this example, the target processor core distributes part of the result data to other processor cores, so that the other processor cores can determine part of the global transposed result data.

[0078] In one example, the target processor core further includes a data exchange unit, and the method further includes:

[0079] Receive partial result data of the local transposition result data allocated to itself from other processor cores through the data exchange unit;

[0080] The partial result data allocated according to its own local transposition result data and the allocated partial result data received from other processor cores are combined into a part of the global transposition result data for performing the transposition operation on the first matrix.

[0081] In this example, the target processor core receives partial result data from other processor cores and can determine a portion of the global transposed result data.

[0082] In one example, the method further includes:

[0083] After the instruction issuing unit issues the first transposition instruction to the transposition executing unit, the instruction recording unit changes the current state of the first transposition instruction to the operation state.

[0084] In this example, the status field corresponding to the first transposition instruction in the instruction catalog table may be updated to the job status.

[0085] Furthermore, the method further comprises:

[0086] After the transposition execution unit completes executing the first transposition instruction, the instruction recording unit changes the current state of the first transposition instruction to an end state.

[0087] In this example, the status field corresponding to the first transposition instruction in the instruction catalog table may be updated to the end status.

[0088] Furthermore, the method further comprises:

[0089] When the first transpose instruction is retired, the first entry in the instruction directory table is changed to an idle state.

[0090] In this example, transpose instructions are retired in a first-in, first-out manner. When a transpose instruction is retired, the state field corresponding to the first transpose instruction in the instruction directory table is updated to an idle state.

[0091] Through the method provided in the embodiments of this specification, an instruction recording unit is included in each of the multiple processor cores, and the instruction recording unit records the status of the transposition instruction in the processor core. Based on the status, the emission condition check of the transposition instruction in the core and the data consistency check of the same transposition instruction between cores are completed, and the synchronization requirements and data consistency requirements of multi-core transposition are solved by hardware, and asynchronous processing of multi-core parallel computing is realized. It can realize multi-core parallel computing of transposition processing and improve its execution efficiency.

[0092] According to another embodiment, a computing device is also provided, the computing device being used to execute the Figure 6 The method provided by the illustrated embodiment. Figure 7 Schematic block diagram of a computing device according to another embodiment is shown. Figure 7 As shown, the computing device 700 includes a plurality of processor cores, wherein any target processor core includes: an instruction emission unit 71, an instruction recording unit 72, and a transposition execution unit 73;

[0093] The instruction recording unit 72 is used to record the current state of the first transposition instruction as a waiting-to-transmit state in response to receiving the first transposition instruction for part of the data of the first matrix;

[0094] The instruction issuing unit 71 is used to check the instruction issuing state in the core for the first transposition instruction, and when the checking result shows that the instruction issuing condition in the core is met, notify the instruction recording unit 72 to change the current state of the first transposition instruction to the waiting synchronization state;

[0095] The instruction recording unit 72 is further used to perform an inter-core instruction issuance status check on the first transposition instruction, and when the first transposition instructions of the first matrix of the multiple processor cores are all in a waiting synchronization state, change the current state of the first transposition instruction to a waiting operation state;

[0096] The instruction transmitting unit 71 is further used to transmit the first transposition instruction in the waiting operation state to the transposition executing unit 73, and the transposition executing unit 73 performs a transposition operation on part of the data of the first matrix to obtain local transposition result data.

[0097] In the embodiments of this specification, the number of the multiple processor cores is not limited, and may be, but is not limited to, 2, 3, or 4, etc. Any processor core may be regarded as the target processor core, and each processor core may have the same structure.

[0098] Optionally, as an embodiment, the target processor core also includes a data interaction unit, which is used to determine that the local transposition result data corresponds to partial result data in each processor core, and distribute it to each processor core so that other processor cores can determine a part of the global transposition result data for performing a transposition operation on the first matrix based on it.

[0099] Optionally, as an embodiment, the target processor core also includes a data interaction unit, which is used to receive partial result data allocated to itself by its local transposition result data from other processor cores; and combine the partial result data allocated by its own local transposition result data and the allocated partial result data received from other processor cores into a part of the global transposition result data for performing a transposition operation on the first matrix.

[0100] Optionally, as an embodiment, the multiple processor cores are used to execute the same fully homomorphic encryption computing task in parallel, which task involves multiple transposition instructions, and the order in which each transposition instruction enters the processor core remains the same for the multiple processor cores.

[0101] Optionally, as an embodiment, the first matrix is ​​composed of polynomial coefficients of a first polynomial.

[0102] Optionally, as an embodiment, the instruction recording unit 72 includes an instruction catalog table and a state machine control module, the instruction catalog table includes an instruction field and a status field, and the state machine control module is used to update the status field of each instruction.

[0103] Furthermore, the instruction recording unit 72 is specifically configured to determine a first entry in an idle state in the instruction catalog table, record the first transposition instruction in the instruction field of the first entry, and record the state field of the first entry as waiting to be issued.

[0104] Optionally, as an embodiment, the instruction transmitting unit 71 includes a scoring board module, and the instruction transmitting unit 71 is specifically configured to use the scoring board module to perform data conflict checking and resource conflict checking.

[0105] Optionally, as an embodiment, the instruction recording unit 72 is further configured to change the current state of the first transposition instruction to a job state after the instruction transmitting unit 71 transmits the first transposition instruction to the transposition executing unit 73 .

[0106] Furthermore, the instruction recording unit 72 is further configured to change the current state of the first transposition instruction to an end state after the transposition execution unit 73 completes execution of the first transposition instruction.

[0107] Furthermore, the instruction recording unit 72 is further configured to change the first entry in the instruction directory table to an idle state when the first transpose instruction is retired.

[0108] The computing device provided by the embodiments of this specification includes an instruction recording unit 72 in each of the multiple processor cores. The instruction recording unit 72 records the status of the transposition instruction in the processor core, and based on the status, the emission condition check of the transposition instruction in the core and the data consistency check of the same transposition instruction between cores are completed. The synchronization requirements and data consistency requirements of multi-core transposition are solved by hardware, and asynchronous processing of multi-core parallel computing is realized. It can realize multi-core parallel computing of transposition processing and improve its execution efficiency.

[0109] Figure 8 FIG. 1 is a schematic diagram of a matrix transposition hardware architecture according to an embodiment. Figure 8, take two processor cores executing the transposition operation of a matrix in parallel as an example, the two processor cores are respectively recorded as Core0 and Core1, each processor core includes an instruction emission unit, an instruction recording unit and a transposition execution unit, the instruction emission unit includes a scheduler, a scoring board module and a transmission queue, and the instruction recording unit includes a state machine control module and an instruction directory table. Among them, the instruction directory table is used to store the state of the transposition instruction. The instruction directory tables inside multiple processor cores form a distributed directory, and the intra-core state and inter-core state of the instruction can be queried through the distributed directory. For example, Core0 can obtain the intra-core state by querying instruction directory table 0, and obtain the inter-core state by querying instruction directory table 1. When a multi-core processor is used to execute the same fully homomorphic encryption computing task, the order in which all transposition instructions of all processor cores enter the processor core remains the same, and multiple transposition instructions constitute a transmission queue.

[0110] When an item in the instruction catalog table is not used, its status is idle, recorded as idle. When the transposition instruction enters the processor core, the state machine control module inside the processor core will allocate an item in the instruction catalog table to record the status of the transposition instruction, and at this time, the status of this item in the instruction catalog table is changed to the waiting state, recorded as wait_i ssue. When the scheduler obtains the transposition instruction in the waiting state, the scheduling score board module performs an instruction emission status check in the core, including data conflict check and resource conflict check. When the instruction emission conditions in the core are met, the scheduler notifies the state machine control module to change the status of this item in the instruction catalog table to waiting for synchronization, recorded as wait_sync. When the transposition instruction is in the waiting state, the state machine control module performs an inter-core instruction emission status check, that is, obtains the status of the transposition instruction from other processor cores. When this instruction of all processor cores containing the same matrix is ​​in the waiting state, the status of this item in the instruction catalog table is changed to the waiting state for work, recorded as wait_work. When the transposition instruction is in the waiting state, it can be normally sent by the instruction issuing unit to the transposition execution unit for transposition operation. When the instruction issuing unit sends the transposition instruction to the transposition execution unit, the state of this item in the instruction catalog table changes to the operation state, recorded as work. After the transposition execution unit completes the execution of the transposition instruction, the state of this item in the instruction catalog table changes to the end state, recorded as done. The transposition instruction is retired in a first-in-first-out manner. When the transposition instruction retires, the state of this item in the instruction catalog table changes to the idle state, recorded as idle.

[0111] Fig. 9 FIG. 1 shows an instruction catalog table and a state transition diagram according to an embodiment. Fig. 9, the instruction catalog table includes several entries, each of which records the information of an instruction, including period, instruction and state. Among them, the state can be transferred. When a state executes certain actions to change to another state, it is a state transfer. The state transfer is to define the transfer process of the state machine. In a certain state, when a certain transfer condition is met, it will transfer to the next state according to the transfer process of the state machine and perform the corresponding action. For example, in the idle state, execute action 1 and transfer to the wait_i ssue state; in the wait_i ssue state, execute action 2 and transfer to the wait_sync state; in the wait_sync state, execute action 3 and transfer to the wait_work state; in the wait_work state, execute action 4 and transfer to the work state; in the work state, execute action 5 and transfer to the done state; in the done state, execute action 6 and transfer to the idle state.

[0112] In the embodiments of this specification, when the application scenario is matrix transposition in FHE, the computing device can be an FHE acceleration chip, and a distributed directory is designed to record the status of the same transposition instruction between different processor cores. After each processor core independently completes the emission condition judgment of its own transposition instruction, the instruction emission status between multiple processor cores is synchronized, thereby ensuring that the transposition operation reaches the emission state in all processor cores before being emitted for execution. The correctness and efficiency of the execution of the transposition instruction are guaranteed by hardware means, thereby realizing a hardware architecture that can distribute a polynomial in multiple cores and perform FHE operations simultaneously.

[0113] According to another embodiment, there is also provided a computer-readable storage medium having a computer program stored thereon, which, when executed in a computer, causes the computer to execute a combination of Figure 6 The method described.

[0114] According to another embodiment of the present invention, a computing device is provided, including a memory and a processor, wherein the memory stores executable code, and when the processor executes the executable code, the Figure 6 The method described.

[0115] Those skilled in the art should be aware that in one or more of the above examples, the functions described in the present invention can be implemented by hardware, software, firmware or any combination thereof. When implemented by software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium.

[0116] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made on the basis of the technical solution of the present invention should be included in the scope of protection of the present invention.

Claims

1. A matrix transposition processing method, executed by any target processor core among a plurality of processor cores, wherein the target processor core comprises an instruction issuing unit, an instruction recording unit and a transposition execution unit, the method comprising: In response to receiving a first transposition instruction for a portion of data of the first matrix, the instruction recording unit records a current state of the first transposition instruction as a waiting-to-transmit state; The instruction issuing unit checks the instruction issuing state in the core for the first transposition instruction, and when the checking result shows that the instruction issuing condition in the core is met, notifies the instruction recording unit to change the current state of the first transposition instruction to a waiting synchronization state; The instruction recording unit performs an inter-core instruction issuance status check on the first transposition instruction, and when the first transposition instructions of the first matrix of the multiple processor cores are all in a waiting synchronization state, changes the current state of the first transposition instruction to a waiting operation state; The instruction issuing unit issues the first transposition instruction in a waiting state to the transposition executing unit, and the transposition executing unit performs a transposition operation on part of the data of the first matrix to obtain local transposition result data.

2. The method of claim 1, wherein: The target processor core also includes a data exchange unit, and the method further includes: The data interaction unit determines that the local transposition result data corresponds to partial result data in each processor core respectively, and distributes it to each processor core so that other processor cores determine a part of the global transposition result data for performing a transposition operation on the first matrix according to it.

3. The method of claim 1, wherein: The target processor core also includes a data exchange unit, and the method further includes: Receive partial result data of the local transposition result data allocated to itself from other processor cores through the data exchange unit; The partial result data allocated according to its own local transposition result data and the allocated partial result data received from other processor cores are combined into a part of the global transposition result data for performing the transposition operation on the first matrix.

4. The method of claim 1, wherein: The multiple processor cores are used to execute the same fully homomorphic encryption computing task in parallel, which involves multiple transposition instructions, and the order in which each transposition instruction enters the processor core remains the same for the multiple processor cores.

5. The method of claim 1, wherein: The first matrix is ​​composed of polynomial coefficients of a first polynomial.

6. The method of claim 1, wherein: The instruction recording unit includes an instruction catalog table and a state machine control module. The instruction catalog table includes an instruction field and a state field. The state machine control module is used to update the state field of each instruction.

7. The method of claim 6, wherein: The step of recording the current state of the first transposition instruction as a waiting-to-issue state comprises: A first entry in an idle state is determined in the instruction catalog table, the first transposition instruction is recorded in an instruction field of the first entry, and a state field of the first entry is recorded as waiting to be issued.

8. The method of claim 1, wherein: The instruction emission unit includes a scoring board module, and the instruction emission status check in the core includes: using the scoring board module to perform data conflict check and resource conflict check.

9. The method of claim 1, wherein: The method further comprises: After the instruction issuing unit issues the first transposition instruction to the transposition executing unit, the instruction recording unit changes the current state of the first transposition instruction to the operation state.

10. The method of claim 9, wherein: The method further comprises: After the transposition execution unit completes executing the first transposition instruction, the instruction recording unit changes the current state of the first transposition instruction to an end state.

11. The method of claim 7, wherein: The method further comprises: When the first transpose instruction is retired, the first entry in the instruction directory table is changed to an idle state.

12. A computing device comprising a plurality of processor cores, wherein any target processor core comprises: Instruction issuing unit, instruction recording unit and transposition execution unit; The instruction recording unit is used to record the current state of the first transposition instruction as a waiting-to-transmit state in response to receiving the first transposition instruction for part of the data of the first matrix; The instruction issuing unit is used to check the instruction issuing state in the core for the first transposition instruction, and when the checking result shows that the instruction issuing condition in the core is met, notify the instruction recording unit to change the current state of the first transposition instruction to the waiting synchronization state; The instruction recording unit is further used to perform an inter-core instruction emission status check on the first transposition instruction, and when the first transposition instructions of the first matrix of the multiple processor cores are all in a waiting synchronization state, change the current state of the first transposition instruction to a waiting operation state; The instruction issuing unit is further used to issue the first transposition instruction in a waiting operation state to the transposition executing unit, and the transposition executing unit performs a transposition operation on part of the data of the first matrix to obtain local transposition result data.

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