Method and system for accelerating time domain and frequency domain conversion based on ZYNQ chip

Abstract

The invention provides an acceleration time domain and frequency domain conversion method and system based on a ZYNQ chip, and the method comprises the steps: carrying a 32bit time domain signal stored in a DDR chip to a PL end of the ZYNQ chip through a DMAIP core, enabling the 32bit time domain signal to enter an FFT IP core (I) through a channel change-over switch MUX, and outputting a frequency domain signal in the FFT IP core (I) through the Fourier FFT; performing complex multiplication operation on the frequency domain signal and a filter coefficient in the ROM IP core to obtain a complex multiplication result, and caching the complex multiplication result in the FIFO; reading the frequency domain signal after the complex multiplication operation from the FIFO, and transmitting the frequency domain signal into an FFT IP core (I) through a channel change-over switch MUX to carry out inverse Fourier transform (IFFT) so as to convert the frequency domain signal into a time domain signal; and caching the converted time domain signal in an FIFO (First In First Out). According to the technical scheme, the technical problems that in the prior art, a DSP chip or a single-chip microcomputer is used, when a large number of operations are carried out, the operation pressure of a CPU is too large, and the operation speed is reduced are solved.

Description

Technical Field

[0001] The present invention relates to the field of quantum sensing technology, and in particular to a method and system for accelerating time-domain and frequency-domain conversion based on a ZYNQ chip. Background Art

[0002] Atomic magnetometers measure magnetic fields based on the Larmor precession of atomic spin ensembles under magnetic fields. Compared with traditional optically pumped magnetometers, they have outstanding features such as high sensitivity, small size, and static magneto / axial frequency magneto composite detection. In the engineering application of atomic magnetometers, DSP chips or single-chip microcomputers are usually used for Fourier transform. When a large number of calculations are performed, the CPU operation pressure will be too high, reducing the operation speed. Summary of the invention

[0003] The present invention provides a method and system for accelerating time-domain and frequency-domain conversion based on a ZYNQ chip, which can solve the technical problem in the prior art that when a large number of operations are performed using a DSP chip or a single-chip microcomputer, the CPU operation pressure is too large and the operation speed is reduced.

[0004] According to one aspect of the present invention, a method for accelerating time-domain to frequency-domain conversion based on a ZYNQ chip is provided. The method for accelerating time-domain to frequency-domain conversion based on a ZYNQ chip comprises: transferring a 32-bit time-domain signal stored in a DDR chip to a PL terminal of a ZYNQ chip through a DMAIP core, entering an (I)FFT IP core through a channel conversion switch MUX, and outputting a frequency-domain signal through Fourier transform in the (I)FFT IP core; performing a complex multiplication operation on the frequency-domain signal and a filter coefficient in a ROM IP core to obtain a complex multiplication result, and caching the complex multiplication result in a FIFO under the control of a complex multiplication operation control state machine; reading out the frequency-domain signal after the complex multiplication operation from the FIFO, and transmitting it again through the channel conversion switch MUX into an (I)FFT IP core for inverse Fourier transform to convert it into a time-domain signal; caching the converted time-domain signal in a FIFO under the control of the complex multiplication operation control state machine, thereby completing the accelerated time-domain to frequency-domain conversion based on a ZYNQ chip.

[0005] Furthermore, in the complex multiplication operation, if two complex numbers are set to be a+bi and c+di respectively, the result of multiplying the two complex numbers is (ac-bd)+(ad+bc)i. Since the 32-bit data stored in the DDR chip is a complex signal containing the I phase and the Q phase, the lower 16-bit data is equivalent to the real part, i.e. a or c, and the upper 16-bit data is equivalent to the imaginary part, i.e. b or d. The high 16-bit imaginary part signal and the low 16-bit real part signal intercepted from the 32-bit data are used as the input of the complex multiplication operation. After the complex multiplication operation, the real part result and the imaginary part result of 33bi are obtained. The high 16 bits of the imaginary part result and the real part result are intercepted and merged into a 32-bit signal and stored in the FIFO.

[0006] Furthermore, the FIFO process is mainly divided into four states, and the specific jump process is as follows: FFT_START state: waiting for the FFT start instruction. After receiving the start instruction, the Fourier FFT operation of the DMA IP core is started, and the FIFO write channel is opened to cache the frequency domain result after the complex multiplication; WAIT_FFT_DONE state: waiting for the FFT completion interrupt. When the completion interrupt is received, the FIFO read channel is opened to read the frequency domain complex multiplication signal in the FIFO; the IFFT operation of the DMA IP core is started, and the frequency domain signal is converted into a time domain signal through the IFFT operation and cached in the FIFO; WAIT_IFFT_LOAD state: waiting for the completion instruction of the frequency domain complex multiplication result reading in the FIFO. After the FIFO reading is completed, stop inputting signals to the (I)FFT IP core; WAIT_IFFT_DONE state: waiting for the IFFT completion interrupt. When the completion interrupt is received, the complex multiplication operation control state machine generates an interrupt to start the DMA IP core, and the time domain filtering result in the FIFO is moved to the DDR chip to prepare for subsequent algorithm operations.

[0007] According to another aspect of the present invention, a ZYNQ chip-based accelerated time-domain-frequency domain conversion system is provided. The ZYNQ chip-based accelerated time-domain-frequency domain conversion system uses the ZYNQ chip-based accelerated time-domain-frequency domain conversion method as described above to perform accelerated time-domain-frequency domain conversion.

[0008] Furthermore, the accelerated time-domain-frequency-domain conversion system based on the ZYNQ chip includes a DMA IP core, a channel conversion switch MUX, a (I)FFT IP core, a ROM IP core, a complex multiplication operation module, a complex multiplication operation control state machine and a FIFO. The 32-bit time-domain signal stored in the DDR chip is transferred to the PL end of the ZYNQ chip through the DMA IP core, enters the (I)FFT IP core through the channel conversion switch MUX, and outputs the frequency-domain signal through Fourier FFT transformation in the (I)FFT IP core; the frequency-domain signal and the filter coefficient in the ROM IP core are complex-multiplied in the complex multiplication operation module to obtain a complex multiplication result, and the complex multiplication result is cached in the FIFO under the control of the complex multiplication operation control state machine; the frequency-domain signal after the complex multiplication operation is read out from the FIFO, and is again transmitted through the channel conversion switch MUX into the (I)FFT IP core for inverse Fourier IFFT transformation to be converted into a time-domain signal; the converted time-domain signal is cached in the FIFO under the control of the complex multiplication operation control state machine, thereby completing the accelerated time-domain-frequency-domain conversion based on the ZYNQ chip.

[0009] According to another aspect of the present invention, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the accelerated time-domain to frequency-domain conversion method based on the ZYNQ chip as described above.

[0010] According to another aspect of the present invention, a computer-readable storage medium is provided, which stores a computer program. When the computer program is executed by a processor, the steps of the accelerated time-domain to frequency-domain conversion method based on the ZYNQ chip as described above are implemented.

[0011] By applying the technical solution of the present invention, a method for accelerating time-domain to frequency-domain conversion based on a ZYNQ chip is provided. The method adopts a ZYNQ chip that integrates a high-performance ARM Cortex-A9 processor and programmable logic resources, replacing the traditional method of using only a DSP chip or a single-chip microcomputer to realize time-domain and frequency-domain conversion. The ZYNQ chip is used to perform frequency-domain complex multiplication operations, and the programmable logic resources on the PL end are used to realize hardware accelerated operations, which can not only reduce the operation pressure of the ARM processor and improve the operation speed, but also greatly improve the processing flexibility of the operation unit by carrying input and output data through the internal DMA. Therefore, compared with the prior art, the accelerated time-domain to frequency-domain conversion method based on a ZYNQ chip provided by the present invention greatly reduces the operation pressure of the CPU, reduces the hardware complexity, and improves the operation speed and data processing flexibility while ensuring the accuracy of the operation, thereby meeting the engineering application requirements of the atomic magnetic detector. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The included drawings are used to provide a further understanding of the embodiments of the present invention, which constitute a part of the specification, are used to illustrate the embodiments of the present invention, and together with the text description, explain the principles of the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 A block diagram of the structure of an accelerated time-domain to frequency-domain conversion system based on a ZYNQ chip according to a specific embodiment of the present invention is shown;

[0014] Figure 2 A flow jump diagram of a FIFO provided according to a specific embodiment of the present invention is shown. DETAILED DESCRIPTION

[0015] It should be noted that, in the absence of conflict, the embodiments in this application and the features in the embodiments can be combined with each other. The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present invention and its application or use. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0016] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0017] Unless otherwise specifically stated, the relative arrangement of the parts and steps described in these embodiments, numerical expressions and numerical values ​​do not limit the scope of the present invention. At the same time, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to the actual proportional relationship. The technology, method and equipment known to ordinary technicians in the relevant field may not be discussed in detail, but in appropriate cases, the technology, method and equipment should be regarded as a part of the authorization specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings.

[0018] like Figure 1 As shown, according to a specific embodiment of the present invention, an accelerated time-domain to frequency-domain conversion method based on a ZYNQ chip is provided. The accelerated time-domain to frequency-domain conversion method based on a ZYNQ chip includes: transferring a 32-bit time-domain signal stored in a DDR chip to a PL end of a ZYNQ chip through a DMAIP core, entering an (I)FFT IP core through a channel conversion switch MUX, and outputting a frequency-domain signal through a Fourier transform in the (I)FFT IP core; performing a complex multiplication operation on the frequency-domain signal and a filter coefficient in a ROM IP core to obtain a complex multiplication result, and caching the complex multiplication result in a FIFO under the control of a complex multiplication operation control state machine; reading out the frequency-domain signal after the complex multiplication operation from the FIFO, and transmitting it again through a channel conversion switch MUX into an (I)FFT IP core for an inverse Fourier transform to convert it into a time-domain signal; caching the converted time-domain signal in a FIFO under the control of a complex multiplication operation control state machine, thereby completing the accelerated time-domain to frequency-domain conversion based on a ZYNQ chip.

[0019] By applying this configuration, a method for accelerating time-domain and frequency-domain conversion based on a ZYNQ chip is provided. The method adopts a ZYNQ chip that integrates a high-performance ARM Cortex-A9 processor and programmable logic resources, replacing the traditional method of using only a DSP chip or a single-chip microcomputer to realize time-domain and frequency-domain conversion. The ZYNQ chip is used to perform frequency-domain complex multiplication operations, and the programmable logic resources on the PL end are used to realize hardware accelerated operations, which can not only reduce the computing pressure of the ARM processor and improve the computing speed, but also greatly improve the processing flexibility of the computing unit by carrying out input and output data through the internal DMA. Therefore, compared with the prior art, the accelerated time-domain and frequency-domain conversion method based on the ZYNQ chip provided by the present invention greatly reduces the computing pressure of the CPU, reduces the hardware complexity, and improves the computing speed and data processing flexibility while ensuring the computing accuracy, so as to meet the engineering application requirements of the atomic magnetic detector.

[0020] Specifically, in the present invention, the ZYNQ-7045 chip is a powerful high-performance system-on-chip (SoC), which integrates a high-performance ARM Cortex-A9 processor (PS) and programmable logic resources (PL) and is suitable for a variety of applications requiring high capacity. By performing signal processing with the ZYNQ chip, not only can the complex algorithm operation functions provided by the DSP chip be realized, but also the flexible and fast circuit design functions provided by the FPGA chip can be realized.

[0021] When choosing the complex multiplication method for signal filtering, it can be implemented in both time domain and frequency domain. Among them, for complex multiplication operations with a large number of points, the frequency domain method can greatly reduce the number of operations and reduce the complexity of hardware. Filtering in the frequency domain can make the changes in frequency components more intuitive, easy to understand and analyze; various complex image processing effects can be achieved by designing different filters; the mathematical properties of Fourier transform can be used to achieve fast image processing operations.

[0022] Using the ZYNQ chip to perform frequency domain complex multiplication operations and using the programmable logic resources on the PL side to implement hardware accelerated operations can not only reduce the computing pressure of the ARM processor and improve the computing speed, but also greatly improve the processing flexibility of the computing unit by carrying out input and output data through the internal DMA. Therefore, the accelerated time domain and frequency domain conversion method based on ZYNQ in the present invention greatly improves the computing speed and reduces the CPU processing pressure while ensuring the computing accuracy, thereby improving the environmental adaptability of the system and meeting the engineering application requirements.

[0023] Furthermore, in the present invention, in the complex multiplication operation, if two complex numbers are set to be a+bi and c+di respectively, the result of multiplying the two complex numbers is (ac-bd)+(ad+bc)i. Since the 32-bit data stored in the DDR chip is a complex signal including the I phase and the Q phase, the lower 16-bit data is equivalent to the real part, i.e., a or c, and the upper 16-bit data is equivalent to the imaginary part, i.e., b or d. The upper 16-bit imaginary part signal and the lower 16-bit real part signal intercepted from the 32-bit data are used as inputs for the complex multiplication operation. After the complex multiplication operation, a 33-bit real part result and an imaginary part result are obtained. The upper 16 bits of the imaginary part result and the real part result are respectively intercepted and merged into a 32-bit signal and stored in the FIFO.

[0024] Specifically, the complex multiplication operation module of the present invention includes four multipliers, an adder and a subtractor, the low 16-bit data a and the high 16-bit data d are input into the first multiplier for operation to obtain data ad; the low 16-bit data c and the high 16-bit data b are input into the second multiplier for operation to obtain data bc, and the data ad and the data bc are input into the adder to obtain data (ad+bc); the low 16-bit data a and the low 16-bit data c are input into the third multiplier for operation to obtain data ac, the high 16-bit data b and the high 16-bit data d are input into the fourth multiplier for operation to obtain data bd, and the data ac and the data bd are input into the subtractor to obtain data (ac-bd), thereby obtaining (ac-bd)+(ad+bc)i through complex multiplication operation.

[0025] Further, in the present invention, if Figure 2 As shown, the FIFO process is mainly divided into four states, and the specific jump process is as follows: FFT_START state: waiting for the FFT start instruction. After receiving the start instruction, the Fourier FFT operation of the DMAIP core is started, and the FIFO write channel is opened to cache the frequency domain result after the complex multiplication; WAIT_FFT_DONE state: waiting for the FFT completion interrupt. When the completion interrupt is received, the FIFO read channel is opened to read the frequency domain complex multiplication signal in the FIFO; the IFFT operation of the DMAIP core is started, and the frequency domain signal is converted into a time domain signal through the IFFT operation and cached in the FIFO; WAIT_IFFT_LOAD state: waiting for the completion instruction of the frequency domain complex multiplication result in the FIFO. After the FIFO reading is completed, stop inputting signals to the (I)FFT IP core; WAIT_IFFT_DONE state: waiting for the IFFT completion interrupt. When the completion interrupt is received, the complex multiplication operation control state machine generates an interrupt to start the DMAIP core, and the time domain filtering result in the FIFO is moved to the DDR chip to prepare for subsequent algorithm operations.

[0026] According to another aspect of the present invention, a ZYNQ chip-based accelerated time-domain-frequency domain conversion system is provided. The ZYNQ chip-based accelerated time-domain-frequency domain conversion system uses the ZYNQ chip-based accelerated time-domain-frequency domain conversion method as described above to perform accelerated time-domain-frequency domain conversion.

[0027] By applying this configuration, an accelerated time-domain-frequency-domain conversion system based on a ZYNQ chip is provided. The system adopts a ZYNQ chip that integrates a high-performance ARM Cortex-A9 processor and programmable logic resources, replacing the traditional method of using only a DSP chip or a single-chip microcomputer to realize time-domain and frequency-domain conversion. The ZYNQ chip is used to perform frequency-domain complex multiplication operations, and the programmable logic resources on the PL side are used to realize hardware accelerated operations, which can not only reduce the computing pressure of the ARM processor and improve the computing speed, but also greatly improve the processing flexibility of the computing unit by carrying out input and output data through the internal DMA. Therefore, compared with the prior art, the accelerated time-domain-frequency-domain conversion system based on the ZYNQ chip provided by the present invention greatly reduces the computing pressure of the CPU, reduces the hardware complexity, and improves the computing speed and data processing flexibility while ensuring the computing accuracy, thereby meeting the engineering application requirements of the atomic magnetic detector.

[0028] Specifically, the accelerated time-domain to frequency-domain conversion system based on the ZYNQ chip includes a DMA IP core, a channel conversion switch MUX, a (I)FFT IP core, a ROM IP core, a complex multiplication operation module, a complex multiplication operation control state machine and a FIFO. The 32-bit time-domain signal stored in the DDR chip is transferred to the PL end of the ZYNQ chip through the DMA IP core, enters the (I)FFT IP core through the channel conversion switch MUX, and outputs the frequency-domain signal through Fourier FFT transformation in the (I)FFT IP core; the frequency-domain signal and the filter coefficient in the ROM IP core are complex-multiplied in the complex multiplication operation module to obtain a complex multiplication result, and the complex multiplication result is cached in the FIFO under the control of the complex multiplication operation control state machine; the frequency-domain signal after the complex multiplication operation is read out from the FIFO, and is again transmitted through the channel conversion switch MUX into the (I)FFT IP core for inverse Fourier IFFT transformation to be converted into a time-domain signal; the converted time-domain signal is cached in the FIFO under the control of the complex multiplication operation control state machine, thereby completing the accelerated time-domain to frequency-domain conversion based on the ZYNQ chip.

[0029] According to another aspect of the present invention, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the accelerated time-domain to frequency-domain conversion method based on the ZYNQ chip as described above.

[0030] According to another aspect of the present invention, a computer-readable storage medium is provided, which stores a computer program. When the computer program is executed by a processor, the steps of the accelerated time-domain to frequency-domain conversion method based on the ZYNQ chip as described above are implemented.

[0031] In order to further understand the present invention, the following Figure 1 and Figure 2 The accelerated time-domain-frequency-domain conversion method based on the ZYNQ chip provided by the present invention is described in detail.

[0032] like Figure 1 and Figure 2 As shown, according to a specific embodiment of the present invention, a method for accelerating time-domain and frequency-domain conversion based on ZYNQ is provided, which is suitable for atomic magnetic detectors whose core chips use ZYNQ chips to perform time-domain and frequency-domain conversion operations in signal processing processes such as frequency domain filtering. This method uses a ZYNQ chip that integrates a high-performance ARM Cortex-A9 processor and programmable logic resources to replace the traditional method of using only DSP chips or single-chip microcomputers to achieve time-domain and frequency-domain conversion. Under the premise of ensuring the accuracy of calculations, the calculation pressure of the CPU is greatly reduced, the hardware complexity is reduced, and the calculation speed and data processing flexibility are improved to meet the engineering application requirements of atomic magnetic detectors.

[0033] The ZYNQ-based accelerated time-domain-frequency-domain conversion method provided by the present invention includes a hardware time-domain-frequency-domain conversion structure design and a frequency-domain complex multiplication operation control state machine. The time-domain-frequency-domain conversion control and operation based on a DSP chip or a single-chip microcomputer are cancelled, and the time-domain-frequency-domain conversion control and operation based on a ZYNQ chip are used to complete the time-domain-frequency-domain conversion control and operation, thereby realizing operation acceleration.

[0034] (1) The overall structure of the time domain and frequency domain acceleration computing unit.

[0035] In the time domain and frequency domain acceleration operation unit, the (I)FFT IP core is controlled by the complex multiplication operation control state machine to realize the Fourier transform of the time domain signal and the inverse Fourier transform of the frequency domain signal, and an adder, a subtractor and four multipliers are controlled to realize the complex multiplication operation of the frequency domain signal and the filter coefficient in the ROM core. The channel conversion switch MUX is controlled by the ARM core on the PS side of the ZYNQ chip to change the signal transmission direction. The specific process is as follows:

[0036] 1. The 32-bit time domain signal stored in the DDR chip is transferred to the PL end of the ZYNQ chip through the DMA module, and enters the (I)FFT IP core through the channel conversion switch MUX. The frequency domain output result is obtained through the 8192-point FFT operation in the IP core;

[0037] 2. The frequency domain signal enters the complex multiplication module. In the module, the 32-bit data is truncated into two 16-bit data, and the frequency domain signal is multiplied by the filter coefficient in the ROM IP core to obtain the filtered result. The complex multiplication result is cached in the FIFO through the state machine control;

[0038] 3. The frequency domain signal after complex multiplication is read out from FIFO, and then transmitted through the channel conversion switch MUX to the (I)FFT IP core for inverse Fourier transform and converted into a time domain signal;

[0039] 4. The converted time domain signal is controlled by the state machine and cached in the FIFO. The time domain signal is transferred by DMA through the channel conversion switch MUX and stored in the DDR chip, ready for the next signal processing.

[0040] (2) The time domain and frequency domain acceleration operation unit operation process state machine.

[0041] In the process of time-domain frequency-domain conversion and complex multiplication, the complex multiplication control state machine plays a very important role. Through the state switching of this module, the FIFO is controlled to write data and cache; the frequency domain signal after the complex multiplication operation is read from the FIFO; the DMA is controlled to carry out data transfer; and the (I)FFT IP core is controlled to perform fast Fourier transform or inverse fast Fourier transform.

[0042] In the complex multiplication operation, if two complex numbers are set to be a+bi and c+di respectively, the result of multiplying the two complex numbers is (ac-bd)+(ad+bc)i. In this system, since the 32-bit data stored in the DDR is a complex signal containing the I phase and the Q phase, the lower 16-bit data is equivalent to the real part, i.e. a or c, and the upper 16-bit data is equivalent to the imaginary part, i.e. b or d. The complex multiplication operation module inputs the upper 16-bit imaginary part signal and the lower 16-bit real part signal intercepted from the 32-bit data, and obtains the 33-bit real part result and imaginary part result through complex multiplication operation. The high bit of the imaginary part result is intercepted and merged into a 32-bit signal and stored in the FIFO.

[0043] The process of controlling the state machine is mainly divided into 4 states. The specific jump process is as follows:

[0044] 1. FFT_START state: Waiting for the FFT start command. After receiving the start command, the FFT operation of the IP core is started, and the FIFO write channel is opened to cache the frequency domain results after the complex multiplication.

[0045] 2. WAIT_FFT_DONE state: Waiting for FFT completion interrupt. When the completion interrupt is received, the FIFO read channel is opened to read the frequency domain multiplication signal in the FIFO; the IFFT operation of the IP core is opened to convert the frequency domain signal into the time domain signal through the IFFT operation and cache it in the FIFO.

[0046] 3. WAIT_IFFT_LOAD state: Waiting for the instruction to complete the reading of the frequency domain multiplication result in FIFO. After the FIFO reading is completed, stop inputting signals to the (I)FFT IP core.

[0047] 4. WAIT_IFFT_DONE state: Waiting for IFFT completion interrupt. After receiving the completion interrupt, the complex multiplication control module generates an interrupt to start DMA, and transfers the time domain filtering results in FIFO to the DDR chip for subsequent algorithm operations.

[0048] The beneficial effects of the present invention compared with the prior art are as follows:

[0049] A ZYNQ-based accelerated time-domain and frequency-domain conversion method is implemented. This method uses the ZYNQ chip that integrates a high-performance ARMCortex-A9 processor and programmable logic resources to replace the traditional DSP chip or single-chip microcomputer to achieve time-domain and frequency-domain conversion. Under the premise of ensuring the accuracy of calculation, the CPU's calculation pressure is greatly reduced, the hardware complexity is reduced, and the calculation speed and data processing flexibility are improved to meet the engineering application requirements of atomic magnetometers.

[0050] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used here to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.

[0051] In addition, it should be noted that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. If not otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of the present invention.

[0052] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for accelerating time-domain to frequency-domain conversion based on a ZYNQ chip, characterized in that: The accelerated time-domain-frequency-domain conversion method based on the ZYNQ chip includes: The 32-bit time domain signal stored in the DDR chip is transferred to the PL end of the ZYNQ chip through the DMAIP core, and enters the (I)FFT IP core through the channel conversion switch MUX. The (I)FFT IP core outputs the frequency domain signal through Fourier FFT transformation; Performing a complex multiplication operation on the frequency domain signal and the filter coefficient in the ROM IP core to obtain a complex multiplication result, and caching the complex multiplication result in a FIFO under the control of a complex multiplication operation control state machine; The frequency domain signal after the complex multiplication operation is read out from the FIFO, and is transmitted again through the channel conversion switch MUX to enter the (I)FFT IP core for inverse Fourier transform IFFT to be converted into a time domain signal; The converted time domain signal is cached in the FIFO under the control of the complex multiplication operation control state machine, completing the accelerated time domain and frequency domain conversion based on the ZYNQ chip.

2. The accelerated time-domain-frequency-domain conversion method based on the ZYNQ chip according to claim 1 is characterized in that: In the complex multiplication operation, if two complex numbers are set to be a+bi and c+di respectively, the result of multiplying the two complex numbers is (ac-bd)+(ad+bc)i. Since the 32-bit data stored in the DDR chip is a complex signal containing the I phase and the Q phase, the lower 16-bit data is equivalent to the real part, i.e. a or c, and the upper 16-bit data is equivalent to the imaginary part, i.e. b or d. The high 16-bit imaginary part signal and the low 16-bit real part signal intercepted from the 32-bit data are used as the input of the complex multiplication operation. After the complex multiplication operation, the 33-bit real part result and imaginary part result are obtained. The high 16 bits of the imaginary part result and the real part result are intercepted and merged into a 32-bit signal and stored in the FIFO.

3. The accelerated time-domain-frequency-domain conversion method based on the ZYNQ chip according to claim 1 is characterized in that: The FIFO process is mainly divided into 4 states, and the specific jump process is as follows: FFT_START state: Waiting for the FFT start command. After receiving the start command, the Fourier FFT operation of the DMAIP core is started, and the FIFO write channel is opened to cache the frequency domain result after the complex multiplication. WAIT_FFT_DONE state: Wait for the FFT completion interrupt. When the completion interrupt is received, the FIFO read channel is opened to read the frequency domain multiplication signal in the FIFO; the IFFT operation of the DMAIP core is opened to convert the frequency domain signal into the time domain signal through the IFFT operation and cache it in the FIFO; WAIT_IFFT_LOAD state: Waiting for the instruction to complete the reading of the frequency domain multiplication result in FIFO. After the FIFO reading is completed, stop inputting signals to the (I)FFT IP core; WAIT_IFFT_DONE state: Waiting for the IFFT completion interrupt. After receiving the completion interrupt, the complex multiplication operation control state machine generates an interrupt to start the DMAIP core, and transfers the time domain filtering results in the FIFO to the DDR chip to prepare for subsequent algorithm operations.

4. An accelerated time-domain-frequency-domain conversion system based on a ZYNQ chip, characterized in that: The ZYNQ chip-based accelerated time-domain and frequency-domain conversion system uses the ZYNQ chip-based accelerated time-domain and frequency-domain conversion method as claimed in claims 1 to 3 to perform accelerated time-domain and frequency-domain conversion.

5. The accelerated time-domain-frequency-domain conversion system based on the ZYNQ chip according to claim 4 is characterized in that: The accelerated time-domain-frequency-domain conversion system based on the ZYNQ chip includes a DMAIP core, a channel conversion switch MUX, a (I)FFT IP core, a ROMIP core, a complex multiplication operation module, a complex multiplication operation control state machine and a FIFO. The 32-bit time domain signal stored in the DDR chip is transferred to the PL end of the ZYNQ chip through the DMAIP core, enters the (I)FFT IP core through the channel conversion switch MUX, and outputs the frequency domain signal through Fourier FFT transformation in the (I)FFT IP core; the frequency domain signal and the filter coefficient in the ROM IP core are complex multiplied in the complex multiplication operation module to obtain a complex multiplication result, and the complex multiplication result is cached in the FIFO under the control of the complex multiplication operation control state machine; the frequency domain signal after the complex multiplication operation is read out from the FIFO, and is transmitted again through the channel conversion switch MUX to enter the (I)FFT The IP core performs an inverse Fourier IFFT transform and converts it into a time domain signal; under the control of the complex multiplication operation control state machine, the converted time domain signal is cached in the FIFO to complete the accelerated time domain and frequency domain conversion based on the ZYNQ chip.

6. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: The processor executes the computer program to implement the steps of the accelerated time-domain to frequency-domain conversion method based on the ZYNQ chip as described in claims 1 to 3.

7. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the accelerated time-domain to frequency-domain conversion method based on the ZYNQ chip as described in claims 1 to 3 are implemented.

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