Dormancy and wake-up method and device for multi-core isomorphic chip system and medium

Abstract

The invention discloses a sleep and wake-up method and device of a multi-core isomorphic chip system and a medium, the system comprises a main core and at least one sub-core, and the main core and the sub-core are provided with corresponding synchronous registers. The method comprises the steps that the main core sends a dormancy instruction, and the main core and the sub-core make dormancy preparation. When dormancy is prepared, if a task execution instruction is received, the main core configures a register of the main core into a parameter value representing dormancy stopping, sends an awakening instruction to the sub-core and makes awakening preparation. After the sub-core receives the wake-up instruction, dormancy is interrupted, wake-up preparation is made, and a register of the sub-core is configured to be a second parameter value representing non-dormancy. And after confirming that the sub-core register is the second parameter value, the main core assigns the own register to the second parameter value, and the system enters an awakening state. According to the embodiment of the invention, sleep wake-up state synchronization among multiple cores can be ensured, and abnormity caused by asynchronous states of the multiple cores is avoided.

Description

Technical Field

[0001] The embodiments of the present application relate to, but are not limited to, the field of signal processing technology, and in particular to a sleep and wake-up method, device, and medium for a multi-core homogeneous chip system. Background Art

[0002] In order to improve the read and write performance of devices, storage device manufacturers gradually use multi-core solutions instead of single-core solutions. However, while the multi-core solution brings performance improvement, it also introduces a series of problems that need to be solved urgently. Among them, the inter-core synchronization problem has become a key factor restricting the performance and stability of multi-core systems. In multi-core embedded storage application scenarios, there is usually one CPU core responsible for processing the storage device protocol, and another core processes the flash memory management algorithm and the flash memory underlying driver. Because different cores undertake different tasks, the working status and processing rhythm of each core are different during the operation of the system. If inter-core synchronization cannot be effectively achieved, it is very easy for multiple CPU states to be out of sync. This asynchrony will cause a series of abnormal events, such as data read and write errors, system response delays, and even system crashes, which seriously affect the reliability and stability of the storage system. At the same time, how to achieve fast wake-up after the multi-core system enters the dormant state is also an important challenge currently faced. The fast wake-up function is crucial to improving the user experience and response speed of the device, but the existing technical means are difficult to balance power consumption control and inter-core synchronization while ensuring fast wake-up, and cannot meet the needs of actual applications.

[0003] Therefore, how to effectively achieve inter-core synchronization and ensure fast wake-up in a multi-core system has become an urgent problem to be solved. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The embodiments of the present application provide a sleep and wake-up method, device and medium for a multi-core homogeneous chip system, which can ensure the synchronization of sleep and wake-up states between multiple cores, and effectively prevent abnormal situations caused by asynchrony of multi-core states.

[0006] In the first aspect, an embodiment of the present application provides a sleep and wake-up method for a multi-core homogeneous chip system, wherein the multi-core homogeneous chip system includes a main core and at least one sub-core, the main core is provided with a main synchronization register, and the sub-core is provided with a sub-synchronization register, and the method includes: the main core sends a sleep instruction to the sub-core, and the sub-core and the main core perform sleep preparation work; during the process of the sub-core and the main core performing sleep preparation work, when receiving an execution task instruction, the main core configures the main synchronization register to a first parameter value, sends a wake-up instruction to the sub-core, and performs wake-up preparation work; the sub-core receives the wake-up instruction, interrupts sleep and performs wake-up preparation work, and configures the sub-synchronization register to a second parameter value; when the main core confirms that the sub-synchronization register is configured as the second parameter value, the main core configures the main synchronization register to the second parameter value, and the system enters a wake-up state; wherein, the main synchronization register is configured as the first parameter value to indicate that the main core is in a stopped sleep state, and the sub-synchronization register is configured as the second parameter value to indicate that the sub-core is in a non-sleep state; the main synchronization register is configured as the second parameter value to indicate that the main core is in a non-sleep state.

[0007] In one embodiment of the present application, during the process of the sub-core performing sleep preparation work, the method includes: if the sub-core confirms that the main synchronization register is configured as the second parameter value or the third parameter value, the sub-core continues to perform the sleep preparation work, and when the sleep preparation work is completed, the sub-core configures the sub-synchronization register to the third parameter value; wherein, the sub-synchronization register is configured as the third parameter value to indicate that the sub-core is in a sleep state.

[0008] In one embodiment of the present application, during the process of the sub-core performing sleep preparation work, the method also includes: when the sub-core confirms that the main synchronization register is configured as the first parameter value, the sub-core performs wake-up preparation work and configures the sub-synchronization register to the second parameter value, and the sub-core exits the sleep state.

[0009] In one embodiment of the present application, during the process of the sub-core performing sleep preparation work, the method further includes: when the sleep preparation work is not completed, the sub-core queries the parameter value of the main synchronization register; when the parameter value of the main synchronization register is configured to the second parameter value or the third parameter value, the sub-core continues to perform the sleep preparation work.

[0010] In one embodiment of the present application, during the process of the main core performing sleep preparation work, the method includes: when the sleep preparation work is completed, querying the parameter value of the sub-synchronization register; when confirming that the parameter value of the sub-synchronization register is the third parameter value, the main core configures the main synchronization register to the third parameter value; the main synchronization register is configured to the third parameter value to indicate that the main core is in a sleep state.

[0011] In an embodiment of the present application, when the main core is in a sleep state, when the main core receives an instruction, the main core interrupts the sleep state and executes the instruction.

[0012] In one embodiment of the present application, the main core executes the instruction, including: if the instruction is an instruction to enter sleep mode, the main core enters the sleep state again; if the instruction is an execution task instruction, the main core configures the main synchronization register to a first parameter value, sends a wake-up instruction to the sub-core, and performs wake-up preparations at the same time.

[0013] In one embodiment of the present application, the main core queries the parameter value of the sub-synchronization register by periodic query, or when the sub-core updates the parameter value of the sub-synchronization register, the main core receives the update message sent by the sub-core, and configures the parameter value of the main synchronization register accordingly according to the update message.

[0014] On the other hand, an embodiment of the present application provides a computer device, which includes a processor, a memory, and a computer program stored in the memory and executable by the processor, wherein when the computer program is executed by the processor, the sleep and wake-up method of the multi-core homogeneous chip system as described above is implemented.

[0015] On the other hand, an embodiment of the present application provides a computer-readable storage medium, which stores a program executable by a processor. When the program executable by the processor is executed by the processor, it is used to execute the sleep and wake-up method of the multi-core homogeneous chip system as described above.

[0016] The embodiment of the present application provides a method for sleeping and waking up a multi-core homogeneous chip system, in which the main core sends a sleep instruction to the sub-core, and then the sub-core and the main core synchronously carry out sleep preparation work. During the sleep preparation, if the execution task instruction is received, the main core will configure the main synchronization register to the first parameter value representing that it is in the stop sleep state. Then, the main core sends a wake-up instruction to the sub-core and starts the relevant wake-up preparation work. After receiving the wake-up instruction, the sub-core immediately interrupts the sleep operation, starts the wake-up preparation work, and configures the sub-synchronization register to the second parameter value representing that it is in the non-sleep state. When the main core confirms that the sub-synchronization register has been configured as the second parameter value, the main core will also configure the main synchronization register to the second parameter value representing that it is in the non-sleep state. At this point, the system officially enters the wake-up state and can execute the received task normally. The embodiment of the present application can ensure the synchronization of the sleep and wake-up states between the multi-cores with the help of the synchronization register and the configured parameter value, for example, to ensure that the main core exits sleep after the sub-core exits sleep, so as to prevent abnormal situations caused by the asynchronous state of the multi-core. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a flowchart of a sleep and wake-up method for a multi-core homogeneous chip system provided in an embodiment of the present application; Figure 2 This is a flowchart of the main core performing sleep preparation work provided by an embodiment of the present application; Figure 3 This is an overall flowchart of sleep and wake-up of a system provided by an embodiment of the present application. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0019] It should be noted that, although the logical order is shown in the flowchart, in some cases, the steps shown or described can be performed in a different order from that in the flowchart. The terms "first", "second", etc. in the specification, claims and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions that can be implemented in this application, so they have no technical substantive significance. Any modification of the structure, change of the proportional relationship or adjustment of the size, without affecting the effects that can be produced by this application and the purposes that can be achieved, should still fall within the scope of the technical content disclosed in this application. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" quoted in this specification are only for the convenience of narration, and are not used to limit the scope of implementation of this application. The change or adjustment of the relative relationship should also be regarded as the scope of implementation of this application without substantial change of the technical content.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0021] In order to improve the read and write performance of devices, storage device manufacturers gradually use multi-core solutions instead of single-core solutions. However, while the multi-core solution brings performance improvement, it also introduces a series of problems that need to be solved urgently. Among them, the inter-core synchronization problem has become a key factor restricting the performance and stability of multi-core systems. In multi-core embedded storage application scenarios, there is usually one CPU core responsible for processing the storage device protocol, and another core processes the flash memory management algorithm and the flash memory underlying driver. Because different cores undertake different tasks, the working status and processing rhythm of each core are different during the operation of the system. If inter-core synchronization cannot be effectively achieved, it is very easy for multiple CPU states to be out of sync. This asynchrony will cause a series of abnormal events, such as data read and write errors, system response delays, and even system crashes, which seriously affect the reliability and stability of the storage system. At the same time, how to achieve fast wake-up after the multi-core system enters the dormant state is also an important challenge currently faced. The fast wake-up function is crucial to improving the user experience and response speed of the device, but the existing technical means are difficult to balance power consumption control and inter-core synchronization while ensuring fast wake-up, and cannot meet the needs of actual applications.

[0022] Therefore, how to effectively achieve inter-core synchronization and ensure fast wake-up in a multi-core system has become a key issue that needs to be solved urgently.

[0023] In view of this, the embodiment of the present application provides a sleep and wake-up method of a multi-core homogeneous chip system, a computer device and a computer-readable storage medium. The multi-core homogeneous chip system includes a main core and at least one sub-core, the main core is provided with a corresponding main synchronization register, and the sub-core is provided with a corresponding sub-synchronization register. The embodiment of the present application mainly achieves inter-core synchronization by configuring the register parameter value. The specific method is as follows: the main core sends a sleep instruction to the sub-core, and then the sub-core and the main core synchronously carry out sleep preparation work. During the sleep preparation, if an execution task instruction (such as a task instruction sent by the host) is received, the main core will configure the main synchronization register to a first parameter value representing that it is in a stop sleep state. Then, the main core sends a wake-up instruction to the sub-core and starts related wake-up preparation work. After receiving the wake-up instruction, the sub-core immediately interrupts the sleep operation, starts the wake-up preparation work, and configures the sub-synchronization register to a second parameter value representing that it is in a non-sleep state. When the main core confirms that the sub-synchronization register has been configured as the second parameter value, the main core will also configure the main synchronization register to the second parameter value representing that it is in a non-sleep state. At this point, the system officially enters the wake-up state and can execute the received task normally. The embodiment of the present application can ensure the synchronization of sleep and wake-up states among multiple cores with the help of synchronization registers and configured parameter values. For example, it can ensure that the main core exits sleep after the sub-core exits sleep, so as to prevent abnormal situations caused by asynchrony of multi-core states.

[0024] The embodiments of the present application are further described below in conjunction with the accompanying drawings.

[0025] Reference Figure 1 , Figure 1 It is a flowchart of the sleep and wake-up method of the multi-core homogeneous chip system provided in the embodiment of the present application. The flowchart mainly describes the complete process of the multi-core homogeneous chip system from entering sleep preparation to being awakened by receiving a task instruction during the sleep preparation process. The whole process revolves around the interaction between the main core and the sub-core, and the configuration of the main synchronization register and the sub-synchronization register. Through these operations, inter-core synchronization is achieved to ensure that the system can respond to tasks stably and efficiently. The process may specifically include but is not limited to steps 110 to 140.

[0026] Step 110: the main core sends a sleep instruction to the sub-core, and the sub-core and the main core prepare for sleep; Step 120: When the sub-core and the main core are performing sleep preparation work, upon receiving the task execution instruction, the main core configures the main synchronization register to the first parameter value, sends a wake-up instruction to the sub-core, and performs wake-up preparation work; Step 130: the sub-core receives the wake-up instruction, interrupts the sleep state, performs wake-up preparation, and configures the sub-synchronization register to the second parameter value; Step 140: When the main core confirms that the sub-synchronization register is configured as the second parameter value, the main core configures the main synchronization register as the second parameter value, and the system enters the awake state.

[0027] Steps 110 to 140 are described in detail below.

[0028] It is understandable that under the architecture of a multi-core homogeneous chip system, the main core that undertakes the core scheduling and task processing responsibilities specializes in running the front-end protocol code. Its core function is to receive and efficiently process various tasks initiated by the host. At the same time, the main core is also responsible for the management of some peripheral modules. When the system enters sleep mode, the main core can turn off these peripheral modules to achieve the effect of reducing power consumption. The sub-core runs the back-end flash management code. When entering sleep mode, the sub-core is mainly responsible for turning off the hardware modules related to the flash memory to reduce power consumption. The main core is mainly responsible for the processing of front-end protocol transactions, so it can perceive the host's operation behavior on the device at the first time. Therefore, the system's sleep and wake-up operations are initiated by the main core.

[0029] In a feasible embodiment, in a multi-core system, the sub-synchronization register and the main synchronization register are used to indicate the current sleep state of the sub-core and the main core, respectively. They can be configured accordingly according to the sleep state of the corresponding core. Specifically, the main synchronization register can be configured with three different parameter values, each parameter value corresponding to a specific sleep state of the main core: the first parameter value represents that the main core is in a stopped sleep state, that is, the main core is ready to resume work from sleep; the second parameter value represents that the main core is in a non-sleep state, at which time the main core may be in the following two situations: one is that it is executing various tasks normally, such as performing data calculations, processing requests from external devices, etc.; the other is that it is in a waiting or idle state, that is, the current task has been completed and is waiting for a new task to be assigned, or waiting for specific external conditions to be met (such as waiting for the coordination signal of other cores, the data transmission completion signal of peripherals, etc.), and there is no actual task execution operation during this period. The third parameter value represents that the main core is in a sleep state (that is, it is completely in a sleep state) to reduce power consumption. Similarly, the sub-synchronization register can also be configured with three parameter values, and the sub-core status represented by the parameter value corresponds to the main core status one by one: the first parameter value indicates that the sub-core is in a stopped sleep state; the second parameter value indicates that the sub-core is in a non-sleep state; the third parameter value indicates that the sub-core is in a sleep state. Through this configuration method, the system can clearly and accurately grasp the sleep state of the main core and sub-core, thereby achieving efficient inter-core synchronization and management.

[0030] In a feasible embodiment, in an actual usage scenario, when configuring the parameters of the main synchronization register and the sub-synchronization register, corresponding state characteristic values ​​can be written to these registers. These state characteristic values ​​are the parameter values ​​mentioned above. Specifically, the main synchronization register and the sub-synchronization register have three parameter value configurations. The state characteristic value corresponding to the first parameter value can be set to PM_STOP; the state characteristic value corresponding to the second parameter value can be set to PM_NONE; the state characteristic value corresponding to the third parameter value can be set to PM_FINISH. Through such a state characteristic value configuration, the different states of the main core and the sub-core can be accurately indicated.

[0031] In a feasible embodiment, in step 110, when the system determines that it needs to enter a sleep state (i.e., a low power consumption state), the main core can act as the initiator to start the entire sleep process. Specifically, if the main core does not obtain a command from the host within a preset time (e.g., 20 milliseconds), the main core will send a sleep instruction to the sub-core through the inter-core communication module to inform the sub-core that the system is about to enter a sleep state. After receiving the sleep instruction, the sub-core can carry out sleep preparations. At the same time, the main core itself will also carry out corresponding sleep preparations. These preparations may include saving the current working state, shutting down some unnecessary modules or functions, etc., in order to minimize power consumption after entering the sleep state.

[0032] In a feasible embodiment, in step 120, during the process of the main core and the sub-core preparing for sleep, if the system receives an execution task instruction (such as a task instruction sent by the host), the wake-up process will be triggered. Specifically, when the main core senses the signal that needs to wake up the system, the main core configures the main synchronization register to the first parameter value, indicating that it is in a stop sleep state, and sends a wake-up instruction to the sub-core, notifying the sub-core that the system needs to wake up immediately to execute a new task. While sending the wake-up instruction, the main core starts its own wake-up preparation work, such as reopening the peripheral module.

[0033] In a feasible embodiment, in step 130, after the sub-core receives the wake-up instruction sent by the main core, it immediately triggers interrupt sleep and exits the wait for interrupt (WFI) mode, wherein the WFI mode enables the system core to enter a low power consumption state, and can be awakened by an interrupt signal, and restore the closed modules, which may include turning on flash memory related hardware modules, etc., to ensure that new tasks can be responded to quickly. After restoring the relevant hardware modules, the sub-core exits the sleep process and configures the sub-synchronization register to a second parameter value, which is used to characterize that the sub-core is in a non-sleep state. By configuring the sub-synchronization register, the sub-core feeds back its own status information to the main core so that the main core can perform subsequent synchronization operations.

[0034] In a feasible embodiment, in step 140, the main core can continuously monitor the value of the sub-synchronous register. When it is confirmed that the sub-synchronous register has been configured as the second parameter value, it means that the sub-core has completed the wake-up preparation and is in a non-sleep state. At this time, the main core can also configure the main synchronization register as the second parameter value. This step realizes the synchronization of the main core and the sub-core state, ensuring that both cores are in a non-sleep state and the state is consistent. When the main core completes the configuration of the main synchronization register, the entire system officially enters the awakened state and can start to execute the received task normally.

[0035] In a feasible embodiment, in order to keep synchronization with the state of the sub-core, the main core can query the parameter value of the sub-synchronization register in the following two ways: on the one hand, the main core can periodically query the parameter value of the sub-synchronization register according to a preset fixed period. The preset period can be flexibly adjusted according to the actual needs and performance requirements of the system to ensure that the sub-core status information is obtained within a suitable time interval. On the other hand, when the sub-core updates the parameter value of the sub-synchronization register, it can actively send a message containing the updated parameter value to the main core. After receiving this message, the main core can immediately configure the main synchronization register according to the parameter value in the message. Through these two methods, the main core can obtain the status information of the sub-core in a timely and accurate manner, thereby ensuring that the status of the main core and the sub-core is always consistent.

[0036] In a feasible embodiment, while the sub-core is performing sleep preparation work, the sub-core may also continuously monitor the configuration status of the main synchronization register. If the sub-core confirms that the main synchronization register is configured as the second parameter value (indicating that the main core is in a non-sleep state but has not initiated a wake-up operation) or the third parameter value (meaning that the main core has entered a sleep state), the sub-core will continue to advance the sleep preparation work. When the sub-core completes all sleep preparations, it will configure its own sub-synchronization register to the third parameter value. The sub-synchronization register is configured as the third parameter value, which means that the sub-core has entered a sleep state. It can be further understood that when the sub-synchronization register presents the third parameter value, the sub-core immediately enters the wait for interrupt (WFI) mode and successfully switches to a low power state to reduce energy consumption.

[0037] It is worth noting that in this embodiment, before the system core enters the waiting interrupt mode, the module clock of the system can be turned off first to reduce unnecessary clock signal consumption. The WFI mode allows the system core to enter a low power consumption state and can be awakened by an interrupt signal. Among them, the module clock is the part that provides the clock signal for a single or a group of specific modules. Turning it off will only stop the module related to the clock, while other parts of the system that do not rely on the module clock can still operate normally. It should be noted that, considering the differences in hardware design, the system may have many different types of sleep modes. Different sleep modes correspond to different wake-up mechanisms. For example, some sleep modes may require specific hardware signals to wake up, while others may be triggered by software instructions to wake up. However, no matter what sleep and wake-up mode is adopted, the management method for realizing fast sleep wake-up and fast mode transition embodied in this embodiment is universal and consistent, and can be effectively applied under various hardware designs.

[0038] In a feasible embodiment, during the sleep preparation of the sub-core, once the sub-core confirms that the main synchronization register is configured as the first parameter value, the sub-core immediately stops the sleep preparation and performs the wake-up preparation, including restoring the closed module, etc. At the same time, the sub-core configures the sub-synchronization register to the second parameter value, thereby indicating that it has exited the sleep state. On the contrary, if the sub-core detects that the parameter value of the main synchronization register is configured as the second parameter value or the third parameter value, the sub-core continues to perform the sleep preparation until the sleep preparation is completed.

[0039] In a possible embodiment, if Figure 2 As shown, when the main core is performing sleep preparation, the working process may include but is not limited to steps 210 to 220.

[0040] Step 210: When the sleep preparation work is completed, query the parameter value of the sub-synchronization register; Step 220: When confirming that the parameter value of the sub-synchronization register is the third parameter value, the main core configures the main synchronization register to the third parameter value, wherein the main synchronization register is configured to the third parameter value to indicate that the main core is in a dormant state.

[0041] In a feasible embodiment, in step 210, the main core can continuously monitor whether there are new task instructions during the process of preparing for sleep. The task instructions here can come from outside the system (such as instructions sent by the host end), or they can be specific task requirements generated inside the system. If there are no new task instructions, the main core will continue to prepare for sleep. When the sleep preparation is completed, such as closing unnecessary modules or functions, the main core can query the parameter value of the sub-synchronous register to understand the current state of the sub-core.

[0042] In a feasible embodiment, in step 220, after the main core queries the parameter value of the sub-synchronization register, it will make a judgment. If it is confirmed that the parameter value of the sub-synchronization register is the third parameter value, according to the previous setting, the third parameter value indicates that the sub-core is in a dormant state. This means that the sub-core has completed the sleep preparation work and entered the dormant state, and the main core can enter the dormant state at this time. It is worth noting that when the main core confirms that the sub-core is in a dormant state (that is, the parameter value of the sub-synchronization register is the third parameter value), the main core can immediately configure its own main synchronization register to the third parameter value. In this way, the main core indicates to other parts of the system that it has also entered a dormant state. This ensures that the state of each core in the entire multi-core system is synchronized, avoiding system anomalies caused by inconsistent states.

[0043] In a feasible embodiment, when the main core is in a dormant state, if an instruction is received, the main core will immediately interrupt the dormant state and execute the corresponding instruction. The process of the main core executing the instruction is as follows: If the instruction received is an instruction to enter the dormant state, the main core will enter the dormant state again after the current instruction is executed. If the instruction received is an execution task instruction, the main core first configures the main synchronization register to the first parameter value. Then, the main core sends a wake-up instruction to the sub-core through the inter-core communication module to notify the sub-core to prepare to resume work. At the same time, the main core itself performs wake-up preparations, such as reinitializing related hardware modules, restoring the previously saved working state, loading necessary data required for task execution, etc., to ensure that the task can be responded to quickly.

[0044] See also Figure 3 , Figure 3 This is a flowchart of the overall sleep and wake-up of a system provided by an embodiment of the present application. In the figure, CPU0 refers to the main core, and CPU1 refers to the sub-core.

[0045] The whole process is as follows: If CPU0 does not receive a command from the HOST within a preset time, it can send a sleep instruction to CPU1 through the inter-core communication module to notify it to prepare for sleep.

[0046] CPU0 side operation After CPU0 notifies CPU1 to start sleeping, it also starts preparations for sleeping. During this period, CPU0 will continue to check whether there are any tasks sent by the HOST (i.e., the host): No task: If there is no task, CPU0 will shut down other peripheral modules one by one (such as non-protocol control modules, non-flash memory control modules, etc.). After completing the preparations before sleep, CPU0 will wait for CPU1 to complete sleep, which is specifically manifested by waiting for the status characteristic value in the synchronization register of CPU1 to be set to PM_FINISH. When CPU1 is detected to enter WFI mode, CPU0 also enters WFI mode.

[0047] Task situation: If there is a task sent by the HOST, CPU0 will set the state characteristic value in its own synchronization register to PM_STOP, which indicates that CPU0 stops sleeping. Then, CPU0 sends a wake-up instruction to CPU1 through the inter-core communication module, causing CPU1 to trigger an interrupt and then exit WFI mode, thus exiting the sleep state. Subsequently, CPU0 restores the closed modules and waits for CPU1 to exit the sleep process, that is, waits for the state characteristic value in CPU1's synchronization register to be set to PM_NONE. When CPU1 completes the exit sleep operation, CPU0 also sets its own state characteristic value to PM_NONE. At this time, the system completely exits sleep and can start executing the task sent by the HOST.

[0048] CPU1 side operation After receiving the sleep command from CPU0, CPU1 starts to prepare for sleep and continues to query the status characteristic value in the current CPU0 synchronization register: CPU0 has not exited the sleep process: If CPU0 has not exited the sleep process (that is, the state characteristic value of CPU0 is not PM_STOP), CPU1 will shut down the modules related to flash memory control one by one. After completing the preparations before sleep, the state characteristic value in its own synchronization register is set to PM_FINISH, and then enter the sleep state.

[0049] CPU0 exits the sleep process: When CPU1 finds that the state characteristic value of CPU0 has changed to PM_STOP, if CPU1 has not completed sleep and entered the sleep state at this time, it will immediately stop the sleep preparation; if CPU1 is already in sleep mode, when receiving the wake-up command sent by CPU0, CPU1 will trigger an interrupt and then exit the WFI mode. Subsequently, CPU1 will restore each module that was previously shut down for sleep in turn. After completing the module restoration work, CPU1 will set the state characteristic value in its own synchronization register to PM_NONE. Through this series of operations, CPU1 successfully exits the sleep process, re-enters the normal working state, and is ready to respond to subsequent tasks.

[0050] It should be noted that this embodiment has no restriction on the number of sub-cores. The system may include two, three or even more sub-cores, and each sub-core is equipped with a corresponding sub-synchronization register. Regardless of the number of sub-cores, inter-core synchronization can be achieved through the parameter configuration between its own sub-synchronization register and the main synchronization register of the main core. This synchronization mechanism is universal and will not fail due to changes in the number of sub-cores. For example, when the system includes a main core and two sub-cores, the main core and the two sub-cores follow the same inter-core synchronization rules. After the main core sends a sleep or wake-up instruction, the two sub-cores perform corresponding sleep or wake-up operations according to the parameter configuration of their own sub-synchronization registers. At the same time, the main core monitors the sub-synchronization register parameter values ​​of the two sub-cores to ensure that the states of all cores remain consistent, thereby achieving stable operation of the entire system.

[0051] An embodiment of the present application also discloses a computer device, wherein the computer device includes a processor, a memory, and a computer program stored in the memory and executable by the processor, wherein when the computer program is executed by the processor, the sleep and wake-up method of the multi-core homogeneous chip system as described above is implemented.

[0052] An embodiment of the present application also discloses a computer-readable storage medium, which stores a program executable by a processor. When the program executable by the processor is executed by the processor, it is used to perform the sleep and wake-up method of the multi-core homogeneous chip system as mentioned above.

[0053] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A sleep and wake-up method for a multi-core homogeneous chip system, characterized in that: The multi-core homogeneous chip system includes a main core and at least one sub-core, the main core is provided with a main synchronization register, and the sub-core is provided with a sub-synchronization register, and the method includes: The main core sends a sleep instruction to the sub-core, and the sub-core and the main core perform sleep preparation work; During the process of the sub-core and the main core performing sleep preparation work, when receiving an execution task instruction, the main core configures the main synchronization register to a first parameter value, sends a wake-up instruction to the sub-core, and performs wake-up preparation work; The sub-core receives the wake-up instruction, interrupts the sleep state and performs wake-up preparation, and configures the sub-synchronization register to a second parameter value; When the main core confirms that the sub-synchronization register is configured as the second parameter value, the main core configures the main synchronization register as the second parameter value, and the system enters a wake-up state; Among them, the main synchronization register is configured with the first parameter value to indicate that the main core is in a stopped sleep state, and the sub-synchronization register is configured with the second parameter value to indicate that the sub-core is in a non-sleep state; the main synchronization register is configured with the second parameter value to indicate that the main core is in a non-sleep state.

2. The sleep and wake-up method of a multi-core homogeneous chip system according to claim 1, characterized in that: During the process of the sub-core performing the sleep preparation work, the method includes: If the sub-core confirms that the main synchronization register is configured as the second parameter value or the third parameter value, the sub-core continues the sleep preparation work, and when the sleep preparation work is completed, the sub-core configures the sub-synchronization register as the third parameter value; The sub-synchronization register is configured as the third parameter value to represent that the sub-core is in a dormant state.

3. The sleep and wake-up method of a multi-core homogeneous chip system according to claim 2, characterized in that: During the process of the sub-core performing the sleep preparation work, the method further includes: When the sub-core confirms that the main synchronization register is configured as the first parameter value, the sub-core performs wake-up preparation, configures the sub-synchronization register as the second parameter value, and the sub-core exits the sleep state.

4. The sleep and wake-up method of a multi-core homogeneous chip system according to claim 2, characterized in that: During the process of the sub-core performing the sleep preparation work, the method further includes: In the case where the sleep preparation work is not completed, the sub-core queries the parameter value of the main synchronization register; When the parameter value of the master synchronization register is configured as the second parameter value or the third parameter value, the sub-core continues the sleep preparation work.

5. The sleep and wake-up method of a multi-core homogeneous chip system according to claim 2, characterized in that: During the process of the main core performing sleep preparation work, the method includes: When the sleep preparation work is completed, querying the parameter value of the sub-synchronization register; When confirming that the parameter value of the sub-synchronization register is the third parameter value, the main core configures the main synchronization register to the third parameter value; The master synchronization register is configured such that the third parameter value indicates that the master core is in a sleep state.

6. The sleep and wake-up method of a multi-core homogeneous chip system according to claim 4, characterized in that: In the case that the main core is in a sleep state, when the main core receives an instruction, the main core interrupts the sleep state and executes the instruction.

7. The sleep and wake-up method of a multi-core homogeneous chip system according to claim 6, characterized in that: The main core executes the instruction, including: If the instruction is a sleep state instruction, the main core enters the sleep state again; If the instruction is the execution task instruction, the main core configures the main synchronization register to the first parameter value, sends a wake-up instruction to the sub-core, and performs wake-up preparation work at the same time.

8. The method according to any one of claims 1 to 7, characterized in that: The main core queries the parameter value of the sub-synchronous register by periodic query, or when the sub-core updates the parameter value of the sub-synchronous register, the main core receives the update message sent by the sub-core and configures the parameter value of the main synchronous register accordingly according to the update message.

9. A computer device comprising a processor, a memory, and a computer program stored in the memory and executable by the processor, characterized in that: When the computer program is executed by the processor, the sleep and wake-up method of the multi-core homogeneous chip system as described in any one of claims 1 to 8 is implemented.

10. A computer-readable storage medium storing a program executable by a processor, characterized in that: The processor-executable program is used to execute the sleep and wake-up method of the multi-core homogeneous chip system as described in any one of claims 1 to 8 when executed by the processor.

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