Memory resource dynamic allocation method and device, electronic equipment and storage medium

Abstract

One or more embodiments of the invention provide a memory resource dynamic allocation method and device, electronic equipment and a storage medium. The method comprises the following steps: acquiring memory behavior characteristic data, wherein the memory behavior characteristic data reflects behavior characteristics of a system or a process in the aspect of memory use; encoding the memory behavior characteristic data to obtain a state code of the memory behavior characteristic data; dynamically selecting a target prediction model according to an actual memory use operation at a historical moment, the actual memory use operation representing information which is generated after a memory allocation strategy at the historical moment is executed and reflects a strategy effect and a system state; obtaining a memory allocation strategy according to the state code and the target prediction model; and dynamically allocating memory resources according to the memory allocation strategy. According to the invention, the memory can be reasonably allocated, the resource utilization rate is effectively improved, and the cost and energy consumption are reduced.

Description

Technical Field

[0001] One or more embodiments of the present disclosure relate to the field of communication technology, and in particular, to a method, device, electronic device, and storage medium for dynamically allocating memory resources. Background Art

[0002] As the process of industrial automation continues to advance, industrial control terminals such as load control terminals and other edge controllers play an extremely critical role in the industrial production system. They are widely used in various industrial scenarios, from precision manufacturing production lines to complex industrial monitoring systems, which are inseparable from the stable operation of these terminal devices. Since industrial control terminals need to operate continuously in harsh environments with high real-time performance and strong stability, their memory management has become a core factor affecting device performance and system reliability.

[0003] The complexity of industrial scenario loads has brought unprecedented challenges to memory management. On the one hand, the operation of the production line has obvious periodicity, just like a precision clock running at a fixed beat, and the operating load of the equipment changes with the production process. On the other hand, tasks such as equipment anomaly detection are sudden, and urgent demands are made on memory resources without any warning. This load characteristic of periodicity and suddenness makes a single prediction model limited in the actual application of memory management. Summary of the invention

[0004] In view of this, an object of one or more embodiments of the present disclosure is to provide a method, device, electronic device and storage medium for dynamically allocating memory resources to solve the problems of the background technology.

[0005] Based on the above objectives, one or more embodiments of the present disclosure provide a method for dynamically allocating memory resources, including: Acquire memory behavior characteristic data, wherein the memory behavior characteristic data reflects the behavior characteristics of the system or process in terms of memory usage; Encoding the memory behavior characteristic data to obtain a state code of the memory behavior characteristic data; Dynamically select a target prediction model based on actual memory usage operations at historical moments, where the actual memory usage operations represent information reflecting policy effects and system status generated after the memory allocation strategy at the historical moment is executed; Obtaining a memory allocation strategy according to the state code and the target prediction model; According to the memory allocation strategy, memory resources are dynamically allocated; Among them, according to the actual memory usage operation at the historical moment, the target prediction model is dynamically selected, including: Get the memory allocation strategy of the historical moment and the actual memory usage operation of the corresponding historical moment; Obtaining an evaluation result of the memory allocation strategy at the historical moment according to the memory allocation strategy at the historical moment and the actual memory usage operation at the historical moment, wherein the evaluation result reflects a prediction error of the memory allocation strategy; In response to the evaluation result satisfying a preset condition, selecting a first prediction model as a target prediction model, wherein the first prediction model is used to cope with periodic tasks; In response to the evaluation result not satisfying a preset condition, a second prediction model is selected as a target prediction model, and the second prediction model is used to cope with sudden tasks.

[0006] Optionally, in response to determining that the target prediction model is the first prediction model, obtaining a memory allocation strategy according to the state code and the target prediction model includes: The state code is input into the first prediction model to obtain a memory allocation strategy output by the first prediction model; wherein the first prediction model is a long short-term memory network model that takes a time series consisting of a state code at the current moment and a state code at a historical moment as input and takes a memory allocation strategy as output.

[0007] Optionally, in response to determining that the target prediction model is the second prediction model, obtaining a memory allocation strategy according to the state code and the target prediction model includes: Obtaining a state transition probability matrix at a current moment, wherein the state transition probability matrix is ​​determined according to the memory behavior characteristic data; The state code and the state transition probability matrix are input into the second prediction model to obtain the memory allocation strategy output by the second prediction model; wherein the second prediction model is a Markov chain model with the current state code and the state transition probability matrix as input and the memory allocation strategy as output.

[0008] Optionally, obtaining an evaluation result of the memory allocation strategy at the historical moment according to the memory allocation strategy at the historical moment and the actual memory usage operation at the historical moment includes: quantifying the memory allocation strategy at the historical moment into the predicted memory usage operation at the historical moment, wherein the predicted memory usage operation includes a predicted memory request action, a memory release action, and a memory fragmentation cleanup action; Calculating the mean absolute error between the actual memory usage operation at the historical moment and the predicted memory usage operation at the historical moment, the actual memory usage operation including the actual memory request action, memory release action and memory fragment cleanup action; The mean absolute error is taken as the evaluation result.

[0009] Optionally, it also includes: The memory allocation efficiency corresponding to the memory allocation strategy is determined according to at least one indicator of memory fragmentation rate, allocation delay and pre-allocation waste; According to the memory allocation efficiency, update the value of the state-action pair, wherein the value of the state-action pair represents the long-term value of evaluating a certain action in a specific state; The prediction model is guided to select a candidate memory allocation strategy according to the value of the state-action pair.

[0010] Optionally, the memory allocation strategy includes: For predicted memory requests whose predicted request amount is less than or equal to a preset threshold, directing them to the two-stage separation adapter allocator; For predicted memory requests whose predicted request amount is greater than a preset threshold, the system is used to directly manage them.

[0011] Optionally, the dynamically allocating memory resources according to the memory allocation strategy includes: Determine the memory allocation amount of each process in the memory allocation strategy, and the memory margin corresponding to each process; In response to a ratio of the memory allocation amount to the memory margin of any process being greater than a preset threshold, the allocation action of the process in the memory allocation strategy is deleted.

[0012] Based on the same inventive concept, one or more embodiments of the present disclosure further provide a memory resource dynamic allocation device, including: An acquisition module is configured to acquire memory behavior characteristic data, wherein the memory behavior characteristic data reflects the behavior characteristics of a system or a process in terms of memory usage; An encoding module, configured to encode the memory behavior characteristic data to obtain a state code of the memory behavior characteristic data; A model selection module is configured to dynamically select a target prediction model according to actual memory usage operations at historical moments, wherein the actual memory usage operations represent information reflecting policy effects and system status generated after the memory allocation policy at the historical moment is executed; A generation module is configured to obtain a memory allocation strategy according to the state code and the target prediction model; an allocation module, configured to dynamically allocate memory resources according to the memory allocation strategy; Among them, according to the actual memory usage operation at the historical moment, the target prediction model is dynamically selected, including: Get the memory allocation strategy of the historical moment and the actual memory usage operation of the corresponding historical moment; Obtaining an evaluation result of the memory allocation strategy at the historical moment according to the memory allocation strategy at the historical moment and the actual memory usage operation at the historical moment, wherein the evaluation result reflects a prediction error of the memory allocation strategy; In response to the evaluation result satisfying a preset condition, selecting a first prediction model as a target prediction model, wherein the first prediction model is used to cope with periodic tasks; In response to the evaluation result not satisfying a preset condition, a second prediction model is selected as a target prediction model, and the second prediction model is used to cope with sudden tasks.

[0013] Based on the same inventive concept, one or more embodiments of the present disclosure also provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, a method for dynamically allocating memory resources as described in any one of the above is implemented.

[0014] Based on the same inventive concept, one or more embodiments of the present disclosure further provide a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to enable the computer to execute any of the above-mentioned methods for dynamically allocating memory resources.

[0015] From the above, it can be seen that the method for dynamic allocation of memory resources provided by one or more embodiments of the present disclosure first obtains memory behavior feature data reflecting the memory usage behavior characteristics of the system or process and encodes it to obtain a state code; then, the memory allocation strategy at the historical moment is evaluated according to the memory allocation strategy at the historical moment and its corresponding actual memory usage operation (that is, the information reflecting the policy effect and the system status after the policy is executed) to obtain an evaluation result reflecting the prediction error; then, the target prediction model is dynamically selected based on the evaluation result. If the evaluation result meets the preset conditions, the first prediction model for coping with periodic tasks is selected. If not, the second prediction model for coping with sudden tasks is selected, and then the memory allocation strategy is obtained by combining the state code and the target prediction model; finally, memory resources are dynamically allocated based on the strategy.

[0016] The implementation of the present disclosure can adapt to the load characteristics of complex industrial control terminals, and can overcome the limitations of a single model by dynamically selecting a prediction model to cope with different load conditions. In addition, the implementation of the present disclosure is based on the memory behavior feature data encoding and the historical memory allocation operation evaluation results, making the memory allocation decision more scientific and reasonable. Through the present disclosure, memory can be reasonably allocated, effectively improving resource utilization, and reducing costs and energy consumption.

[0017] The memory resource dynamic allocation device, electronic device and computer-readable storage medium provided by the present disclosure can all implement the steps of the above-mentioned memory resource dynamic allocation method, and therefore also have the beneficial effects of the above-mentioned memory resource dynamic allocation method. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate one or more embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only one or more embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A flowchart of a method for dynamically allocating memory resources according to one or more embodiments of the present disclosure; Figure 2 A schematic diagram of a process for dynamically selecting a target prediction model according to one or more embodiments of the present disclosure; Figure 3 A schematic diagram of the structure of a memory resource dynamic allocation device according to one or more embodiments of the present disclosure; Figure 4 A schematic diagram of the hardware structure of an electronic device according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0020] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0021] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in one or more embodiments of the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in one or more embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0022] refer to Figure 1 The method for dynamically allocating memory resources in one or more embodiments of the present disclosure includes the following steps: Step S101: Acquire memory behavior characteristic data, where the memory behavior characteristic data reflects the behavior characteristics of a system or process in terms of memory usage; Step S102: Encode the memory behavior characteristic data to obtain a state code of the memory behavior characteristic data; Step S103: dynamically selecting a target prediction model according to actual memory usage operations at historical moments, where the actual memory usage operations represent information reflecting the policy effect and system status generated after the memory allocation strategy at the historical moment is executed; Step S104: obtaining a memory allocation strategy according to the state code and the target prediction model; Step S105: dynamically allocate memory resources according to the above memory allocation strategy; Among them, Figure 2 As shown in the figure, the target prediction model is dynamically selected based on the actual memory usage operation at the historical moment, including: Step S201: Obtain the memory allocation strategy of the historical moment and the actual memory usage operation of the corresponding historical moment; Step S201: obtaining an evaluation result of the memory allocation strategy at the historical moment according to the memory allocation strategy at the historical moment and the actual memory usage operation at the historical moment, wherein the evaluation result reflects a prediction error of the memory allocation strategy; Step S203: In response to the evaluation result satisfying a preset condition, selecting a first prediction model as a target prediction model, wherein the first prediction model is used to cope with periodic tasks; Step S204: In response to the above evaluation result not satisfying the preset condition, a second prediction model is selected as the target prediction model, and the above second prediction model is used to cope with sudden tasks.

[0023] In the implementation of the present disclosure, the above-mentioned memory behavior characteristics may include one or more of memory usage behavior characteristics, process attribute characteristics, resource constraint characteristics and memory access efficiency characteristics.

[0024] Among them, the above-mentioned memory usage behavior characteristics can reflect the dynamic pattern and granularity characteristics of memory usage; the above-mentioned process attribute characteristics can reflect the priority attributes of the process in the system scheduling and other characteristics; the above-mentioned resource constraint characteristics can reflect the system's hard constraints on process memory usage; the above-mentioned memory access efficiency characteristics can reflect the locality of memory access and system memory pressure.

[0025] In the embodiments of the present disclosure, a dynamic detection mechanism (such as kprobe) can be used to inject monitoring probes into a memory mapping mechanism function (such as a do_mmap function) and a memory mapping release mechanism function (such as a do_munmap function) to capture the process virtual memory area (Virtual Memory Area, VMA) application sequence, thereby obtaining dynamic pattern characteristics reflecting memory usage; the requested memory of 16-2048 bytes can also be divided into a preset number of intervals (such as 32) according to a logarithmic scale, and the low-frequency intervals can be dynamically merged according to the threshold adjusted by the configuration file path (such as / proc / sys / vm / mdp_bucket_merge) used to adjust the memory request interval merging threshold in the system virtual memory, so as to obtain the granularity characteristics of memory usage. The above-mentioned dynamic pattern characteristics and granularity characteristics of memory usage can be regarded as memory usage behavior characteristics.

[0026] In an embodiment of the present disclosure, the static priority (static_prio) and the control group memory limit (memory.low) can also be extracted from the task structure (task_struct) to obtain the priority attributes of the process in the system scheduling and the hard constraints of the system on the process memory usage as process attribute characteristics and resource constraint characteristics.

[0027] In the embodiments of the present disclosure, the historical page fault rate can also be obtained by collecting performance monitoring unit (PMU) events through the perf_event_open function, so as to understand the efficiency of process memory access and system memory pressure and obtain memory access efficiency characteristics.

[0028] Although the preferred embodiments of obtaining memory behavior characteristic data of the present invention are disclosed as above, they are not intended to limit the present invention. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the claims.

[0029] In order to facilitate the calculation of the prediction model, the implementation of the present disclosure also needs to encode the memory behavior feature data. The original memory behavior feature data often presents high-dimensional, complex and diverse format characteristics. Directly inputting the prediction model will not only increase the computational burden, but may also make it difficult for the model to effectively learn and extract key information. Through encoding, these raw data can be converted into a more regular, low-dimensional and semantically clear form, thereby significantly improving the efficiency and accuracy of the prediction model in processing data.

[0030] In the embodiments of the present disclosure, a fast hash algorithm may be used to generate a state code of a preset length (eg, an 8-bit state code).

[0031] In the implementation of the present disclosure, the above state code can also be obtained and stored in a preset location. For example, the above state code can be stored in a radix tree (radix_tree) to provide real-time input for the prediction model.

[0032] The key part of the technical solution disclosed in the present invention is to dynamically select the target prediction model according to the actual memory usage operation at the historical moment.

[0033] As mentioned above, the load of industrial scenarios presents significant complexity. On the one hand, production line operation tasks have periodic characteristics, and their memory requirements will change regularly with the cycle of the production process; on the other hand, tasks such as equipment anomaly detection are sudden, and such tasks often generate urgent and unpredictable demands for memory resources when they occur.

[0034] In related technologies, a single prediction model is usually used to allocate memory resources in industrial scenarios. However, this approach has obvious limitations, because there is currently no prediction model that can properly deal with the periodic and sudden characteristics of industrial scenario loads at the same time, making it difficult for memory resource allocation to meet actual needs, and easily leading to problems such as unreasonable memory allocation, waste or insufficient resources, etc.

[0035] In the implementation of the present disclosure, the target prediction model is dynamically selected based on the actual memory usage operation at the historical moment. Specifically, the memory allocation strategy adopted at the historical moment is evaluated based on the actual memory usage operation at the historical moment, so as to clarify the actual usage effect of the prediction model selected at that moment, and then determine the prediction model to be selected in this round.

[0036] Given that the prediction model of the present disclosure needs to handle two different types of loads, periodic tasks and burst tasks, the prediction model settings will also be performed separately according to these two characteristics. That is to say, in the implementation of the present disclosure, the selection range of the prediction model covers two models: one is a first prediction model specifically used to deal with periodic tasks, and the other is a second prediction model designed for burst tasks. Through such model settings and dynamic selection mechanisms, it is possible to better adapt to the complex and changeable memory requirements in industrial scenarios and improve the rationality and effectiveness of memory resource allocation.

[0037] In an embodiment of the present disclosure, the first prediction model may be constructed based on a long short-term memory network (LSTM), and the second prediction model may be constructed based on a Markov chain.

[0038] The gating mechanism unique to the LSTM model can effectively handle long-term dependency issues. In periodic tasks, information from past cycles is crucial to predicting future trends. The LSTM model can accurately capture the periodic characteristics of data such as memory usage in periodic tasks. For example, in typical periodic tasks such as industrial production line operation, it can accurately predict the memory requirements for the next cycle based on the memory usage data patterns accumulated over multiple previous cycles.

[0039] The Markov chain model has obvious advantages in dealing with sudden problems. The Markov chain model determines the probability distribution of the next state based only on the current state, without considering the complex historical state sequence, and can respond quickly to sudden situations.

[0040] In an embodiment of the present disclosure, the first prediction model can be deployed in the drivers / misc directory. The lstm_weights.bin weight file in FP16 format is loaded through sysfs (a virtual file system provided by the Linux kernel for data interaction between user space and kernel space) to complete the initialization of the model. In the inference stage, the corresponding instruction set is used for acceleration according to different hardware architectures. If it is an ARM architecture, the kernel_neon_begin / end function is called to enable the NEON instruction set (NEON is the SIMD instruction set of the ARM processor, which can significantly improve the data processing speed) for inference acceleration; if it is an x86 platform, the AVX2 instruction set is used instead (AVX2 is the advanced vector extension instruction set of the Intel processor, which can improve the floating-point operation performance). After the first prediction model completes the inference, the prediction result is stored in current->mdp_prediction (here current usually represents the structure of the current process, and mdp_prediction is a member variable in the structure used to store the prediction result) for subsequent pre-allocation decisions.

[0041] Specifically, in the technical solution disclosed in the present invention, a dynamic prediction device / dev / predict_ctrl can be constructed based on the character device framework, providing a basic device interface for the prediction function of the system, using a ring buffer to efficiently manage the input timing data, and using DMA-coherent memory to ensure that alignment can be maintained when using NEON or AVX instructions for data access, thereby improving the efficiency of data processing. In addition, a weight loading interface file / sys / class / misc / predict / load_weights can be defined to facilitate users to load the weights required for the model. In order to support concurrent prediction requests, a multi-producer single-consumer mode can also be implemented through kfifo, so that multiple requests can be processed in an orderly manner.

[0042] The FP16 weight loading subsystem undertakes the important task of processing weight files. First, it developed a binary parser to parse the weight file header, which contains key information such as the number of layers, dimensions, and quantization flags. In terms of weight data conversion, SIMD accelerated conversion from FP16 to FP32 is implemented. Different conversion instructions are used for different hardware platforms: under the ARMv8.2 architecture, the vcvt_f32_f16 instruction is used (CONFIG_ARM64_FP16 needs to be enabled); on the x86 platform, the vcvtph2ps instruction is used in conjunction with the AVX512-FP16 extension. For weight memory, the CMA pre-allocated pool is used for management, and device mapping is established through dma_map_single to ensure that the device can access the weight data efficiently.

[0043] The heterogeneous computing acceleration layer fully utilizes the advantages of different hardware architectures and provides optimized kernels for ARM and x86 platforms. On the ARM platform, the lstm_neon_kernel function is the core acceleration module. It uses the kernel_neon_begin() and kernel_neon_end() functions to turn on and off the use of the NEON instruction set, and uses assembly instructions such as VMLA.F16 inside the function to complete the SIMD implementation of LSTM Cell. On the x86 platform, the lstm_avx2_kernel function is the core of the optimization. It uses the kernel_fpu_begin() and kernel_fpu_end() functions to manage the FPU state, and uses AVX2 instruction-level expansion calculations such as _mm256_fmadd_ps to improve the performance of LSTM calculations. These optimization measures enable the system to achieve efficient computing in different hardware environments.

[0044] In the embodiment of the present disclosure, the construction and initialization of the state transfer matrix of the second prediction model can be achieved through the following steps: calling the kernel initialization function through module_init to construct a sparse state transfer matrix in CSR format. The probability of each state transition of the matrix is ​​initialized to 1 / N+1e-5 (where N is the total number of states and 1e-5 is the Laplace smoothing factor), which not only ensures the initial uniform distribution characteristics, but also avoids the zero probability problem. In terms of memory management, kmalloc_node is used to allocate matrix storage space locally on the NUMA node, and high-frequency transfer rows are preloaded into L3Cache through copy_to_user, and prefetch_range is used to optimize data access locality, significantly reducing the cross-node memory access latency of the industrial control board. It should be noted that this step only initializes the probability distribution of the state transfer matrix and has nothing to do with the initial state vector of the Markov chain (determined by the system runtime state).

[0045] In the embodiment of the present disclosure, data collection is performed by capturing and compressing memory event streams. The specific process may include: inserting tracepoints in the tlsf_malloc and tlsf_free functions to capture state transition events generated by memory allocation and release operations; creating a double-buffered circular queue of 4KB per buffer through relayfs to efficiently store high-frequency memory events in a producer-consumer model; compressing the event into a 4-tuple containing a timestamp, process ID, memory block size, and operation type compressed into 16 bits using Delta encoding by the kworker kernel thread, wherein the timestamp records the offset relative to the reference time, the process ID retains the lower 16 bits of valid data, the memory block size is aligned to 4KB, and the operation type marks allocation or release; the compressed event stream is written to / sys / kernel / debug / mdp_events, and the user-mode program can directly access it through mmap to achieve real-time data acquisition with μs-level delay, and the Delta encoding of the timestamp compresses the storage volume to 1 / 4 of the original value while keeping the timing information intact, reducing the data transmission pressure in the industrial control scenario.

[0046] In the embodiment of the present disclosure, the state feature extraction is obtained in real time through the sliding window statistics, and dynamic data preprocessing is performed, and the time series characteristics of the memory event stream are counted in real time to provide support for the state transition probability calculation. The specific process includes: defining a circular queue with a maintenance capacity of 100 for the struct sliding_window structure, using atomic64_t atomic operations to ensure the atomicity of window count updates in a multi-core environment; implementing incremental calculations of mean and variance based on the Welford algorithm (time complexity O(1)), and storing the results in the mdp_stats field of task_struct; performing LRU elimination on process statistics that have not been updated for more than 1 second, and managing data timeliness through a bidirectional linked list; using the RCU mechanism to ensure the safety of multi-core concurrent reading and writing, the write operation is updated without lock through the synchronization mechanism, and the read operation obtains the latest data without blocking. These statistics (such as the allocation delay mean and fluctuation variance) are the core components of the Markov chain state characteristics, and dynamically track the trend of memory behavior changes through online calculations, providing real-time input for subsequent Bayesian matrix updates. Among them, the recursive calculation characteristics of the Welford algorithm ensure that the statistical results reflect the latest memory behavior patterns while maintaining computational efficiency.

[0047] In the embodiment of the present disclosure, when the model prediction error exceeds the threshold, the optimal path solution is realized by constructing a state transfer matrix and combining the Viterbi algorithm to provide a reliable prediction continuity guarantee for the system. The specific process may include: firstly, constructing a Markov state transfer matrix based on the historical memory event data, and the matrix elements represent the transition probability between states. When the error monitoring system triggers the model switching demand, the Viterbi algorithm is used to perform dynamic programming calculations, and the recursive formula is used to calculate the optimal path. Find the maximum probability path in state k at time t, where Generate observations for state k The probability of emission, Record the path predecessor status. After completing the optimal path calculation, the RCU (Read-Copy Update) mechanism is used to implement atomic model switching, ensuring seamless migration of prediction parameters in a multi-core concurrent environment and avoiding data inconsistency caused by context switching. This mechanism provides a mathematically rigorous fallback solution for the prediction strategy through probabilistic modeling of the state transition matrix and optimal path search of the Viterbi algorithm, effectively coping with the risk of model failure in complex industrial control scenarios.

[0048] In the embodiment of the present disclosure, the state transition probability is dynamically adjusted according to the new observation data, so that the model can better adapt to the real-time changes of the system. The specific process may include: every time 100 new events are received, a matrix update operation will be triggered. First, the number of historical state transitions is exponentially decayed, and the decay coefficient λ is 0.9, that is, counts[i][j]*=0.9 is used to reduce the influence of old data on the current transition probability, reflecting the importance of recent data. At the same time, for the newly observed state transition (s→s'), the corresponding transition count is increased by 0.1, that is, counts[i][j]+=0.1 is executed. Afterwards, in order to obtain a valid state transition probability, the normalization calculation is performed asynchronously through the workqueue, and the formula prob[i][j]=counts[i][j] / sum_counts[i] is used to calculate the probability of each state transition. In this process, in order to ensure the security of the update operation in the interrupt context of the industrial control environment, spin_lock_bh is used to protect the row-level update to avoid data inconsistency caused by concurrent operations, thereby ensuring that the Markov chain model can accurately reflect the current state transition of the system.

[0049] Hereinafter, how to obtain the evaluation result of the memory allocation strategy at a historical moment is described in detail. First, the memory allocation strategy in the implementation of the present disclosure represents a predicted memory allocation scheme, which may include one or more of the memory area, size, time, priority and memory recycling strategy allocated to a specific task or process. These memory allocation strategies reflect predicted memory usage operations, which may include one or more of the memory request actions, memory release actions and memory fragmentation cleanup actions that occur. The memory allocation strategy may be implemented based on the prediction of the memory request for a specific task or process.

[0050] The evaluation result of the memory allocation strategy is determined based on the gap between the actual memory usage operation and the predicted memory allocation strategy. The actual memory usage operation is determined based on the memory request actually generated by the specific task or process.

[0051] According to the average absolute error of the actual memory usage operation and the predicted memory usage operation at the historical moment, the error of the prediction result of the prediction model at the historical moment can be determined. Taking the above error as the evaluation result of the memory allocation strategy can reflect the adaptability of the selected prediction model to the memory usage changes in the current scenario. When the error of the prediction result of the prediction model is small, it can be considered that the selected prediction model can better complete the memory prediction in the current scenario; when the error of the prediction result of the prediction model is large, it can be considered that the selected prediction model can no longer better complete the memory prediction in the current scenario.

[0052] In an embodiment of the present disclosure, when the average absolute error between the actual memory usage operation and the predicted memory usage operation at a historical moment is less than or equal to a preset threshold, it is considered that the first prediction model for periodic tasks can be selected; when the average absolute error is greater than the preset threshold, it can be considered that a sudden task has occurred, and the second prediction model for sudden tasks can be selected.

[0053] In addition to the mean absolute error of the actual memory usage operation and the predicted memory usage operation at the historical moment, the embodiments of the present disclosure may also include other evaluation indicators, such as memory resource utilization, or system performance evaluation indicators such as task execution time and response time. As long as the different evaluation methods can achieve the corresponding purpose, the different methods will not affect the protection scope of the present invention.

[0054] In the embodiments of the present disclosure, a dynamic error monitoring system is used to perform rolling statistics on the absolute errors between the predicted values ​​and the actual observed values. The specific process may include: using the Mean Absolute Error Calculator (MAE) and the error state machine of the three states of NORMAL, WARNING and CRITICAL included in the monitoring system, triggering state migration when the MAE exceeds a preset threshold. In order to prevent false alarms caused by high-frequency noise, jiffies are used to record the abnormal start timestamp, and the state change is confirmed only when the same state lasts for more than 100ms. These error statistics are directly used as the triggering conditions of the Markov backoff mechanism. When the state machine enters the CRITICAL state, the system will start the Viterbi algorithm to perform model switching evaluation to ensure dynamic adjustment of the prediction strategy.

[0055] In addition, in the embodiments of the present disclosure, the kernel-level prediction service integration can also be used to undertake the system-level context management and scheduling coordination functions, and provide kernel-state full-process support for the prediction strategy. The specific implementation may include: extending the mdp_prediction structure in the process control block task_struct, and defining a joint data domain containing the prediction mode (LSTM_MODE / MARKOV_MODE) and the corresponding context. By registering the scheduler notifier, the prediction parameters are automatically injected when the process switches to ensure that the context of the LSTM model or Markov chain model is bound to the task state. In addition, the system creates the / proc / mdp_stats interface through debugfs to expose key indicators such as prediction error and model switching frequency in real time. This mechanism realizes the deep coupling of prediction services and kernel scheduling. When error monitoring triggers Markov fallback, the context switch protected by RCU can ensure the atomic migration of the prediction state. At the same time, the parameter injection during process scheduling ensures the continuity of the prediction, and provides the industrial real-time control system with the model switching capability of μs level response.

[0056] In order to further improve the prediction accuracy of the prediction model disclosed in the present invention, the Q-Learning strategy can also be used to guide the strategy optimization of the prediction model.

[0057] Specifically, in the implementation of the present disclosure, the reward value may be calculated in a preset manner, and the Q value may be updated according to the reward value to guide the prediction model action.

[0058] In an embodiment of the present disclosure, the reward value may be calculated based on the memory fragmentation rate, allocation delay, and pre-allocation waste of executing the memory allocation strategy. In an embodiment of the present disclosure, the above data may be obtained through the perf_event performance monitoring framework.

[0059] In the embodiment of the present disclosure, the calculation formula of the reward value can be defined as: ; in, Indicates the current timestamp, represents the smoothing factor, which can be set to , Indicates the rate of change of memory fragmentation rate, , Indicates the monitoring window, which can be set through / proc / sys / vm / mdp_window. For example, it can be set to 300 milliseconds. Indicates the memory fragmentation rate, , It represents the number of free page blocks of order k in the partner system. The fraction in the formula represents the largest continuous memory block (calculated by the highest non-zero order), and the denominator represents the total number of free pages. The closer the ratio is to 1, the lower the fragmentation rate. Indicates allocation delay, , you can use perf_event to monitor the CPU cycle consumption of memory allocation functions (such as kmalloc), Indicates the CPU main frequency, converted to actual delay time ( ), when the actual delay time decreases, the allocation delay optimization item increases and the reward item value increases. Conversely, the allocation delay optimization item decreases and the reward item value decreases. Indicates the pre-allocated waste amount, , Indicates the memory page size, represents the waste baseline, which can be defined as , which means taking the total system memory The larger of 10% and 64MB is used to prevent excessive penalties on small memory systems.

[0060] In the embodiments of the present disclosure, a weight adaptive mechanism and an emergency state detection mechanism may also be introduced. Specifically, the weight adaptive mechanism may include: when monitoring that the real-time task delay exceeds the limit, the weight of the memory fragmentation rate change item is reduced, and the weight of the allocation delay optimization item is increased. The weight can be transitioned through exponential smoothing. The emergency state detection mechanism includes: when the conditions are met: or When , the reward function is set to .in, represents the amount of fragment mutation, , Indicates the comprehensive reward value.

[0061] In the embodiment of the present disclosure, the update formula of the Q value can be defined as: ; in, represents the learning rate, In the embodiment of the present disclosure, the initial value of the learning rate can be set to 0.1 and dynamically adjusted during the calculation process, and the discount factor can be set to 0.9.

[0062] The encoding formula of the state-action pair can be defined as: ; , , .

[0063] In the embodiments of the present disclosure, the eligibility trace may be used to represent the importance of each state-action pair to the current learning process.

[0064] Qualification The update rule can be defined as: ; Among them, you can set constraints: , and elimination strategy: when When from Removed.

[0065] In the process of updating the state-action pair, the calculation effect can also be improved by setting the following conditions.

[0066] In the embodiment of the present disclosure, the above time can be selected The initial value is set to , and use the timer interval to dynamically adjust the formula for error compensation, . In an embodiment of the present disclosure, a batch update buffer mechanism can be introduced, which can include a kfifo data structure and a batch processing algorithm. Among them, the buffer size of the kfifo data structure can be designed to be N=1024 items. The batch processing algorithm is triggered when the ratio of the number of items in the current buffer to the total buffer size is greater than or equal to a preset threshold (such as 0.8). The principle of the batch processing algorithm can be to use AVX-512 instructions to parallelly calculate the update of 256 Q values.

[0067] In the embodiments of the present disclosure, resource-constrained optimization strategies may also be introduced, which may include low-power consumption mode, interrupt context optimization mechanism and safety degradation mechanism. The low-power consumption mode means that when the system enters the idle state, the timer interval is set to the maximum value of 100 milliseconds and 1.5 times the current timer interval, and the update of the qualification trace is suspended. The interrupt context optimization mechanism may include: the system adopts a Per-CPU copy Q table mechanism, each CPU core maintains an independent local Q table Q_local, and retains a globally unified Q_global table. When multiple CPU cores update Q values ​​at the same time and conflict occurs, a weighted merging strategy is adopted: Q_merged=0.7Q_local+0.3Q_global, that is, 70% of the weight of the local update is retained first, and 30% of the weight of the global table is merged. The safety degradation mechanism may include that when the memory pressure is greater than a preset threshold (such as 80%), the learning rate is updated to half of the current learning rate, the qualification trace attenuation factor is updated to 0.8 times the current qualification trace attenuation factor, and AVX acceleration is turned off, and pure software floating-point calculation is adopted.

[0068] In order to further improve the efficiency of Q value calculation, reduce the query delay of multi-axis control tasks, and enhance the performance and response speed of the system in multi-axis control scenarios, the embodiments of the present disclosure can also be configured from the following aspects.

[0069] Convert Q value floating point operations to Q8.8 fixed point format, using the fixed32 type of linux / fixed_point.h. Fixed point operations are usually faster than floating point operations in hardware processing because they do not need to deal with complex floating point representation and operation rules. In embedded systems or environments with limited computing resources, fixed point operations can significantly reduce computing time. At the same time, SSE / AVX accelerated matrix multiplication is enabled through kernel_fpu_begin / end. These instruction sets can implement single instruction multiple data (SIMD) operations and process multiple data elements in one clock cycle, greatly improving the speed of matrix multiplication operations, thereby accelerating the calculation process of Q value.

[0070] The Q value of the top 20% high-frequency state is pre-calculated and stored in the shared memory / dev / shm / mdp_qtable. Shared memory allows different processes to directly access the same physical memory area, avoiding the overhead of data copying and transmission, and reducing the delay when the multi-axis control task queries the Q value. The physical page is locked by mlock to ensure that these pre-calculated Q value data always resides in the physical memory, avoiding additional delays caused by page swapping (such as paging to disk), and ensuring that the multi-axis control task can quickly obtain the required Q value information.

[0071] In multi-axis control scenarios, it is necessary to quickly and accurately calculate and query the Q value to make decisions. Through the above-mentioned hardware acceleration optimization and shared memory design, the calculation and query of the Q value can be completed in a shorter time, allowing the system to respond to the needs of multi-axis control tasks more quickly, improving the overall performance and stability of the system, especially suitable for industrial control and other fields with high real-time requirements.

[0072] According to the memory allocation strategy obtained in the above steps, memory resources can be dynamically allocated. In the embodiment of the present disclosure, the memory allocation strategy can be based on the following principles: in the Linux kernel of the load control terminal, by deeply integrating the two-level separation adaptation (Two-Level Segregated Fit, TLSF) memory pool and the buddy system (Buddy System), a hierarchical memory management architecture is constructed, and for high-frequency small memory requests (such as sensor data cache) in industrial control scenarios, the allocation request with a request amount less than or equal to a preset threshold (such as 204 bytes) is directed to the TLSF memory pool, and dma_map_single is used to map the TLSF metadata to the Write Combining memory area, and combined with the prefetchw instruction to preload hot data, the x86 industrial computer allocation delay can be measured to be ≤12μs, which meets the real-time requirements of motion control. Among them, the TLSF cache pool construction can be constructed with 256B primary blocks (creating a dedicated Slab cache through kmem_cache_create) and 16B secondary blocks (bitmap management), realizing O(1) time allocation. This strategy can eliminate the delay jitter caused by cache line contention while ensuring data consistency, fully meeting the stringent real-time requirements of industrial terminals for memory access.

[0073] In the embodiments of the present disclosure, the lazy memory commit strategy can also be used to optimize memory usage and ensure stable operation of the system. The specific process may include: first, virtual address space management is performed, and the PROT_NONE virtual address area is created using mmap. When the process first accesses the area, a page fault exception is triggered, and mdp_commit_allocation is called in handle_mm_fault to allocate physical pages. At the same time, the pre-allocation hit rate is updated in the mdp_fault function through vma->vm_ops to achieve on-demand memory allocation to avoid waste. Then, the PSI dynamic adjustment algorithm is adopted, and the PSI trigger is registered to monitor the memory pressure. In the psi_trigger callback function, the pre-allocation intensity is dynamically adjusted according to the memory pressure level, the intensity is reduced when the pressure is high, and the intensity is increased when the pressure is small, and update_allocation_policy is called to update the page allocation policy to prevent memory overload. Finally, through the statistical indicator visualization interface, debugfs is used to expose statistical information. Users can reset information by writing / sys / kernel / debug / mdp / stats_reset and read / sys / kernel / debug / mdp / prealloc_hit_rate to obtain pre-allocation hit rate information such as PID=1123, HitRate=87.5%, PressureLevel=3, etc., which is convenient for monitoring and adjusting system memory usage and ensuring stable and efficient calculation of Markov chain model.

[0074] In the process of executing the memory allocation strategy, in order to further improve the system performance, preprocessing can also be performed before the memory allocation action. Specifically, it may include: First, we use the cgroup memory monitoring subsystem integration to obtain the memory usage information of the process in real time. Using the memory.current interface of cgroup v2, the kernel can accurately read the memory usage of the process. For example, this function can be implemented through the code struct page_counter*counter=&memcg->memory; u64 current_usage=page_counter_read(counter). In user mode, the remaining quota is obtained by calculating the difference between / sys / fs / cgroup / memory.high and / sys / fs / cgroup / memory.current. Based on this, when the preallocated memory prealloc_size of an action exceeds 50% of the remaining quota, the action is removed from the candidate set to avoid memory overflow problems caused by excessive preallocation and ensure the memory safety of the system.

[0075] In addition, the red-black tree action set can also be used to maintain a filtered valid action set. The red-black tree action set defines a struct action_set structure, which contains a red-black tree root node, a spin lock, and a recently used linked list. When inserting actions, the actions are automatically sorted. For example, in the action_insert function, ordered insertion is achieved by comparing actions and adjusting the positions of red-black tree nodes; actions can also be added to the recently used linked list at the same time. The use of spin locks can also ensure the security of action set operations in a multi-core concurrent environment, ensuring data consistency and correctness of operations.

[0076] By designing and optimizing the user-mode interface, we can build an interactive bridge between the kernel and the user-mode, and perform special processing on key processes. The action list is exposed to the user-mode through the custom ioctl command MDP_GET_ACTIONS, and the user-mode can obtain relevant information based on the struct mdp_action_info structure. For key processes such as the PID regulator, the mdp_weight weight parameter can be set. When the process is judged to have a higher priority, its weight will be adjusted dynamically. For example, you can set mdp_weight=clamp(mdp_weight*2,0,MAX_MDP_WEIGHT) and increase the reserved memory pages to ensure the memory quota of key processes and the normal operation of important tasks in the system.

[0077] During system operation, in order to ensure that motion control tasks are performed stably and efficiently, the embodiments of the present disclosure may also adopt the following strategies and mechanisms.

[0078] The first is the dual Q table policy rollback protection mechanism. The system maintains the Active and Shadow dual Q tables. When the average delay is monitored by / proc / mdp_stats to increase by more than 15% for three consecutive times, the atomic_swap operation is used to switch the currently used Q table to the old table to maintain system stability. At the same time, the genetic algorithm optimization thread (kthread_run) is started to perform cross-mutation operations on the Q table parameters. The mutation results will be written to debugfs for offline analysis to ensure that the motion control task will not be interrupted.

[0079] The second is DMA-assisted memory defragmentation. When / proc / buddyinfo shows that the proportion of continuous free page blocks is less than 10%, the system calls dma_engine_alloc to apply for a DMA channel and uses dma_alloc_coherent to copy scattered pages to a continuous area. During this process, the low-priority log process is suspended through the cgroup freezer to ensure that the core control threads (such as the real-time scheduler) continue to run. After the defragmentation is completed, the physical mapping of vm_area_struct is updated.

[0080] Then there is cgroup resource arbitration and recycling. The mdp_weight parameter is extended in the memory controller of cgroup v2, so that high-weight processes (such as motion controllers) can have priority in approving pre-allocation requests in the mem_cgroup_threshold callback. 20% of the memory (memory.reserve) is reserved for key subsystems such as system.slice. When an excess request occurs and is about to trigger OOM, the pre-allocated cache is recycled through the LRU strategy first.

[0081] Finally, full-stack verification and hot upgrade implementation. Use kvm-unit-test to simulate stress-ng memory pressure scenarios and verify that the Slab fragmentation rate drops by at least 50%. Develop the mdpctl user-mode tool to support dynamic adjustment of learning rate, discount factor and other parameters through / sys / module / mdp / parameters. Use the EFICapsule mechanism to implement restart-free hot updates of Q tables and LSTM models to meet the requirements of 7×24 hours of uninterrupted operation in industrial sites.

[0082] It can be understood that the method can be executed by any device, equipment, platform, or device cluster having computing and processing capabilities.

[0083] It should be noted that the method of one or more embodiments of the present disclosure may be performed by a single device, such as a computer or server. The method of this embodiment may also be applied in a distributed scenario and completed by multiple devices cooperating with each other. In the case of such a distributed scenario, one of the multiple devices may only perform one or more steps in the method of one or more embodiments of the present disclosure, and the multiple devices may interact with each other to complete the described method.

[0084] It should be noted that the above is a description of a specific embodiment of the present disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0085] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments and methods, the present disclosure also provides a memory resource dynamic allocation device. Figure 3 As shown, the above device comprises: The acquisition module 11 is configured to acquire memory behavior characteristic data, wherein the memory behavior characteristic data reflects the behavior characteristics of the system or process in terms of memory usage; The encoding module 12 is configured to encode the memory behavior characteristic data to obtain a state code of the memory behavior characteristic data; The model selection module 13 is configured to dynamically select a target prediction model according to actual memory usage operations at historical moments, where the actual memory usage operations represent information reflecting policy effects and system status generated after the memory allocation strategy at the historical moment is executed; A generation module 14 is configured to obtain a memory allocation strategy according to the state encoding and the target prediction model; An allocation module, configured to dynamically allocate memory resources according to the above memory allocation strategy; Among them, according to the actual memory usage operation at the historical moment, the target prediction model is dynamically selected, including: Get the memory allocation strategy of the historical moment and the actual memory usage operation of the corresponding historical moment; According to the memory allocation strategy at the historical moment and the actual memory usage operation at the historical moment, an evaluation result of the memory allocation strategy at the historical moment is obtained, wherein the evaluation result reflects a prediction error of the memory allocation strategy; In response to the evaluation result satisfying a preset condition, selecting a first prediction model as a target prediction model, wherein the first prediction model is used to cope with periodic tasks; In response to the above evaluation result not meeting the preset condition, a second prediction model is selected as the target prediction model, and the above second prediction model is used to cope with sudden tasks.

[0086] For the convenience of description, the above devices are described in terms of functions divided into various modules. Of course, when implementing one or more embodiments of the present disclosure, the functions of each module can be implemented in the same or multiple software and / or hardware.

[0087] The apparatus of the above-mentioned embodiment is used to implement the corresponding method in the above-mentioned embodiment, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.

[0088] Figure 4 A more specific schematic diagram of the hardware structure of an electronic device provided in this embodiment is shown, and the device may include: a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040 are connected to each other through the bus 1050 in the device.

[0089] The processor 1010 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present disclosure.

[0090] The memory 1020 may be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 may store an operating system and other application programs. When the technical solution provided by the embodiment of the present disclosure is implemented by software or firmware, the relevant program code is stored in the memory 1020 and is called and executed by the processor 1010.

[0091] The input / output interface 1030 is used to connect the input / output module to realize information input and output. The input / output module can be configured in the device as a component (not shown in the figure), or it can be externally connected to the device to provide corresponding functions. The input device may include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output device may include a display, a speaker, a vibrator, an indicator light, etc.

[0092] The communication interface 1040 is used to connect a communication module (not shown) to realize communication interaction between the device and other devices. The communication module can realize communication through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0093] The bus 1050 includes a path that transmits information between the various components of the device (eg, the processor 1010 , the memory 1020 , the input / output interface 1030 , and the communication interface 1040 ).

[0094] It should be noted that, although the above device only shows the processor 1010, the memory 1020, the input / output interface 1030, the communication interface 1040 and the bus 1050, in the specific implementation process, the device may also include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the above device may also only include the components necessary for implementing the embodiments of the present disclosure, and does not necessarily include all the components shown in the figure.

[0095] The electronic device of the above embodiment is used to implement the corresponding method in the above embodiment, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.

[0096] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device.

[0097] A person skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples. Based on the concept of the present disclosure, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of different aspects of one or more embodiments of the present disclosure as described above, which are not provided in detail for the sake of simplicity.

[0098] In addition, to simplify the description and discussion, and in order not to make one or more embodiments of the present disclosure difficult to understand, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided figures. In addition, devices may be shown in the form of block diagrams to avoid making one or more embodiments of the present disclosure difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform on which one or more embodiments of the present disclosure will be implemented (that is, these details should be fully within the scope of understanding of those skilled in the art). Where specific details (e.g., circuits) are set forth to describe exemplary embodiments of the present disclosure, it is apparent to those skilled in the art that one or more embodiments of the present disclosure may be implemented without these specific details or with changes in these specific details. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0099] Although the present disclosure has been described in conjunction with specific embodiments of the present disclosure, many alternatives, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the discussed embodiments.

[0100] One or more embodiments of the present disclosure are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A method for dynamically allocating memory resources, characterized in that: include: Acquire memory behavior characteristic data, wherein the memory behavior characteristic data reflects the behavior characteristics of the system or process in terms of memory usage; Encoding the memory behavior characteristic data to obtain a state code of the memory behavior characteristic data; Dynamically select a target prediction model based on actual memory usage operations at historical moments, where the actual memory usage operations represent information reflecting the policy effect and system status generated after the memory allocation policy at the historical moment is executed; Obtaining a memory allocation strategy according to the state code and the target prediction model; According to the memory allocation strategy, memory resources are dynamically allocated; Among them, according to the actual memory usage operation at the historical moment, the target prediction model is dynamically selected, including: Get the memory allocation strategy of the historical moment and the actual memory usage operation of the corresponding historical moment; Obtaining an evaluation result of the memory allocation strategy at the historical moment according to the memory allocation strategy at the historical moment and the actual memory usage operation at the historical moment, wherein the evaluation result reflects a prediction error of the memory allocation strategy; In response to the evaluation result satisfying a preset condition, selecting a first prediction model as a target prediction model, wherein the first prediction model is used to cope with periodic tasks; In response to the evaluation result not satisfying a preset condition, a second prediction model is selected as a target prediction model, and the second prediction model is used to cope with sudden tasks.

2. The method according to claim 1, characterized in that In response to determining that the target prediction model is the first prediction model, obtaining a memory allocation strategy according to the state code and the target prediction model includes: The state code is input into the first prediction model to obtain a memory allocation strategy output by the first prediction model; wherein the first prediction model is a long short-term memory network model that takes a time series consisting of a state code at the current moment and a state code at a historical moment as input and takes a memory allocation strategy as output.

3. The method according to claim 1, characterized in that In response to determining that the target prediction model is the second prediction model, obtaining a memory allocation strategy according to the state code and the target prediction model includes: Obtaining a state transition probability matrix at a current moment, wherein the state transition probability matrix is ​​determined according to the memory behavior characteristic data; The state code and the state transition probability matrix are input into the second prediction model to obtain the memory allocation strategy output by the second prediction model; wherein the second prediction model is a Markov chain model with the current state code and the state transition probability matrix as input and the memory allocation strategy as output.

4. The method according to claim 1, characterized in that: The obtaining, according to the memory allocation strategy at the historical moment and the actual memory usage operation at the historical moment, an evaluation result of the memory allocation strategy at the historical moment comprises: quantifying the memory allocation strategy at the historical moment into the predicted memory usage operation at the historical moment, wherein the predicted memory usage operation includes a predicted memory request action, a memory release action, and a memory fragmentation cleanup action; Calculating the mean absolute error between the actual memory usage operation at the historical moment and the predicted memory usage operation at the historical moment, the actual memory usage operation including the actual memory request action, memory release action and memory fragment cleanup action; The mean absolute error is taken as the evaluation result.

5. The method according to claim 2 or 3, characterized in that: Also includes: The memory allocation efficiency corresponding to the memory allocation strategy is determined according to at least one indicator of memory fragmentation rate, allocation delay and pre-allocation waste; According to the memory allocation efficiency, update the value of the state-action pair, wherein the value of the state-action pair represents the long-term value of evaluating a certain action in a specific state; According to the value of the state-action pair, the prediction model is guided to select a candidate memory allocation strategy.

6. The method according to claim 1, characterized in that The memory allocation strategy includes: For predicted memory requests whose predicted request amount is less than or equal to a preset threshold, directing them to the two-stage separation adapter allocator; For predicted memory requests whose predicted request volume is greater than a preset threshold, the system is used to directly manage them.

7. The method according to claim 6, characterized in that The dynamically allocating memory resources according to the memory allocation strategy includes: Determine the memory allocation amount of each process in the memory allocation strategy, and the memory margin corresponding to each process; In response to a ratio of the memory allocation amount to the memory margin of any process being greater than a preset threshold, the allocation action of the process in the memory allocation strategy is deleted.

8. A memory resource dynamic allocation device, characterized in that: include: An acquisition module is configured to acquire memory behavior characteristic data, wherein the memory behavior characteristic data reflects the behavior characteristics of a system or a process in terms of memory usage; An encoding module, configured to encode the memory behavior characteristic data to obtain a state code of the memory behavior characteristic data; A model selection module is configured to dynamically select a target prediction model according to actual memory usage operations at historical moments, wherein the actual memory usage operations represent information reflecting policy effects and system status generated after the memory allocation policy at the historical moment is executed; A generation module is configured to obtain a memory allocation strategy according to the state code and the target prediction model; an allocation module, configured to dynamically allocate memory resources according to the memory allocation strategy; Among them, according to the actual memory usage operation at the historical moment, the target prediction model is dynamically selected, including: Get the memory allocation strategy of the historical moment and the actual memory usage operation of the corresponding historical moment; Obtaining an evaluation result of the memory allocation strategy at the historical moment according to the memory allocation strategy at the historical moment and the actual memory usage operation at the historical moment, wherein the evaluation result reflects a prediction error of the memory allocation strategy; In response to the evaluation result satisfying a preset condition, selecting a first prediction model as a target prediction model, wherein the first prediction model is used to cope with periodic tasks; In response to the evaluation result not satisfying a preset condition, a second prediction model is selected as a target prediction model, and the second prediction model is used to cope with sudden tasks.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the method according to any one of claims 1 to 7 is implemented.

10. A non-transitory computer-readable storage medium, characterized in that: The non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to cause the computer to execute any one of claims 1 to 7.

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