Chip aging test method, upper computer and aging test device

Abstract

According to the chip aging test method, the upper computer and the aging test device, incremental compiling can be carried out on vector files, and due to the fact that the unmodified vector files are not recompiled, the compiling speed can be increased, and then the aging test speed is increased. The chip aging test method comprises the following steps: calculating a check code list of a to-be-compiled vector file group, and determining a revised vector file and a non-revised vector file from the to-be-compiled vector file group according to a comparison result of a check code list of a first historical vector file group and the check code list of the to-be-compiled vector file group, and compiling the revised vector file into a first target vector file, acquiring a second target vector file corresponding to the non-revised vector file from the second historical vector file group, generating an aging test vector program package according to the first target vector file and the second target vector file, and sending the aging test vector program package to the aging test device.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a chip aging test method, a host computer and an aging test device. Background Art

[0002] During the development and production of chips, chip aging tests are required. Chip aging tests refer to the method of accelerating chip aging and evaluating chip life and durability based on aging test data.

[0003] Currently, there is a chip aging test method including: after the host computer receives the compilation instruction, it compiles a group of atp vector files into a group of bin vector files according to the compilation instruction, and then generates an aging test vector program package according to the group of bin format vector files, and sends the aging test vector program package to the aging test device, which performs an aging test on the aging board loaded with the chip under test.

[0004] In actual applications, the atp vector file is usually modified during the chip debugging phase, and then the entire set of atp vector files is recompiled into a bin vector file, which takes more than tens of minutes to compile. Summary of the invention

[0005] The present application provides a chip aging test method, which can incrementally compile vector files, that is, not recompile unmodified vector files, thereby improving the compilation speed and further improving the test speed.

[0006] A first aspect provides a chip aging test method, the method comprising: after obtaining a vector file group to be compiled, a check code list of a first historical vector file group and a second historical vector file group, calculating the check code list of the vector file group to be compiled; determining a modified vector file and an unchanged vector file from the vector file group to be compiled according to a comparison result of the check code list of the first historical vector file group and the check code list of the vector file group to be compiled, compiling the modified vector file into a first target vector file and obtaining a second target vector file corresponding to the unchanged vector file from the second historical vector file group; generating an aging test vector program package according to the first target vector file and the second target vector file; generating a loading message carrying an identifier of the aging test vector program package and a package check code; and sending the loading message to an aging test device.

[0007] The format of the vector files in the vector file group to be compiled and the first historical vector file group is the first format, and the format of the vector files in the second historical vector file group is the second format. Optionally, the first format is the atp format, and the second format is the bin format. The second historical vector file group is obtained by compiling the first historical vector file group, and the vector files in the first historical vector file group correspond one-to-one to the vector files in the vector file group to be compiled, and the two vector files having the corresponding relationship have the same file name. The check code list of the first historical vector file group includes the check code of each vector file in the first historical vector file group.

[0008] According to this implementation, the modified vector files in the vector file group to be compiled can be identified based on the check code, and they are recompiled, and the unchanged vector files are not recompiled, that is, the incremental compilation method. Compared with the prior art, in which the entire group of vector files is recompiled (i.e., full compilation), the incremental compilation method of the present application can greatly reduce the computational overhead and time overhead of compiling vector files. Moreover, the packet check code carried by the loading message can be used to determine whether the aging test device has stored the aging test vector program package corresponding to the packet check code. In the case where the aging test vector program package corresponding to the packet check code has been stored, the step of loading the aging test vector program package can be skipped, thereby shortening the aging test duration and increasing the aging test speed.

[0009] In a possible implementation, the chip aging test method of the present application further includes: receiving a download package request sent by the aging test device; obtaining a aging test vector package according to the download package request; and sending the aging test vector package to the aging test device. When the package check code included in the loading message is different from the package check code stored in the aging test device, the aging test device will send a download package request, so that the aging test vector package not stored in the aging test device can be loaded.

[0010] In another possible implementation, according to the comparison result of the check code list of the first historical vector file group and the check code list of the vector file group to be compiled, determining the modified vector file and the unchanged vector file from the vector file group to be compiled includes: selecting one check code from the check code list of the vector file group to be compiled in turn as the check code of the vector file to be processed; selecting the historical check code corresponding to the vector file to be processed from the check code list of the first historical vector file group; when the check code of the vector file to be processed and the historical check code corresponding to the vector file to be processed are different, determining that the vector file to be processed is a modified vector file; when the check code of the vector file to be processed and the historical check code corresponding to the vector file to be processed are the same, determining that the vector file to be processed is an unchanged vector file. Optionally, the check code of the vector file to be processed and the historical check code corresponding to the vector file to be processed are both calculated using a hash algorithm for the vector file. Specifically, the hash algorithm can be but is not limited to a message digest algorithm or a secure hash algorithm. In this way, the modified vector file and the unchanged vector file in the vector file group to be processed can be identified.

[0011] The second aspect provides a chip aging test method, which includes: receiving a loading message sent by a host computer, searching for a target packet verification code corresponding to the aging test vector package identifier in a locally stored packet verification code according to the aging test vector package identifier carried in the loading message; when the packet verification code included in the loading message is the same as the target packet verification code, performing a chip aging test according to the locally stored target aging test vector package. The target aging test vector package corresponds to the aging test vector package identifier, and the target packet verification code is the packet verification code of the target aging test vector package.

[0012] When the packet verification code included in the loading message is the same as the target packet verification code, it indicates that the aging test device has stored the target aging test vector program package corresponding to the packet verification code. The step of loading the aging test vector program package can be skipped, and the chip aging test can be performed directly according to the locally stored target aging test vector program package. This can shorten the aging test time and increase the aging test speed.

[0013] In a possible implementation, the chip aging test method of the present application also includes: when the packet check code included in the loading message is different from the target packet check code, sending a download package request to the host computer; receiving the aging test vector program package sent by the host computer; loading the aging test vector program package into an external memory, and performing a chip aging test according to the loaded aging test vector program package. After the host computer modifies the aging test vector package corresponding to the aging test vector package identifier, the packet check code corresponding to the aging test vector package identifier in the aging test device is different from the packet check code included in the loading message, and after judging that the aging test device does not store the modified aging test vector program package according to the packet check code, the modified aging test vector program package and aging test can be loaded from the host computer.

[0014] In a possible implementation, the chip aging test method of the present application also includes: when the locally stored packet verification code does not include the target packet verification code, sending a download package request to the host computer; after the host computer obtains the aging test vector program package according to the download package request, receiving the aging test vector program package sent by the host computer; loading the aging test vector program package into an external memory, and performing a chip aging test according to the loaded aging test vector program package. When the locally stored packet verification code does not include the target packet verification code, it indicates that the aging test device has not loaded the aging test vector program package, and the first loading and aging test can be performed.

[0015] The third aspect provides a host computer, which includes a processing module and a communication interface, the processing module is used to obtain a to-be-compiled vector file group, a check code list of a first historical vector file group and a second historical vector file group; calculate the check code list of the to-be-compiled vector file group; determine the modified vector file and the unchanged vector file from the to-be-compiled vector file group according to the comparison result of the check code list of the first historical vector file group and the check code list of the to-be-compiled vector file group, and compile the modified vector file into a first target vector file; obtain the second target vector file corresponding to the unchanged vector file from the second historical vector file group; generate an aging test vector program package according to the first target vector file and the second target vector file; the communication interface is used to send the aging test vector program package to an aging test device.

[0016] In a possible implementation, the communication interface is also used to receive a download package request sent by the aging test device; the processing module is also used to obtain the aging test vector package according to the download package request; the communication interface is also used to send the packet verification code of the aging test vector package to the aging test device.

[0017] In another possible implementation, the processing module is specifically used to select one check code from the check code list of the vector file group to be compiled in turn as the check code of the vector file to be processed; select a historical check code corresponding to the vector file to be processed from the check code list of the first historical vector file group; when the check code of the vector file to be processed and the historical check code corresponding to the vector file to be processed are different, determine that the vector file to be processed is a modified vector file; when the check code of the vector file to be processed and the historical check code corresponding to the vector file to be processed are the same, determine that the vector file to be processed is an unchanged vector file.

[0018] For the explanation of terms in the third aspect, the steps performed by each module and the beneficial effects, please refer to the corresponding description of the first aspect.

[0019] The fourth aspect provides an aging test device, which includes a communication interface, a processing module and an aging test module; the communication interface is used to receive a loading message sent by a host computer; the processing module is used to search for a target packet verification code corresponding to an aging test vector package identifier in a locally stored packet verification code; the aging test module is used to perform a chip aging test on the chip according to a locally stored target aging test vector package when the packet verification code included in the loading message is the same as the target packet verification code.

[0020] In a possible implementation, the communication interface is also used to send a download package request to the host computer when the packet check code included in the loading message is different from the target packet check code or the locally stored packet check code does not include the target packet check code; receive the aging test vector program package sent by the host computer; the processing module is also used to send the aging test vector program package sent by the host computer to the aging test module; the aging test module is also used to load the aging test vector program package sent by the processing module into an external memory; and perform chip aging test on the chip according to the loaded aging test vector program package.

[0021] In another possible implementation, the aging test device also includes a physical layer chip, which is connected to the processing module via SGMII, and the physical layer chip is connected to the aging test module via RGMII; the processing module is specifically used to send the received aging test vector program package to the physical layer chip via SGMII; the physical layer chip is used to send the aging test vector program package sent by the processing module to the aging test module via RGMII.

[0022] In another possible implementation, the processing module is connected to the aging test module via SGMII; the processing module is specifically configured to send the received aging test vector program package to the aging test module via SGMII.

[0023] In another possible implementation, the processing module is connected to the aging test module via RGMII, and the processing module is specifically configured to send the received aging test vector program package to the aging test module via RGMII.

[0024] In combination with any possible implementation of the fourth aspect, in another possible implementation, the aging test module includes an FPGA and multiple CPLDs; the FPGA is used to load the aging test vector program package sent by the processor module into an external memory; the FPGA is also used to read multiple vector data of the aging test vector program package from the external memory, and send the multiple vector data to multiple CPLDs respectively; the CPLD is used to perform chip aging test on the chip according to the vector data sent by the FPGA.

[0025] In any possible implementation manner of the fourth aspect, the aging test module is an FPGA.

[0026] In any possible implementation manner of the fourth aspect, the aging test device further includes a connected power supply board and a adapter board, and the power supply board includes a power supply module for supplying power to the aging test device and the aging board.

[0027] For the explanation of terms in the fourth aspect, the steps performed by each module and the beneficial effects, please refer to the corresponding description of the second aspect.

[0028] A fifth aspect provides a computing device, comprising a processor and a memory, wherein the processor is used to execute instructions stored in the memory so that the computing device executes the method described in the first aspect or any possible implementation of the first aspect.

[0029] A sixth aspect provides a computing device, comprising a processor and a memory, wherein the processor is used to execute instructions stored in the memory so that the computing device executes the method described in the second aspect or any possible implementation of the second aspect.

[0030] A seventh aspect provides a computer-readable storage medium storing a computer program. When the computer program is executed by a computing device, the computing device executes the method described in the first aspect or any possible implementation of the first aspect.

[0031] An eighth aspect provides a computer-readable storage medium storing a computer program. When the computer program is executed by a computing device, the computing device executes the method described in the second aspect or any possible implementation of the second aspect.

[0032] A ninth aspect provides a computer program product comprising instructions, which, when executed by a computing device, causes the computing device to execute the method described in the first aspect or any possible implementation of the first aspect.

[0033] The tenth aspect provides a computer program product comprising instructions, which, when executed by a computing device, causes the computing device to execute the method described in the second aspect or any possible implementation of the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A schematic diagram of a chip testing system in an embodiment of the present application;

[0035] Figure 2 Another schematic diagram of a chip testing system in an embodiment of the present application;

[0036] Figure 3 A schematic diagram of a CPU and an FPGA connected via a local bus in the prior art;

[0037] Figure 4 A schematic diagram showing the connection between the CPU and the FPGA through a physical layer chip in an embodiment of the present application;

[0038] Figure 5 A schematic diagram of the connection between the CPU and the FPGA via the SGMII in an embodiment of the present application;

[0039] Figure 6 A schematic diagram of the CPU and FPGA being connected via RGMII in an embodiment of the present application;

[0040] Figure 7 A schematic diagram of a chip testing system and an aging testing module in an embodiment of the present application;

[0041] Figure 8 A schematic diagram of a chip testing system and a power board in an embodiment of the present application;

[0042] Fig. 9 A flow chart of a chip aging test method in an embodiment of the present application;

[0043] Fig.10 A schematic diagram of a row of a vector file in an embodiment of the present application;

[0044] Fig.11 A schematic diagram of a checksum and recompile mark of a vector file in an embodiment of the present application;

[0045] Fig.12 A schematic diagram of an aging test vector program package in an embodiment of the present application;

[0046] Fig.13 A schematic diagram of loading a message in an embodiment of the present application;

[0047] Fig.14A schematic diagram of the name of the aging test vector program package, the cached packet check code, the received packet check code and the flag bit that needs to be loaded in the embodiment of the present application;

[0048] Fig.15 A flow chart of compiling a vector file in an embodiment of the present application. DETAILED DESCRIPTION

[0049] The chip aging test method of the present application can be applied to a chip test system. Figure 1 In one example, the chip testing system includes a host computer 100 and an aging test device 200. The aging test device 200 includes a main control board 210 and a burn-in board (burn in board, BIB) 220. The host computer 100 can be a personal desktop computer, a server, a portable terminal (such as a tablet computer, a mobile phone), etc. The host computer can be installed with a Windows system, a Unix system, or a Linux system, etc. The host computer 100 is connected to the aging test device 200 via a network cable. The main control board 210 is connected to the burn-in board 220. The burn-in board 220 includes one or more sockets.

[0050] See also Figure 2 In one embodiment, the host computer 100 includes a processing module 110 and a communication interface 120 .

[0051] The processing module 110 may include any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP) or a digital signal processor (DSP). The communication interface 120 uses, but is not limited to, a transceiver module such as a network interface card or a transceiver to realize the communication between the host computer 100 and the aging test device 200. The communication interface 120 may be, but is not limited to, an Ethernet interface, which may be connected to a twisted pair.

[0052] The processing module 110 is used to obtain a check code list of a vector file group to be compiled, a first historical vector file group and a second historical vector file group; calculate the check code list of the vector file group to be compiled; determine the modified vector file and the unchanged vector file from the vector file group to be compiled according to the comparison result of the check code list of the first historical vector file group and the check code list of the vector file group to be compiled; compile the modified vector file into a first target vector file; obtain the second target vector file corresponding to the unchanged vector file from the second historical vector file group; generate an aging test vector program package according to the first target vector file and the second target vector file; the communication interface 120 is used to generate a loading message carrying the identifier of the aging test vector program package and the package check code; and send the loading message to the aging test device 200.

[0053] In an optional embodiment, the processing module 110 is used to receive a download package request sent by the aging test device 200; obtain the aging test vector package according to the download package request; and send the aging test vector package to the aging test device 200. Specifically, the host computer 100 can set a file transfer protocol (FTP) server function, and the FTP server stores the aging test vector package. The aging test device 200 is configured with an FTP client. When the package check code carried by the loading message is different from the package check code stored by the aging test device 200, the FTP client can download the above-mentioned aging test vector package from the FTP server through a Get command. When the package check code carried by the loading message is the same as the package check code stored by the aging test device 200, the aging test device 200 does not load the above-mentioned aging test vector package, thereby avoiding repeated loading of the same aging test vector package.

[0054] In another optional embodiment, the processing module 110 is specifically used to select one check code from the check code list of the vector file group to be compiled as the check code of the vector file to be processed; select a historical check code corresponding to the vector file to be processed from the check code list of the first historical vector file group; when the check code of the vector file to be processed and the historical check code corresponding to the vector file to be processed are different, determine that the vector file to be processed is a modified vector file; when the check code of the vector file to be processed and the historical check code corresponding to the vector file to be processed are the same, determine that the vector file to be processed is an unchanged vector file.

[0055] The processing module 110 can realize the functions of the vector compiling module, the power-on function module, the power-off function module, the vector loading module, and the vector testing module. It should be understood that the vector compiling module, the power-on function module, the power-off function module, the vector loading module, and the vector testing module can be realized by software.

[0056] The vector compilation module is used to compile the vector file in atp format into a vector file in bin format, and to generate the checksum of the vector file in atp format. Before vector compilation, check whether the checksum of the vector file is consistent with the historical checksum corresponding to the vector file. If not, recompile the vector file.

[0057] The power-on function module is used to power on the aging board 220 and the distributed power supply module of the aging board 220 after the chip is put into the furnace and before the aging test, which can be considered as hot-plugging the aging board. The power-off function module is used to power off the aging board 220 and the distributed power supply module of the aging board 220 after the aging test is completed and before the chip is taken out of the furnace. During the chip aging test, placing the chip under test on the socket and pushing the aging board into the cavity of the aging machine to start the aging test is called "entering the furnace". After the aging test is completed, after the power supply system of the aging board and the chip under test is turned off, pulling out the aging board and removing the chip is called "coming out of the furnace". The "coming out of the furnace" and "entering the furnace" operations can be performed multiple times during the chip aging test, and the aging test procedures for the same type of chips are the same.

[0058] The vector loading module is used to send a loading message to the aging test device 200. When the packet check code included in the loading message is consistent with the packet check code stored in the aging test device 200, the aging test vector program package is not loaded. When the two packet check codes are inconsistent, the vector loading module is also used to send the aging test vector program package to the aging test device 200, and the aging test vector program package is loaded by the aging test device 200. The vector test module is used to start the vector test and collect the vector test results. The vector test module of the host computer 100 interacts with the vector test module of the aging test device 200 to automatically complete the chip aging test function.

[0059] It should be noted that the host computer 100 also includes a memory, in which executable program codes are stored, and the processor 110 executes the executable program codes to implement Fig. 9 The steps performed by the host computer in the illustrated embodiment. The present application does not limit the number of processing modules 110 and the number of memories.

[0060] The aging test device 200 includes a main control board 210 , a aging board 220 and a transfer board 230 .

[0061] The main control board 210 includes a communication interface 211, a processing module 212, a temporary storage 213, a centralized power supply module 214, an aging test module 215 and an external storage 216. It should be understood that the aging test device 200 may also include a machine, a cabinet, a power supply system for powering the machine, a heating rod for heating the chip under test, a heat dissipation system (such as a fan and a wind chamber) for dissipating heat from the chip under test, and other functional boards, which can be specifically set according to actual conditions, and this application does not limit it. Among them, the communication interface 211 uses but is not limited to a transceiver module such as a network interface card and a transceiver to realize the communication between the main control board 210 and the host computer 100.

[0062] The communication interface 211 is used to receive the loading message sent by the host computer; the processing module 212 is used to search for the target packet verification code corresponding to the aging test vector package identifier in the locally stored packet verification code; the aging test module 215 is used to perform chip aging test on the chip according to the locally stored target aging test vector package when the packet verification code included in the loading message is the same as the target packet verification code.

[0063] In an optional embodiment, the communication interface 211 is also used to send a download package request to the host computer when the packet verification code included in the loading message is different from the target packet verification code or the locally stored packet verification code does not include the target packet verification code; receive the aging test vector program package sent by the host computer; the processing module 212 is also used to send the aging test vector program package sent by the host computer to the aging test module 215; the aging test module 215 is also used to load the aging test vector program package sent by the processing module 212 into the external memory 216; and perform chip aging test on the chip according to the loaded aging test vector program package.

[0064] The temporary memory 213 may be a double data rate synchronous dynamic random access memory (DDR-SDRAM) or a non-volatile memory (such as a non-volatile flash memory). The temporary memory 213 is connected to the processing module 212 and is used to temporarily store the aging test vector program package and the packet check code.

[0065] The centralized power supply module 214 is used as a DC-DC power supply of the aging test device 200. The centralized power supply module can be integrated on the main control board 210, or can be connected to the adapter board as an independent power supply module.

[0066] The processing module 212 may be, but is not limited to, a CPU, which includes an ARM instruction set or other instruction sets. The processing module 212 may implement the functions of a power-on function module, a power-off function module, a vector loading module, and a vector testing module. It should be understood that the power-on function module, the power-off function module, the vector loading module, and the vector testing module may be implemented by software.

[0067] The power-on function module of the aging test device 200 is used to receive the instruction sent by the power-on function module of the host computer 100, and turn on the board-level power supply of the aging board and the distributed power supply module according to the instruction. Optionally, the power-on function module is also used to initialize the functions associated with the aging board and the distributed power supply module, and then report the execution results to the host computer 100. It is necessary to interact with the power-on function module of the host computer 100 to complete the "hot plug" function of the aging board 220 together.

[0068] The power-off function module of the aging test device 200 is used for the instructions sent by the power-off function module of the host computer 100. Optionally, the power-off function module is also used to initialize the functions associated with the aging board 220 and the distributed power supply module, turn off the board-level power supply of the aging board 220 and the distributed power supply module, and then report the execution results to the host computer 100. The power-off function module of the aging test device 200 interacts with the power-on function module of the host computer 100 to complete the "hot unplug" function of the aging board 220.

[0069] The vector loading module of the aging test device 200 is used to receive the vector loading instruction of the host computer 100, download the aging test vector program package through the Ethernet interface, temporarily store the aging test vector program package in the temporary memory 213, and then load the aging test vector program package into the external memory 216. Specifically, after receiving the loading message, the vector loading module of the aging test device 200 determines whether the packet check code stored in the temporary memory 213 is the same as the received packet check code. If they are the same, the aging test vector program package is not loaded. If they are different, the aging test vector program package is downloaded from the host computer 100 and the aging test vector program package is stored in the external memory 216.

[0070] The vector test module of the aging test device 200 is used to receive the vector test instruction sent by the host computer 100, configure the register of the field programmable gate array (FPGA), start the vector test, collect the vector test results, and report the vector test results to the host computer 100. The vector test module of the aging test device 200 interacts with the vector test module of the host computer 100 to control the FPGA to generate the excitation signal of the chip aging test and receive and process the response signal output by the chip under test, output the aging test result, and complete the chip aging test function.

[0071] Optionally, the aging test module 215 may include one or more FPGAs, and the number of FPGAs may be set according to actual conditions, which is not limited in this application. The aging test module 215 may receive the loaded aging test vector program package sent by the processing module 212 through the Gigabit Ethernet interface, and write the aging test vector program package into the external memory 216 at high speed. The aging test module 215 is also used to read the vector file from the external memory 216, generate an excitation signal according to each line of data in the vector file, receive a response signal output by the chip under test, and output an aging test result according to the response signal output by the chip under test and the expected response signal.

[0072] The external memory 216 may be a DDR-SDRAM or a non-volatile memory (such as a non-volatile flash memory). The external memory 216 is connected to the aging test module 215 and is used to store the aging test vector program package.

[0073] The aging board 220 includes a chip under test 1 to a chip under test n, a socket for connecting the chip under test, and a distributed power supply module. The aging board 220 supports parallel aging tests of multiple chips. The distributed power supply module is used to power the chip under test. The number of chips under test, the number of sockets, and the number of power supply paths of the distributed power supply module can be set according to actual conditions, and this application does not limit it.

[0074] In the aging test device 200, the processing module 212 is a CPU, and the aging test module 215 is an FPGA. The CPU and the FPGA are connected via a local bus (i.e., a local bus). The CPU is also connected to a temporary memory 213, and the FPGA is also connected to an external memory 216. Figure 3 shown.

[0075] The local bus, also known as the system bus, is an electronic bus that connects the CPU and other devices (such as memory, hard disk, graphics card, etc.). It allows data to be transferred quickly within the system to support efficient system operation. Different types of computer systems and electronic devices may use different types of local buses, such as peripheral component interconnect express (PCI Express), industry standard architecture (ISA) bus, etc. Each local bus has its own dedicated bus control chip and protocol standard to manage data transmission and communication to ensure the correctness and integrity of data transmission.

[0076] During the chip aging test process, the CPU transmits the aging test vector package to the FPGA via the local bus. In one example, the bandwidth of the local bus does not exceed 16Mbps (million bits per second). If the size of the aging test vector package is 100MB, then the time overhead for writing the aging test vector package to the memory is at least 48 seconds. The complete vector loading process takes about 60 seconds. Usually, the data volume of the aging test vector package can reach hundreds of MB or more than 1GB, and the loading overhead ranges from a few minutes to tens of minutes.

[0077] In this application, the CPU and FPGA can use a faster communication interface to transmit data, and the transmitted data includes but is not limited to the aging test vector program package. The following introduces various connection methods between the CPU and FPGA:

[0078] In an optional embodiment, the aging test device 200 also includes a physical layer chip, which is connected to the processing module 212 via a serial gigabit media independent interface (SGMII), and the physical layer chip is connected to the aging test module 215 via a reduced gigabit media independent interface (RGMII); the processing module 212 is specifically used to send the aging test vector program package to the physical layer chip via SGMII when the packet check code included in the loading message is different from the packet check code stored locally; the physical layer chip is used to send the aging test vector program package to the aging test module 215 via RGMII.

[0079] See also Figure 4 In one example, the processing module 212 is a CPU, the aging test module 215 is an FPGA, and a physical layer chip is connected between the CPU and the FPGA. One end of the physical layer chip is connected to the SGMII of the CPU through SGMII, and the other end of the physical layer chip is connected to the RGMII of the FPGA through RGMII. The SGMII of the CPU can be implemented through a serializer and a deserializer, and the serializer and the deserializer are collectively referred to as SerDes, also known as SD. The RGMII of the FPGA can be implemented through the media access control layer (MAC). Through such a connection method, the CPU and the FPGA can write vector data to the external memory 216 at high speed, and the transmission bandwidth can be close to 1000Mbps. If the vector data is 100MB, the overhead of a single CPU writing the data to the memory only takes 1 second, and the complete vector loading process is about 13 seconds, so the time overhead of loading the aging test vector package can be greatly reduced.

[0080] See also Figure 5 In another optional embodiment, the processing module 212 is a CPU, the aging test module 215 is an FPGA, and the CPU is connected to the FPGA via SGMII; the CPU is specifically used to send the aging test vector program package to the FPGA via SGMII.

[0081] See also Figure 6 In another optional embodiment, the processing module 212 is a CPU, the aging test module 215 is an FPGA, the CPU is connected to the FPGA via RGMII, and the CPU is specifically used to send the aging test vector program package to the FPGA via RGMII. Compared with using the local bus to transmit the aging test vector program package, the speed of transmitting the aging test vector program package via SGMII or RGMII is faster, thereby improving the loading efficiency.

[0082] In an optional embodiment, the aging test module 215 is an FPGA. The process of performing chip aging test on the FPGA is introduced below. The FPGA is specifically used to generate an excitation signal according to the aging test vector program package, and send the excitation signal to the aging board; receive the feedback signal output by the aging board, and determine the aging test result according to the feedback signal and the expected response signal.

[0083] See also Figure 7 In another optional embodiment, the aging test module 215 includes an FPGA and multiple complex programmable logic devices (CPLDs); the FPGA is used to load the aging test vector package sent by the processor module into an external memory, and distribute multiple vector data to the CPLD; each CPLD is used to perform chip aging test on the chip according to the vector data sent by the FPGA. Specifically, the multiple CPLDs are specifically used to generate an excitation signal according to the vector data sent by the FPGA, and send the excitation signal to the aging board; receive the feedback signal output by the aging board, and determine the aging test result according to the feedback signal and the expected response signal. Figure 7 CPLD1 to CPLD8 are illustrative examples, and the specific number can be set according to actual conditions.

[0084] The adapter board 230 transmits signals (such as input and output channel signals) between the main control board and the aging board 220. One end of the adapter board 230 is connected to the adapter board connector of the main control board, and the other end of the adapter board 230 is connected to the adapter board connector of the aging board 220.

[0085] In another optional embodiment, the aging test device 200 further includes a power board 240 connected to the adapter board, and the power board 240 includes a power module. In this embodiment, the aging test device 200 may not be configured with a centralized power module 214, and the aging board 220 may not be configured with a distributed power module. The power module connected to the adapter board 230 supplies power to the main control board 210 and the aging board 220. Figure 8 shown.

[0086] It should be noted that the external memory 216 stores executable program codes, and the processor 212 executes the executable program codes to implement Fig. 9 The steps performed by the aging test device in the illustrated embodiment. The present application does not limit the number of processing modules 121 and the number of external memories 216 .

[0087] The chip aging test method of the present application is introduced below based on the host computer 100 and the aging test device 200 of the present application. Fig. 9 , an embodiment of the chip aging test method in the present application includes:

[0088] Step 901: The host computer obtains the to-be-compiled vector file group, the check code list of the first historical vector file group, and the second historical vector file group.

[0089] In this embodiment, the vector files in the first historical vector file group correspond to the vector files in the vector file group to be compiled one by one, and the two vector files with a corresponding relationship have the same file name. For example, the first vector file in the first historical vector file group is vector file 1 at time point 1, and the first vector file in the vector file group to be compiled is vector file 1 after time point 1, and other vector files with a corresponding relationship can be deduced in the same way. The second historical vector file group is compiled based on the first historical vector file group, that is, each vector file of the second format in the second historical vector file group is compiled from the vector file of the first format in the first historical vector file group.

[0090] For example, the first historical vector file group is the vector file group 1 compiled during the i-th compilation, the vector file group to be compiled is the vector file group 1 compiled during the i+1-th compilation, and the second historical vector file group is the vector file group 1 compiled during the i-th compilation. i is a positive integer.

[0091] The format of the vector files in the vector file group to be compiled and the first historical vector file group is the first format, and the format of the vector files in the second historical vector file group is the second format. Optionally, the first format is the atp format and the second format is the bin format. The atp format is a vector file format automatically generated by an automatic test pattern generation (ATPG) tool. The bin format is a multi-channel test vector file format based on an aging board. Vector files based on the bin format can perform aging tests on multiple chips at the same time, thereby improving the efficiency of aging tests. It should be noted that the first format can also be other formats generated by other electronic design automation (EDA) tools, and the second format can also be other vector file formats used for aging tests, which are not limited in this application.

[0092] See also Fig.10 In one example, the row attributes of a bin vector file include a row number, a microinstruction, a vector, a cyclic redundancy check (CRC) code, and a reserved field. The row number is used to identify the row of the vector file. The microinstruction is used to operate on the row of the vector file. The CRC code is used to verify the correctness of the vector file.

[0093] In one example, the bin vector file includes microinstructions as shown in Table 1:

[0094] serial number Microinstructions Microinstruction meaning 0 NEXT Sequential execution 1 REPEAT Repeat 2 JUMP Jump execution

[0095] Table 1

[0096] The length of the line number is 4 bytes, the length of the microinstruction is 4 bytes, the length of the vector is 48 bytes, the length of the CRC code is 4 bytes, and the length of the reserved field is 4 bytes. The length of each attribute can be set according to the actual situation and is not limited.

[0097] The vector includes multiple channels, such as CH0, CH1, CH2, CH3, CH4, etc. Each channel includes a direction, a most significant bit (MSB), and a least significant bit (LSB). Each channel occupies 4 bits, the direction occupies 2 bits, the most significant bit occupies 1 bit, and the least significant bit occupies 1 bit. In this application, the number of channels in the vector, the size of the channels and channel attributes can be set according to actual conditions, and are not specifically limited.

[0098] Step 902: The host computer calculates a checksum list of the vector file group to be compiled.

[0099] Step 903: The host computer determines modified vector files and unchanged vector files from the vector file group to be compiled based on the comparison result between the verification code list of the first historical vector file group and the verification code list of the vector file group to be compiled.

[0100] In an optional embodiment, step 903 includes: selecting one check code in turn from the check code list of the vector file group to be compiled as the check code of the vector file to be processed; selecting a historical check code corresponding to the vector file to be processed from the check code list of the first historical vector file group, the historical check code corresponding to the vector file to be processed refers to the check code of the vector file corresponding to the vector file to be processed in the first historical vector file group; when the check code of the vector file to be processed and the historical check code corresponding to the vector file to be processed are different, determining that the vector file to be processed is a modified vector file; when the check code of the vector file to be processed and the historical check code corresponding to the vector file to be processed are the same, determining that the vector file to be processed is an unchanged vector file.

[0101] The check codes in the check code list of the first historical vector file group can be considered as historical check codes, and the check codes in the check code list of the vector file group to be compiled can be considered as current check codes. Both the historical check code and the current check code are check codes calculated for the vector file using a hash algorithm. The hash algorithm can be a message digest algorithm (message digest algorithm, MD), and the MD can be MD2, MD4, MD5 or other MD algorithms, which is not limited in this application. The hash algorithm can also be a secure hash algorithm (secure hash algorithm, SHA), and SHA can be SHA1, SHA256, SHA384, SHA512 or other SHA algorithms, which is not limited in this application.

[0102] See also Fig.11 In one example, the vector file group to be compiled includes vector file 1 to vector file N, and each vector file has a corresponding historical check code, a current check code, and a recompilation flag. When the vector file is a modified vector file, the recompilation flag is set to 1, indicating that recompilation is required. When the vector file is an unchanged vector file, the recompilation flag is set to 0, indicating that recompilation is not required. The value of the recompilation flag can be set according to actual conditions, and this application does not limit it.

[0103] In the case where all vector files in the vector file group to be compiled are unchanged vector files, the vector file group to be compiled is the same as the first historical vector file group. All vector files in the vector file group to be compiled may also be modified vector files.

[0104] Step 904: The host computer compiles the modified vector file into a first target vector file.

[0105] After the modified vector file is compiled into the first target vector file, the checksum of the modified vector file can be used as the historical checksum for the next compilation. The present application does not limit the execution order of step 904 and step 905 , and step 905 can also be executed before step 904 .

[0106] Step 905: The host computer obtains a second target vector file corresponding to the unchanged vector file from the second historical vector file group.

[0107] Step 906: The host computer generates an aging test vector program package according to the first target vector file and the second target vector file.

[0108] The first target vector file and the second target vector file are both vector files in the second format. The aging test vector package includes one or more vectors, such as a power-on vector, a service vector 1, a service vector n, a power-off vector, etc. Fig.12 The vectors in the aging test vector program package can be set according to actual conditions, and this application does not limit this.

[0109] Step 907: The host computer generates a loading message carrying the identifier of the aging test vector program package and the package verification code.

[0110] The identification of the aging test vector program package may include but is not limited to the name of the aging test vector program package. The package check code is obtained by calculating the aging test vector program package using a hash algorithm, and is used to check the consistency of the aging test vector program package. The hash algorithm of the present application may be but is not limited to a message digest algorithm or a secure hash algorithm.

[0111] See also Fig.13 In one example, the loading message includes the name of the aging test vector program package, the length of the aging test vector program package, and a package checksum. The length of the aging test vector program package is optional.

[0112] Step 908: The host computer sends the loading message to the aging test device.

[0113] Step 909: Search the locally stored packet verification codes for a target packet verification code corresponding to the aging test vector program package identifier.

[0114] Optionally, when the locally stored packet check code does not include the target packet check code, a request to download a program package is sent to a host computer; an aging test vector program package sent by the host computer is received; the aging test vector program package sent by the host computer is loaded into an external memory; and a chip aging test is performed according to the loaded aging test vector program package. For an aging test vector program package that has not been loaded by the aging test device, the first loading and aging test can be performed.

[0115] Step 910 , the aging test device determines whether the packet verification code included in the loading message is the same as the target packet verification code, if so, execute step 911 , if not, execute step 912 .

[0116] The locally stored packet check code refers to the packet check code stored in a temporary memory (i.e., cache) or an external memory. The aging test device determines whether the packet check code included in the loading message is the same as the target packet check code. If they are the same, it indicates that the aging test device has stored the target aging test vector program package corresponding to the packet check code, and the aging test can be performed based on the stored target aging test vector program package without reloading the aging test vector program package. If they are different, it indicates that the aging test device has not stored the target aging test vector program package corresponding to the packet check code, and the aging test vector program package needs to be loaded.

[0117] See also Fig.14 In one example, the aging test vector program package has a corresponding cached packet check code, a packet check code included in the loading message, and a need-to-load flag. When the cached packet check code and the packet check code included in the loading message are the same, the need-to-load flag is set to 0, indicating that loading is not required. When the cached packet check code and the packet check code included in the loading message are different, the need-to-load flag is set to 1, indicating that loading is required. The value of the loading flag can be set according to actual conditions, and this application does not limit it.

[0118] Step 911: The aging test device performs a chip aging test according to a locally stored target aging test vector program package.

[0119] The locally stored target aging test vector program package refers to the aging test vector program package corresponding to the aging test vector program package identifier in the external memory.

[0120] Step 912: The aging test device sends a request to download the program package to the host computer.

[0121] Step 913: The host computer obtains the aging test vector program package according to the download program package request.

[0122] Step 914: The host computer sends the aging test vector program package to the aging test device.

[0123] Step 915: The aging test device loads the aging test vector program package into the external memory.

[0124] Step 916: The aging test device performs chip aging test according to the loaded aging test vector program package.

[0125] In this embodiment, the modified vector files can be identified according to the check code and recompiled, and the unchanged vector files are not recompiled, that is, the incremental compilation method. In the existing chip debugging stage, the vector files will be modified once or multiple times, and the entire set of vector files will be recompiled each time (i.e., full compilation), which causes a lot of time overhead. The incremental compilation method of this embodiment can greatly reduce the computational overhead and time overhead of compiling vector files.

[0126] Secondly, after the aging test vector package consistent with the received aging test vector package is identified in the aging test device according to the packet check code, the loading step is skipped to avoid repeated loading of the same aging test vector package. The time cost of loading the aging test vector package is tens of minutes or even more than 1 hour, so reducing the loading steps of the aging test vector package can increase the speed of chip aging test.

[0127] In this application, for each vector file, after determining whether it is a modified vector file or an unmodified vector file, the modified vector file can be compiled, and then the next vector file can be determined until all modified vector files are compiled. Fig.15 In an optional embodiment, the present application provides a method for compiling a vector file group including:

[0128] Step 1501: Generate a current verification code for the vector file.

[0129] The host computer receives the vector compilation instruction input by the user, and after starting the compilation, generates the current check code of the vector file in the vector file group to be compiled. The current check code is relative to the historical check code, and is specifically a check code calculated according to the hash algorithm.

[0130] Step 1502, determine whether the current verification code is the same as the historical verification code, if not, execute step 1503, if yes, execute step 1504.

[0131] Step 1503: recompile the vector file.

[0132] Step 1504, determine whether the vector file is the last vector file, if not, execute step 1505, if yes, end.

[0133] Step 1505 , obtain the next vector file and jump to step 1501 .

[0134] This embodiment can verify each vector file in the vector file group to be compiled, and recompile each modified vector file.

[0135] The embodiment of the present application also provides a computer program product including instructions. The computer program product may be software or a program product including instructions that can be run on a computing device or stored in any available medium. When the computer program product is run on at least one computing device, the at least one computing device executes the chip aging test method.

[0136] The embodiment of the present application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium that can be stored by a computer or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk). The computer-readable storage medium includes instructions that instruct the computer to execute the chip aging test method.

[0137] The present application also provides a chip system, which includes a processor and a memory coupled to each other. The memory is used to store computer programs or instructions, and the processor is used to execute the computer programs or instructions stored in the memory to enable the computing device to execute Figure 2 The steps performed by the communication interface 120 and the processing module 110 in the illustrated embodiment. Optionally, the memory is a memory in the chip, such as a register, a cache, etc. The memory may also be a memory located outside the chip in the station, such as a read-only memory or other types of static storage devices that can store static information and instructions, a random access memory, etc. The processor mentioned in any of the above may be a general-purpose central processing unit, a microprocessor, a dedicated integrated circuit, or one or more integrated circuits for implementing the above chip aging test method.

[0138] The present application also provides a chip system, which includes a processor and a memory coupled to each other. The memory is used to store computer programs or instructions, and the processor is used to execute the computer programs or instructions stored in the memory, so that the computing device executes the steps performed by the communication interface 211, the processing module 212 and the aging test module 215 in the above embodiment. Optionally, the memory is a memory in the chip, such as a register, a cache, etc. The memory can also be a memory located outside the chip in the site, such as a read-only memory or other types of static storage devices that can store static information and instructions, a random access memory, etc. The processor mentioned in any of the above places can be a general-purpose central processing unit, a microprocessor, a dedicated integrated circuit or one or more integrated circuits for implementing the above-mentioned chip aging test method.

[0139] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A chip aging test method, characterized in that: include: Obtaining a vector file group to be compiled, a check code list of a first historical vector file group, and a second historical vector file group, wherein the vector files in the first historical vector file group correspond one-to-one to the vector files in the vector file group to be compiled, and the two vector files having the corresponding relationship have the same file name, and the second historical vector file group is obtained by compiling the first historical vector file group; Calculating a checksum list of the vector file group to be compiled; Determining modified vector files and unchanged vector files from the vector file group to be compiled according to a comparison result of the check code list of the first historical vector file group and the check code list of the vector file group to be compiled; Compiling the modified vector file into a first target vector file; Acquire a second target vector file corresponding to the unchanged vector file from the second historical vector file group; Generate an aging test vector program package according to the first target vector file and the second target vector file; generating a loading message carrying the identifier of the aging test vector program package and a package verification code; The loading message is sent to the aging test device.

2. The method according to claim 1, characterized in that The method further comprises: receiving a downloading program package request sent by the aging test device; Acquire the aging test vector program package according to the download program package request; The aging test vector program package is sent to the aging test device.

3. The method according to claim 1, characterized in that The step of determining the modified vector files and the unchanged vector files from the vector file group to be compiled according to the comparison result of the verification code list of the first historical vector file group and the verification code list of the vector file group to be compiled comprises: Selecting one check code from the check code list of the vector file group to be compiled in turn as the check code of the vector file to be processed; Selecting a historical check code corresponding to the vector file to be processed from the check code list of the first historical vector file group; When the check code of the vector file to be processed is different from the historical check code corresponding to the vector file to be processed, determining that the vector file to be processed is a modified vector file; When the verification code of the vector file to be processed is the same as the historical verification code corresponding to the vector file to be processed, it is determined that the vector file to be processed is an unchanged vector file.

4. The method according to claim 3, characterized in that The check code of the vector file to be processed and the historical check code corresponding to the vector file to be processed are both obtained by calculating the vector file using a hash algorithm.

5. The method according to any one of claims 1 to 4, characterized in that The formats of the vector files in the to-be-compiled vector file group and the first historical vector file group are both in atp format, and the format of the vector files in the second historical vector file group is in bin format.

6. A chip aging test method, characterized in that: include: Receiving a loading message sent by a host computer, wherein the loading message includes an aging test vector program package identifier and a package check code; Searching for a target packet check code corresponding to the aging test vector program package identifier in the locally stored packet check codes; When the packet verification code included in the loading message is the same as the target packet verification code, a chip burn-in test is performed according to a locally stored target burn-in test vector program package, the target burn-in test vector program package corresponding to the burn-in test vector program package identifier.

7. The method according to claim 6, characterized in that The method further comprises: When the packet verification code included in the loading message is different from the target packet verification code or the locally stored packet verification code does not include the target packet verification code, sending a download package request to the host computer; Receiving an aging test vector program package sent by the host computer; Loading the aging test vector program package sent by the host computer into an external memory; Perform chip aging test according to the loaded aging test vector package.

8. A host computer, characterized in that: include: a processing module, configured to obtain a vector file group to be compiled, a check code list of a first historical vector file group, and a second historical vector file group, wherein the second historical vector file group is obtained by compiling the first historical vector file group, and the vector files in the first historical vector file group correspond one-to-one to the vector files in the vector file group to be compiled, and the two vector files having the corresponding relationship have the same file name; Calculating a checksum list of the vector file group to be compiled; According to the comparison result of the check code list of the first historical vector file group and the check code list of the vector file group to be compiled, determining the modified vector files and the unchanged vector files from the vector file group to be compiled, and compiling the modified vector files into the first target vector files; Acquire a second target vector file corresponding to the unchanged vector file from the second historical vector file group; Generate an aging test vector program package according to the first target vector file and the second target vector file; generate a loading message carrying an identifier and a package check code of the aging test vector program package; The communication interface is used to send the loading message to the aging test device.

9. The host computer according to claim 8, characterized in that: The host computer also includes: The communication interface is also used to receive a download package request sent by the aging test device; The processing module is further used to obtain the aging test vector program package according to the download program package request; The communication interface is also used to send the packet check code of the aging test vector program package to the aging test device.

10. The host computer according to claim 8, characterized in that: The processing module is specifically used to select one check code from the check code list of the vector file group to be compiled as the check code of the vector file to be processed; select the historical check code corresponding to the vector file to be processed from the check code list of the first historical vector file group; when the check code of the vector file to be processed and the historical check code corresponding to the vector file to be processed are different, determine that the vector file to be processed is a modified vector file; when the check code of the vector file to be processed and the historical check code corresponding to the vector file to be processed are the same, determine that the vector file to be processed is an unchanged vector file.

11. The host computer according to claim 10, characterized in that: The check code of the vector file to be processed and the historical check code corresponding to the vector file to be processed are both obtained by calculating the vector file using a hash algorithm.

12. The host computer according to any one of claims 8 to 11, characterized in that: The formats of the vector files in the to-be-compiled vector file group and the first historical vector file group are both in atp format, and the format of the vector files in the second historical vector file group is in bin format.

13. An aging test device, characterized in that: include: A communication interface, used for receiving a loading message sent by a host computer, wherein the loading message includes an aging test vector package identifier and a package check code; A processing module, used for searching the locally stored packet verification codes for a target packet verification code corresponding to the aging test vector program package identifier; The aging test module is used to perform a chip aging test on the chip according to a locally stored target aging test vector program package when the packet verification code included in the loading message is the same as the target packet verification code.

14. The device according to claim 13, characterized in that The communication interface is also used to send a download package request to the host computer when the packet verification code included in the loading message is different from the target packet verification code or the locally stored packet verification code does not include the target packet verification code; receive the aging test vector program package sent by the host computer; The processing module is further used to send the aging test vector program package sent by the host computer to the aging test module; The aging test module is also used to load the aging test vector program package sent by the processing module into an external memory; and perform chip aging test on the chip according to the loaded aging test vector program package.

15. The device according to claim 14, characterized in that The device further comprises a physical layer chip, wherein the physical layer chip is connected to the processing module via a serial gigabit media independent interface SGMII, and the physical layer chip is connected to the aging test module via a reduced gigabit media independent interface RGMII; The processing module is specifically used to send the received aging test vector program package to the physical layer chip through SGMII; The physical layer chip is used to send the aging test vector program package sent by the processing module to the aging test module through RGMII.

16. The device according to claim 14, characterized in that The processing module is connected to the aging test module via SGMII; The processing module is specifically configured to send the received aging test vector program package to the aging test module via the SGMII.

17. The device according to claim 14, characterized in that The processing module is connected to the aging test module via RGMII, and the processing module is specifically configured to send the received aging test vector program package to the aging test module via the RGMII.

18. The device according to any one of claims 14 to 17, characterized in that The aging test module includes FPGA and multiple complex programmable logic devices CPLD; The FPGA is used to load the aging test vector program package sent by the processor module into an external memory; The FPGA is also used to read multiple vector data of the aging test vector program package from the external memory, and send the multiple vector data to the multiple CPLDs respectively; The CPLD is used to perform a chip aging test on the chip according to the vector data sent by the FPGA.

19. The device according to any one of claims 13 to 17, characterized in that The aging test module is a field programmable gate array FPGA.

20. A computing device, characterized in that The method comprises a processor and a memory, wherein the processor is configured to execute instructions stored in the memory so that the computing device executes the method according to any one of claims 1 to 5.

21. A computing device, characterized in that The method comprises a processor and a memory, wherein the processor is configured to execute instructions stored in the memory so that the computing device executes the method according to any one of claims 6 to 7.

22. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a computing device, the computing device performs the method according to any one of claims 1 to 7.

23. A computer program product comprising instructions, characterized in that When the instructions are executed by a computing device, the computing device is caused to perform the method according to any one of claims 1 to 7.

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