A memory-based multi-channel parallel testing system and method thereof

Abstract

The present invention relates to the field of storage channel testing technology, and in particular to a memory multi-channel parallel testing system and method thereof. The method comprises the following steps: obtaining memory test channel raw data; performing topological analysis on the memory test channel raw data to generate storage channel node distribution data; performing dynamic weight calculation on the storage channel node distribution data to obtain channel priority data; performing resource competition arbitration on the storage channel node distribution data according to the channel priority data to generate channel resource allocation data; performing control plane mapping on the channel resource allocation data to generate network topology virtualization data; performing routing strategy optimization processing on the network topology virtualization data to generate dynamic routing table data. The present invention improves the efficiency and accuracy of memory multi-channel parallel testing by optimizing channel resource allocation, topology virtualization management, elastic scheduling synchronization, fault prediction and data matching.

Description

Technical Field

[0001] The present invention relates to the technical field of storage channel testing, and in particular to a memory-based multi-channel parallel testing system and method thereof. Background Art

[0002] With the rapid advancement of computer technology and semiconductor manufacturing, memory, as a critical component of computing systems, continues to increase in capacity, speed, and complexity. However, the growth in memory size and complexity has also significantly increased testing challenges. Traditional single-channel memory testing methods are no longer able to meet the efficiency and coverage requirements of modern memory manufacturing. Early memory testing relied primarily on sequential read and write testing, which determined memory integrity by individually checking the functional status of memory cells. However, this approach was time-consuming for large-capacity memories, severely limiting test efficiency. With the emergence of multi-channel memory architectures, such as DDR and HBM (High Bandwidth Memory), traditional test methods have been unable to fully utilize the parallel nature of multiple channels, resulting in low resource utilization. To address these issues, multi-channel parallel testing has emerged. By simultaneously activating multiple channels to run test tasks in parallel, this approach significantly improves test speed and effectively covers complex failure modes. However, current traditional technologies lack in-depth analysis of storage channel node distribution and resource competition in multi-channel testing, which can easily lead to uneven or conflicting channel resource allocation. At the same time, pipeline scheduling and cache synchronization mechanisms are often inflexible, which can easily cause data inconsistencies and performance bottlenecks, resulting in low efficiency and accuracy of multi-channel parallel testing of memory. Summary of the Invention

[0003] Based on this, it is necessary to provide a memory-based multi-channel parallel testing system and method thereof to solve at least one of the above technical problems.

[0004] To achieve the above object, a memory-based multi-channel parallel testing method is provided, the method comprising the following steps:

[0005] Step S1: acquiring raw data of a memory test channel; performing topological analysis on the raw data of the memory test channel to generate memory channel node distribution data; performing dynamic weight calculation on the memory channel node distribution data to obtain channel priority data; performing resource competition arbitration on the memory channel node distribution data according to the channel priority data to generate channel resource allocation data;

[0006] Step S2: Perform control plane mapping on the channel resource allocation data to generate network topology virtualization data; perform routing policy optimization processing on the network topology virtualization data to generate dynamic routing table data; perform elastic pipeline concurrent scheduling on the dynamic routing table data to generate parallel test pipeline data; perform adaptive cache synchronization on the parallel test pipeline data to generate channel parallel cache consistency state data;

[0007] Step S3: extracting timing features from the parallel test pipeline data based on the cache coherence state data to obtain parallel test timing feature data; performing streaming calculations on the parallel test timing feature data to obtain real-time abnormality indicator data; constructing a model based on the real-time abnormality indicator data to generate a memory multi-channel fault probability distribution prediction model; importing the parallel test timing feature data into the memory multi-channel fault probability distribution prediction model to perform test fault prediction and generate fault probability prediction data;

[0008] Step S4: perform test data collection on the parallel test pipeline data according to the fault probability prediction data to obtain channel parallel actual test data; perform data matching on the channel parallel actual test data and the fault probability prediction data to generate a memory multi-channel parallel test matching report to perform parallel test detection operations.

[0009] The present invention effectively improves the efficiency and fairness of channel resource allocation through topology analysis, dynamic weight calculation and resource competition arbitration, avoids resource conflicts and uneven distribution problems, and provides an efficient channel scheduling foundation for subsequent parallel testing. Network topology virtualization is achieved through control plane mapping, which improves the network management flexibility of memory testing; routing strategy optimization and elastic pipeline concurrent scheduling improve the efficiency and throughput of parallel testing, and adaptive cache synchronization ensures data consistency, reducing data delays and errors during testing. Based on the extraction of timing features based on cache consistency state data, combined with streaming computing to generate real-time abnormality indicator data, and constructing a fault probability distribution prediction model, it can achieve early prediction and location of potential faults, significantly improving the accuracy of testing and fault detection efficiency. By collecting parallel test data and matching it with fault probability prediction data, a multi-channel parallel test matching report is generated, which comprehensively improves the credibility of test results, provides accurate decision support for parallel test detection operations, and ensures the efficiency and reliability of detection operations. The above steps are closely linked, from resource allocation to network optimization, to fault prediction and result verification, comprehensively improving the efficiency, accuracy and intelligence level of multi-channel parallel testing of memory. Therefore, the present invention improves the efficiency and accuracy of multi-channel parallel testing of memory by optimizing channel resource allocation, topology virtualization management, elastic scheduling synchronization, fault prediction and data matching.

[0010] Preferably, step S1 includes the following steps:

[0011] Step S11: obtaining raw data of the memory test channel;

[0012] Step S12: performing data preprocessing on the raw data of the memory test channel to generate standard memory test channel data, wherein the data preprocessing includes data cleaning, data denoising, data missing value filling and data standardization; performing NUMA topology analysis on the standard memory test channel data to generate storage channel node distribution data;

[0013] Step S13: performing node edge computing resource evaluation on the storage channel node distribution data to generate node computing load distribution data; performing dynamic weight calculation on the storage channel nodes based on the node computing load distribution data to obtain channel priority data;

[0014] Step S14: performing resource contention arbitration on the storage channel node distribution data according to the channel priority data to generate channel resource allocation data.

[0015] This invention accurately collects raw data from memory test channels, ensuring that the underlying data for subsequent analysis is comprehensive and accurate, providing reliable input for the entire process. Through data cleaning, denoising, missing value filling, and standardization, data quality and consistency are improved, eliminating the interference of noise and outliers on analysis. NUMA (non-uniform memory access) topology analysis is performed to clarify the distribution of storage channel nodes and optimize the physical and logical structure analysis of the memory. Edge computing resource assessment identifies the computational load of each node and provides accurate node load distribution information. A dynamic weight calculation mechanism optimizes the priority configuration of storage channel nodes based on load distribution, ensuring fair and efficient resource scheduling. Through resource competition arbitration based on channel priorities, storage resources are rationally allocated, resource utilization is maximized, and potential conflicts and performance bottlenecks are reduced. Dynamic and precise channel resource allocation strategies are provided to improve the overall efficiency and responsiveness of the system.

[0016] Preferably, step S14 includes the following steps:

[0017] Step S141: performing resource contention identification on the storage channel node distribution data to obtain channel node resource contention data;

[0018] Step S142: defining arbitration rules for channel node resource competition data based on the first-in-first-out principle to obtain node resource competition arbitration rule data;

[0019] Step S143: performing local resource allocation on the channel node resource contention data according to the node resource contention arbitration rule data to generate node resource allocation data;

[0020] Step S144: using the channel priority data to perform global channel resource allocation adjustment on the node resource allocation data to generate channel resource allocation data.

[0021] By identifying resource contention based on storage channel node distribution data, this invention accurately locates contention hotspots, clarifies resource contention at each node, and reduces blind spots and uneven resource allocation. The generated channel node resource contention data provides a scientific basis for subsequent arbitration, enhancing the targeted nature of resource allocation. Based on the first-in-first-out (FIFO) principle, resource contention arbitration rules are formulated to ensure fair resource allocation and prevent high-priority nodes from occupying resources for extended periods, leading to starvation of lower-priority nodes. The standardization and automation of arbitration rules improves the efficiency and transparency of the resource allocation decision-making process. Local allocation of resource contention data based on the arbitration rules effectively reduces the complexity of resource contention and avoids overload on a single node or region. The generated node resource allocation data optimizes node-level resource utilization and balances resource distribution. Node-level allocation results are globally adjusted using channel priority data, enabling dynamic cross-node and cross-region resource optimization. This ensures that the resource requirements of high-priority channels are fully met while also balancing overall system performance and stability. This combined global and local allocation approach optimizes resource utilization, avoiding resource waste and unnecessary conflicts. Resource arbitration and dynamic adjustment mechanisms reduce delays and bottlenecks caused by resource competition, improving overall system performance. Resource allocation strategies based on node priorities and dynamic adjustment rules enable the system to flexibly adapt to the needs of different workloads and application scenarios. Through fair arbitration rules and efficient resource allocation mechanisms, the long-term impact of resource imbalances on system operations is reduced, extending the system's stable operation period.

[0022] Preferably, step S2 includes the following steps:

[0023] Step S21: performing resource data abstraction on the channel resource allocation data to obtain channel resource allocation abstract data, wherein the resource data abstraction includes device type abstraction, connection relationship abstraction, and address information abstraction; performing topology modeling on the channel resource allocation abstract data to generate resource allocation physical network topology data;

[0024] Step S22: performing control plane mapping on the resource allocation physical network topology data through the SDN controller to generate network topology virtualization data; performing routing demand analysis on the network topology virtualization data to generate routing demand data; performing routing policy optimization processing on the network topology virtualization data based on the routing demand data to generate dynamic routing table data;

[0025] Step S23: performing link aggregation analysis on the dynamic routing table data to generate bandwidth allocation policy data; performing topology adaptive processing on the bandwidth allocation policy data to generate channel interconnection topology data; performing elastic pipeline concurrent scheduling on the channel interconnection topology data to generate parallel test pipeline data;

[0026] Step S24: performing adaptive cache synchronization on the parallel test pipeline data to generate channel parallel cache consistency state data.

[0027] By abstracting device types, connection relationships, and address information, the present invention reduces direct reliance on physical resources and achieves standardized and modular management of channel resources. Topology modeling provides a clear physical network view for resource allocation, improving the accuracy and dynamic adjustment capabilities of resource scheduling, and reducing resource waste and conflicts. Network topology virtualization and control plane mapping based on the SDN controller transform resource allocation from a static model to a dynamic and intelligent one, adapting to dynamic demand changes in complex network environments. Routing policy optimization not only reduces the path overhead of data transmission but also improves network load balancing capabilities, thereby enhancing transmission stability and efficiency. Link aggregation analysis combined with bandwidth allocation strategies effectively improves the system's overall bandwidth utilization, ensuring smooth operation of high-throughput test scenarios. Elastic pipeline concurrent scheduling enables dynamic resource allocation and multi-task collaborative processing, reducing resource contention and waiting time between test tasks. Adaptive cache synchronization technology ensures data consistency in multi-channel parallel processing, avoiding data loss, duplication, or delays. The data consistency monitoring mechanism improves the system's fault tolerance to sudden anomalies and ensures the accuracy and traceability of test results. Dynamic routing tables and topology adaptive processing mechanisms enable the system to adapt to changing business needs in real time, reducing manual intervention and improving automation. The modular process design provides high compatibility and flexibility for subsequent functional expansion and policy optimization, meeting the requirements of test scenarios of varying scale and complexity.

[0028] Preferably, performing flexible pipeline concurrent scheduling on channel interconnection topology data includes:

[0029] Extract key channel features from the channel interconnection topology data to obtain channel interconnection key feature data, where the channel interconnection key feature data includes key node data and channel interconnection link data; perform dependency analysis on the key node data and the channel interconnection link data to generate channel interconnection dependency data;

[0030] Divide the channel interconnection topology data into service units based on the channel interconnection dependency data to generate independent service unit data; segment the channel interconnection topology data into microservices based on the independent service unit data to generate service unit division data;

[0031] Perform service unit containerization on the service unit partition data to generate containerized service unit data; perform container network orchestration on the containerized service unit data to generate unit container network orchestration data; perform container orchestration mapping on the containerized service unit data using the unit container network orchestration data to generate container scheduling policy data;

[0032] Perform concurrent optimization on container scheduling policy data to generate task parallelism data; perform pipeline synchronization on task parallelism data to generate parallel test pipeline data.

[0033] The present invention accurately identifies the core factors affecting channel performance through feature extraction and dependency analysis of key node and interconnected link data, providing a reliable foundation for subsequent service partitioning and reducing redundancy and resource waste. Service unit partitioning deconstructs complex channel topology data into independent modules, significantly improving the system's modular management capabilities. Microservice segmentation ensures that each service unit has good collaboration while operating independently, reducing the complexity of global resource scheduling. Containerized service units provide a unified operating environment, ensuring compatibility and isolation between different service units, reducing deployment conflicts and debugging costs. Container network orchestration enables efficient connection and communication between service units, optimizing network performance and operational efficiency. The scheduling policy data generated by the container orchestration mapping fully considers the dependencies and load characteristics of the service units, enabling dynamic allocation and optimized utilization of resources, and improving scheduling efficiency. The concurrency optimization strategy maximizes resource utilization based on task parallelism data, effectively reducing task execution time and improving overall parallel processing performance. The pipeline synchronization mechanism ensures data consistency and process orderliness between tasks, avoiding conflicts and bottlenecks in processing. By combining containerization with flexible scheduling, the system maintains efficient operation under varying load conditions, significantly enhancing adaptability and scalability. The automated processes for data processing and task scheduling reduce human intervention, lowering operational costs while improving system reliability and stability.

[0034] Preferably, concurrent optimization of container scheduling policy data includes:

[0035] Perform policy execution on the container scheduling policy data to generate container scheduling policy execution data; perform scheduling node screening on the storage channel node distribution data based on the container scheduling policy execution data to obtain the policy execution scheduling node; perform scheduling timestamp analysis on the policy execution scheduling node to generate the node scheduling timestamp;

[0036] According to the node scheduling timestamp, the strategy execution scheduling nodes are divided into nodes with timestamp differences, and concurrent synchronous timestamp node data and concurrent non-synchronous timestamp node data are generated; the concurrent synchronous timestamp node data are batch processed for node tasks, and a concurrent synchronous node task batch processing strategy is generated;

[0037] Perform concurrent timestamp calibration on the data of the concurrent non-synchronous timestamp node and the concurrent synchronous timestamp node to obtain concurrent timestamp calibration data; based on the concurrent timestamp calibration data, perform transaction rollback within the difference timestamp on the concurrent non-synchronous timestamp node to generate a non-concurrent synchronous node task rollback strategy;

[0038] The concurrent synchronization node task batch processing strategy and the non-concurrent synchronization node task rollback strategy are used to concurrently optimize the container scheduling strategy data and generate task parallelism data.

[0039] The present invention accurately screens the distribution of storage channel nodes based on container scheduling policy execution data, ensuring that the selected scheduling nodes have high adaptability and priority, thereby reducing the occupation of invalid resources and optimizing the scheduling path. Timestamp analysis and difference division are performed on scheduling nodes to clarify the characteristics of synchronous and asynchronous nodes, ensure the timing consistency during the execution of concurrent tasks, and effectively avoid conflicts and delays caused by time differences. For synchronous timestamp node data, a task batch processing strategy is generated to efficiently allocate resources, reduce the switching and waiting time required for task execution, and significantly improve system processing throughput. Timestamp calibration is performed on asynchronous nodes to eliminate task errors caused by node timing differences, ensure data consistency between tasks and the accuracy of operation logic. A timestamp rollback mechanism is introduced in asynchronous node transaction processing to effectively deal with transaction anomalies caused by timing differences, enhance the system's fault tolerance and task recovery capabilities, and improve the robustness of the overall scheduling. By combining synchronous node batch processing strategies with asynchronous node rollback strategies, the parallel execution process of tasks is further optimized, while ensuring task consistency, maximizing task parallelism and shortening the overall task execution time. This full-process optimization fully utilizes system resources, avoiding performance degradation caused by resource waste or conflicts, and ensuring that the container scheduling system maintains stable and efficient operation even under high loads. Through the comprehensive implementation of concurrency optimization, the scheduling system has become highly flexible, rapidly responding to task priority adjustments and operating environment changes while maintaining stability, providing reliable support for containerized task management in complex scenarios.

[0040] Preferably, performing adaptive cache synchronization on parallel test pipeline data includes:

[0041] Perform distributed cache stratification on parallel test pipeline data to generate cache hierarchy data; perform memory queue optimization on cache hierarchy data to generate queue scheduling strategy data;

[0042] The queue scheduling policy data is processed by consistency protocol to generate synchronization state machine data; conflict detection is performed on the synchronization state machine data. When a conflict is detected in the synchronization state machine data, the conflicting data is merged to generate cache consistency state data.

[0043] The present invention forms a structured cache hierarchy by performing a cache hierarchical design on the parallel test pipeline data, making data storage and access more efficient and reducing data retrieval delays. The cache hierarchical structure data is optimized for memory queues to generate scientific and efficient queue scheduling policy data, significantly improving the task distribution and execution efficiency of the cache queue and reducing the ineffective occupation of system resources. The introduction of consistency protocol processing on the queue scheduling policy data ensures the synchronous update of cache data in multiple nodes or distributed environments, effectively avoiding data inconsistency problems and improving the stability and reliability of task execution. The introduction of the synchronization state machine provides dynamic monitoring capabilities for cache synchronization, eliminating task blocking and resource waste caused by data competition by detecting conflicting data in real time and performing reasonable merging. In the process of merging conflicting data, the data integrity and consistency between different cache nodes are guaranteed, effectively supporting reliable data interaction under high-concurrency tasks and avoiding the risk of data loss or repeated processing. The adaptive cache synchronization mechanism fully optimizes the system's memory and computing resource allocation, making cache management more efficient, maximizing system resource utilization, and providing strong support for system operation. In the high-intensity task processing of the parallel test pipeline, the adaptive cache synchronization optimization strategy significantly improved the pipeline's task throughput, enabling the system to quickly respond to highly concurrent requests and improving task execution efficiency. This optimization solution not only ensures data consistency but also enhances the system's robustness, making it adaptable to diverse scenarios and providing good scalability to support future feature upgrades and performance improvements.

[0044] Preferably, step S3 includes the following steps:

[0045] Step S31: extracting timing features of the parallel test pipeline data based on the cache coherence state data to obtain parallel test timing feature data;

[0046] Step S32: Perform streaming calculation on the parallel test time series feature data to obtain real-time abnormality indicator data; divide the real-time abnormality indicator data into data sets to generate a model training set and a model test set;

[0047] Step S33: training the model training set using a long short-term memory neural network algorithm to generate a memory multi-channel fault probability distribution prediction pre-model; optimizing and iterating the memory multi-channel fault probability distribution prediction pre-model using a model test set to generate a memory multi-channel fault probability distribution prediction model;

[0048] Step S34: importing the parallel test timing feature data into the memory multi-channel fault probability distribution prediction model to perform test fault prediction and generate fault probability prediction data.

[0049] The present invention extracts time series features from parallel test pipeline data based on cache consistency state data, effectively capturing the dynamic characteristics of data changes, providing a high-precision input foundation for subsequent fault prediction, and improving the accuracy and reliability of data analysis. Streaming calculations on parallel test time series feature data can generate anomaly indicators in real time, quickly identifying potential anomalies in the test process, ensuring that faults can be discovered and handled in a timely manner at an early stage, and reducing the risk of problem spread. The data set partitioning strategy ensures the diversity of the model training set and the representativeness of the model test set, providing a scientific sample distribution foundation for the training and optimization of the neural network model, and improving the model's generalization ability and prediction effect. The long short-term memory (LSTM) neural network algorithm is applied to fully utilize the temporal correlation of time series feature data to construct an efficient fault probability distribution prediction model, improving the ability to accurately predict multi-channel faults. By optimizing and iterating the memory multi-channel fault probability distribution prediction pre-model, the performance and stability of the model are significantly enhanced, ensuring that the model's prediction of fault modes is closer to actual scenarios. By importing parallel test timing feature data into a predictive model to generate failure probability prediction data, we can monitor and predict potential system failures in real time, providing proactive guidance for system operations and maintenance, and avoiding the risk of performance degradation or interruption caused by failures. Automated fault prediction shortens problem diagnosis and troubleshooting time, reduces the frequency and complexity of manual intervention, and effectively saves manpower and time during the testing process.

[0050] Preferably, step S4 includes the following steps:

[0051] Step S41: Generate test signals for the parallel test pipeline data according to the fault probability prediction data to obtain channel parallel test signals; collect test data for the channel parallel test signals to obtain channel parallel actual test data;

[0052] Step S42: Perform data matching calculation on the channel parallel actual test data and the fault probability prediction data to obtain channel parallel test matching data; perform data visualization on the channel parallel test matching data to generate a memory multi-channel parallel test matching report to perform parallel test detection operations.

[0053] This invention automatically generates channel-parallel test signals based on fault probability prediction data, achieving dynamic adaptation of test signals. This reduces the complexity of manual intervention and improves test efficiency. Test data acquisition is performed on the channel-parallel test signals to comprehensively obtain actual test data from multiple channels, ensuring data diversity and integrity and providing a rich data foundation for subsequent analysis. The actual channel-parallel test data is matched and calculated with the fault probability prediction data, accurately comparing the predicted and actual results, significantly improving the credibility of the test results and the accuracy of fault location. Data visualization based on the matching calculation results generates an intuitive and clear memory multi-channel parallel test matching report, providing engineers and maintenance teams with intuitive data presentation and problem analysis tools, improving decision-making efficiency. Combining test signal generation with data matching analysis achieves in-depth optimization of multi-channel parallel testing and significantly enhances the concurrent processing capabilities of the test system in large-scale testing scenarios. By matching and verifying actual test data with predicted data, the error range in fault detection is effectively reduced, ensuring the accuracy of fault location and the reliability of diagnostic results. The dynamic generation of test signals and the automated processing of data matching significantly enhance the intelligence level of the test system and lay the foundation for further expansion of automated testing processes. The generation of matching reports for multi-channel parallel memory testing provides a transparent overview of the entire process, providing a traceable basis for fault detection and optimization, and meeting the high-standard audit requirements for test operations. Automated test signal generation, data acquisition, and report output shortens test cycles, reduces reliance on human resources, saves costs, and improves overall operational efficiency.

[0054] In this specification, a memory-based multi-channel parallel testing system is provided for executing the above-mentioned memory-based multi-channel parallel testing method. The memory-based multi-channel parallel testing system includes:

[0055] A channel resource allocation module is configured to obtain raw data from a memory test channel; perform topological analysis on the raw data to generate memory channel node distribution data; perform dynamic weight calculation on the memory channel node distribution data to obtain channel priority data; perform resource competition arbitration on the memory channel node distribution data based on the channel priority data to generate channel resource allocation data;

[0056] The concurrent scheduling module is used to perform control plane mapping on channel resource allocation data to generate network topology virtualization data; perform routing policy optimization processing on network topology virtualization data to generate dynamic routing table data; perform elastic pipeline concurrent scheduling on dynamic routing table data to generate parallel test pipeline data; perform adaptive cache synchronization on parallel test pipeline data to generate channel parallel cache consistency state data;

[0057] A fault prediction module is used to extract timing features from parallel test pipeline data based on cache consistency state data to obtain parallel test timing feature data; perform streaming calculations on the parallel test timing feature data to obtain real-time abnormality indicator data; construct a model based on the real-time abnormality indicator data to generate a memory multi-channel fault probability distribution prediction model; import the parallel test timing feature data into the memory multi-channel fault probability distribution prediction model to perform test fault prediction and generate fault probability prediction data;

[0058] The parallel test module is used to collect test data for the parallel test pipeline data according to the fault probability prediction data to obtain the actual channel parallel test data; match the actual channel parallel test data with the fault probability prediction data to generate a memory multi-channel parallel test matching report to perform parallel test detection operations.

[0059] The beneficial effects of the present invention are that through topology analysis and dynamic weight calculation, resources can be accurately allocated to each storage channel, avoiding resource conflicts and unnecessary delays, ensuring faster response times for high-priority channels, and improving overall system performance. Through network topology virtualization and route optimization, efficient and smooth data transmission is ensured, the risk of network congestion is reduced, and the reliability of data transmission is improved. Through adaptive cache synchronization in the parallel test pipeline, data consistency between multiple test channels is ensured, test errors caused by cache inconsistencies are avoided, and the stability of parallel testing is improved. Through timing feature extraction and streaming computing, potential faults in the system can be detected and predicted in real time. By constructing a multi-channel memory fault probability distribution prediction model, potential faults can be warned in advance, improving system reliability. By matching fault probability prediction data with actual test data, a parallel test matching report is generated, providing an accurate execution basis for parallel test operations of the memory, helping to reduce test time and cost, while also improving the accuracy of fault detection. Therefore, the present invention improves the efficiency and accuracy of multi-channel parallel testing of memory by optimizing channel resource allocation, topology virtualization management, flexible scheduling synchronization, fault prediction, and data matching. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 A schematic diagram of the steps of a multi-channel parallel testing method based on memory;

[0061] Figure 2 for Figure 1 Detailed implementation steps of step S2 in FIG.

[0062] Figure 3 for Figure 1 Detailed implementation steps of step S3 in FIG.

[0063] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0064] The following is a clear and complete description of the technical method of the present invention in conjunction with the accompanying drawings. It is obvious that the embodiments described are part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts are within the scope of protection of the present invention.

[0065] In addition, the accompanying drawings are merely schematic illustrations of the present invention and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor and / or microcontroller approaches.

[0066] It should be understood that although the terms "first," "second," and the like may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the exemplary embodiments. The term "and / or" as used herein includes any and all combinations of one or more of the listed associated items.

[0067] To achieve this, please refer to Figures 1 to 3 , a memory-based multi-channel parallel testing method, the method comprising the following steps:

[0068] Step S1: acquiring raw data of a memory test channel; performing topological analysis on the raw data of the memory test channel to generate memory channel node distribution data; performing dynamic weight calculation on the memory channel node distribution data to obtain channel priority data; performing resource competition arbitration on the memory channel node distribution data according to the channel priority data to generate channel resource allocation data;

[0069] Step S2: Perform control plane mapping on the channel resource allocation data to generate network topology virtualization data; perform routing policy optimization processing on the network topology virtualization data to generate dynamic routing table data; perform elastic pipeline concurrent scheduling on the dynamic routing table data to generate parallel test pipeline data; perform adaptive cache synchronization on the parallel test pipeline data to generate channel parallel cache consistency state data;

[0070] Step S3: extracting timing features from the parallel test pipeline data based on the cache coherence state data to obtain parallel test timing feature data; performing streaming calculations on the parallel test timing feature data to obtain real-time abnormality indicator data; constructing a model based on the real-time abnormality indicator data to generate a memory multi-channel fault probability distribution prediction model; importing the parallel test timing feature data into the memory multi-channel fault probability distribution prediction model to perform test fault prediction and generate fault probability prediction data;

[0071] Step S4: perform test data collection on the parallel test pipeline data according to the fault probability prediction data to obtain channel parallel actual test data; perform data matching on the channel parallel actual test data and the fault probability prediction data to generate a memory multi-channel parallel test matching report to perform parallel test detection operations.

[0072] The present invention effectively improves the efficiency and fairness of channel resource allocation through topology analysis, dynamic weight calculation and resource competition arbitration, avoids resource conflicts and uneven distribution problems, and provides an efficient channel scheduling foundation for subsequent parallel testing. Network topology virtualization is achieved through control plane mapping, which improves the network management flexibility of memory testing; routing strategy optimization and elastic pipeline concurrent scheduling improve the efficiency and throughput of parallel testing, and adaptive cache synchronization ensures data consistency, reducing data delays and errors during testing. Based on the extraction of timing features based on cache consistency state data, combined with streaming computing to generate real-time abnormality indicator data, and constructing a fault probability distribution prediction model, it can achieve early prediction and location of potential faults, significantly improving the accuracy of testing and fault detection efficiency. By collecting parallel test data and matching it with fault probability prediction data, a multi-channel parallel test matching report is generated, which comprehensively improves the credibility of test results, provides accurate decision support for parallel test detection operations, and ensures the efficiency and reliability of detection operations. The above steps are closely linked, from resource allocation to network optimization, to fault prediction and result verification, comprehensively improving the efficiency, accuracy and intelligence level of multi-channel parallel testing of memory. Therefore, the present invention improves the efficiency and accuracy of multi-channel parallel testing of memory by optimizing channel resource allocation, topology virtualization management, elastic scheduling synchronization, fault prediction and data matching.

[0073] In the embodiment of the present invention, reference Figure 1 FIG. 1 is a flow chart of a method for parallel testing a memory using multiple channels according to the present invention. In this example, the method for parallel testing a memory using multiple channels includes the following steps:

[0074] Step S1: acquiring raw data of a memory test channel; performing topological analysis on the raw data of the memory test channel to generate memory channel node distribution data; performing dynamic weight calculation on the memory channel node distribution data to obtain channel priority data; performing resource competition arbitration on the memory channel node distribution data according to the channel priority data to generate channel resource allocation data;

[0075] In an embodiment of the present invention, raw channel data from the memory test process is collected via an interface protocol, including key performance indicators (KPIs) such as test results, latency, bandwidth, and data throughput for each channel. The collected raw data is stored in a unified format to form a memory test channel raw data set. A topology analysis algorithm is used to analyze the structural relationships of the memory channels and construct a node network topology diagram of the channels. Nodes can represent storage controllers, switches, data cache modules, and other components, while edges represent data paths and communication relationships between nodes. The output topology analysis results are storage channel node distribution data, which includes the connection relationships of each node, channel bandwidth distribution, latency distribution, and other indicators. Dynamic weighting is performed on the storage channel node distribution data based on channel performance indicators. This weighting calculation process determines the priority of each channel node by comprehensively considering multiple performance indicators such as channel bandwidth, latency, throughput, and reliability. The specific calculation method is as follows: The bandwidth value of the current node is compared with the maximum bandwidth value of all nodes, and the percentage is calculated. A higher bandwidth percentage indicates a stronger transmission capability for the node. The minimum latency value of all nodes is compared with the latency value of the current node to determine its latency priority. A lower latency value has a higher priority. The current node's throughput is compared with the maximum throughput of all nodes to calculate their contribution. A higher throughput indicates a node with greater data processing capabilities. The current node's reliability index is directly used, with nodes with higher reliability receiving higher priority. By assigning weights to bandwidth, latency, throughput, and reliability, each node's final overall weight is calculated. These weights balance the importance of different performance metrics. Finally, node priorities are ranked based on each node's overall weight, generating channel priority data. Resource contention arbitration is performed based on channel priority data to determine a resource allocation plan: resources are dynamically allocated based on node priority, with higher-priority nodes receiving resources first. Resource allocation algorithms (such as the improved maximum flow algorithm or the fair scheduling algorithm) are used to resolve resource conflicts. The arbitration results ensure that performance constraints such as bandwidth, latency, and throughput are met. The arbitration results are organized into structured data, including the resource allocation amount for each node and the final priority ranking between channels. This final channel resource allocation data is used to guide subsequent storage resource scheduling and optimization.

[0076] Step S2: Perform control plane mapping on the channel resource allocation data to generate network topology virtualization data; perform routing policy optimization processing on the network topology virtualization data to generate dynamic routing table data; perform elastic pipeline concurrent scheduling on the dynamic routing table data to generate parallel test pipeline data; perform adaptive cache synchronization on the parallel test pipeline data to generate channel parallel cache consistency state data;

[0077] In this embodiment of the present invention, control plane mapping is performed on channel resource allocation data. By associating the control plane of the storage network, a mapping relationship between resource nodes and logical networks is established, thereby generating network topology virtualization data, which includes the distribution of virtual nodes and virtual links. Subsequently, routing policy optimization is performed on the network topology virtualization data. Based on rules such as shortest path first, load balancing, and fault recovery, a heuristic algorithm (such as the Dijkstra or modified Bellman-Ford algorithm) is used to dynamically adjust the routing policy to generate dynamic routing table data. Based on this dynamic routing table data, tasks are elastically scheduled concurrently in pipelines. Using a pipeline concurrency approach, data transmission tasks are broken down into multiple stages. Resources are allocated and adjusted through priority scheduling and real-time load monitoring, generating parallel test pipeline data. Finally, adaptive cache synchronization is implemented on the parallel test pipeline data, allocating an independent cache area to each pipeline. By dynamically adjusting cache size, resolving cache read / write conflicts, and synchronizing the cache states of each pipeline in real time, cache consistency checks are performed on the cache states using a hash check mechanism, and inconsistent states are processed to restore the correct data version, thereby generating channel parallel cache consistency state data.

[0078] Step S3: extracting timing features from the parallel test pipeline data based on the cache coherence state data to obtain parallel test timing feature data; performing streaming calculations on the parallel test timing feature data to obtain real-time abnormality indicator data; constructing a model based on the real-time abnormality indicator data to generate a memory multi-channel fault probability distribution prediction model; importing the parallel test timing feature data into the memory multi-channel fault probability distribution prediction model to perform test fault prediction and generate fault probability prediction data;

[0079] In an embodiment of the present invention, by extracting timing features from parallel test pipeline data based on cache consistency state data, and by analyzing the time changes of the cache state, key timing features such as data transmission delay, read and write rate fluctuations, and cache conflict frequency are extracted. Then, these timing feature data are stream-calculated, and the streaming computing framework is used to process the data in real time, and real-time abnormality indicators such as delay exceedance rate and throughput reduction rate are calculated. Subsequently, based on the real-time abnormality indicator data, a model is constructed, and a suitable machine learning algorithm (such as random forest, XGBoost, etc.) is selected to train a memory multi-channel fault probability distribution prediction model, and a fault prediction model is generated using the abnormal indicator data. Finally, the parallel test timing feature data is imported into the prediction model, and a fault probability prediction is performed to calculate the probability of failure of each channel, and the prediction result is output to identify the possibility of occurrence of memory multi-channel failure.

[0080] Step S4: perform test data collection on the parallel test pipeline data according to the fault probability prediction data to obtain channel parallel actual test data; perform data matching on the channel parallel actual test data and the fault probability prediction data to generate a memory multi-channel parallel test matching report to perform parallel test detection operations.

[0081] In this embodiment of the present invention, test data is collected from parallel test pipeline data based on fault probability prediction data. Actual channel parallel test data is collected from the channels to generate actual channel parallel test data. The actual channel parallel test data is then matched with the fault probability prediction data and compared to ensure consistency between the test data and the prediction results. Finally, a matching report for the memory multi-channel parallel test is generated, which includes the correspondence between the actual test results and the predicted fault probability for each channel, providing support for subsequent parallel test and inspection operations.

[0082] Preferably, step S1 includes the following steps:

[0083] Step S11: obtaining raw data of the memory test channel;

[0084] Step S12: performing data preprocessing on the raw data of the memory test channel to generate standard memory test channel data, wherein the data preprocessing includes data cleaning, data denoising, data missing value filling and data standardization; performing NUMA topology analysis on the standard memory test channel data to generate storage channel node distribution data;

[0085] Step S13: performing node edge computing resource evaluation on the storage channel node distribution data to generate node computing load distribution data; performing dynamic weight calculation on the storage channel nodes based on the node computing load distribution data to obtain channel priority data;

[0086] Step S14: performing resource contention arbitration on the storage channel node distribution data according to the channel priority data to generate channel resource allocation data.

[0087] In an embodiment of the present invention, raw data from 10 test channels are collected from a memory test system. Each channel records the data of the most recent 100 operations, including operation time, resource usage, and access times. In the raw data, 5 records were found to have obvious errors (for example, resource usage was negative), and these abnormal records were directly removed. The resource usage data of each channel was denoised using the average smoothing method. For example, the raw resource usage data of channel 1 was [20, 22, 18, 100, 21], which became [20, 22, 20, 21, 21] after denoising, eliminating the obvious outlier 100. In the record of channel 2, there were 2 missing values in resource usage, which were filled with the average value (25) of the resource usage of the same channel. The resource usage data was normalized to the range of [0, 1]. For example, the resource usage data for channel 1, [20, 22, 20, 21, 21], becomes [0.0, 1.0, 0.0, 0.5, 0.5] after normalization. After data preprocessing, standard memory test channel data is generated. Subsequently, NUMA topology analysis is performed based on this data to determine the distribution relationship between nodes. For example, channel 1 includes three nodes, numbered N1, N2, and N3, with a topological connection relationship of N1 → N2 → N3. The computing load of each node is evaluated. Assuming that the total resource usage of node N1 is 100 units and the actual usage is 60 units, the node load is calculated as: node load = usage ÷ total resource usage = 0.6. The calculated loads for nodes N2 and N3 are 0.7 and 0.5, respectively. Based on the node load values, the dynamic weight of the node is calculated, which is the inverse of the load value. For example, N1's weight is 1 / 0.6 = 1.67, N2's weight is 1 / 0.7 = 1.43, and N3's weight is 1 / 0.5 = 2.00. Priorities are arranged from highest to lowest by weight, resulting in the channel priority data: N3 > N1 > N2. Based on channel priority, a weighted allocation method is used to allocate resources to each node. Assume there are currently 300 units of resources to be allocated: N1's allocation is 1.67 / (1.67 + 1.43 + 2.00) × 300 ≈ 91 units, N2's allocation is 1.43 / (1.67 + 1.43 + 2.00) × 300 ≈ 78 units. N3's allocation is 2.00 / (1.67 + 1.43 + 2.00) × 300 ≈ 131 units. The final allocation results are: N1: 91 units of resources, N2: 78 units of resources, N3: 131 units of resources. Output results: channel resource allocation data, providing a basis for subsequent resource scheduling.

[0088] Preferably, step S14 includes the following steps:

[0089] Step S141: performing resource contention identification on the storage channel node distribution data to obtain channel node resource contention data;

[0090] Step S142: defining arbitration rules for channel node resource competition data based on the first-in-first-out principle to obtain node resource competition arbitration rule data;

[0091] Step S143: performing local resource allocation on the channel node resource contention data according to the node resource contention arbitration rule data to generate node resource allocation data;

[0092] Step S144: using the channel priority data to perform global channel resource allocation adjustment on the node resource allocation data to generate channel resource allocation data.

[0093] In an embodiment of the present invention, resource conflicts are identified by performing contention analysis on node resource usage information in storage channel node distribution data, thereby generating channel node resource contention data. Assume that a storage channel includes three nodes (N1, N2, and N3) and resource requests are as follows: N1 requests 50 units of resources, but actually has 30 units available (contention volume 20 units); N2 requests 40 units of resources, but actually has 20 units available (contention volume 20 units); and N3 requests 60 units of resources, but actually has 50 units available (contention volume 10 units). Based on the first-in-first-out (FIFO) principle, arbitration rules are defined for resource contention, generating node resource contention arbitration rule data. Resource priority is assigned based on the order of node requests: the first requesting node (N1) receives priority; the second requesting node (N2) receives second-best allocation; and the third requesting node (N3) receives last allocation. The node resource contention arbitration rule data is as follows: N1: Priority 1, N2: Priority 2, N3: Priority 3. Based on the arbitration rules, resources are locally allocated to competing nodes, generating node resource allocation data. Assuming the total amount of contended resources is currently 50 units, the following allocations are made according to the arbitration rules: N1 (priority 1) receives 40% of the remaining contended resources (i.e., 20 units). N2 (priority 2) receives 40% of the remaining contended resources (i.e., 20 units). N3 (priority 3) receives 20% of the remaining contended resources (i.e., 10 units). Channel priority data is used to globally adjust node resource allocation data to ensure that allocated resources meet channel priority requirements and generate channel resource allocation data. Assume the channel priority data is: Channel 1 (N1): weight 1.5, Channel 2 (N2): weight 1.2, Channel 3 (N3): weight 1.0. The resources allocated to each node are adjusted based on the weights: N1: allocated resources adjusted to 20 × 1.5 = 30 units, N2: allocated resources adjusted to 20 × 1.2 = 24 units, and N3: allocated resources adjusted to 10 × 1.0 = 10 units. The final channel resource allocation data is used for resource scheduling optimization decisions.

[0094] As an example of the present invention, refer to Figure 2 As shown, in this example, step S2 includes:

[0095] Step S21: performing resource data abstraction on the channel resource allocation data to obtain channel resource allocation abstract data, wherein the resource data abstraction includes device type abstraction, connection relationship abstraction, and address information abstraction; performing topology modeling on the channel resource allocation abstract data to generate resource allocation physical network topology data;

[0096] Step S22: performing control plane mapping on the resource allocation physical network topology data through the SDN controller to generate network topology virtualization data; performing routing demand analysis on the network topology virtualization data to generate routing demand data; performing routing policy optimization processing on the network topology virtualization data based on the routing demand data to generate dynamic routing table data;

[0097] Step S23: performing link aggregation analysis on the dynamic routing table data to generate bandwidth allocation policy data; performing topology adaptive processing on the bandwidth allocation policy data to generate channel interconnection topology data; performing elastic pipeline concurrent scheduling on the channel interconnection topology data to generate parallel test pipeline data;

[0098] Step S24: performing adaptive cache synchronization on the parallel test pipeline data to generate channel parallel cache consistency state data.

[0099] In this embodiment of the present invention, channel resource allocation abstraction data is generated by abstracting the device information, connection relationships, and address information in the channel resource allocation data. Specific devices (such as storage nodes and switches) are abstracted into device categories (such as "storage" and "network." Physical connections (such as cables or wireless) are abstracted into logical connections. Address information is normalized, for example, from specific IP addresses to subnet-level information. Assume that the channel resource allocation data contains the following information: Devices: N1 (storage node), S1 (switch). Connection relationship: N1 ↔ S1 (physical connection). Address information: N1 address is 192.168.1.10, S1 address is 192.168.1.1. After abstraction, the device type is abstracted: N1 → "storage," S1 → "network." The connection relationship is abstracted: N1 ↔ S1 → logical connection. Address information is abstracted: 192.168.1.10 → subnet 192.168.1.0 / 24. Based on the channel resource allocation abstract data, physical network topology data for resource allocation is constructed, including node and connection weights. Nodes: Storage (N1) and Network (S1). Weights: Storage nodes have a weight of 1.5, and network nodes have a weight of 1.2. The SDN controller maps the physical network topology data to the virtualized control plane, generating network topology virtualization data. The SDN controller identifies nodes N1 and S1 and assigns virtual node numbers V1 and V2. Based on the network topology virtualization data, the SDN controller analyzes data traffic and transmission path requirements and generates routing requirements data. The requirements are 100MB of data transmission between nodes V1 and V2, with a traffic flow of 10MB per second and a latency of less than 5ms. Based on the routing requirements data, the virtualized topology is optimized and dynamic routing table data is generated. The path selected is: V1→S1→V2, meeting the rate and latency requirements. Link aggregation is performed on the dynamic routing table data to optimize bandwidth allocation and generate bandwidth allocation policy data. The total bandwidth is 100MB / s. Allocation: 20MB / s is allocated to the path V1→S1→V2, with the remaining bandwidth allocated to other paths. Based on the bandwidth allocation strategy, the network topology is adjusted to generate channel interconnection topology data. Dynamic path adjustment is performed: a redundant path (V1→S2→V2) is added to improve reliability. Using this topology data, a parallel test pipeline is designed and parallel test pipeline data is generated. Test tasks are divided into four parallel pipelines, and the scheduling strategy is task priority queuing. Output: Parallel test pipeline data: Pipelines 1-4: Tasks are allocated in parallel, with high-priority tasks prioritized. Cache synchronization is performed on the parallel test pipeline data to ensure consistency among concurrent tasks. Channel parallel cache consistency state data is generated, and a distributed lock mechanism is used to ensure task state synchronization.

[0100] Preferably, performing flexible pipeline concurrent scheduling on channel interconnection topology data includes:

[0101] Extract key channel features from the channel interconnection topology data to obtain channel interconnection key feature data, where the channel interconnection key feature data includes key node data and channel interconnection link data; perform dependency analysis on the key node data and the channel interconnection link data to generate channel interconnection dependency data;

[0102] Divide the channel interconnection topology data into service units based on the channel interconnection dependency data to generate independent service unit data; segment the channel interconnection topology data into microservices based on the independent service unit data to generate service unit division data;

[0103] Perform service unit containerization on the service unit partition data to generate containerized service unit data; perform container network orchestration on the containerized service unit data to generate unit container network orchestration data; perform container orchestration mapping on the containerized service unit data using the unit container network orchestration data to generate container scheduling policy data;

[0104] Perform concurrent optimization on container scheduling policy data to generate task parallelism data; perform pipeline synchronization on task parallelism data to generate parallel test pipeline data.

[0105] In this embodiment of the present invention, key node data and link data are extracted from the channel interconnection topology data to identify nodes that have a significant impact on network communications (such as high-traffic nodes and low-latency nodes). Information about the links connecting these key nodes, including bandwidth, latency, and stability, is recorded. The channel interconnection topology data is as follows: Nodes: A, B, C, D, and E. Links: AB (10ms, 1Gbps), BC (20ms, 500Mbps), CD (15ms, 800Mbps), and DE (5ms, 2Gbps). Feature extraction is performed to extract key node data for B and D (due to their significant impact due to traffic and latency), and channel interconnection link data for AB, BC, CD, and DE (recording the latency and bandwidth of each link). This key node data and channel interconnection link data are analyzed to generate channel interconnection dependency data, which describes the logical relationships between nodes and links. Node dependency: B is a relay node between C and A, and D is a relay node between C and E. Link dependency: AB and BC rely on the relay capability of B. Based on channel interconnection dependency data, the channel interconnection topology data is divided into independent service units. The service units are divided as follows: Unit 1: Nodes A and B (including link AB). Unit 2: Nodes C and D (including links BC and CD). Unit 3: Node E (including link DE). The independent service unit data is further segmented to generate service unit partitioning data, which is then encapsulated into containers to generate containerized service unit data. Unit 1 → container C1, unit 2 → container C2, and unit 3 → container C3. Based on the containerized service unit data, communication rules and data transmission paths between containers are defined to generate unit container network orchestration data. The container communication rules are as follows: C1 → C2: Priority channel with a bandwidth limit of 500 Mbps. C2 → C3: Redundant path with a latency of <15 ms. Container scheduling policy data is generated based on the unit container network orchestration data, including task allocation priorities and execution policies. Priority tasks: Tasks with high bandwidth requirements are assigned to the C1 → C2 channel. Normal tasks: Tasks with low latency requirements are assigned to the C2 → C3 channel. Based on the container scheduling policy data, the task parallelism is optimized and task parallelism data is generated. High-priority task parallelism: 4. Normal task parallelism: 2. The task parallelism data is synchronized across the pipeline to ensure data consistency and generate parallel test pipeline data. Pipeline structure: Stage 1: C1 → C2. Stage 2: C2 → C3. Stage parallel synchronization is complete, and the task allocation consistency check passes.

[0106] Preferably, concurrent optimization of container scheduling policy data includes:

[0107] Perform policy execution on the container scheduling policy data to generate container scheduling policy execution data; perform scheduling node screening on the storage channel node distribution data based on the container scheduling policy execution data to obtain the policy execution scheduling node; perform scheduling timestamp analysis on the policy execution scheduling node to generate the node scheduling timestamp;

[0108] According to the node scheduling timestamp, the strategy execution scheduling nodes are divided into nodes with timestamp differences, and concurrent synchronous timestamp node data and concurrent non-synchronous timestamp node data are generated; the concurrent synchronous timestamp node data are batch processed for node tasks, and a concurrent synchronous node task batch processing strategy is generated;

[0109] Perform concurrent timestamp calibration on the data of the concurrent non-synchronous timestamp node and the concurrent synchronous timestamp node to obtain concurrent timestamp calibration data; based on the concurrent timestamp calibration data, perform transaction rollback within the difference timestamp on the concurrent non-synchronous timestamp node to generate a non-concurrent synchronous node task rollback strategy;

[0110] The concurrent synchronization node task batch processing strategy and the non-concurrent synchronization node task rollback strategy are used to concurrently optimize the container scheduling strategy data and generate task parallelism data.

[0111] In this embodiment of the present invention, container scheduling policy execution data is generated by executing operations on container scheduling policy data and recording the specific scheduling status of each node. The container scheduling policy includes the following rules: Priority tasks are assigned to node group {N1, N2}. Normal tasks are assigned to node group {N3, N4}. Based on the container scheduling policy execution data, storage channel node distribution data is filtered to determine the execution scheduling nodes. The filtering results are: policy execution scheduling nodes: N1, N2, N3, N4. Timestamp analysis is performed on the policy execution scheduling nodes, recording task start time, end time, delay, and other information for each node to generate node scheduling timestamp data. N1: Start time T1, end time T2, delay 5ms. N2: Start time T3, end time T4, delay 3ms. N3: Start time T5, end time T6, delay 7ms. N4: Start time T7, end time T8, delay 6ms. Based on the differences in node scheduling timestamps, nodes are divided into concurrent synchronous timestamp nodes and concurrent asynchronous timestamp nodes. Synchronous timestamp nodes: N1 and N2 (latency difference less than 2ms), asynchronous timestamp nodes: N3 and N4 (latency difference greater than 2ms). Data from concurrent synchronized timestamp nodes is batched to optimize node task execution efficiency and generate a batch processing strategy for concurrent synchronized node tasks. The batch processing strategy merges tasks from N1 and N2, processing high-priority tasks uniformly. The merged tasks are executed in a priority queue: {N1, N2}. Timestamps are aligned between data from concurrent asynchronous timestamp nodes and data from concurrent synchronized timestamp nodes to ensure consistent task execution and generate concurrent timestamp alignment data. The alignment method adjusts the execution times of N3 and N4 to synchronize them with N1 and N2. For concurrent asynchronous timestamp nodes, tasks are rolled back to a safe state based on the alignment data. A rollback strategy for asynchronous tasks is generated, with the rollback scope covering the task states of N3 and N4. The rollback strategy resets tasks to times T5 and T7. The batch processing strategy and rollback strategy are used to comprehensively optimize container scheduling policy data and generate task parallelism data. The parallelism of synchronous execution tasks is 4 (including N1 and N2), and the parallelism of asynchronous execution tasks is 2 (including N3 and N4).

[0112] Preferably, performing adaptive cache synchronization on parallel test pipeline data includes:

[0113] Perform distributed cache stratification on parallel test pipeline data to generate cache hierarchy data; perform memory queue optimization on cache hierarchy data to generate queue scheduling strategy data;

[0114] The queue scheduling policy data is processed by consistency protocol to generate synchronization state machine data; conflict detection is performed on the synchronization state machine data. When a conflict is detected in the synchronization state machine data, the conflicting data is merged to generate cache consistency state data.

[0115] In an embodiment of the present invention, distributed caching is performed on parallel test pipeline data, and cache levels are divided according to data access frequency and characteristics to generate cache hierarchy data. Level 1 cache: high-frequency access data (task metadata, status data). Level 2 cache: medium-frequency access data (intermediate result data). Level 3 cache: low-frequency access data (historical test pipeline data). Load analysis is performed on queues at each level of the cache hierarchy data to evaluate the read and write pressure and occupancy of the queues: Level 1 cache queue: frequent reads and fewer writes; Level 2 cache queue: balanced read and write; Level 3 cache queue: fewer reads and more writes. Based on the load analysis results, the priority and allocation strategy of the memory queue are adjusted to generate queue scheduling strategy data: Level 1 cache queue: prioritize allocating more memory and enabling asynchronous write strategy. Level 2 cache queue: evenly allocate memory and enable read-write balance strategy. Level 3 cache queue: enable delayed write strategy to reduce real-time occupancy. Perform consistency protocol processing on the queue scheduling policy data, build a synchronization mechanism, generate synchronized state machine data, use a distributed consistency protocol (such as Paxos or Raft) to ensure that each cache layer is synchronized and consistent across multiple nodes, and record transaction logs of state changes to support rollback. Detect the synchronized state machine data to determine whether there is conflicting data caused by concurrent writes from multiple nodes. Conflict conditions: two or more nodes modify the same cache key at the same time or the order of state changes is inconsistent. When a conflict is detected in the synchronized state machine data, merge the conflicting data based on the timestamp priority or the last write rule to generate cache consistency state data. Conflict merge rule: Use the data with the newer timestamp. If the timestamps are the same, select according to the write priority (node ID). Output: Cache consistency state data: Key_1 merge completed, Key_2 merge completed.

[0116] As an example of the present invention, refer to Figure 3 As shown, in this example, step S3 includes:

[0117] Step S31: extracting timing features of the parallel test pipeline data based on the cache coherence state data to obtain parallel test timing feature data;

[0118] Step S32: Perform streaming calculation on the parallel test time series feature data to obtain real-time abnormality indicator data; divide the real-time abnormality indicator data into data sets to generate a model training set and a model test set;

[0119] Step S33: training the model training set using a long short-term memory neural network algorithm to generate a memory multi-channel fault probability distribution prediction pre-model; optimizing and iterating the memory multi-channel fault probability distribution prediction pre-model using a model test set to generate a memory multi-channel fault probability distribution prediction model;

[0120] Step S34: importing the parallel test timing feature data into the memory multi-channel fault probability distribution prediction model to perform test fault prediction and generate fault probability prediction data.

[0121] In this embodiment of the present invention, parallel test pipeline data is cleaned and normalized based on cache coherence state data to remove invalid or missing data points and normalize the data to a uniform range (e.g., [0, 1]). A sliding window mechanism is used to extract time series features from parallel tests, generating parallel test timing feature data. Features include task latency, queue length, read / write rate, and data consistency update frequency. Specifically, the sliding window size is 10 seconds. Extracted features include queue length mean of 20 and latency standard deviation of 2 milliseconds. Real-time streaming computation is performed on the parallel test timing feature data to generate real-time anomaly indicator data. Anomalous fluctuations are detected using sliding mean and standard deviation calculations. Threshold conditions are: latency > mean + 3 × standard deviation, queue length > 95th percentile. Anomaly detected: timestamp 2024-12-12T12:00:15, metric: latency 50 milliseconds (abnormal). The real-time anomaly indicator data is divided into a training set and a test set: 80% for model training and 20% for model testing. A long short-term memory (LSTM) neural network was used to train the model training set to generate a pre-model for predicting the probability distribution of multi-channel memory failures. The network architecture was a 3-layer LSTM with 128 units. The optimization algorithm was Adam with a learning rate of 0.001. The pre-model was iteratively optimized using the model test set, adjusting the learning rate and model parameters to reduce overfitting. The stopping condition was convergence of the test set loss (change < 0.001). Parallel test timing feature data was imported into the prediction model to perform test failure predictions, generate failure probability prediction data, and output the multi-channel failure probability distribution for each time step. Input data included a 10 millisecond latency, a queue length of 15, and a read / write rate of 5 MB / s. The prediction output was: Time step 1 (one second into the future): channel 1 failure probability 0.01, channel 2 failure probability 0.03. Time step 2 (two seconds into the future): channel 1 failure probability 0.02, channel 2 failure probability 0.05.

[0122] Preferably, step S4 includes the following steps:

[0123] Step S41: Generate test signals for the parallel test pipeline data according to the fault probability prediction data to obtain channel parallel test signals; collect test data for the channel parallel test signals to obtain channel parallel actual test data;

[0124] Step S42: Perform data matching calculation on the channel parallel actual test data and the fault probability prediction data to obtain channel parallel test matching data; perform data visualization on the channel parallel test matching data to generate a memory multi-channel parallel test matching report to perform parallel test detection operations.

[0125] In an embodiment of the present invention, channel parallel test signals are designed and generated based on failure probability prediction data to stimulate parallel testing of memory channels. Test signal types include random read and write operations and load stress test signals. Signal generation logic dynamically adjusts test intensity based on the failure probability of each channel. For high-failure probability channels, the proportion of high-load random signals is increased, while for low-failure probability channels, the basic test signals are maintained. Specifically, channel 1 (failure probability 0.3) generates high-load read and write signals (80% random read and write, 20% sequential read and write). Channel 2 (failure probability 0.1) generates medium-load signals (50% random read and write, 50% sequential read and write). Output channel parallel test signals describe the strength, type, and timing of each channel's test signal. Test signals are executed through a parallel test pipeline, and the operating status of each channel is collected in real time to generate actual channel parallel test data. Collection metrics include read and write latency, throughput, error rate, data consistency status, etc. Collection tools: A logging system and performance monitoring tool based on distributed memory nodes. Specifically, channel 1 has a read / write latency of 12 milliseconds and an error rate of 0.05%, while channel 2 has a read / write latency of 8 milliseconds and an error rate of 0.01%. The actual channel parallel test data is matched with the failure probability prediction data to generate channel parallel test matching data. The actual test value at each time step is compared with the predicted value to calculate the matching deviation and accuracy. Deviation: D = |P−A|; where P is the predicted value, A is the actual value, and D is the deviation. Accuracy: R = 1−D÷A. Channel 1: predicted latency 10 milliseconds, actual latency 12 milliseconds, deviation 2 milliseconds, accuracy 83%. Channel 2: predicted latency 8 milliseconds, actual latency 8 milliseconds, deviation 0 milliseconds, accuracy 100%. Output channel parallel test matching data: matching deviation and accuracy for each channel. Data visualization of the channel parallel test matching data is performed to generate a memory multi-channel parallel test matching report. The visualization content includes a matching deviation heat map: showing the matching deviation of each channel at different time steps; an accuracy trend chart: a curve chart showing the matching accuracy of each channel changing over time; and an output memory multi-channel parallel test matching report: summarizing the test results in the form of tables and charts for executing subsequent parallel test detection tasks.

[0126] In this specification, a memory-based multi-channel parallel testing system is provided for executing the above-mentioned memory-based multi-channel parallel testing method. The memory-based multi-channel parallel testing system includes:

[0127] A channel resource allocation module is configured to obtain raw data from a memory test channel; perform topological analysis on the raw data to generate memory channel node distribution data; perform dynamic weight calculation on the memory channel node distribution data to obtain channel priority data; perform resource competition arbitration on the memory channel node distribution data based on the channel priority data to generate channel resource allocation data;

[0128] The concurrent scheduling module is used to perform control plane mapping on channel resource allocation data to generate network topology virtualization data; perform routing policy optimization processing on network topology virtualization data to generate dynamic routing table data; perform elastic pipeline concurrent scheduling on dynamic routing table data to generate parallel test pipeline data; perform adaptive cache synchronization on parallel test pipeline data to generate channel parallel cache consistency state data;

[0129] A fault prediction module is used to extract timing features from parallel test pipeline data based on cache consistency state data to obtain parallel test timing feature data; perform streaming calculations on the parallel test timing feature data to obtain real-time abnormality indicator data; construct a model based on the real-time abnormality indicator data to generate a memory multi-channel fault probability distribution prediction model; import the parallel test timing feature data into the memory multi-channel fault probability distribution prediction model to perform test fault prediction and generate fault probability prediction data;

[0130] The parallel test module is used to collect test data for the parallel test pipeline data according to the fault probability prediction data to obtain the actual channel parallel test data; match the actual channel parallel test data with the fault probability prediction data to generate a memory multi-channel parallel test matching report to perform parallel test detection operations.

[0131] The beneficial effects of the present invention are that through topology analysis and dynamic weight calculation, resources can be accurately allocated to each storage channel, avoiding resource conflicts and unnecessary delays, ensuring faster response times for high-priority channels, and improving overall system performance. Through network topology virtualization and route optimization, efficient and smooth data transmission is ensured, the risk of network congestion is reduced, and the reliability of data transmission is improved. Through adaptive cache synchronization in the parallel test pipeline, data consistency between multiple test channels is ensured, test errors caused by cache inconsistencies are avoided, and the stability of parallel testing is improved. Through timing feature extraction and streaming computing, potential faults in the system can be detected and predicted in real time. By constructing a multi-channel memory fault probability distribution prediction model, potential faults can be warned in advance, improving system reliability. By matching fault probability prediction data with actual test data, a parallel test matching report is generated, providing an accurate execution basis for parallel test operations of the memory, helping to reduce test time and cost, while also improving the accuracy of fault detection. Therefore, the present invention improves the efficiency and accuracy of multi-channel parallel testing of memory by optimizing channel resource allocation, topology virtualization management, flexible scheduling synchronization, fault prediction, and data matching.

[0132] The present invention is therefore intended to be illustrative and non-restrictive in all respects, with the scope of the invention being defined by the appended claims rather than the foregoing description, and all changes that come within the meaning and range of equivalents of the application documents are intended to be embraced therein.

[0133] The foregoing description is intended only to provide specific embodiments of the present invention, which will enable those skilled in the art to understand and implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not intended to be limited to the embodiments shown herein, but is to be construed in the widest possible manner consistent with the principles and novel features disclosed herein.

Claims

1. A memory-based multi-channel parallel testing method, characterized in that: The following steps are involved: Step S1: Obtaining raw data of the memory test channel; Perform topological analysis on the original data of the memory test channel to generate the memory channel node distribution data; Perform dynamic weight calculation on the storage channel node distribution data to obtain channel priority data; Perform resource competition arbitration on the storage channel node distribution data according to the channel priority data to generate channel resource allocation data; Step S2: performing control plane mapping on the channel resource allocation data to generate network topology virtualization data; Optimize routing strategies for network topology virtualization data to generate dynamic routing table data; perform elastic pipeline concurrent scheduling on dynamic routing table data to generate parallel test pipeline data; Adaptively synchronize cache data for parallel test pipelines to generate channel parallel cache consistency state data; Step S3: extracting timing features of the parallel test pipeline data based on the cache coherence state data to obtain parallel test timing feature data; Perform streaming calculations on parallel test time series feature data to obtain real-time abnormal indicator data; Build a model based on real-time abnormal indicator data to generate a memory multi-channel fault probability distribution prediction model; import parallel test timing feature data into the memory multi-channel fault probability distribution prediction model to perform test fault prediction and generate fault probability prediction data; Step S4: collecting test data from the parallel test pipeline data based on the fault probability prediction data to obtain actual channel parallel test data; The actual channel parallel test data and the fault probability prediction data are matched to generate a memory multi-channel parallel test matching report to perform parallel test detection operations.

2. The memory-based multi-channel parallel testing method according to claim 1, characterized in that: Step S1 includes the following steps: Step S11: obtaining raw data of the memory test channel; Step S12: performing data preprocessing on the raw data of the memory test channel to generate standard memory test channel data, wherein the data preprocessing includes data cleaning, data denoising, data missing value filling and data standardization; performing NUMA topology analysis on the standard memory test channel data to generate storage channel node distribution data; Step S13: performing node edge computing resource evaluation on the storage channel node distribution data to generate node computing load distribution data; performing dynamic weight calculation on the storage channel nodes based on the node computing load distribution data to obtain channel priority data; Step S14: performing resource contention arbitration on the storage channel node distribution data according to the channel priority data to generate channel resource allocation data.

3. The memory-based multi-channel parallel testing method according to claim 2, characterized in that: Step S14 includes the following steps: Step S141: performing resource contention identification on the storage channel node distribution data to obtain channel node resource contention data; Step S142: defining arbitration rules for channel node resource competition data based on the first-in-first-out principle to obtain node resource competition arbitration rule data; Step S143: performing local resource allocation on the channel node resource contention data according to the node resource contention arbitration rule data to generate node resource allocation data; Step S144: using the channel priority data to perform global channel resource allocation adjustment on the node resource allocation data to generate channel resource allocation data.

4. The memory-based multi-channel parallel testing method according to claim 1, characterized in that: Step S2 includes the following steps: Step S21: performing resource data abstraction on the channel resource allocation data to obtain channel resource allocation abstract data, wherein the resource data abstraction includes device type abstraction, connection relationship abstraction, and address information abstraction; performing topology modeling on the channel resource allocation abstract data to generate resource allocation physical network topology data; Step S22: performing control plane mapping on the resource allocation physical network topology data through the SDN controller to generate network topology virtualization data; performing routing demand analysis on the network topology virtualization data to generate routing demand data; performing routing policy optimization processing on the network topology virtualization data based on the routing demand data to generate dynamic routing table data; Step S23: performing link aggregation analysis on the dynamic routing table data to generate bandwidth allocation policy data; performing topology adaptive processing on the bandwidth allocation policy data to generate channel interconnection topology data; performing elastic pipeline concurrent scheduling on the channel interconnection topology data to generate parallel test pipeline data; Step S24: performing adaptive cache synchronization on the parallel test pipeline data to generate channel parallel cache consistency state data.

5. The memory-based multi-channel parallel testing method according to claim 4, characterized in that: Flexible pipeline concurrent scheduling of channel interconnect topology data includes: Extract key channel features from the channel interconnection topology data to obtain channel interconnection key feature data, where the channel interconnection key feature data includes key node data and channel interconnection link data; perform dependency analysis on the key node data and the channel interconnection link data to generate channel interconnection dependency data; Divide the channel interconnection topology data into service units based on the channel interconnection dependency data to generate independent service unit data; segment the channel interconnection topology data into microservices based on the independent service unit data to generate service unit division data; Perform service unit containerization on the service unit partition data to generate containerized service unit data; perform container network orchestration on the containerized service unit data to generate unit container network orchestration data; perform container orchestration mapping on the containerized service unit data using the unit container network orchestration data to generate container scheduling policy data; Perform concurrent optimization on container scheduling policy data to generate task parallelism data; perform pipeline synchronization on task parallelism data to generate parallel test pipeline data.

6. The memory-based multi-channel parallel testing method according to claim 5, characterized in that: Concurrency optimization of container scheduling policy data includes: Perform policy execution on the container scheduling policy data to generate container scheduling policy execution data; perform scheduling node screening on the storage channel node distribution data based on the container scheduling policy execution data to obtain the policy execution scheduling node; perform scheduling timestamp analysis on the policy execution scheduling node to generate the node scheduling timestamp; According to the node scheduling timestamp, the strategy execution scheduling nodes are divided into nodes with timestamp differences, and concurrent synchronous timestamp node data and concurrent non-synchronous timestamp node data are generated; the concurrent synchronous timestamp node data are batch processed for node tasks, and a concurrent synchronous node task batch processing strategy is generated; Perform concurrent timestamp calibration on the data of the concurrent non-synchronous timestamp node and the concurrent synchronous timestamp node to obtain concurrent timestamp calibration data; based on the concurrent timestamp calibration data, perform transaction rollback within the difference timestamp on the concurrent non-synchronous timestamp node to generate a non-concurrent synchronous node task rollback strategy; The concurrent synchronization node task batch processing strategy and the non-concurrent synchronization node task rollback strategy are used to concurrently optimize the container scheduling strategy data and generate task parallelism data.

7. The memory-based multi-channel parallel testing method according to claim 4, characterized in that: Adaptive cache synchronization of parallel test pipeline data includes: Perform distributed cache stratification on parallel test pipeline data to generate cache hierarchy data; perform memory queue optimization on cache hierarchy data to generate queue scheduling strategy data; The queue scheduling policy data is processed by consistency protocol to generate synchronization state machine data; conflict detection is performed on the synchronization state machine data. When a conflict is detected in the synchronization state machine data, the conflicting data is merged to generate cache consistency state data.

8. The memory-based multi-channel parallel testing method according to claim 1, characterized in that: Step S3 includes the following steps: Step S31: extracting timing features of the parallel test pipeline data based on the cache coherence state data to obtain parallel test timing feature data; Step S32: Perform streaming calculation on the parallel test time series feature data to obtain real-time abnormality indicator data; divide the real-time abnormality indicator data into data sets to generate a model training set and a model test set; Step S33: training the model training set using a long short-term memory neural network algorithm to generate a memory multi-channel fault probability distribution prediction pre-model; optimizing and iterating the memory multi-channel fault probability distribution prediction pre-model using a model test set to generate a memory multi-channel fault probability distribution prediction model; Step S34: importing the parallel test timing feature data into the memory multi-channel fault probability distribution prediction model to perform test fault prediction and generate fault probability prediction data.

9. The memory-based multi-channel parallel testing method according to claim 1, characterized in that: Step S4 includes the following steps: Step S41: Generate test signals for the parallel test pipeline data according to the fault probability prediction data to obtain channel parallel test signals; collect test data for the channel parallel test signals to obtain channel parallel actual test data; Step S42: Perform data matching calculation on the channel parallel actual test data and the fault probability prediction data to obtain channel parallel test matching data; perform data visualization on the channel parallel test matching data to generate a memory multi-channel parallel test matching report to perform parallel test detection operations.

10. A memory-based multi-channel parallel test system, characterized in that: For executing the memory-based multi-channel parallel testing method according to claim 1, the memory-based multi-channel parallel testing system comprises: A channel resource allocation module is configured to obtain raw data from a memory test channel; perform topological analysis on the raw data to generate memory channel node distribution data; perform dynamic weight calculation on the memory channel node distribution data to obtain channel priority data; perform resource competition arbitration on the memory channel node distribution data based on the channel priority data to generate channel resource allocation data; The concurrent scheduling module is used to perform control plane mapping on channel resource allocation data to generate network topology virtualization data; perform routing policy optimization processing on network topology virtualization data to generate dynamic routing table data; perform elastic pipeline concurrent scheduling on dynamic routing table data to generate parallel test pipeline data; perform adaptive cache synchronization on parallel test pipeline data to generate channel parallel cache consistency state data; A fault prediction module is used to extract timing features from parallel test pipeline data based on cache consistency state data to obtain parallel test timing feature data; perform streaming calculations on the parallel test timing feature data to obtain real-time abnormality indicator data; construct a model based on the real-time abnormality indicator data to generate a memory multi-channel fault probability distribution prediction model; import the parallel test timing feature data into the memory multi-channel fault probability distribution prediction model to perform test fault prediction and generate fault probability prediction data; The parallel test module is used to collect test data for the parallel test pipeline data according to the fault probability prediction data to obtain the actual channel parallel test data; match the actual channel parallel test data with the fault probability prediction data to generate a memory multi-channel parallel test matching report to perform parallel test detection operations.

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