PCIE physical layer test method, system, apparatus and device, and storage medium

Abstract

The embodiment of the invention discloses a PCIE physical layer test method, system, device and equipment and a storage medium, in the method, on one hand, delay parameter configuration is carried out on each communication link, the delay difference of transmission signals between different chips can be compensated, so that synchronous sampling of the transmission signals in each communication link by a receiving end is realized, and the reliability of the communication link is improved; the risk of wrong signal acquisition or wrong shooting is avoided; and on the other hand, the receiving cache is cleaned in time when the clock is switched, so that the risk of link establishment failure caused by overflow of the receiving cache can be avoided, and the function test performed on the PCIE physical layer through the third-party PCIE controller can be more accurate.

Description

Technical Field

[0001] The present application relates to the technical field of PCIE physical layer testing, and in particular to a PCIE physical layer testing method, system, device, equipment and storage medium. Background Art

[0002] Currently, in integrated circuit design, the design of PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) is divided into a controller and a PHY (Physical Layer). Normally, the PHY and the controller are used and tested together, but in some special cases, the controller or PHY may need to be tested separately.

[0003] In the related art, the PHY is usually functionally tested through a third-party PCIE controller. However, when the PHY is functionally tested through a third-party PCIE controller, there is a risk of parallel signal acquisition errors or mis-beats, as well as a risk of PCIE link establishment failure, which makes the functional test of the PCIE physical layer inaccurate. Summary of the invention

[0004] To solve the above technical problems, the embodiments of the present application provide a PCIE physical layer testing method, system, device, equipment and storage medium, so as to more accurately perform functional testing on the PCIE physical layer.

[0005] According to one aspect of an embodiment of the present application, a method for testing a PCIE physical layer is provided, which is applied to a test system, wherein the test system includes a component under test and a test component, wherein the component under test includes a test piece provided with a PCIE physical layer, and the test component includes a third-party PCIE controller, and the third-party PCIE controller is used to perform a functional test on the PCIE physical layer; the method includes: obtaining a test requirement of the component under test; when the test requirement includes testing a transmission function of the component under test, performing delay parameter configuration on each communication link between the third-party PCIE controller and the PCIE physical layer to achieve synchronous sampling of transmission signals in each communication link by a receiving end; when the test requirement includes testing a link establishment function of the component under test, performing reset control on a first data buffer corresponding to the component under test and a second data buffer corresponding to the test component to clear data received by the first data buffer and the second data buffer during a clock frequency switching process; wherein the first data buffer is used to receive data sent by the test component, and the second data buffer is used to receive data sent by the component under test.

[0006] In some embodiments, the component under test also includes a first control module, which is arranged between the PCIE physical layer and the third-party PCIE controller, and the test component also includes a second control module, which is connected to the third-party PCIE controller; the delay parameters of each communication link between the third-party PCIE controller and the PCIE physical layer include a first delay parameter; the first delay parameter is used to adjust the delay time of the transmission signal in each communication link; the delay parameter configuration of each communication link between the third-party PCIE controller and the PCIE physical layer to achieve synchronous sampling of the transmission signal in each communication link by the receiving end includes: performing pseudo-random number training through the first control module and the second control module to obtain the first delay parameter; wherein the pseudo-random number training is used to determine the first delay parameter of each communication link between the third-party PCIE controller and the PCIE physical layer; and configuring the first delay parameter to the parameter register corresponding to each transmission signal in each communication link.

[0007] In some embodiments, the pseudo-random number training is performed by the first control module and the second control module to obtain the first delay parameter, including: performing initial delay parameter configuration on the first control module according to a preset delay parameter sequence; wherein the delay parameter sequence includes a plurality of preset delay times sorted according to an arithmetic progression; the first control module and the second control module after configuring the delay parameters send pseudo-random numbers to each other, and verify the received pseudo-random numbers to obtain a data verification result sequence; wherein the data verification result sequence includes data verification results corresponding to each of the preset delay times, and each data verification result Arrange in the order of the preset delay times in the delay parameter sequence; determine the first critical value and the second critical value corresponding to the effective sampling window according to the data verification result sequence; wherein the first critical value is used to characterize the preset delay time configured by the first control module from data verification success to data verification failure in the data verification result sequence; the second critical value is used to characterize the preset delay time configured by the first control module from data verification failure to data verification success; determine the first delay parameter of each transmission signal in each communication link according to the first critical value and the second critical value.

[0008] In some embodiments, the delay parameters of each communication link between the third-party PCIE controller and the PCIE physical layer also include a second delay parameter; the second delay parameter is used to adjust the number of delay bits of the transmission signal in each communication link; the delay parameter configuration of each communication link between the third-party PCIE controller and the PCIE physical layer to achieve synchronous sampling of the transmission signal in each communication link by the receiving end includes: performing constant training through the first control module and the second control module to obtain the second delay parameter; wherein the constant training is used to determine the second delay parameter of each communication link between the third-party PCIE controller and the PCIE physical layer; and configuring the second delay parameter to the parameter register corresponding to each transmission signal in each communication link.

[0009] In some embodiments, the constant training is performed by the first control module and the second control module to obtain the second delay parameter, including: configuring the delay parameters of the first control module according to a preset number of delay bits; the first control module and the second control module after configuring the delay parameters exchange constants to obtain a data reception result; wherein the data reception result includes the received data of each communication link under the preset number of delay bits; determining reference data and a flag bit in the reference data from the data reception result; comparing all received data in the data reception result with the flag bit in the reference data respectively to obtain a relative delay difference between all received data and the flag bit in the reference data; and determining the second delay parameter of each transmission signal in each communication link according to the relative delay difference.

[0010] In some embodiments, the test component further includes a third control module, and the third control module is connected to the third-party PCIE controller; The resetting control of the first data buffer corresponding to the component under test and the second data buffer corresponding to the test component to clear the data received by the first data buffer and the second data buffer during the clock frequency switching process includes: sending a rate signal to the component under test through the test component, and generating a second reset signal to reset the second data buffer; wherein the rate signal is used to trigger the third control module to switch the clock frequency of the PCIE physical layer and the third-party PCIE controller, and the second reset signal is used to restore the second data buffer to an initial state; when the component under test receives the rate signal sent by the test component, generating a first reset signal to reset the first data buffer; wherein the first reset signal is used to restore the first data buffer to an initial state; when the component under test and the test component complete the clock frequency switching, canceling the first reset signal and the second reset signal.

[0011] In some embodiments, the method further includes: after the component under test and the test component complete the clock frequency switching, sending a clock gating signal to the test component through the component under test, so that the clock frequencies after the switching of the PCIE physical layer and the third-party PCIE controller can take effect at the same time; wherein, the clock gating signal is used to indicate the clock status of the PCIE physical layer and the third-party PCIE controller; when the clock gating signal is a first preset level, the clock status is a valid state, and when the clock gating signal is a second preset level, the clock status is an invalid state.

[0012] According to one aspect of an embodiment of the present application, a test system for a PCIE physical layer is provided, comprising: a component under test, comprising a test piece provided with a PCIE physical layer; a test component, comprising a third-party PCIE controller; the test component is used to obtain the test requirements of the component under test, and when the test requirements include the transmission function of the component under test, the delay parameters of each communication link between the third-party PCIE controller and the PCIE physical layer are configured to achieve synchronous sampling of the transmission signals in each communication link by the receiving end; and when the test requirements include testing the link establishment function of the component under test, the first data buffer corresponding to the component under test and the second data buffer corresponding to the test component are reset and controlled to clear the data received by the first data buffer and the second data buffer during the clock frequency switching process; wherein the first data buffer is used to receive data sent by the test component, and the second data buffer is used to receive data sent by the component under test.

[0013] In some embodiments, the component under test also includes a first control module, which is arranged between the PCIE physical layer and the third-party PCIE controller; the test component includes a first test component, which includes the third-party PCIE controller and a second control module; the first control module and the second control module are used to configure delay parameters of each communication link between the third-party PCIE controller and the PCIE physical layer to achieve synchronous sampling of transmission signals in each communication link by the receiving end.

[0014] In some embodiments, the first test component also includes a third control module, which is connected to the third-party PCIE controller; the third control module is used to reset the first data buffer corresponding to the component under test and the second data buffer corresponding to the test component to clear the data received by the first data buffer and the second data buffer during the clock frequency switching process.

[0015] In some embodiments, the test component also includes a second test component; the second test component is used to obtain the test requirements of the component under test, and call the corresponding test case according to the test requirements to perform functional testing on the component under test.

[0016] According to one aspect of an embodiment of the present application, a test device for a PCIE physical layer is provided, which is applied to a test system, wherein the test system includes a component under test and a test component, wherein the component under test includes a test piece provided with a PCIE physical layer, and the test component includes a third-party PCIE controller, and the third-party PCIE controller is used to perform a functional test on the PCIE physical layer; the device includes: an acquisition module, configured to acquire a test requirement of the component under test; a configuration module, configured to, when the test requirement includes testing a transmission function of the component under test, perform delay parameter configuration on each communication link between the third-party PCIE controller and the PCIE physical layer, so as to achieve synchronous sampling of transmission signals in each communication link by a receiving end; a control module, configured to, when the test requirement includes testing a link establishment function of the component under test, perform reset control on a first data buffer corresponding to the component under test and a second data buffer corresponding to the test component, so as to clear data received by the first data buffer and the second data buffer during a clock frequency switching process; wherein the first data buffer is used to receive data sent by the test component, and the second data buffer is used to receive data sent by the component under test.

[0017] According to one aspect of an embodiment of the present application, an electronic device is provided, comprising: one or more processors; and a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the electronic device implements the PCIE physical layer testing method as described above.

[0018] According to one aspect of an embodiment of the present application, a computer-readable storage medium is provided, on which computer-readable instructions are stored. When the computer-readable instructions are executed by a processor of a computer, the computer executes the PCIE physical layer test method as described above.

[0019] In the technical solution provided in the embodiments of the present application, on the one hand, by configuring the delay parameters of each communication link, the delay difference of the transmission signal between different chips can be compensated, thereby realizing the synchronous sampling of the transmission signal in each communication link by the receiving end, avoiding the risk of signal acquisition error or wrong beat; on the other hand, by clearing the receiving buffer in time when the clock is switched, the risk of link establishment failure caused by the overflow of the receiving buffer can be avoided, so that the functional test of the PCIE physical layer performed by the third-party PCIE controller can be more accurate.

[0020] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings: Figure 1 It is a structural schematic diagram of a PCIE physical layer test system shown in an exemplary embodiment of the present application; Figure 2 is a schematic structural diagram of a component under test shown in an exemplary embodiment of the present application; Figure 3 is a structural schematic diagram of a first test component shown in an exemplary embodiment of the present application; Figure 4 is a structural schematic diagram of a second test component shown in an exemplary embodiment of the present application; Figure 5 is a flow chart of a method for testing a PCIE physical layer shown in an exemplary embodiment of the present application; Figure 6 yes Figure 5Step S520 in the illustrated embodiment is a flow chart of configuring delay parameters in an exemplary embodiment; Figure 7 yes Figure 6 Step S610 in the illustrated embodiment is a flow chart of performing pseudo-random number training in an exemplary embodiment; Figure 8 yes Figure 5 Step S520 in the illustrated embodiment is a flow chart of configuring delay parameters in another exemplary embodiment; Fig. 9 yes Figure 8 Step S810 in the illustrated embodiment is a flow chart of performing constant training in an exemplary embodiment; Fig.10 yes Figure 5 Step S530 in the illustrated embodiment is a flow chart of resetting control of the first data buffer and the second data buffer in an exemplary embodiment; Fig.11 is a timing diagram of clock switching management shown in an exemplary embodiment of the present application; Fig.12 is an application schematic diagram of clock switching management shown in an exemplary embodiment of the present application; Fig.13 is a structural schematic diagram of a test device for a PCIE physical layer shown in an exemplary embodiment of the present application; Fig.14 A schematic diagram of the structure of a computer system suitable for implementing an electronic device of an embodiment of the present application is shown.

[0022] Figure numerals: 110: component under test; 111: test piece provided with PCIE physical layer; 112: first control module; 113: on-chip processor; 114: on-chip PCIE controller; 120: test component; 121: first test component; 1210: IO interface; 1211: data selection module; 1212: second control module; 1213: test module; 1214: third-party PCIE controller; 1215: third-party QDMA controller; 1216: register module; 1217: data storage and test module; 1218: third control module; 1219: first serial port communication controller; 1220: second serial port communication controller; 122: second test component; 1221: PCIE-RC controller; 1222: third-party PCIE physical layer; 1223: test interface; 1224: test case module; 130: external debugging computer. DETAILED DESCRIPTION

[0023] Here, exemplary embodiments will be described in detail, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments that are the same as the present application. Instead, they are only examples of devices and methods that are the same as some aspects of the present application as detailed in the attached claims.

[0024] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in the form of an application program, or in one or more hardware modules or integrated circuits, or in different models and / or processor devices and / or microcontroller devices.

[0025] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0026] It should be noted that the "multiple" mentioned in this application refers to two or more than two. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship.

[0027] Currently, in integrated circuit design, the design of PCIE (Peripheral Component Interconnect Express) is divided into controller and PHY (Physical Layer). Usually, PHY and controller are used and tested together, but in some special cases, it may be necessary to test the controller or PHY separately.

[0028] In the related art, the functional test of PHY is usually performed through a third-party PCIE controller. However, when the functional test of PHY is performed through a third-party PCIE controller, there is a risk of parallel signal acquisition errors or misbeats, as well as a risk of PCIE link establishment failure, which makes the functional test of the PCIE physical layer not accurate enough.

[0029] Based on this, an embodiment of the present application provides a test method for the PCIE physical layer. The method can compensate for the delay differences in transmission signals between different chips by configuring delay parameters for each communication link, thereby realizing synchronous sampling of transmission signals in each communication link by the receiving end, avoiding the risk of signal acquisition errors or misbeats; and, by timely clearing the receiving buffer when performing clock switching, the risk of link establishment failure caused by receiving buffer overflow can be avoided, thereby making the functional test of the PCIE physical layer performed by a third-party PCIE controller more accurate.

[0030] To facilitate understanding of the PCIE physical layer test method provided in the embodiment of the present application, Figure 1 The implementation environment shown introduces the test scenario of the PCIE physical layer; the implementation environment is specifically a test system of the PCIE physical layer, such as Figure 1 As shown, the test system of the PCIE physical layer includes a component under test 110 and a test component 120. The component under test 110 includes a test piece 111 provided with a PCIE physical layer, and the test component 120 includes a third-party PCIE controller.

[0031] In some embodiments, the test component 120 includes a first test component 121 and a second test component 122. For example, the first test component 121 may be a FPGA (Field Programmable Gate Array) test board, and the second test component 122 is used to obtain the test requirements of the component under test 110, and call the corresponding test case according to the test requirements to perform a functional test on the component under test. For example, the second test component 122 may be a computer or server with a PCIE expansion interface, etc., and the second test component 122 is installed with relevant test software.

[0032] In some embodiments, when the test requirements include the transmission function of the component under test, the first test component 121 can configure delay parameters for each communication link between the third-party PCIE controller and the PCIE physical layer to achieve synchronous sampling of the transmission signals in each communication link by the receiving end.

[0033] The first test component 121 can also perform reset control on the first data buffer corresponding to the component under test and the second data buffer corresponding to the test component when the test requirements include testing the link building function of the component under test, so as to clear the data received by the first data buffer and the second data buffer during the clock frequency switching process; wherein the first data buffer is used to receive data sent by the test component, and the second data buffer is used to receive data sent by the component under test.

[0034] In some embodiments, the test system further includes an external debugging computer 130 , and the external debugging computer 130 includes a serial communication controller. The external debugging computer 130 initiates a register read / write operation through the serial communication controller.

[0035] Combination Figure 2 As shown, Figure 2 FIG. 1 is a schematic diagram of the structure of the component under test shown in an exemplary embodiment of the present application. Figure 2 As shown, the component under test 110 includes a test chip 111 provided with a PCIE physical layer, a first control module 112 , an on-chip processor 113 and an on-chip PCIE controller 114 .

[0036] In some embodiments, the test piece 111 provided with a PCIE physical layer supports the PCIE protocol and supports a maximum communication rate of Gen5. The test piece 111 provided with a PCIE physical layer can form a standard PCIE-EP (Endpoint) device with an external third-party PCIE controller, such as a graphics card, SSD (Solid-State Drive), network card, etc. inserted in a PCIe slot, but a first control module 112 is added between the test piece 111 provided with a PCIE physical layer and the third-party PCIE controller. At the same time, the test piece 111 provided with a PCIE physical layer and the on-chip PCIE controller 114 can also form a standard PCIE-EP device.

[0037] The signals between the test piece 111 provided with the PCIE physical layer and the third-party PCIE controller are mainly PCIE-PIPE (Physical Interface for PCI Express, physical layer interface) signals, including signals from the third-party PCIE controller to the PCIE physical layer direction (TX direction) and signals from the PCIE physical layer to the third-party PCIE controller direction (RX direction). The test piece 111 provided with the PCIE physical layer is directly interconnected with the third-party PCIE physical layer in the second test component 122 to complete the communication between the PCIE-RC device and the PCIE-EP device.

[0038] In some embodiments, the first control module 112 is arranged between the test piece 111 provided with the PCIE physical layer and the third-party PCIE controller. The first control module 112 can control the delay of the signal in the TX direction and the transmission signal in the RX direction, as well as the generation and verification of pseudo-random numbers. Through the training process of pseudo-random numbers, it can be ensured that these signals can be correctly sampled under the 500M PIPE-PCLK (PHY Clock, the clock of the PCIE physical layer) clock, and then through the constant training process, the data alignment function is completed. In some embodiments, the first control module 112 is internally provided with a first data buffer FIFO for receiving the transmission data from the first test component 121. The first control module 112 is interconnected with the on-chip processor 113 through the APB bus.

[0039] In some embodiments, the on-chip processor 113 is used to configure the relevant parameters of the test piece 111 provided with the PCIE physical layer and the on-chip PCIE controller 114, and the operation process after power-on, and output a serial port to the first test component 121, and complete the signal pseudo-random number training process and constant training process between the first control module 112 and the first test component 121, thereby realizing a highly reliable parallel data transmission method. The on-chip processor 113 accesses the internal registers of the first control module through the APB bus, and accesses the relevant registers of the second control module 1212 through the serial port.

[0040] In some embodiments, a test chip 111 provided with a PCIE physical layer can choose to use an on-chip PCIE controller 114 or a third-party PCIE controller to form a PCIE device. The PCIE physical layer test method and test system in this application both use a third-party PCIE controller, and the on-chip PCIE controller 114 may not be used.

[0041] Combination Figure 3 As shown, Figure 3 It is a schematic structural diagram of a first test component shown in an exemplary embodiment of the present application. Figure 3 In the figure, the first test component 121 includes an IO (Input / Output) interface 1210, a data selection module 1211, a second control module 1212, a test module 1213, a third-party PCIE controller 1214, a third-party QDMA (Queue-based Direct Memory Access) controller 1215, a register module 1216, a data storage and test module 1217, a third control module 1218, a first serial port communication controller 1219 and a second serial port communication controller 1220.

[0042] The IO interface 1210 is a high-speed IO interface provided by a third party in the FPGA test board, which supports a maximum of 1.8 Gbps and a clock DDR sampling mode. The data selection module 1211 is used to control the transmission data source and the processing mode of the received data of the IO interface 1210. The transmission data includes the first data from the second control module 1212, the second data from the test module 1213 and the third data from the third-party PCIE controller 1214; wherein the first data is used to train the signal, the second data is used to test the stability of the data transmission on the line after the system performs signal training, and the third data is used to test the stability of the PCIE protocol and PCIE communication.

[0043] The second control module 1212 is used to realize the generation of pseudo-random numbers in the TX direction and the verification of pseudo-random numbers in the RX direction, as well as the transmission and verification of constants in constant training, and save the verification results in the register module 1216, and finally transmit them to the on-chip processor 113 in the component under test 110 through the first serial port communication controller 1219, so as to complete the pseudo-random number training function and the constant training function, thereby realizing a highly reliable parallel data transmission method. At the same time, the second control module 1212 is internally provided with a second data buffer FIFO for receiving the transmission data from the component under test 110.

[0044] The test module 1213 is used to test the stability of signal transmission in the TX direction and the RX direction after the pseudo-random number training and the constant training are completed. The test module 1213 generates incremental data, which is then sent to the component under test 110 by the IO interface 1210. After receiving the incremental data, the first control module 112 in the component under test 110 sends the received incremental data through the sending interface, and the IO interface 1210 receives the incremental data back, and then completes the data comparison in the test module 1213.

[0045] The third-party PCIE controller 1214 supports the PCIE protocol and the communication rates of Gen1, Gen2, Gen3, Gen4, and Gen5. The corresponding single-channel communication rates are 2.5 Gbps, 5 Gbps, 8 Gbps, 16 Gbps, and 32 Gbps, respectively. The PIPE-PCLK clock frequencies of the PIPE interface are 125 MHz, 250 MHz, 250 MMHz, 500 MHz, and 500 MHz, respectively. The effective data bit widths of the PIPE interface communication are 16 bits, 16 bits, 32 bits, 32 bits, and 64 bits, respectively. In some embodiments, the third-party PCIE controller 1214 is a PCIE-EP controller.

[0046] The third-party QDMA controller 1215 is used to parse the data packets from the third-party PCIE controller 1214, and send them out through the third-party PCIE controller 1214 after being packaged according to the protocol; at the same time, the third-party QDMA controller 1215 contains a QDMA controller inside, which mainly completes the DMA read and DMA write functions; the user interface mainly includes an AXI interface and an AXI-LITE interface, the AXI interface is a DMA interface, which is interconnected with the data storage and test module 1217 to complete the DMA read and DMA write tests, and the AXI-LITE interface is a register read and write interface, which is interconnected with the register module 1216 and can configure the registers required by the user.

[0047] The register module 1216 is used to configure all registers in the application. The register module 1216 includes three configuration interfaces, which are respectively connected to the third-party QDMA controller 1215, the first serial port communication controller 1219 and the second serial port communication controller 1220. The configuration request of the third-party QDMA controller 1215 comes from the PCIE-RC controller 1221, the configuration request of the first serial port communication controller 1219 comes from the on-chip processor 113, and the configuration request of the second serial port communication controller 1220 comes from the external debugging computer 130. The registers in the register module 1216 include four types: data selection registers, training registers, interface test registers and DMA test registers, which correspond to the data selection module 1211, the second control module 1212, the test module 1213 and the data storage and test module 1217 respectively.

[0048] The data storage and testing module 1217 includes a storage module RAM as a storage medium for DMA data. In some embodiments, the DMA test supports three modes: a DMA read test mode, a DMA write test mode, and a DMA read / write alternating test mode; in the DMA read test mode, namely the H2C (Host to Card) mode, data is moved from the memory of the PCIE-RC controller 1221 to the data storage and test module 1217, the data changes according to an increasing rule, and then the data is compared, and the data comparison result is saved; in the DMA write test mode, namely the C2H (Card to Host) mode, data is moved from the data storage and test module 1217 to the memory of the PCIE-RC controller 1221, the data changes according to an increasing rule, and then the data is compared, and the data comparison result is saved; in the DMA read / write alternating test mode, namely the H2C mode and the C2H mode are alternately tested, the host side first writes the data into the storage module RAM in the data storage and test module 1217 through the H2C mode, and then transmits the data back to the host side through the C2H mode, and then compares the data, and the cycle is repeated.

[0049] The third control module 1218 is used for clock generation and clock switching. The clock generation mainly includes the clock required by the IO interface 1210 and the clock required by the third-party PCIE controller 1214. The clock switching mainly refers to the switching of the PIPE-PCLK clock between 125MHz, 250MHz and 500MHz during the PCIE link establishment process from Gen1 to Gen5 by the third-party PCIE controller 1214.

[0050] The first serial port communication controller 1219 is used to implement the serial port protocol and the custom communication transmission protocol. The first serial port communication controller 1219 is a serial port slave controller. The serial port master controller is on the on-chip processor 113. The register read / write operation is initiated by the on-chip processor 113, received and parsed by the first serial port communication controller 1219, and then the register module 1216 training class register is accessed, and finally the pseudo-random number training function and the constant training function are completed in cooperation with the on-chip processor 113.

[0051] The second serial port communication controller 1220 has the same function as the first serial port communication controller 1219 and is used to implement serial port protocols and custom communication transmission protocols. It is a serial port slave controller. The serial port master controller is on the external debugging computer 130. The register read / write operation is initiated by the external debugging computer 130, received and parsed by the second serial port communication controller 1220, and then all registers of the register module 1216 are accessed, so that the debugger can obtain the status of all registers.

[0052] Combination Figure 4 As shown, Figure 4 It is a schematic structural diagram of a second test component shown in an exemplary embodiment of the present application. Figure 4 In the example, the second test component 122 can be used to obtain the test requirements of the component under test, and call the corresponding test case according to the test requirements to perform functional testing on the component under test. The second test component 122 includes a PCIE-RC controller 1221, a third-party PCIE physical layer 1222, a test interface 1223 and a test case module 1224.

[0053] The PCIE-RC (Root Complex) controller 1221, together with the third-party PCIE physical layer, forms a standard PCIE-RC device, supports the PCIE protocol, supports the communication rates of Gen1, Gen2, Gen3, Gen4, and Gen5, and can establish links and communicate with PCIE-EP devices.

[0054] The third-party PCIE physical layer 1222 and the PCIE-RC controller 1221 form a standard PCIE-RC device, and are used together to directly interconnect with the test piece 111 provided with the PCIE physical layer to complete the communication between the PCIE-RC device and the PCIE-EP device.

[0055] The test interface 1223 includes interface models that can initiate various data packets on the PCIE-RC device (host device), such as a configuration write request interface, a configuration read request interface, a configuration read completion interface, a memory write request interface, a memory read request interface, a memory read completion interface, a QDMA-H2C test interface, a QDMA-C2H test interface, a manufacturer / device ID acquisition interface, a PCIE link establishment interface, a base address register BAR space initialization interface, etc. In some embodiments, other test interface models may also be included, such as a serial port write access interface, a serial port read access interface, a power-on initialization interface of a component under test, a training initialization interface, a TX direction pseudo-random number training interface, a TX direction constant training interface, a RX direction pseudo-random number training interface, a RX direction constant training interface, a test mode configuration interface, etc. The test interface 1223 may be called in the test case module 1224 to complete the relevant test cases.

[0056] In some embodiments, the serial port write access interface and the serial port read access interface respectively run on the on-chip processor 113 and the external debugging computer 130. The tested component power-on initialization interface, the training initialization interface, the TX direction pseudo-random number training interface, the TX direction constant training interface, the RX direction pseudo-random number training interface, the RX direction constant training interface and the test mode configuration interface can run on the on-chip processor 113.

[0057] The test case module 1224 is used to call the test case through the test interface 1223 according to the test requirements. Exemplarily, the test cases include: training function test case, increment function test case, PCIE link building function test case, register read and write function test case, QDMA transmission test case, serial communication test case, etc. The serial communication test is also used in the training function test case, or when the user uses the debugging serial port.

[0058] In some embodiments, the training function test case is used to test the reliability of parallel data transmission between chips; the increment number function test case is used to test the stability of parallel data transmission; the PCIE link establishment function test case is used to test the basic functions of PCIE to achieve successful link establishment at Gen5 rate; the register read and write function test case is used to test the basic communication function of PCIE; the QDMA transmission test case is used to test the stability of PCIE communication.

[0059] The following is a detailed description of the PCIE physical layer testing method provided in the embodiment of the present application.

[0060] Please continue reading Figure 5 , Figure 5 FIG. 1 is a flow chart of a method for testing a PCIE physical layer shown in an exemplary embodiment of the present application. The method can be applied to Figure 1 The test system shown is specifically executed by the test component 120 in the implementation environment. It should be understood that the method can also be applied to other exemplary implementation environments and specifically executed by the test component 120 in other implementation environments, and this embodiment does not limit the implementation environment to which the method is applicable.

[0061] like Figure 5 As shown, in an exemplary embodiment, a test method for a PCIE physical layer is applied to a test system, the test system includes a component under test and a test component, the component under test includes a test piece provided with a PCIE physical layer, and the test component includes a third-party PCIE controller; the method includes at least steps S510 to S530, which are described in detail as follows: Step S510, obtaining the test requirements of the component under test.

[0062] In an embodiment of the present application, the test component may include a first test component and a second test component, the second test component being a device such as a computer having a PCIE expansion interface, and the computer having test software installed therein. When it is necessary to perform a functional test on the component under test, the corresponding test requirements may be input into the test software, and the test case may be called from the corresponding test interface according to the test requirements to implement the functional test on the component under test. Therefore, in an embodiment of the present application, the test requirements of the component under test may be obtained through the second test component in the test component. For example, the test requirements may include testing the training function of the component under test, testing the incrementing function of the component under test, testing the link building function of the component under test, testing the register reading and writing function of the component under test, and testing the QDMA transmission function of the component under test.

[0063] Step S520, when the test requirement includes testing the transmission function of the component under test, delay parameters are configured for each communication link between the third-party PCIE controller and the PCIE physical layer to achieve synchronous sampling of the transmission signals in each communication link by the receiving end.

[0064] It is understandable that the design of PCIE in an integrated circuit includes a PCIE controller and a PCIE physical layer. Usually, when performing PCIE-related tests, the PCIE physical layer and the PCIE controller are tested together. However, in some cases, if the PCIE physical layer is tested alone, a third-party PCIE controller is required to form a PCIE-EP device with the PCIE physical layer under test, and then cross-chip communication is performed to perform functional testing of the PCIE physical layer.

[0065] When performing cross-chip communication, data transmission can include two directions: from the third-party PCIE controller to the PCIE physical layer, that is, the TX (Transmit) direction; and from the PCIE physical layer to the third-party PCIE controller, that is, the RX (Receive) direction. When performing PCIE functional testing, the third-party PCIE controller and the PCIE physical layer will send and receive data to each other. Therefore, in the TX direction, the receiving end can be the PCIE physical layer; in the RX direction, the receiving end can be the third-party PCIE controller.

[0066] In an embodiment of the present application, when it is detected that the transmission function of the component under test needs to be tested, by configuring the delay parameters of each communication link between the third-party PCIE controller and the PCIE physical layer, not only can the sampling window be calibrated, but also the offset between the communication links can be compensated, thereby eliminating the propagation delay difference of each communication link, so that the receiving end can synchronously sample the transmission signals in each communication link.

[0067] Step S530, when the test requirement includes testing the link building function of the component under test, reset control is performed on the first data buffer corresponding to the component under test and the second data buffer corresponding to the test component to clear the data received by the first data buffer and the second data buffer during the clock frequency switching process.

[0068] It should be understood that the differences in transmission rates and encoding methods of different generations require different clock frequencies to maintain the correctness and efficiency of data transmission. Therefore, different generations require different transmission rates and clock frequencies. In some embodiments, clock switching is usually triggered by the test process of the PCIE link establishment function, and the third-party PCIE controller automatically adjusts the PIPE-PCLK frequency, that is, the clock frequency, according to the link width and the rate supported by the device. When the clock frequency is switched during the link establishment process, due to the delay in data transmission between the third-party PCIE controller and the PCIE physical layer, the clock is generated locally, and the clock switching time may not be synchronized, which will cause the third-party PCIE controller and the PCIE physical layer to overflow the local data buffer receiving buffer when the clock is switched, resulting in the failure of PCIE link establishment, making the functional test results for the PCIE physical layer inaccurate.

[0069] In the embodiment of the present application, when testing the link establishment function of the PCIE physical layer, by resetting the first data buffer corresponding to the component under test and the second data buffer corresponding to the test component, the data received by the first data buffer and the second data buffer during the clock frequency switching process can be cleared in time, thereby avoiding the risk of link establishment failure due to receive buffer overflow, making the functional test of the PCIE physical layer more accurate.

[0070] In some embodiments, the PCIE physical layer in the embodiments of the present application supports a maximum communication rate of Gen5. Therefore, when testing the PCIE link establishment function, the link is usually established and tested in sequence from Gen1, Gen2, Gen3, Gen4, and Gen5.

[0071] Exemplarily, the single-channel communication rate corresponding to Gen1 is 2.5Gbps, and the corresponding PIPE-PCLK frequency is 125MHz; the single-channel communication rate corresponding to Gen2 is 5Gbps, and the corresponding PIPE-PCLK frequency is 250MHz; the single-channel communication rate corresponding to Gen3 is 8Gbps, and the corresponding PIPE-PCLK frequency is 250MHz; the single-channel communication rate corresponding to Gen4 is 16Gbps, and the corresponding PIPE-PCLK frequency is 500MHz; the single-channel communication rate corresponding to Gen5 is 32Gbps, and the corresponding PIPE-PCLK frequency is 500MHz.

[0072] See also Figure 6 , Figure 6 yes Figure 5Step S520 in the illustrated embodiment is a flowchart for configuring a delay parameter in an exemplary embodiment; wherein the tested component further includes a first control module, the first control module is arranged between the PCIE physical layer and the third-party PCIE controller, the test component further includes a second control module, the second control module is connected to the third-party PCIE controller; the delay parameters of each communication link between the third-party PCIE controller and the PCIE physical layer include a first delay parameter; the first delay parameter is used to adjust the delay time of the transmission signal in each communication link; at least steps S610 to S620 are included, which are described in detail as follows: Step S610: Perform pseudo-random number training through the first control module and the second control module to obtain a first delay parameter, wherein the pseudo-random number training is used to determine the first delay parameter of each communication link between the third-party PCIE controller and the PCIE physical layer.

[0073] In an embodiment of the present application, when testing a PCIE-EP device composed of a third-party PCIE controller and a PCIE physical layer, a test piece provided with a PCIE physical layer communicates high-speed parallel signals with the third-party PCIE controller across chips. Due to different parallel signal delays, there may be a risk of signal acquisition errors or parallel signal misbeats. By setting a first control module between the third-party PCIE controller and the PCIE physical layer, and performing pseudo-random number training through the first control module and the second control module in the test component, the sampling phase of each communication link between the third-party PCIE controller and the PCIE physical layer can be dynamically optimized to ensure the correct sampling of complex data patterns under high-speed clocks, thereby solving the problem of acquisition errors or misbeats caused by different transmission delays of parallel signals.

[0074] Based on the above description of the data transmission direction for cross-chip communication, it can be known that data transmission may include two directions: from the third-party PCIE controller to the PCIE physical layer, that is, the TX (Transmit) direction; and from the PCIE physical layer to the third-party PCIE controller, that is, the RX (Receive) direction. Therefore, the first delay parameter in the embodiment of the present application includes the first delay parameter in the TX direction and the first delay parameter in the RX direction.

[0075] In some embodiments, the first delay parameter in the TX direction refers to the delay parameter of the first control module receiving the signal, and the first delay parameter in the RX direction refers to the delay parameter of the first control module sending the signal. On this basis, the pseudo-random number training includes pseudo-random number training in the TX direction and pseudo-random number training in the RX direction, thereby obtaining the first delay parameter in the TX direction and the first delay parameter in the RX direction.

[0076] Combination Figure 7As shown, Figure 7 yes Figure 6 Step S610 in the illustrated embodiment is a flowchart of performing pseudo-random number training in an exemplary embodiment; it includes at least steps S710 to S740, which are described in detail as follows: Step S710: performing initial delay parameter configuration on the first control module according to a preset delay parameter sequence.

[0077] It can be understood that, through the above description of the data transmission direction for cross-chip communication, the first delay parameter includes the first delay parameter in the TX direction and the first delay parameter in the RX direction, the first delay parameter in the TX direction refers to the delay parameter for the first control module to receive the signal, and the first delay parameter in the RX direction refers to the delay parameter for the first control module to send the signal. Therefore, when the initial delay parameter configuration of the first control module is performed, it includes configuring the initial delay parameter for the first control module to receive the signal, and configuring the initial delay parameter for the first control module to send the signal.

[0078] In some embodiments, the delay parameter sequence includes a plurality of preset delay times arranged in an arithmetic progression. For example, the delay parameter sequence includes an arithmetic progression with a first term of 0, a last term of Tmax, and a tolerance of d.

[0079] Exemplarily, when performing pseudo-random number training in the TX direction, the first control module is initially configured with delay parameters according to a preset delay parameter sequence, including: traversing the preset delay parameter sequence, and configuring the preset delay time in the delay parameter sequence as the initial delay parameter for the first control module to receive the signal in order from small to large.

[0080] For example, the preset delay parameter sequence is {0, 2, 4, 6}. When performing pseudo-random number training in the TX direction, the initial delay parameter position of the signal received by the first control module is first set to 0. After a round of pseudo-random number transmission, reception and verification, the initial delay parameter position of the signal received by the first control module is then set to 2. Repeat the above operation until the delay sequence parameters are traversed.

[0081] Exemplarily, when performing pseudo-random number training in the RX direction, initial delay parameter configuration is performed on the first control module according to a preset delay parameter sequence, including: configuring initial delay parameters of signals sent by the first control module according to the preset delay parameter sequence.

[0082] For example, the preset delay parameter sequence is {0, 2, 4, 6}. When performing pseudo-random number training in the RX direction, the initial delay parameter position of the signal sent by the first control module is first set to 0. After a round of pseudo-random number transmission, reception and verification, the initial delay parameter position of the signal sent by the first control module is then set to 2. Repeat the above operation until the delay sequence parameters are traversed.

[0083] Step S720: After the delay parameters are configured, the first control module and the second control module send pseudo-random numbers to each other, and verify the received pseudo-random numbers to obtain a data verification result sequence.

[0084] It can be understood that, by configuring the first control module and the second control module to send pseudo-random numbers to each other after the initial delay parameters are configured, and the received pseudo-random numbers are verified, the first control module can realize the reception and transmission and verification of data under different initial delay parameters, and obtain the data verification results under different initial delay parameters, thereby facilitating the determination of the optimal delay parameters according to the data verification results under different initial delay parameters.

[0085] In some embodiments, since the data transmission directions during the test process include TX direction and RX direction, it is necessary to configure the first delay parameters of each communication link in different directions. After configuring the initial delay parameters, the first control module and the second control module send pseudo-random numbers to each other, and verify the received pseudo-random numbers, thereby realizing pseudo-random number training in the TX direction and pseudo-random number training in the RX direction, and obtaining the first delay parameters of each communication link in different directions.

[0086] Exemplarily, the pseudo-random number training in the TX direction (from the third-party PCIE controller to the PCIE physical layer direction) includes: sending the pseudo-random number to the first control module after configuring the receiving signal delay parameter through the second control module, and the first control module after configuring the receiving signal delay parameter verifies the received pseudo-random number.

[0087] Exemplarily, the pseudo-random number training in the RX direction (from the PCIE physical layer to the third-party PCIE controller direction) includes: the first control module sends the pseudo-random number to the second control module after configuring the signal delay parameter, and the second control module verifies the received pseudo-random number.

[0088] In some embodiments, the data verification result sequence includes data verification results corresponding to each preset delay time, and each data verification result is arranged in the order of the preset delay time in the delay parameter sequence.

[0089] For example, the preset delay parameter sequence is {0, 2, 4, 6}. For the pseudo-random number training in the TX direction, according to the delay parameter sequence, the delay parameter configuration of the first control module receiving the signal can be first configured to 0, and then the pseudo-random number is sent through the second control module, and the first control module after the delay parameter 0 is configured receives the pseudo-random number, and performs verification to obtain the data verification result; then the delay parameter configuration of the first control module receiving the signal is configured to 2, and then the pseudo-random number is sent through the second control module, and the first control module after the delay parameter 2 is configured receives the pseudo-random number, and performs verification to obtain the data verification result; then the delay parameter configuration of the first control module receiving the signal is configured to 4, ... Repeat the above operations until the delay parameter sequence is traversed, and then stop sending, receiving and verifying the pseudo-random number.

[0090] For example, the preset delay parameter sequence is {0, 2, 4, 6}. For the pseudo-random number training in the RX direction, according to the delay parameter sequence, the delay parameter configuration of the signal sent by the first control module can be first configured to 0, and then the pseudo-random number is sent by the first control module after the delay parameter is configured to 0, and the pseudo-random number is received by the second control module and verified to obtain the data verification result; then the delay parameter configuration of the signal sent by the first control module is configured to 2, and then the pseudo-random number is sent by the first control module after the delay parameter is configured to 2, and the pseudo-random number is received by the second control module and verified to obtain the data verification result; then the delay parameter configuration of the signal sent by the first control module is configured to 4, ... Repeat the above operations until the delay parameter sequence is traversed, and then stop sending, receiving and verifying the pseudo-random number.

[0091] Step S730: determining a first critical value and a second critical value corresponding to the valid sampling window according to the data verification result sequence.

[0092] It should be understood that the first critical value and the second critical value mark the boundaries of the valid data window of the current cycle and the next cycle respectively, and the area between the two is the verification failure area, and the valid window may be distributed in two discontinuous areas, namely, the minimum preset delay parameter to the first critical value, and the second critical value to the maximum preset delay parameter. Therefore, the first critical value is used to characterize the preset delay time configured by the first control module from the data verification success to the data verification failure in the data verification result sequence; the second critical value is used to characterize the preset delay time configured by the first control module from the data verification failure to the data verification success.

[0093] In some embodiments, from data verification success to data verification failure means: when the delay parameter increases to the first critical value, the sampling point slides out from the right edge of the data valid window, resulting in verification failure. Therefore, from data verification success to data verification failure, the preset delay time configured by the first control module is determined as the first critical value.

[0094] From data verification failure to data verification success means: when the delay parameter increases to the second critical value, the sampling point enters the left edge of the data valid window of the next cycle due to cycle slippage, so that the data re-verification is successful. Therefore, from data verification failure to data verification success, the preset delay time configured by the first control module is determined as the second critical value.

[0095] For example, the preset delay parameter sequence includes {0, 2, 4, 6}, and the corresponding data verification result sequence includes {verification failed (0), verification successful (2), verification successful (4), verification failed (6)}. It can be seen from the data verification result sequence that when the preset delay parameter is 4, the corresponding data verification result is verification successful, and when the preset delay parameter is 6, the verification result is failure, and the first critical value is 4; when the preset delay parameter is 0, the corresponding data verification result is verification failed, and when the preset delay parameter is 2, the verification result is success, and the second critical value is 2.

[0096] Step S740: determining a first delay parameter of each transmission signal in each communication link according to the first critical value and the second critical value.

[0097] It should be understood that when determining the first delay parameter of each transmission signal in each communication link, it is necessary to transmit, receive and verify data through each communication link, so as to determine the first critical value and the second critical value corresponding to each communication link, and then determine the first delay parameter of each transmission signal in each communication link according to the first critical value and the second critical value corresponding to each communication link. The embodiment of the present application only takes the current communication link (i.e., one of the communication links) as an example for illustration.

[0098] Exemplarily, the first delay parameter of each transmission signal in each communication link is determined according to the first critical value and the second critical value, including: comparing the first critical value with the second critical value to obtain a comparison result; when the comparison result is that the first critical value is greater than the second critical value, the first delay parameter of the current communication link is obtained by calculating TXBest=(X0+X1) / 2; wherein TXBest is the first delay parameter, X0 is the first critical value, and X1 is the second critical value. In this way, when the first critical value is greater than the second critical value, it can be considered that the data valid window is continuous, and the optimal point can be taken as the midpoint, so the average value between the first critical value and the second critical value is determined as the optimal delay parameter, that is, the first delay parameter.

[0099] Exemplarily, determining the first delay parameter of each transmission signal in each communication link according to the first critical value and the second critical value includes: comparing the first critical value with the second critical value to obtain a comparison result; when the comparison result is that the first critical value is less than the second critical value, and the first critical value is greater than the reference delay parameter, obtaining the first delay parameter of the current communication link by calculating TXBest=X0-(Tmax-X1+X0) / 2; wherein TXBest is the first delay parameter, X0 is the first critical value, X1 is the second critical value, and Tmax is the maximum preset delay parameter. The reference delay parameter is the difference between the maximum preset delay parameter and the second critical value. In this way, when the first critical value is less than the second critical value, it can be considered that the data valid window is divided into two segments, namely, the minimum preset delay parameter to the first critical value (from 0 to X0), and the second critical value to the maximum preset delay parameter (from X1 to Tmax); then it is necessary to determine which segment is longer, and the reference delay parameter is the difference between the maximum preset delay parameter and the second critical value. Therefore, the reference delay parameter can represent the length of the second segment, and X0 can represent the length of the first segment; if the first critical value is greater than the reference delay parameter, the first segment is longer, so the optimal point can be placed to the left of the center of the first segment.

[0100] Exemplarily, determining the first delay parameter of each transmission signal in each communication link according to the first critical value and the second critical value includes: comparing the first critical value with the second critical value to obtain a comparison result; when the comparison result is that the first critical value is less than the second critical value, and the first critical value is equal to the reference delay parameter, determining the preset delay parameter as the first delay parameter of the current communication link; in some embodiments, the preset delay parameter is 0. In this way, when the first critical value is less than the second critical value, it can be considered that the data valid window is divided into two sections, namely, the minimum preset delay parameter to the first critical value (from 0 to X0), and the second critical value to the maximum preset delay parameter (from X1 to Tmax); then it is necessary to determine which section is longer. If the first critical value is equal to the reference delay parameter, the two sections are equal in length, so the default starting point is directly taken as the sampling point, that is, the minimum preset delay parameter.

[0101] Exemplarily, the first delay parameter of each transmission signal in each communication link is determined according to the first critical value and the second critical value, including: comparing the first critical value with the second critical value to obtain a comparison result; when the comparison result is that the first critical value is less than the second critical value, and the first critical value is less than the reference delay parameter, the first delay parameter of the current communication link is obtained by calculating TXBest=X1+(Tmax-X1+X0) / 2; wherein TXBest is the first delay parameter, X0 is the first critical value, X1 is the second critical value, and Tmax is the maximum preset delay parameter. Wherein, the reference delay parameter is the difference between the maximum preset delay parameter and the second critical value. In this way, when the first critical value is less than the second critical value, it can be considered that the data valid window is divided into two sections, namely, the minimum preset delay parameter to the first critical value (from 0 to X0), and the second critical value to the maximum preset delay parameter (from X1 to Tmax); then it is necessary to determine which section is longer. If the first critical value is less than the reference delay parameter, the second section is longer, and the optimal point can be placed at a position slightly to the right of its center.

[0102] Step S620: configure the first delay parameter to the parameter register corresponding to each transmission signal in each communication link.

[0103] In the embodiment of the present application, since the first delay parameter includes the first delay parameter in the TX direction and the first delay parameter in the RX direction, when configuring the first delay parameter, the first delay parameter in the TX direction is configured to the delay time register of each signal in the TX direction of the first control module; and the first delay parameter in the RX direction is configured to the delay time register of each signal in the RX direction of the first control module.

[0104] For example, pseudo-random number training in the TX direction (from the third-party PCIE controller to the PCIE physical layer) can be performed through the following process: Step 1: The on-chip processor in the component under test configures the first control module and the second control module into a pseudo-random number training mode through the APB bus and the serial port respectively; Step 2: the on-chip processor in the component under test starts the second control module to send a pseudo-random number instruction through the serial port, and sends it infinitely; Step 3: The on-chip processor in the tested component configures the delay parameters of the first control module receiving the signal according to the preset delay parameter sequence through the APB bus; Step 4: the on-chip processor in the tested component starts the pseudo-random number receiving verification instruction of the first control module through the APB bus, and performs verification according to the preset fixed data number; and returns the receiving completion status and data verification result after the verification is completed; Step 5: The on-chip processor in the tested component queries the first control module through the APB bus for the reception completion status and data verification result; Step 6, re-execute step 3 to step 5, re-configure the preset delay parameters in the delay parameter sequence from the minimum value to the maximum value in sequence; and record the preset delay parameter of each signal from verification success to verification failure as the first critical value, and the preset delay parameter from verification failure to verification success as the second critical value. After the preset delay parameters in the delay parameter sequence are traversed and the verification is completed, execute step 7; Step 7: Calculate the optimal delay parameter for each signal, that is, the first delay parameter: When A0>A1, then TABest=(A0+A1) / 2; When A0<A1, and A0>(Tmax-A1); then TABest=A0-(Tmax-A1+A0) / 2; When A0<A1, and A0=(Tmax-A1); then TABest=minimum preset delay parameter; in some embodiments, the minimum preset delay parameter is 0; When A0<A1, and A0<(Tmax-A1); then TABest=A0+(Tmax-A1+A0) / 2; Wherein, A0 is the first critical value in the TX direction, A1 is the second critical value in the TX direction, TABest is the first delay parameter in the TX direction, and Tmax is the maximum preset delay parameter in the delay parameter sequence; Step 8: configure the first delay parameter into the delay parameter register of each signal in the TX direction of the first control module.

[0105] By adopting the TX direction pseudo-random number training method in the embodiment of the present application, it is possible to configure the delay parameters of the receiving signal of the first control module, so that when the component under test receives data as a receiving end, the sampling point can be adjusted to the center of the effective window, ensuring that even if there is timing jitter or path delay difference, the receiving end can still sample the data stably.

[0106] For example, pseudo-random number training in the RX direction (from the PCIE physical layer to the third-party PCIE controller) can be performed through the following process: Step 1: The on-chip processor in the component under test configures the first control module and the second control module into a pseudo-random number training mode through the APB bus and the serial port respectively; Step 2: the on-chip processor in the component under test starts the first control module to send a pseudo-random number instruction through the APB bus, and sends it infinitely; Step 3: The on-chip processor in the tested component configures the delay parameters of the signal sent by the first control module according to the preset delay parameter sequence through the APB bus; Step 4: the on-chip processor in the tested component starts the pseudo-random number receiving verification instruction of the second control module through the serial port, and performs verification according to the preset fixed number of data; and returns the receiving completion status and data verification result after the verification is completed; Step 5: the on-chip processor in the tested component queries the second control module through the serial port to receive the completion status and data verification result; Step 6, re-execute step 3 to step 5, re-configure the preset delay parameters in the delay parameter sequence from the minimum value to the maximum value in sequence; and record the preset delay parameter of each signal from verification success to verification failure as the first critical value, and the preset delay parameter from verification failure to verification success as the second critical value. After the preset delay parameters in the delay parameter sequence are traversed and the verification is completed, execute step 7; Step 7: Calculate the optimal delay parameter for each signal, that is, the first delay parameter: When B0>B1, then TBBest=(B0+B1) / 2; When B0<B1, and B0>(Tmax-B1); then TBBest=B0-(Tmax-B1+B0) / 2; When B0<B1, and B0=(Tmax-B1); then TBBest=minimum preset delay parameter; in some embodiments, the minimum preset delay parameter is 0; When B0<B1, and B0<(Tmax-B1); then TBBest=B0+(Tmax-B1+B0) / 2; Wherein, B0 is the first critical value in the RX direction, B1 is the second critical value in the RX direction, TBBest is the first delay parameter in the RX direction, and Tmax is the maximum preset delay parameter in the delay parameter sequence; Step 8: configure the first delay parameter into the delay parameter register of each signal in the RX direction of the first control module.

[0107] By adopting the RX direction pseudo-random number training method in the embodiment of the present application, it is possible to configure the delay parameters of the receiving signal of the first control module, so that when the test component receives data as the receiving end, the sampling point can be adjusted to the center of the valid window, ensuring that even if there is timing jitter or path delay difference, the receiving end can still sample the data stably.

[0108] See also Figure 8 , Figure 8 yes Figure 5Step S520 in the illustrated embodiment is a flowchart of configuring a delay parameter in another exemplary embodiment; the delay parameter of each communication link between the third-party PCIE controller and the PCIE physical layer also includes a second delay parameter; the second delay parameter is used to adjust the number of delay bits of the transmission signal in each communication link; the method includes at least steps S810 to S820, which are described in detail as follows: Step S810: Perform constant training through the first control module and the second control module to obtain a second delay parameter. The constant training is used to determine the second delay parameter of each communication link between the third-party PCIE controller and the PCIE physical layer.

[0109] In the embodiment of the present application, when a PCIE-EP device is tested by a third-party PCIE controller and a PCIE physical layer, a test piece provided with a PCIE physical layer communicates high-speed parallel signals across chips with a third-party PCIE controller. When parallel signals are transmitted at high speed, due to path length, impedance differences or process deviations, the transmission delays of different signal lines are inconsistent, which may cause the bit position of each communication link transmission signal to be misaligned when the receiving end samples. Constant training is performed by the first control module and the second control module, so that the bit position offset of each signal at the receiving end can be detected, and the delay parameters of the sending end can be adjusted to ensure that the data bits of each channel are aligned to the same position, thereby achieving data alignment and enabling the signals to be sampled synchronously.

[0110] Based on the above description of the data transmission direction for cross-chip communication, it can be known that data transmission may include two directions: from the third-party PCIE controller to the PCIE physical layer, that is, the TX (Transmit) direction; and from the PCIE physical layer to the third-party PCIE controller, that is, the RX (Receive) direction. Therefore, the second delay parameter in the embodiment of the present application includes the second delay parameter in the TX direction and the second delay parameter in the RX direction.

[0111] In some embodiments, the second delay parameter in the TX direction refers to the delay parameter of the first control module receiving the signal, and the second delay parameter in the RX direction refers to the delay parameter of the first control module sending the signal. On this basis, the constant training includes the constant training in the TX direction and the constant training in the RX direction, thereby obtaining the second delay parameter in the TX direction and the second delay parameter in the RX direction.

[0112] Combination Fig. 9 As shown, Fig. 9 yes Figure 8 Step S810 in the illustrated embodiment is a flow chart of performing constant training in an exemplary embodiment; it includes at least steps S910 to S950, which are described in detail as follows: Step S910: configuring delay parameters of the first control module according to a preset number of delay bits.

[0113] It can be understood that, through the above description of the data transmission direction for cross-chip communication, the second delay parameter includes the second delay parameter in the TX direction and the second delay parameter in the RX direction, the second delay parameter in the TX direction refers to the delay parameter of the first control module receiving the signal, and the second delay parameter in the RX direction refers to the delay parameter of the first control module sending the signal. Therefore, when configuring the delay parameters of the first control module, it includes configuring the delay bit number of the first control module receiving the signal and the delay bit number of the first control module sending the signal.

[0114] In some embodiments, the delay parameters of the first control module are configured according to a preset number of delay bits, including: when performing constant training in the TX direction, the number of delay bits of the signal received by the first control module is configured to be the preset number of delay bits; when performing constant training in the RX direction, the number of delay bits of the signal sent by the first control module is configured to be the preset number of delay bits.

[0115] Step S920, the first control module and the second control module after configuring the delay parameters exchange constants to obtain a data reception result, wherein the data reception result includes the reception data of each communication link under the preset delay bit number.

[0116] In some embodiments, the constant sent between the first control module and the second control module may be 16-bit data 0x0100, which is transmitted on each communication link in a serial manner.

[0117] In some embodiments, after obtaining the data receiving result, the method further includes: verifying the received data to obtain the data verification result. In some embodiments, 16 bits of data are received each time for verification.

[0118] Step S930, determining reference data and a flag bit in the reference data from the data receiving result.

[0119] It should be understood that the reference data is used to characterize the reference signal, and the flag bit in the reference data actually represents the delay of the signal at the receiving end. In some embodiments, the flag bit in the reference data is the position of the data "1" in the reference data.

[0120] Step S940: compare all received data in the data receiving result with the flag bits in the reference data respectively to obtain the relative delay difference between all received data and the flag bits in the reference data.

[0121] In the embodiment of the present application, the reference data is used to characterize the reference signal, and the flag bit in the reference data actually represents the delay of the signal at the receiving end. By comparing the position of the flag bit in each signal with that in the reference data, the delay difference of each signal relative to the reference signal can be determined.

[0122] In some embodiments, comparing all received data in the data receiving result with the flag bits in the reference data respectively means comparing the positions of the flag data in all received data with the positions of the flag data in the reference data.

[0123] In some embodiments, reference data and a flag bit in the reference data are determined from the data reception result, including: taking the data with the last position of the flag data in the data reception result as the reference data, and determining the position of the flag data in the reference data as the flag bit.

[0124] For example, the data receiving results include 0x0100, 0x0080 and 0x0040, and the flag data is "1". These three data are converted into corresponding binary data: 0000 0001 0000 0000, 0000 0000 1000 0000, 00000000 0100 0000. It can be seen that the data with the flag data "1" at the end is 0x0040, so 0x0040 is determined as the reference data. Counting from left to right, the position of the flag data "1" in 0x0040 is the 8th bit, so the flag data "1" at the 8th bit is determined as the flag bit. Then the flag data "1" in the other two data 0x0100 and 0x0080 are compared with the flag bit in the reference data to obtain the relative delay difference. It can be seen that the relative delay difference between the flag data "1" and the flag bit in 0x0080 is 1 bit, and the relative delay difference between the flag data "1" and the flag bit in 0x0100 is 2 bits. Therefore, the data sender sending 0x0040 does not need to delay, and the second delay parameter can be set to 0. The data sender sending 0x0080 needs to delay 1 bit, and the data sender sending 0x0100 needs to delay 2 bits.

[0125] Step S950: determining a second delay parameter of each transmission signal in each communication link according to the relative delay difference.

[0126] In some embodiments, determining the second delay parameter of each transmission signal in each communication link according to the relative delay difference includes: determining the relative delay difference as the second delay parameter of each transmission signal in each communication link.

[0127] For example, there are only three communication links, each of which transmits 16-bit data 0x0100. The data received by the data receiving end include 0x0100, 0x0080 and 0x0040. Then, 0x0040 is used as the reference data, the relative delay difference between 0x0080 and 0x0040 is 1 bit, and the relative delay difference between 0x0100 and 0x0040 is 2 bits. Therefore, the delay bit number of the data sending end corresponding to 0x0040 is configured as 0, the delay bit number of the data sending end corresponding to 0x0080 is configured as 1, and the delay bit number of the data sending end corresponding to 0x0100 is configured as 2.

[0128] Step S820: configure the second delay parameter to the parameter register corresponding to each transmission signal in each communication link.

[0129] In the embodiment of the present application, since the second delay parameter includes the second delay parameter in the TX direction and the second delay parameter in the RX direction, when configuring the second delay parameter, the second delay parameter in the TX direction is configured to the delay bit number register of each signal in the TX direction of the first control module; and the second delay parameter in the RX direction is configured to the delay bit number register of each signal in the RX direction of the first control module.

[0130] For example, the constant training in the TX direction (from the third-party PCIE controller to the PCIE physical layer) can be performed through the following process: Step 1: The on-chip processor in the tested component configures the first control module and the second control module to the constant training mode through the APB bus and the serial port respectively; the sending constant is set to 16-bit data 0x0100 and transmitted on each communication link in a serial manner; Step 2, the on-chip processor in the component under test starts the sending constant instruction of the second control module through the serial port, and sends it infinitely; Step 3: the on-chip processor in the tested component configures the number of delayed bits of the signal received by the first control module to a preset number of bits via the APB bus; Step 4: The on-chip processor in the tested component starts the constant receiving verification instruction of the first control module through the APB bus, and receives 16-bit data each time; and returns the receiving completion status and data receiving result after the verification is completed; Step 5: the on-chip processor in the tested component queries the first control module for receiving completion status and data receiving result through the APB bus; Step 6: Determine the reference data and the flag bit in the reference data from the data reception result, and compare all the received data in the data reception result with the flag bit in the reference data to obtain the relative delay difference between all the received data and the flag bit in the reference data; Step 7: determine the relative delay difference as the second delay parameter, and configure the second delay parameter required by each communication link into the delay bit register of each signal in the TX direction of the first control module.

[0131] By adopting the constant training method in the TX direction in the embodiment of the present application, the relative delay difference of each signal relative to the reference signal can be determined, and then the delay parameters of the transmitting end can be dynamically adjusted according to the relative delay difference to ensure that all signals can be aligned to the same clock cycle at the receiving end, thereby solving the misalignment problem between multiple signals and improving the reliability and stability of data transmission.

[0132] For example, the constant training in the RX direction (from the PCIE physical layer to the third-party PCIE controller) can be performed through the following process: Step 1: The on-chip processor in the tested component configures the first control module and the second control module to the constant training mode through the APB bus and the serial port respectively; the sending constant is set to 16-bit data 0x0100 and transmitted on each communication link in a serial manner; Step 2, the on-chip processor in the component under test starts the sending constant instruction of the first control module through the APB bus, and sends it infinitely; Step 3: the on-chip processor in the tested component configures the number of delayed bits of the signal received by the first control module to a preset number of bits via the APB bus; Step 4: The on-chip processor in the tested component starts the constant receiving verification instruction of the second control module through the serial port, and receives 16-bit data each time it starts; and returns the receiving completion status and data receiving result after the verification is completed; Step 5: the on-chip processor in the tested component queries the second control module through the serial port for the receiving completion status and the data receiving result; Step 6: Determine the reference data and the flag bit in the reference data from the data reception result, and compare all the received data in the data reception result with the flag bit in the reference data to obtain the relative delay difference between all the received data and the flag bit in the reference data; Step 7: determine the relative delay difference as the second delay parameter, and configure the second delay parameter required by each communication link into the delay bit register of each signal in the RX direction of the first control module.

[0133] By adopting the constant training method in the RX direction in the embodiment of the present application, the relative delay difference of each signal relative to the reference signal can be determined, and then the delay parameters of the transmitting end can be dynamically adjusted according to the relative delay difference to ensure that all signals can be aligned to the same clock cycle at the receiving end, thereby solving the misalignment problem between multiple signals and improving the reliability and stability of data transmission.

[0134] Please continue reading Fig.10 , Fig.10 yes Figure 5 Step S530 in the illustrated embodiment is a flow chart of resetting the first data buffer and the second data buffer in an exemplary embodiment; wherein the test component further includes a third control module, and the third control module is connected to the third-party PCIE controller; at least steps S1010 to S1030 are described in detail as follows: Step S1010, sending a rate signal to the component under test through the test component, and generating a second reset signal to reset the second data buffer. The rate signal is used to trigger the third control module to switch the clock frequency of the PCIE physical layer and the third-party PCIE controller, and the second reset signal is used to restore the second data buffer to an initial state.

[0135] It should be understood that during the PCIE link establishment process from Gen1 to Gen5, the PIPE-PCLK clock needs to be dynamically switched. The main reason is that different generations of link rates need to match different clock frequencies. This can optimize the bandwidth and enable high-frequency clocks only when needed to avoid unnecessary signal attenuation and power consumption.

[0136] Therefore, when receiving a signal of a different rate, the clock frequency will be switched to a clock frequency that matches the rate. During the clock switching process, due to the delay in data transmission between the third-party PCIE controller and the PCIE physical layer, the clocks are generated locally. In addition, the timing of the clock switching may not be synchronized, which will cause the local data buffer receive cache of the third-party PCIE controller and the PCIE physical layer to overflow during the clock switching, resulting in the failure of PCIE link establishment and inaccurate functional test results for the PCIE physical layer.

[0137] In the embodiment of the present application, by generating a reset signal to reset the data buffer when switching the clock frequency, invalid data received during the clock switching process can be cleared in time, thereby avoiding cache overflow and link establishment failure due to cache overflow, thereby improving the accuracy of the test.

[0138] In some embodiments, the clocks of the component under test and the test component are of the same source, which can ensure that the clocks of the PCIE physical layer, the first control module, the IO interface of the test component, the second control module and the third-party PCIE controller are of the same source.

[0139] Exemplarily, the test component sends a rate signal from the test component to the component under test through the transmission mode of the IO interface and the first control module. The rate signal can be used as a clock switching trigger signal of the third-party PCIE controller, that is, after sending the rate signal, the clock of the third-party PCIE controller is switched to a clock frequency corresponding to the rate signal; and a second reset signal of the second data buffer (that is, the local receive FIFO) is generated to restore the second data buffer to an initial state.

[0140] In some embodiments, since the transmission delay of the rate signal is relatively large, the transmission delay of the rate signal is recorded as DT.

[0141] Step S1020: When the component under test receives the rate signal sent by the test component, a first reset signal is generated to reset the first data buffer, wherein the first reset signal is used to restore the first data buffer to an initial state.

[0142] In an embodiment of the present application, after the component under test receives the rate signal, the rate signal can be used as a clock switching trigger signal for the PCIE physical layer, that is, after receiving the rate signal, the clock of the PCIE physical layer is switched to a clock frequency corresponding to the rate signal; and a first reset signal of the first data buffer (that is, the local receive FIFO) is generated to restore the first data buffer to an initial state.

[0143] In this way, when the clock frequency of the third-party PCIE controller and the PCIE physical layer is switched according to the rate signal, the local receiving FIFOs of the third-party PCIE controller and the PCIE physical layer can be restored to their initial states by generating corresponding reset signals, thereby clearing invalid data received during the clock switching process.

[0144] Step S1030: when the clock frequency switching of the component under test and the testing component is completed, the first reset signal and the second reset signal are cancelled.

[0145] It should be understood that in the embodiment of the present application, the clock switching completion signal is sent by means of GPIO. This is because GPIO transmits signals by directly controlling the level (high / low) of the hardware pin, without the need for complex operations such as data packaging, verification, and timing synchronization as in protocols such as SPI, I2C, and UART. This eliminates the additional delay caused by protocol parsing, and is through a direct hardware connection, so the transmission delay of GPIO can be ignored.

[0146] In some embodiments, after the PCIE physical layer in the component under test completes the clock frequency switching, the component under test generates a clock switching completion signal (i.e., SWITCH_RATE_ACK signal), cancels the first reset signal, and sends the clock switching completion signal to the test component. After receiving the clock switching completion signal, the test component cancels the second reset signal; in this way, after the test component and the component under test complete the clock switching, the first reset signal and the second reset signal can be canceled, so that the first data buffer and the second data buffer start receiving data again.

[0147] In some embodiments, after the tested component and the test component complete the clock frequency switching, it also includes: sending a clock gating signal to the test component through the tested component, so that the clock frequencies after the PCIE physical layer and the third-party PCIE controller switch can take effect at the same time. The clock gating signal is used to indicate the clock state of the PCIE physical layer and the third-party PCIE controller; when the clock gating signal is a first preset level, the clock state is a valid state, and when the clock gating signal is a second preset level, the clock state is an invalid state.

[0148] In the embodiment of the present application, the component under test and the test component send a clock gating signal (CLOCK_GATE signal) via GPIO.

[0149] For example, when the clock needs to be switched, the clock gating signal can be set to a low level first, so that the clocks at both ends of the PCIE physical layer and the third-party PCIE controller are stopped, ensuring that no new data is generated or received. At this time, the sending end stops sending, and the receiving end stops sampling due to clock failure, preventing invalid data from continuing to enter the data buffer. During the period when the clock gating signal is at a low level, a first reset signal and a second reset signal are generated to reset the FIFO buffer of the receiving end, and the read and write pointers of the receiving FIFO are reset to the initial position, so that the residual data received but not processed in the receiving FIFO is cleared. After the reset, the receiving FIFO is in an "empty" state, ensuring that only new data is received after the clock is switched. Then, after the clock frequency switching is completed, the clock gating signal is set to a high level, so that the new clocks after the switching at both ends can take effect at the same time, the sending end starts to send data, the receiving end resamples based on the new clock frequency, and the receiving FIFO has been reset to empty, and only valid data is received.

[0150] Combination Fig.11 As shown, Fig.11 It is a timing diagram of clock switching management shown in an exemplary embodiment of the present application; it at least includes steps S1110 to S1190, which are described in detail as follows: Step S1110, the first test component sends the rate signal to the component under test through the IO interface, and generates a second reset signal for the second data buffer. In some embodiments, the second reset signal may be an RFIFO_RST signal, and the second reset signal is used to restore the second data buffer to an initial state.

[0151] Step S1120: the first test component switches the clock frequency of the third-party PCIE controller according to the rate signal.

[0152] Step S1130, the component under test receives the rate signal and generates a first reset signal for the first data buffer. In some embodiments, the first reset signal may be an RFIFO_RST signal, and the first reset signal is used to restore the first data buffer to an initial state.

[0153] Step S1140: the component under test performs clock switching according to the rate signal, and generates a clock switching completion signal after the clock frequency switching is completed. In some embodiments, the clock switching completion signal may be a SWITCH_RATE_ACK signal.

[0154] Step S1150: the component under test cancels the first reset signal.

[0155] Step S1160: The component under test sends a clock switching completion signal to the first test component via GPIO.

[0156] Step S1170: After receiving the clock switching completion signal, the first test component cancels the second reset signal.

[0157] Step S1180, the component under test sends a clock gating signal to the first test component through GPIO. In some embodiments, the clock gating signal may be a CLOCK_GATE signal, which is used to indicate the clock state of the PCIE physical layer and the third-party PCIE controller; when the clock gating signal is a first preset level (high level), the clock state is a valid state, and when the clock gating signal is a second preset level (low level), the clock state is an invalid state.

[0158] In an embodiment of the present application, when performing clock switching, the data buffer is controlled by setting a reset signal, and a clock switching completion signal is generated by the component under test and sent to the test component to cancel the first reset signal and the second reset signal, so that invalid data received by the data buffer during the clock switching process can be cleared in time; after the component under test and the test component complete the clock frequency switching, the component under test can send a high-level clock gating signal to the first test component via GPIO, so that the new clock frequencies after the switching of the third-party PCIE controller and the PCIE physical layer take effect at the same time.

[0159] In some embodiments, in combination Fig.12 As shown, Fig.12 It is a schematic diagram of the application of clock switching management shown in an exemplary embodiment of the present application. Fig.12 In the test, the PCIE-EP end PHY_RATE is used to characterize the timing of the rate signal of the third-party PCIE controller in the first test component; the PCIE-EP end RXFIFO_RST is used to characterize the timing of the second reset signal of the second buffer; the PCIE-PHY end PHY_RATE is used to characterize the timing of the rate signal received by the PCIE physical layer in the tested component; the PCIE-PHY end RXFIFO_RST is used to characterize the timing of the first reset signal of the first buffer; the GPIO signal SWITCH_RATE_ACK is used to characterize the timing of the clock switching completion signal generated by the tested component after completing the clock frequency switching; the GPIO signal CLOCK_GATE is used to characterize the timing indicating the clock status of the PCIE physical layer and the third-party PCIE controller.

[0160] Fig.12 In the figure, time T1 is used to represent the time when the first test component sends the rate signal, time T2 is used to represent the time when the tested component receives the rate signal, and time T3 is used to represent the time when the first reset signal and the second reset signal are cancelled.

[0161] Depend on Fig.12 It can be seen that at time T1, the first test component switches from Gen1 to Gen2, and then sends a rate signal to the component under test. Since the transmission delay of the rate signal is large, the transmission delay of the rate signal is recorded as DT. At the same time, the first test component will switch the clock frequency of the third-party controller. During the DT period, the first data buffer in the component under test and the second data buffer in the test component will receive invalid data. At this time, the second data buffer is reset by generating a high-level second reset signal (i.e., PCIE-EP end RXFIFO_RST). At time T2, the component under test receives the rate signal sent by the first test component, and at this time, the rate is switched from Gen1 to Gen2, and a high-level first reset signal (i.e., PCIE-PHY end RXFIFO_RST) is generated to reset the first data buffer. At the same time, the component under test will switch the clock frequency of the PCIE physical layer. At the same time, at time T2, after the component under test receives the rate signal, a low-level clock gating signal is generated in the component under test, and the low-level clock gating signal is sent to the first test component, making the clock frequencies at both ends invalid. After time T3, that is, after the switching of the clock frequency signals at both ends is completed, the clock gating signal can be set to a high level so that the new clocks after the switching at both ends is effective at the same time.

[0162] Combination Fig.13 As shown, Fig.13 The present invention is a test device for the PCIE physical layer shown in an exemplary embodiment of the present application. The device is applied to a test system, and the test system includes a component under test and a test component. The component under test includes a test piece provided with a PCIE physical layer, and the test component includes a third-party PCIE controller, and the third-party PCIE controller is used to perform a functional test on the PCIE physical layer. The device includes an acquisition module 1310, a configuration module 1320, and a control module 1330. The acquisition module 1310 is configured to acquire the test requirements of the component under test. The configuration module 1320 is configured to configure the delay parameters of each communication link between the third-party PCIE controller and the PCIE physical layer when the test requirements include testing the transmission function of the component under test, so as to realize the synchronous sampling of the transmission signal in each communication link by the receiving end. The control module 1330 is configured to reset the first data buffer corresponding to the component under test and the second data buffer corresponding to the test component when the test requirements include testing the link establishment function of the component under test, so as to clear the data received by the first data buffer and the second data buffer during the clock frequency switching process. The first data buffer is used to receive data sent by the test component, and the second data buffer is used to receive data sent by the component under test.

[0163] It should be noted that the PCIE physical layer test device provided in the above embodiment and the PCIE physical layer test method provided in the above embodiment belong to the same concept, wherein the specific manner in which each module and unit performs the operation has been described in detail in the method embodiment, and will not be repeated here. In practical applications, the PCIE physical layer test device provided in the above embodiment can allocate the above functions to different functional modules as needed, that is, divide the internal structure of the device into different functional modules to complete all or part of the functions described above, and this is not limited here.

[0164] An embodiment of the present application also provides an electronic device, comprising: one or more processors; a storage device for storing one or more programs, and when the one or more programs are executed by the one or more processors, the electronic device implements the PCIE physical layer testing method provided in the above-mentioned embodiments.

[0165] Fig.14 The structure diagram of the computer system suitable for implementing the electronic device of the embodiment of the present application is shown. It should be noted that: Fig.14 The computer system 1400 of the electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0166] like Fig.14As shown, the computer system 1400 includes a central processing unit (CPU) 1401, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 1402 or the program loaded from the storage part 1408 to the random access memory (RAM) 1403, such as executing the method described in the above embodiment. In the RAM 1403, various programs and data required for system operation are also stored. The CPU 1401, the ROM 1402, and the RAM 1403 are connected to each other through the bus 1404. The input / output (I / O) interface 1405 is also connected to the bus 1404.

[0167] The following components are connected to the I / O interface 1405: an input section 1406 including a keyboard, a mouse, etc.; an output section 1407 including devices such as a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker; a storage section 1408 including a hard disk, etc.; and a communication section 1409 including a model interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 1409 performs communication processing via a model such as the Internet. A drive 1410 is also connected to the I / O interface 1405 as needed. A removable medium 1411, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 1410 as needed so that a computer program read therefrom is installed into the storage section 1408 as needed.

[0168] In particular, according to an embodiment of the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a computer program for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the model through the communication part 1409, and / or installed from the removable medium 1411. When the computer program is executed by the central processing unit (CPU) 1401, various functions defined in the system of the present application are executed.

[0169] It should be noted that the computer-readable medium shown in the embodiment of the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier, which carries a computer-readable computer program. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. A computer program contained on a computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0170] Another aspect of the present application further provides a computer-readable storage medium having a computer program stored thereon, which implements the PCIE physical layer test method as described above when the computer program is executed by a processor. The computer-readable storage medium may be included in the electronic device described in the above embodiment, or may exist independently without being assembled into the electronic device.

[0171] The above content is only a preferred exemplary embodiment of the present application and is not intended to limit the implementation scheme of the present application. A person skilled in the art can easily make corresponding changes or modifications based on the main concept and spirit of the present application. Therefore, the scope of protection of the present application shall be based on the scope of protection required by the claims.

Claims

1. A method for testing a PCIE physical layer, characterized in that: Applied to a test system, the test system includes a component under test and a test component, the component under test includes a test piece provided with a PCIE physical layer, the test component includes a third-party PCIE controller, and the third-party PCIE controller is used to perform a functional test on the PCIE physical layer; the method includes: Obtaining the test requirements of the component under test; In the case where the test requirement includes testing the transmission function of the component under test, delay parameter configuration is performed on each communication link between the third-party PCIE controller and the PCIE physical layer to achieve synchronous sampling of transmission signals in each communication link by the receiving end; In a case where the test requirement includes testing a link establishment function of the component under test, resetting a first data buffer corresponding to the component under test and a second data buffer corresponding to the test component to clear data received by the first data buffer and the second data buffer during a clock frequency switching process; The first data buffer is used to receive data sent by the test component, and the second data buffer is used to receive data sent by the component under test.

2. The method according to claim 1, characterized in that: The component under test further includes a first control module, which is arranged between the PCIE physical layer and the third-party PCIE controller; the test component further includes a second control module, which is connected to the third-party PCIE controller; the delay parameters of each communication link between the third-party PCIE controller and the PCIE physical layer include a first delay parameter; the first delay parameter is used to adjust the delay time of the transmission signal in each communication link; The delay parameter configuration of each communication link between the third-party PCIE controller and the PCIE physical layer to achieve synchronous sampling of transmission signals in each communication link by the receiving end includes: Performing pseudo-random number training through the first control module and the second control module to obtain the first delay parameter; wherein the pseudo-random number training is used to determine the first delay parameter of each communication link between the third-party PCIE controller and the PCIE physical layer; The first delay parameter is respectively configured into a parameter register corresponding to each transmission signal in each communication link.

3. The method according to claim 2, characterized in that The performing pseudo-random number training by the first control module and the second control module to obtain the first delay parameter includes: Performing initial delay parameter configuration on the first control module according to a preset delay parameter sequence; wherein the delay parameter sequence includes a plurality of preset delay times arranged in an arithmetic progression; The first control module and the second control module after configuring the delay parameters mutually send pseudo-random numbers, and verify the received pseudo-random numbers to obtain a data verification result sequence; wherein the data verification result sequence includes data verification results corresponding to each of the preset delay times, and each data verification result is arranged in the order of the preset delay times in the delay parameter sequence; Determine a first critical value and a second critical value corresponding to a valid sampling window according to the data verification result sequence; wherein the first critical value is used to represent the preset delay time configured by the first control module from a data verification success to a data verification failure in the data verification result in the data verification result sequence; and the second critical value is used to represent the preset delay time configured by the first control module from a data verification failure to a data verification success; A first delay parameter of each transmission signal in each communication link is determined according to the first critical value and the second critical value.

4. The method according to claim 2, characterized in that: The delay parameter of each communication link between the third-party PCIE controller and the PCIE physical layer further includes a second delay parameter; the second delay parameter is used to adjust the number of delay bits of the transmission signal in each communication link; The delay parameter configuration of each communication link between the third-party PCIE controller and the PCIE physical layer to achieve synchronous sampling of transmission signals in each communication link by the receiving end includes: Performing constant training through the first control module and the second control module to obtain the second delay parameter; wherein the constant training is used to determine the second delay parameter of each communication link between the third-party PCIE controller and the PCIE physical layer; The second delay parameter is respectively configured in the parameter register corresponding to each transmission signal in each communication link.

5. The method according to claim 4, characterized in that The performing constant training by the first control module and the second control module to obtain the second delay parameter includes: Performing delay parameter configuration on the first control module according to a preset number of delay bits; The first control module and the second control module after configuring the delay parameter mutually send constants to obtain a data reception result; wherein the data reception result includes the reception data of each communication link under the preset number of delay bits; Determining reference data and a flag bit in the reference data from the data receiving result; Compare all received data in the data reception result with the flag bits in the reference data respectively to obtain the relative delay difference between all received data and the flag bits in the reference data; A second delay parameter of each transmission signal in each communication link is determined according to the relative delay difference.

6. The method according to claim 1, characterized in that The test component further includes a third control module, and the third control module is connected to the third-party PCIE controller; The resetting control of the first data buffer corresponding to the component under test and the second data buffer corresponding to the test component to clear the data received by the first data buffer and the second data buffer during the clock frequency switching process includes: Sending a rate signal to the component under test through the test component, and generating a second reset signal to reset the second data buffer; wherein the rate signal is used to trigger the third control module to switch the clock frequency of the PCIE physical layer and the third-party PCIE controller, and the second reset signal is used to restore the second data buffer to an initial state; When the component under test receives the rate signal sent by the test component, a first reset signal is generated to reset the first data buffer; wherein the first reset signal is used to restore the first data buffer to an initial state; When the component under test and the testing component complete the clock frequency switching, the first reset signal and the second reset signal are cancelled.

7. The method according to claim 1, characterized in that The method further comprises: After the tested component and the test component complete the clock frequency switching, the tested component sends a clock gating signal to the test component, so that the switched clock frequencies of the PCIE physical layer and the third-party PCIE controller can take effect at the same time; Wherein, the clock gating signal is used to indicate the clock state of the PCIE physical layer and the third-party PCIE controller; when the clock gating signal is a first preset level, the clock state is a valid state, and when the clock gating signal is a second preset level, the clock state is an invalid state.

8. A PCIE physical layer test system, characterized in that: include: The component under test includes a test piece provided with a PCIE physical layer; Test components, including third-party PCIE controllers; The test component is used to obtain the test requirements of the component under test, and when the test requirements include the transmission function of the component under test, the delay parameter configuration is performed on each communication link between the third-party PCIE controller and the PCIE physical layer to achieve synchronous sampling of the transmission signals in each communication link by the receiving end; And, in the case where the test requirement includes testing the link building function of the component under test, the first data buffer corresponding to the component under test and the second data buffer corresponding to the test component are reset to clear the data received by the first data buffer and the second data buffer during the clock frequency switching process; wherein the first data buffer is used to receive data sent by the test component, and the second data buffer is used to receive data sent by the component under test.

9. The system according to claim 8, characterized in that The component under test further includes a first control module, which is arranged between the PCIE physical layer and the third-party PCIE controller; the test component includes a first test component, which includes the third-party PCIE controller and a second control module; The first control module and the second control module are used to configure delay parameters for each communication link between the third-party PCIE controller and the PCIE physical layer, so as to achieve synchronous sampling of transmission signals in each communication link by the receiving end.

10. The system according to claim 9, characterized in that The first test component also includes a third control module, and the third control module is connected to the third-party PCIE controller; The third control module is used to perform reset control on the first data buffer corresponding to the component under test and the second data buffer corresponding to the test component to clear the data received by the first data buffer and the second data buffer during the clock frequency switching process.

11. The system according to claim 8, characterized in that The test assembly also includes a second test assembly; The second test component is used to obtain the test requirements of the component under test, and call the corresponding test case according to the test requirements to perform functional testing on the component under test.

12. A PCIE physical layer testing device, characterized in that: Applied to a test system, the test system includes a component under test and a test component, the component under test includes a test piece provided with a PCIE physical layer, the test component includes a third-party PCIE controller, and the third-party PCIE controller is used to perform a functional test on the PCIE physical layer; the device includes: An acquisition module, configured to acquire the test requirements of the component under test; A configuration module, configured to, when the test requirement includes testing the transmission function of the component under test, configure delay parameters for each communication link between the third-party PCIE controller and the PCIE physical layer, so as to achieve synchronous sampling of transmission signals in each communication link by a receiving end; a control module configured to, when the test requirement includes testing a link building function of the component under test, reset a first data buffer corresponding to the component under test and a second data buffer corresponding to the test component, so as to clear data received by the first data buffer and the second data buffer during the clock frequency switching process; The first data buffer is used to receive data sent by the test component, and the second data buffer is used to receive data sent by the component under test.

13. An electronic device, characterized in that: include: one or more processors; A storage device for storing one or more programs, when the one or more programs are executed by the one or more processors, enables the electronic device to implement the PCIE physical layer testing method as described in any one of claims 1 to 7.

14. A computer-readable storage medium, characterized in that: Computer-readable instructions are stored thereon, and when the computer-readable instructions are executed by a processor of a computer, the computer is enabled to execute the PCIE physical layer testing method according to any one of claims 1 to 7.

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