System and method for simulating power-on overtime and power-down overtime of power supply module

Abstract

The invention provides a system and method for simulating power-on timeout and power-down timeout of power modules, the system comprises a controller, a programmable logic device, a plurality of power modules and fault modules, the number of the fault modules is the same as that of the power modules, and the fault modules are connected in parallel to the electric energy output ends of the corresponding power modules; the controller is configured to write data of a register of the programmable logic device, so that the programmable logic device sends enable signals to a target power supply module and a fault module corresponding to the target power supply module based on power-on overtime logic or power-down overtime logic, the state of the target power supply module is monitored by reading data of a register of the editable logic device; wherein the target power supply module is at least one power supply module in the plurality of power supply modules.

Description

Technical Field

[0001] The present disclosure relates to the field of power failure, and in particular to a system and method for simulating power-on timeout and power-off timeout of a power module. Background Art

[0002] As a carrier of data processing and data storage, servers play an increasingly important role. In order to ensure the normal operation of each chip constituting the server, it is necessary to provide each chip with a stable power module; and when the power module generates a power-on timeout or power-off timeout due to a fault such as overcurrent (short circuit), overvoltage or overtemperature, the baseboard management controller (BMC) inside the server must effectively monitor the power-on timeout or power-off timeout generated by each power module.

[0003] In order to verify that each power module power-on timeout and power-off timeout trigger can be recorded by the BMC normally every time, and ensure the diagnosability of the system, it is necessary to design test cases, repeatedly simulate the injection of faults into each power module, and then verify the monitoring status of the BMC. Figure 1 As shown, in the related art, the means of simulating fault injection is to manually weld the output of the power module 101 to short-circuit the power module to the ground through a flying wire during testing, thereby causing an overcurrent fault in the power module 101, and then collect the monitoring log of the BMC. However, since there are a large number of power modules 101 in the server, the test method of manually welding the output of the power module 101 to short-circuit the power module to the ground through a flying wire has low test efficiency and high time cost. Summary of the invention

[0004] The present disclosure provides a system and method for simulating power-on timeout and power-off timeout of a power module, which can solve the problems of low test efficiency and high time cost in a test method in which the output of the power module is manually welded to short-circuit the power module to the ground through a flying wire.

[0005] In order to solve the above technical problems, the present disclosure provides a system for simulating power-on timeout and power-off timeout of a power module, comprising:

[0006] A controller, a programmable logic device, a plurality of power modules and fault modules having the same number as the power modules, wherein the fault modules are connected in parallel to the power output ends of the corresponding power modules;

[0007] The controller is configured to write data of the register of the programmable logic device so that the programmable logic device sends an enable signal to the target power module and the fault module corresponding to the target power module based on the power-on timeout logic or the power-off timeout logic, and monitor the status of the target power module by reading data of the register of the editable logic device; wherein the target power module is at least one power module among the multiple power modules.

[0008] Optionally, the programmable logic device includes at least one group of input and output ports, the number of which is the same as that of the power supply modules; the input and output ports include a power enable output terminal, a fault enable output terminal and a power status input terminal;

[0009] The power enable output terminal is connected to the power enable input terminal of the corresponding power module, the fault enable output terminal is connected to the fault enable input terminal of the corresponding fault module, and the power state input terminal is connected to the power state output terminal of the corresponding power module.

[0010] Optionally, the fault module includes at least one of an overcurrent fault module, an overvoltage fault module or an overtemperature fault module.

[0011] Optionally, the overcurrent fault module includes:

[0012] Metal oxide semiconductor tube and discharge resistor;

[0013] The source of the metal oxide semiconductor tube is grounded, the drain of the metal oxide semiconductor tube is connected to the power output end of the power module through the discharge resistor, and the gate of the metal oxide semiconductor tube serves as the fault enable input end of the overcurrent fault module.

[0014] In order to solve the above technical problems, the present disclosure also provides a method for simulating power-on timeout and power-off timeout of a power module, comprising:

[0015] The controller writes data of the register of the programmable logic device so that the programmable logic device sends an enable signal to the target power module and the fault module corresponding to the target power module based on the power-on timeout logic or the power-off timeout logic, and monitors the status of the target power module by reading data of the register of the editable logic device; wherein the target power module is at least one power module among the multiple power modules.

[0016] Optionally, the controller writes data of the register of the programmable logic device so that the programmable logic device sends an enable signal to the target power module and the fault module corresponding to the target power module based on the power-on timeout logic or the power-off timeout logic, and monitors the state of the target power module by reading data of the register of the editable logic device, including:

[0017] Acquire a register list of the programmable logic device; the register list includes a power module enable status register list, a fault module enable status register list and a power module general register list;

[0018] Based on the power module enable status register list, determine the first target write register bit corresponding to the target power module; and, based on the fault module enable status register list, determine the second target write register bit corresponding to the fault module corresponding to the target power module; and, based on the power module general register list, determine the target read register bit corresponding to the target power module;

[0019] Writing data of the first target write register bit and the second target write register bit of the register of the programmable logic device so that the programmable logic device sends an enable signal to a target power module and a fault module corresponding to the target power module based on a power-on timeout logic or a power-off timeout logic;

[0020] After a preset time, the state of the target power module is monitored by reading the data of the target read register bit of the editable logic device.

[0021] Optionally, after the preset time period, monitoring the state of the target power module by reading data of the target read register bit of the editable logic device includes:

[0022] After a preset time, the data of the target read register bit of the editable logic device is read. If the data of the target read register bit contains a fault code corresponding to the target power module, it is determined that the state of the target power is a power-on timeout or a power-off timeout.

[0023] Optionally, the register list also includes a power module status register list; the register bits in the power module status register list are used to store the status of the corresponding power module; the data of the target read register bit is the fault code corresponding to the target power module stored by the programmable logic device after the preset time length if the status of the target power module is an abnormal state.

[0024] Optionally, the data of the first target write register bit and the second target write register bit of the register of the programmable logic device are written so that the programmable logic device sends an enable signal to a target power module and a fault module corresponding to the target power module based on a power-on timeout logic, including:

[0025] Writing data of the second target write register bit of the register of the programmable logic device so that the programmable logic device sends an enable signal to the fault module corresponding to the target power module, so that the fault module corresponding to the target power module triggers a fault;

[0026] The data of the first target write register bit of the register of the programmable logic device is written so that the programmable logic device sends an enable signal to the target power module.

[0027] Optionally, the data of the first target write register bit and the second target write register bit of the register of the programmable logic device are written so that the programmable logic device sends an enable signal to a target power module and a fault module corresponding to the target power module based on a power-off timeout logic, including:

[0028] Writing data of the first target write register bit of the register of the programmable logic device so that the programmable logic device sends an enable signal to a target power module to power on the target power module;

[0029] By writing data of the second target write register of the editable logic device, the programmable logic device sends an enable signal to the fault module corresponding to the target power module.

[0030] The present disclosure provides a system for simulating power-on timeout and power-off timeout of a power module, comprising: a controller, a programmable logic device, a plurality of power modules and fault modules having the same number as the power modules, wherein the fault modules are connected in parallel to the power output terminals of the corresponding power modules;

[0031] The controller is configured to write data of the register of the programmable logic device so that the programmable logic device sends an enable signal to the target power module and the fault module corresponding to the target power module based on the power-on timeout logic or the power-off timeout logic, and monitor the status of the target power module by reading data of the register of the editable logic device; wherein the target power module is at least one power module among the multiple power modules.

[0032] According to the scheme disclosed in the present invention, the controller can send an enable signal to the target power module and the fault module corresponding to the target power module by reading and writing the data of the register of the programmable logic device, thereby enabling the target power module and the fault module corresponding to the target power module, thereby achieving the purpose of simulating the power module failure; compared with the test method in the related art of manually welding the output of the power module to short-circuit the power module to the ground through a flying wire, the test efficiency is high and time cost is saved.

[0033] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

[0035] Figure 1 It is a schematic diagram of the principle of simulating power-on timeout and power-off timeout of a power module in the related art;

[0036] Figure 2 A schematic diagram of the structure of a system for simulating power-on timeout and power-off timeout of a power module provided by an embodiment of the present disclosure;

[0037] Figure 3 A structural diagram of another system for simulating power-on timeout and power-off timeout of a power module provided by an embodiment of the present disclosure;

[0038] Figure 4 A schematic diagram of the principle of a method for simulating power-on timeout and power-off timeout of a power module provided in an embodiment of the present disclosure;

[0039] Figure 5 A schematic diagram of the principle of another method for simulating power-on timeout and power-off timeout of a power module provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0041] A system and method for simulating power-on timeout and power-off timeout of a power module proposed in an embodiment of the present disclosure will be described below with reference to the accompanying drawings.

[0042] In order to solve the problems of low test efficiency and high time cost in the related art of manually welding the output of the power module to short-circuit the power module to the ground through a flying wire, the present invention provides a system for simulating power-on timeout and power-off timeout of the power module. Figure 2 As shown, the system for simulating power-on timeout and power-off timeout of a power module provided by an embodiment of the present disclosure includes:

[0043] A controller 102, a programmable logic device 103, a plurality of power modules 101 and fault modules 104 having the same number as the power modules, wherein the fault modules 104 are connected in parallel to the power output terminals of the corresponding power modules 101;

[0044] The controller 102 is configured to write data of the register of the programmable logic device 103 so that the programmable logic device 103 sends an enable signal to the target power module and the fault module corresponding to the target power module based on the power-on timeout logic or the power-off timeout logic, and monitor the status of the target power module by reading data of the register of the editable logic device 103; wherein the target power module is at least one power module among the multiple power modules 101.

[0045] In one embodiment, the controller 102 may be a component with processing functions such as a microprocessor or a central processing unit. Specifically, in a server, in order to simulate power-on timeout and power-off timeout of multiple power modules in the server, the controller 102 may be a BMC in the server.

[0046] In one embodiment, the programmable logic device 103 (PLD) may adopt programmable array logic (PAL), generic array logic (GAL), field programmable gate array (FPGA), erasable programmable logic device (EPLD), complex programmable logic device (CPLD), etc.; optionally, in the embodiment of the present disclosure, the programmable logic device 103 adopts CPLD.

[0047] In one embodiment, the controller 102 and the programmable logic device 103 are connected via I2C communication, and the controller 102 can read and write the register of the programmable logic device 103 via I2C. For example, the controller 102 can write a specific register bit of the register of the programmable logic device 103 to enable the programmable logic device 103 to send an enable signal to the power module 101 and the fault module 104 corresponding to the specific register bit, thereby enabling the power module 101 and the fault module 104, thereby simulating the power-on timeout and power-off timeout of the power module 101; at the same time, the controller 102 can effectively monitor the status of the power module 101 by reading the specific register bit of the register of the programmable logic device 103.

[0048] In one embodiment, the number of the power modules 101 may be two or more, which is not limited in the present disclosure. If the number of the power modules 101 is two, the number of the fault modules 104 is also two, that is, the power modules 101 and the fault modules 104 are in a one-to-one correspondence, and the power output end of each power module 101 is connected in parallel with the fault module 104, and the fault module 104 is used to inject a fault into the corresponding power module 101. For example, the fault module 104 may include at least one of an overcurrent fault module, an overvoltage fault module or an overtemperature fault module. Taking the overcurrent fault module as an example, when the overcurrent fault module is activated, since the overcurrent fault module is connected in parallel to the power output end of the corresponding power module 101, it will cause the corresponding power module 101 to have an overcurrent fault.

[0049] In summary, according to the scheme disclosed in the present invention, the controller 102 can send an enable signal to the target power module and the fault module corresponding to the target power module by reading and writing the data of the register of the programmable logic device 103, thereby enabling the target power module and the fault module corresponding to the target power module, thereby achieving the purpose of simulating the failure of the power module 101; compared with the test method in the related art of manually welding the output of the power module 101 to short-circuit the power module 101 to the ground through a flying wire, the test efficiency is high and time cost is saved.

[0050] In one embodiment, the programmable logic device 103 includes at least one group of input and output ports of the same number as the power module 101; the input and output ports include a power enable output terminal, a fault enable output terminal and a power status input terminal;

[0051] The power enable output terminal is connected to the power enable input terminal of the corresponding power module 101 , the fault enable output terminal is connected to the fault enable input terminal of the corresponding fault module 104 , and the power state input terminal is connected to the power state output terminal of the corresponding power module 101 .

[0052] In one embodiment, the programmable logic device 103 can output a power enable signal at the power enable output terminal and a fault enable signal at the fault enable output terminal by receiving data written into its register by the controller 102, and at the same time receive the power status signal of the power module through the power status input terminal, determine whether the real-time status of the power supply is abnormal or normal, and store the power status in the corresponding register bit; thereby realizing the function that the controller 102 can simply and conveniently simulate the power-on timeout and power-off timeout of the power module 101 through the programmable logic device 103, and monitor the status of the power module 101.

[0053] In one embodiment, if Figure 3 As shown, the overcurrent fault module includes:

[0054] Metal-Oxide-Semiconductor 106 (MOS for short) and discharge resistor 105;

[0055] The source of the metal oxide semiconductor tube 106 is grounded, the drain of the metal oxide semiconductor tube 106 is connected to the power output end of the power module 101 through the discharge resistor 105, and the gate of the metal oxide semiconductor tube 106 serves as the fault enable input end of the overcurrent fault module.

[0056] In one embodiment, the metal oxide semiconductor tube 106 may be an NMOS tube. Compared with the relay usually used as the overcurrent fault module, the NMOS tube is smaller in size. The discharge resistor 105 may be a single resistor with a suitable resistance, or a plurality of resistors with the same resistance value may be connected in parallel to form the discharge resistor 105, wherein the resistance of the discharge resistor 105 formed by connecting a plurality of resistors in parallel is reduced after being connected in parallel, thereby effectively increasing the overcurrent, thereby ensuring the reliability of the overcurrent fault.

[0057] Based on the system for simulating power-on timeout and power-off timeout of a power module provided in the embodiment of the present disclosure, the embodiment of the present disclosure also provides a method for simulating power-on timeout and power-off timeout of a power module, such as Figure 4 As shown, including:

[0058] Step 401, the controller writes data of the register of the programmable logic device so that the programmable logic device sends an enable signal to the target power module and the fault module corresponding to the target power module based on the power-on timeout logic or the power-off timeout logic, and monitors the status of the target power module by reading data of the register of the editable logic device.

[0059] In one embodiment, the target power module is at least one power module among a plurality of power modules.

[0060] Similar to the system for simulating power-on timeout and power-off timeout of a power module provided in the embodiment of the present disclosure, the method for simulating power-on timeout and power-off timeout of a power module provided in the embodiment of the present disclosure belongs to the same inventive concept as the system for simulating power-on timeout and power-off timeout of a power module provided in the embodiment of the present disclosure, and therefore can also achieve the purpose of simulating power module failure; compared with the testing method in the related art of manually welding the output of the power module to short-circuit the power module to the ground through flying wires, the testing efficiency is high and time cost is saved.

[0061] At the same time, the process of the controller reading and writing registers of the programmable logic device can also be implemented through an automated script, thereby realizing automatic fault injection and collection of power-on timeouts and power-off timeouts without manual intervention, thus saving labor costs.

[0062] In one embodiment, if Figure 5 As shown, step 401 includes:

[0063] Step 501, obtaining a register list of the programmable logic device; the register list includes a power module enable status register list, a fault module enable status register list and a power module status register list;

[0064] In one embodiment, registers of a programmable logic device may be defined so that the programmable logic device outputs an accurate enable signal when receiving a read / write instruction from a controller. The registers of the programmable logic device that may be defined include a power module enable status register, a fault module enable status register, and a power module status register, which correspond to a power module enable status register list, a fault module enable status register list, and a power module status register list, respectively.

[0065] In the embodiment of the present disclosure, eight power modules and corresponding eight fault modules are used as examples for explanation. It should be noted that the number of power modules may also be other numbers. As shown in Table 1 below, Table 1 is a list of power module enable status registers. Among them, the power module enable status register list includes the definition of the power enable output terminal of the programmable logic device corresponding to each power module in the eight power modules, and the register bit where each power enable output terminal is located.

[0066]

[0067]

[0068] Table 1 Power module enable status register list

[0069] As shown in Table 1 below, Table 1 is a fault module enable status register list, wherein the fault module enable status register list includes the definition of the fault enable output terminal of the programmable logic device corresponding to each fault module in the eight fault modules, and the register bit where each fault enable output terminal is located.

[0070]

[0071] Table 2 Fault module enable status register list

[0072] As shown in Table 3 below, Table 3 is a list of general registers of the power module, wherein the list of general registers of the power module includes the definition of the power-on timeout of the power module and the power-off timeout of the power module, and the register bits where the power-on timeout of the power module and the power-off timeout of the power module are located.

[0073]

[0074] Table 3 Power module general register list

[0075] In order to facilitate recording the error codes in Table 3, a power module power-on timeout error code and a power module power-off timeout error code may also be defined, as shown in Table 4 and Table 5 below:

[0076] Power module power-on timeout error code Power module name 0×00 default 0×01 VR1 0×02 VR2 0×03 VR3 0×04 VR4 0×05 VR5 0×06 VR6 0×07 VR7 0×08 VR8

[0077] Table 4 Power module power-on timeout error code

[0078]

[0079]

[0080] Table 5 Power module power failure timeout error code

[0081] As shown in Tables 4 and 5, if the power module VR3 powers on and times out, the data recorded in the 0×0032 position of the register of the programmable logic device is 0×03; if the power module VR3 powers off and times out, the data recorded in the 0×0033 position of the register of the programmable logic device is 0×03; if there is no power-on timeout or power-off timeout of the power module, the data recorded in the 0×0032 and 0×0033 positions of the register of the programmable logic device are both 0×00.

[0082] Step 502, based on the power module enable status register list, determine the first target write register bit corresponding to the target power module; and, based on the fault module enable status register list, determine the second target write register bit corresponding to the fault module corresponding to the target power module; and, based on the power module general register list, determine the target read register bit corresponding to the target power module;

[0083] In one embodiment, taking the target power module as the power module VR3 as an example, according to the power module enable status register list shown in Table 1, it can be determined that the first target write register bit corresponding to the power module VR3 is bit 2 of the register 0×0050 of the programmable logic device, and according to the fault module enable status register list shown in Table 2, it can be determined that the second target write register bit corresponding to the power module VR3 is bit 2 of the register 0×0070 of the programmable logic device. If the power-on timeout of the simulated power module VR3 is reached, the record data of the power-on timeout of the power module VR3 should be in 0×0032 of the register of the programmable logic device. If the power-off timeout of the simulated power module VR3 is reached, the record data of the power-off timeout of the power module VR3 should be in 0×0033 of the register of the programmable logic device.

[0084] Step 503, writing data of the first target write register bit and the second target write register bit of the register of the programmable logic device, so that the programmable logic device sends an enable signal to the target power module and the fault module corresponding to the target power module based on the power-on timeout logic or the power-off timeout logic;

[0085] In one embodiment, the power-on timeout of the simulated power module VR3 is used as an example to illustrate:

[0086] The controller writes 1 to bit2 of the second target write register bit 0×0070, then the EN SHORT MOD3 output is high, the fault module corresponding to the power module VR3 is enabled, and the fault module fault is triggered; then the controller writes 1 to bit2 of the first target write register bit 0×0050, then the EN_VR3 output is high, the power module VR3 is enabled, and the power module is powered on; at this time, since the fault module makes the output of the power module VR3 faulty, the power module VR3 is always in an abnormal state. At this time, after the preset time (preset timeout time), 0×03 can be recorded in 0×0032 of the register of the programmable logic device.

[0087] Take the analog power module VR3 power failure timeout as an example:

[0088] The controller writes 1 to bit2 of register bit 0×0050 of the first target, then the output of EN_VR3 is high, the power module VR3 is enabled, and the power module is powered on; then the controller writes 1 to bit2 of register bit 0×0070 of the second target, then the output of EN_SHORT_MOD3 is high, the fault module corresponding to the power module VR3 is enabled, and the fault module fault is triggered; at this time, since the fault module causes the output of the power module VR3 to fail, the power module VR3 loses power and remains in an abnormal state. At this time, after the preset time (preset timeout time), 0×03 can be recorded in 0×0033 of the register of the programmable logic device.

[0089] Step 504 : After a preset time period, monitor the state of the target power module by reading the data of the target read register bit of the editable logic device.

[0090] Specifically, step 504 includes:

[0091] After a preset time, the data of the target read register bit of the editable logic device is read. If the data of the target read register bit contains a fault code corresponding to the target power module, it is determined that the state of the target power is a power-on timeout or a power-off timeout.

[0092] In one embodiment, the register list also includes a power module status register list; the register bits in the power module status register list are used to store the status of the corresponding power module; the data of the target read register bit is the fault code corresponding to the target power module stored by the programmable logic device after the preset time length if the status of the target power module is an abnormal state.

[0093] As shown in Table 6 below, Table 6 is a power module status register list, wherein the power module status register list includes the definition of the power state input terminal of the programmable logic device corresponding to each power module in the eight power modules, and the register bit where each power state input terminal is located.

[0094]

[0095] Table 6 Power module status register list

[0096] Combined with the above step 503, when the analog power module VR3 is in an abnormal state, bit 2 of 0×0060 of the register of the programmable logic device records 0; after a preset period of time, if the record of bit 2 of 0×0060 of the programmable logic device is still 0, then when the power module VR3 times out when powered on, 0×0032 of the register of the programmable logic device may be recorded as 0×03, and when the power module VR3 times out when powered off, 0×03 may be recorded as 0×0032 of the register of the programmable logic device.

[0097] Therefore, the setting of the power module status register list facilitates the programmable logic device to monitor the status of the power module in real time. When the power module is still in an abnormal state after a preset period of time, the programmable logic device can record the fault code of the power module at 0×0032 or 0×0033.

[0098] In one embodiment, the data of the first target write register bit and the second target write register bit of the register of the programmable logic device written in step 503 enables the programmable logic device to send an enable signal to the target power module and the fault module corresponding to the target power module based on the power-on timeout logic, including:

[0099] Writing data of the second target write register bit of the register of the programmable logic device so that the programmable logic device sends an enable signal to the fault module corresponding to the target power module, so that the fault module corresponding to the target power module triggers a fault;

[0100] The data of the first target write register bit of the register of the programmable logic device is written so that the programmable logic device sends an enable signal to the target power module.

[0101] In one embodiment, since the power-on timeout of the analog power module occurs, the power module needs to fail before the power-on timeout occurs. Therefore, it is necessary to first write the data of the second target write register bit of the register of the programmable logic device so that the fault module corresponding to the power module triggers the fault; and then write the data of the first target write register bit of the register of the programmable logic device so that the power module is powered on.

[0102] In one embodiment, the data of the first target write register bit and the second target write register bit of the register of the programmable logic device written in step 503 enables the programmable logic device to send an enable signal to the target power module and the fault module corresponding to the target power module based on the power-off timeout logic, including:

[0103] Writing data of the first target write register bit of the register of the programmable logic device so that the programmable logic device sends an enable signal to a target power module to power on the target power module;

[0104] By writing data of the second target write register of the editable logic device, the programmable logic device sends an enable signal to the fault module corresponding to the target power module.

[0105] In one embodiment, since the power-off timeout of the simulated power module occurs, the power module needs to be powered on before the power-off timeout can occur. Therefore, it is necessary to first write the data of the first target write register bit of the register of the programmable logic device to power on the power module and then write the data of the second target write register bit of the register of the programmable logic device to cause the fault module corresponding to the power module to trigger the fault.

[0106] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0107] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A system for simulating power-on timeout and power-off timeout of a power module, characterized in that: include: A controller, a programmable logic device, a plurality of power modules and fault modules having the same number as the power modules, wherein the fault modules are connected in parallel to the power output ends of the corresponding power modules; The controller is configured to write data of the register of the programmable logic device so that the programmable logic device sends an enable signal to the target power module and the fault module corresponding to the target power module based on the power-on timeout logic or the power-off timeout logic, and monitor the status of the target power module by reading data of the register of the editable logic device; wherein the target power module is at least one power module among the multiple power modules.

2. The system according to claim 1, characterized in that The programmable logic device comprises at least one group of input and output ports having the same number as the power supply module; the input and output ports comprise a power enable output terminal, a fault enable output terminal and a power status input terminal; The power enable output terminal is connected to the power enable input terminal of the corresponding power module, the fault enable output terminal is connected to the fault enable input terminal of the corresponding fault module, and the power state input terminal is connected to the power state output terminal of the corresponding power module.

3. The system according to claim 1, characterized in that The fault module includes at least one of an overcurrent fault module, an overvoltage fault module or an overtemperature fault module.

4. The system according to claim 3, characterized in that The overcurrent fault module comprises: Metal oxide semiconductor tube and discharge resistor; The source of the metal oxide semiconductor tube is grounded, the drain of the metal oxide semiconductor tube is connected to the power output end of the power module through the discharge resistor, and the gate of the metal oxide semiconductor tube serves as the fault enable input end of the overcurrent fault module.

5. A method for simulating power-on timeout and power-off timeout of a power module, applied to the system according to any one of claims 1 to 4, characterized in that: The method includes: The controller writes data of the register of the programmable logic device so that the programmable logic device sends an enable signal to the target power module and the fault module corresponding to the target power module based on the power-on timeout logic or the power-off timeout logic, and monitors the status of the target power module by reading data of the register of the editable logic device; wherein the target power module is at least one power module among the multiple power modules.

6. The method according to claim 5, characterized in that The controller writes data of the register of the programmable logic device so that the programmable logic device sends an enable signal to the target power module and the fault module corresponding to the target power module based on the power-on timeout logic or the power-off timeout logic, and monitors the state of the target power module by reading data of the register of the editable logic device, including: Acquire a register list of the programmable logic device; the register list includes a power module enable status register list, a fault module enable status register list and a power module general register list; Based on the power module enable status register list, determine the first target write register bit corresponding to the target power module; and, based on the fault module enable status register list, determine the second target write register bit corresponding to the fault module corresponding to the target power module; and, based on the power module general register list, determine the target read register bit corresponding to the target power module; Writing data of the first target write register bit and the second target write register bit of the register of the programmable logic device so that the programmable logic device sends an enable signal to a target power module and a fault module corresponding to the target power module based on a power-on timeout logic or a power-off timeout logic; After a preset time, the state of the target power module is monitored by reading the data of the target read register bit of the editable logic device.

7. The method according to claim 6, characterized in that After the preset time, monitoring the state of the target power module by reading the data of the target read register bit of the editable logic device includes: After a preset time, the data of the target read register bit of the editable logic device is read. If the data of the target read register bit contains a fault code corresponding to the target power module, it is determined that the state of the target power is a power-on timeout or a power-off timeout.

8. The method according to claim 6, characterized in that The register list also includes a power module status register list; the register bits in the power module status register list are used to store the status of the corresponding power module; the data of the target read register bit is the fault code corresponding to the target power module stored by the programmable logic device after the preset time length if the status of the target power module is an abnormal state.

9. The method according to claim 6, characterized in that The data of the first target write register bit and the second target write register bit of the register of the programmable logic device are written, so that the programmable logic device sends an enable signal to a target power module and a fault module corresponding to the target power module based on a power-on timeout logic, including: Writing data of the second target write register bit of the register of the programmable logic device so that the programmable logic device sends an enable signal to the fault module corresponding to the target power module, so that the fault module corresponding to the target power module triggers a fault; The data of the first target write register bit of the register of the programmable logic device is written so that the programmable logic device sends an enable signal to the target power module.

10. The method according to claim 6, characterized in that The data of the first target write register bit and the second target write register bit of the register of the programmable logic device are written, so that the programmable logic device sends an enable signal to the target power module and the fault module corresponding to the target power module based on the power-off timeout logic, including: Writing data of the first target write register bit of the register of the programmable logic device so that the programmable logic device sends an enable signal to a target power module to power on the target power module; By writing data of the second target write register of the editable logic device, the programmable logic device sends an enable signal to the fault module corresponding to the target power module.

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