Communication chip and DDR access method thereof, arbiter and electronic equipment
By introducing DDR access method and QoS dynamic control mechanism in communication chip, the problems of bandwidth waste and bandwidth congestion in DDR access control are solved, and more efficient bandwidth utilization and communication performance improvement are achieved.
Patent Information
- Application Number
- CN202411999226.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-05-02
AI Technical Summary
In the prior art, DDR access control is difficult to balance bandwidth waste and bandwidth congestion.
By introducing a DDR access method into the communication chip, the priority of the processing module and the QoS dynamic control mechanism are used to adjust the DDR access bandwidth to avoid bandwidth waste and congestion.
It effectively reduces bandwidth waste during the process of processing module accessing DDR, reduces resource consumption, improves bandwidth utilization, solves the problem of bandwidth waste and bandwidth congestion, and thus accelerates the bit processing rate and improves the working performance of communication chips.
Smart Images
Figure CN119917424A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of communication technology, and in particular to a communication chip and a DDR access method thereof, an arbitrator, and an electronic device. Background Art
[0002] In communication chips, the amount of data allowed to access DDR (double data rate synchronous dynamic random access memory) within a certain period of time is limited. Currently, bandwidth is generally set to restrict the access of processing modules to DDR, preventing a processing module from occupying the access channel to DDR for a long time and blocking other processing modules from accessing DDR. When bandwidth congestion is solved by setting bandwidth to restrict the access of processing modules to DDR, if no other processing modules access DDR, bandwidth will be wasted. Summary of the invention
[0003] The technical problem to be solved by the present disclosure is to overcome the defect that the DDR access control method in the prior art is difficult to balance bandwidth waste and bandwidth congestion, and to provide a communication chip and its DDR access method, arbitrator, and electronic device.
[0004] The present invention solves the above technical problems through the following technical solutions:
[0005] In a first aspect, a DDR access method is provided, which is applied to a communication chip, wherein the communication chip includes a DDR, a first processing module and a second processing module, wherein the first processing module and the second processing module are respectively connected to the DDR through a bus, and the first processing module and the second processing module are respectively preset with a priority for accessing the DDR; the DDR access method includes:
[0006] In response to the access request of the first processing module to the DDR, allocating a DDR access bandwidth matching the priority of the first processing module to the first processing module;
[0007] In response to the access request of the second processing module to the DDR, determining whether the usage of the DDR access bandwidth of the first processing module reaches a bandwidth threshold;
[0008] In response to the DDR access bandwidth of the first processing module reaching a bandwidth threshold, the priority of the first processing module is lowered and / or the QoS value of the bus is lowered, and the DDR access bandwidth is reallocated to the first processing module and / or the second processing module.
[0009] Optionally, determining whether usage of the DDR access bandwidth of the first processing module reaches a bandwidth threshold includes:
[0010] Determine whether the usage of the DDR access bandwidth of the first processing module reaches a bandwidth threshold within a time period;
[0011] In response to the DDR access bandwidth of the first processing module reaching a bandwidth threshold, lowering the priority of the first processing module and / or lowering the QoS value of the bus, including:
[0012] In response to the DDR access bandwidth of the first processing module reaching a bandwidth threshold within a time period, the priority of the first processing module is reduced and / or the QoS value of the bus is reduced.
[0013] Optionally, the bandwidth threshold is determined according to the time taken for statistically determining the access bandwidth once and the number of operations for accessing the DDR; wherein the time taken for statistically determining the access bandwidth once and the number of operations for accessing the DDR are obtained through the bus statistics.
[0014] Optionally, the access request is a write request; and the DDR access method further includes:
[0015] In response to a write operation corresponding to the write request of the first processing module failing and a usage of the DDR access bandwidth reaching a bandwidth threshold, controlling the bus to stop the write data operation on the DDR;
[0016] Alternatively, in response to the DDR access bandwidth of the first processing module reaching the bandwidth threshold and the first processing module is processing the current code block, the bus is controlled to continue writing the code block into the DDR and stop writing back and stopping updating the storage area of the code block.
[0017] Optionally, the access request is a read request; and the DDR access method further includes:
[0018] In response to a read operation corresponding to the read request of the first processing module failing and the usage of the DDR access bandwidth reaching a bandwidth threshold, the ITI_AXI bus is controlled to stop the read-back data operation on the DDR.
[0019] Optionally, the DDR access method further comprises: in response to the first processing module accessing the DDR exceeding a preset working time period, discarding soft bits of remaining code blocks of the first processing module.
[0020] Optionally, the DDR access method further comprises: in response to the DDR access bandwidth of the first processing module reaching the bandwidth threshold and the first processing module is processing a current code block, determining a reduction amount of the QoS value according to a remaining processing amount of the code block; the remaining processing amount is positively correlated with the reduction amount;
[0021] And / or, the first processing module and the second processing module are connected to the DDR via a set of buses;
[0022] And / or, after the step of reducing the QoS value of the bus, the method further includes: limiting the number of outstanding commands to be less than or equal to 3.
[0023] In a second aspect, an arbitrator is provided, which is applied to a communication chip, wherein the communication chip further includes a DDR, a first processing module and a second processing module, wherein the first processing module and the second processing module are respectively connected to the DDR via a bus, and the first processing module and the second processing module are respectively preset with a priority for accessing the DDR; the arbitrator includes:
[0024] an allocation module, configured to allocate, to the first processing module, a DDR access bandwidth matching the priority of the first processing module in response to the access request of the first processing module to the DDR;
[0025] a determination module, configured to determine, in response to the access request of the second processing module to the DDR, whether the usage of the DDR access bandwidth of the first processing module reaches a bandwidth threshold;
[0026] A control module is used to reduce the priority of the first processing module and / or reduce the QoS value of the bus in response to the DDR access bandwidth of the first processing module reaching a bandwidth threshold, and reallocate DDR access bandwidth to the first processing module and / or the second processing module.
[0027] According to a third aspect, a communication chip is provided, comprising at least one processor, wherein the processor is configured to execute program instructions to perform the DDR access method as described in any one of the first aspects.
[0028] According to a fourth aspect, a computer program product is provided, comprising a computer program, wherein when the computer program is executed by a processor, the DDR access method according to any one of the first aspects is implemented.
[0029] On the basis of being in accordance with the common sense in the art, the above-mentioned preferred conditions can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.
[0030] The positive progressive effect of the present disclosure lies in that: in the present disclosure, a dynamic control mechanism of QOS is introduced into the bandwidth limitation function according to the changes in the scheduling of the processing module, and QoS control is added to optimize the bandwidth limitation mechanism, thereby reducing the bandwidth waste in the process of the processing module accessing DDR, reducing resource consumption, and improving bandwidth utilization. It can well solve the balance problem of bandwidth waste and bandwidth congestion, thereby accelerating the bit processing rate and improving the working performance of the communication chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1A flowchart of a DDR access method provided by an exemplary embodiment of the present disclosure;
[0032] Figure 2 A schematic diagram of a communication chip to which a DDR access method provided by an exemplary embodiment of the present disclosure is applied;
[0033] Figure 3 A schematic diagram of a bandwidth control strategy adopted by a DDR access method provided by an exemplary embodiment of the present disclosure;
[0034] Figure 4 The present invention provides a schematic structural diagram of an electronic device according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION
[0035] The present disclosure is further described below by way of examples, but the present disclosure is not limited to the scope of the examples.
[0036] Prefixes such as "first" and "second" are used in the embodiments of the present disclosure only to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. The use of prefixes such as ordinal numbers to distinguish description objects in the embodiments of the present disclosure does not constitute a limitation on the described objects. For the statement of the described objects, please refer to the description in the context of the embodiments, and no unnecessary limitation should be constituted due to the use of such prefixes. In addition, in the description of the present embodiment, unless otherwise specified, the meaning of "plurality" is two or more.
[0037] In the embodiments of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.
[0038] Figure 1 A flowchart of a DDR access method provided by an exemplary embodiment of the present disclosure is applied to a communication chip, wherein the communication chip includes a DDR and at least two processing modules. Each processing module is connected to the DDR via a bus, and each processing module is preset with a priority for accessing the DDR. For ease of understanding, the following describes the access process of the DDR access by taking the communication chip including a first processing module and a second processing module as an example.
[0039] See also Figure 1 , the DDR access method comprises the following steps:
[0040] Step 101: In response to a DDR access request from a first processing module, allocate a DDR access bandwidth matching the priority of the first processing module to the first processing module.
[0041] The first processing module allocated with the DDR access bandwidth can access the DDR according to the DDR access bandwidth. The access request includes a read request and a write request, and correspondingly, the access of the processing module to the DDR includes a read operation and a write operation.
[0042] Step 102: In response to the access request to the DDR from the second processing module, determine whether the usage of the DDR access bandwidth of the first processing module reaches a bandwidth threshold.
[0043] The number of second processing modules that simultaneously initiate access requests to the DDR may be one or more. When multiple second processing modules simultaneously initiate access requests to the DDR, the access request initiated by the second processing module with the highest priority is responded to.
[0044] In step 102, it is determined whether the usage of the DDR access bandwidth of the first processing module reaches a bandwidth threshold, that is, it is determined whether the DDR access bandwidth resources allocated to the first processing module are exhausted.
[0045] Step 103: in response to the DDR access bandwidth of the first processing module reaching the bandwidth threshold, lower the priority of the first processing module and / or lower the QoS value of the bus, and reallocate DDR access bandwidth to the first processing module and / or the second processing module.
[0046] The first processing module and / or the second processing module to which the DDR access bandwidth is reallocated can access the DDR. The specific implementation process of the second processing module accessing the DDR is similar to that of the first processing module accessing the DDR, which will not be repeated here.
[0047] It should be noted that, when the first processing module accesses the DDR according to the DDR access bandwidth, if no second processing module initiates an access request to the DDR, there is no need to execute steps 102 to 103, that is, even if the DDR access bandwidth of the first processing module reaches the bandwidth threshold, the DDR can still be accessed.
[0048] In this embodiment, through the priority adjustment strategy and / or QoS dynamic control mechanism, when the first processing module has a "bandwidth share" (that is, the DDR access bandwidth does not reach the bandwidth threshold), the first processing module has a relatively high priority to access the DDR. If the "bandwidth share" has been used up, the priority of accessing the DDR can be lowered or the QoS value can be reduced. This ensures that the second processing module is not blocked from accessing the DDR (the second processing module has a higher priority than the first processing module). When the second processing module does not access the DDR, the first processing module can access the DDR, thereby avoiding the waste of bandwidth.
[0049] In this embodiment, according to the changes in the scheduling of the processing module, a dynamic control mechanism of QOS is introduced in the bandwidth limitation function, and QoS control is added to optimize the bandwidth limitation mechanism, thereby reducing the bandwidth waste and resource consumption in the process of the processing module accessing DDR, and improving bandwidth utilization. It can well solve the balance problem of bandwidth waste and bandwidth congestion, thereby accelerating the bit processing rate and improving the working performance of the communication chip.
[0050] In one embodiment, the processing module includes a BRP module (bit rand process, bit level data processor) and other data processing modules included in the communication chip. The following takes the first processing module as an example of the BRP module to briefly introduce the BRP module. Figure 2 A structural schematic diagram of a BRP module provided for an exemplary embodiment of the present disclosure, in which the BRP module mainly includes: HARQ_SFT_RD, HARQ_RD, HARQ_COMB, HARQ_WB, DE-RM, LDPC_DEC, HBITS_OUT, and DLMAC_OUT are all data processing units.
[0051] All or part of the above data processing units are connected to DDR, DLMAC_ACC, and MAC_BUF through ITI_ARBITER (arbitrator) and ITI_AXI (bus). Steps 101 to 103 in this embodiment can be specifically executed by the arbitrator.
[0052] In the BRP mechanism, DDR is usually used to store the computer's operating system, running programs, and temporary data, and directly exchanges data with the CPU as main memory.
[0053] DLMAC_ACC may involve the data buffering and access control mechanism of the MAC layer in the downlink, ensuring effective management and transmission of data at the MAC layer.
[0054] MAC_BUF usually refers to the buffer associated with the MAC layer, which is used to temporarily store data.
[0055] HARQ_SFT_RD (HARQ shift Read): used to read the newly transmitted CB (after TB segmentation and other processing).
[0056] HARQ_RD (HARQ Read): used to read the CB with decoding errors.
[0057] HARQ_COMB (HARQ Combining): HARQ combining is used in the HARQ mechanism for the communication chip (receiver) to soft combine the received code blocks. Soft combining allows the receiver to combine the first transmitted and retransmitted code blocks to increase the probability of successful decoding.
[0058] HARQ_WB (HARQ Write back): used to compress the CB with verification errors and transmit it to DDR.
[0059] DE-RM (De-rate Matching): Rate matching is used to remove or adjust redundant bits during the rate matching process of encoded data to adapt to a specific transmission rate. This process helps optimize data transmission and ensure that data is transmitted at the optimal rate.
[0060] LDPC_DEC (LDPC Decoder): LDPC decoder, a decoder for Low-Density Parity-Check (LDPC) codes. LDPC is an efficient error-correcting code used for error detection and correction in data transmission. The LDPC decoder is responsible for decoding the received data to recover the original information.
[0061] HBITS_OUT (Harq Bits Out): HARQ bit output, used for the output of data bits after HARQ processing. These bits are sent to the physical layer for transmission after coding, modulation and HARQ processing.
[0062] DLMAC_OUT (Downlink MAC Out): Downlink MAC output, used to send downlink data to the physical layer after processing at the MAC layer. This includes data that has gone through HARQ processing, scheduling, and MAC layer (Media Access Control) functions.
[0063] The above units are key components of the HARQ mechanism in communication chips, and together ensure high reliability and efficiency of data transmission.
[0064] The implementation mechanism of BRP is described below.
[0065] The decoder of the communication chip completes a CB (code block) decoding to obtain hard bits, and performs cyclic redundancy check CRC calculation on the hard bits to determine whether the check result is correct. If the CRC check is correct, it is transmitted to the address space specified by the software through DLMAC_OUT or HBITS_OUT. For the hard bits of the common channel, they are output through HBITS_OUT. For the hard bits of the unicast channel, when DLMAC bypass (bypass function at the MAC layer), the information bits are output to DDR through HBITS_OUT; when DLMAC (Data Link and Medium Access Control) is enabled, the information bits are output to DDR or MAC_BUF through DLMAC_OUT, and DLMAC_ACC is notified to read.
[0066] If the current transmission data is new and the CB cyclic redundancy check is correct, DLMAC_OUT will output the information bits to MAC_BUF. When the data transmission of a TB (transpaort block) is completed, the cyclic redundancy check of all CBs is correct and the cyclic redundancy check of TB is also correct, DLMAC_ACC is notified for processing. On the contrary, if a CB cyclic redundancy check error or the last TB cyclic redundancy check error is found, all the information bits that have been transmitted to IRAM (internal random access memory) need to be moved to DDR and the space of MAC_BUF is released.
[0067] If the current transmission data is a retransmission, then when the CB cyclic redundancy check is correct, DLMAC_OUT will transfer the information bits to the corresponding position of DDR. When all CB cyclic redundancy checks are correct and TB cyclic redundancy checks are correct, DLMAC_ACC is notified for processing.
[0068] The working mechanism of HARQ_RD in the HARQ mechanism: when CB is retransmitted, read the relevant information of the current HARQ request processing according to the CB buffer (buffer used to store coded bits), read the historical data from DDR, and prepare the data merge of HARQ_COMB; before executing the HARQ_RD task, it is necessary to read the corresponding CB buffer position to obtain whether the destination is the DDR space, and determine whether HARQ_RD's access to DDR is restricted, that is, whether reading data from DDR will be restricted. If it is restricted, adjust its bandwidth priority (for example, adjust the priority to the highest), and read directly without restriction. If CB is in DDR, HARQ_RD uses the read head pointer as the address of DDR, HARQ_RD reads data through the ITI structure, and writes the data in the FIFO (first-in-first-out buffer), and reads it out if it exceeds one page (the maximum amount of data that the FIFO buffer can store at one time).
[0069] The working mechanism of HARQ_WB in the HARQ mechanism: When the CRC check of the current CB fails or the software configuration forces the output of soft bits, the data of the current CB after HARQ_COMB is compressed and written to DDR. Before executing the HARQ_WB task, it is necessary to consider whether the destination space is DDR and whether the writing of DDR is restricted, that is, whether the compression into DDR will be restricted. If it is restricted, adjust its bandwidth priority (for example, adjust the priority to the highest) and write directly to DDR without restriction. When the page length is newly updated, HARQ_WB controls the writing of soft bits to DDR; or when the software forces writing to DDR, HARQ_WB controls the writing of soft bits to DDR. HARQ_WB calculates the address of the page to be written outside the chip based on the configuration information {cc_id, harq_id, tb_index, cb_index} and the base address. DDR reserves enough space for each CB to completely write each CB into DDR. If the historical CB has been stored in the internal storage space or is newly transmitted, all soft bits are directly written to DDR; if the historical CB has been stored in DDR and the code block has not changed, only the data of the current transmission part is written back. The CB buffer is updated after the HARQ_WB ends.
[0070] In one embodiment, in order to save resources, each processing unit is connected to the DDR through a set of buses. For example, see Figure 2, BRP has only one set of ITI_AXI buses to access the external space, while there are multiple processing units inside the BRP that need to access this bus. When two processing units access the bus at the same time, a suitable arbitration mechanism needs to be adopted to avoid conflicts. Preferably, each processing unit included in the BRP uses a QoS mechanism to access the bus. BRP mainly completes the access arbitration of HARQ_RD / HARQ_WB / DLMA C_OUT / HBITS_OUT. HARQ_RD has a high priority, and the other three can be set with the same priority. Data transmission is carried out in sequence according to the order of initiating access requests or based on the LRG (Least Recently Granted, bus arbitration) strategy.
[0071] In one embodiment, determining whether the usage of the DDR access bandwidth of the first processing module reaches the bandwidth threshold includes: determining whether the usage of the DDR access bandwidth of the first processing module reaches the bandwidth threshold within a time period. In response to the DDR access bandwidth of the first processing module reaching the bandwidth threshold within the time period, lowering the priority of the first processing module. The time period can be set according to actual needs.
[0072] The bandwidth limitation function sets a certain time period and the number of beats allowed to access the read / write DDR within this period. This setting is used to restrict the access of the processing module to the DDR, preventing a processing module from occupying the access channel to the DDR for a long time and blocking the access of other processing modules to the DDR.
[0073] In this embodiment, two DDR bandwidth controllers are provided: a write DDR bandwidth controller and a read DDR bandwidth controller. The bandwidth limitation function provides a set of functions that count the number of data read in and written out actually completed by the ITI_AXI bus, and make judgments based on the software configuration value. Among them, the wr and rd of the register represent the write bandwidth judgment process and the read bandwidth judgment process respectively. The two results indicate whether a write operation or a read operation can be performed, but they do not represent only statistics of write or read operations. The specific configuration parameters of the register are as follows:
[0074] FEC DDR BW CTRL.bw budget en control enable, when it is 1, it starts the statistics and judgment behavior. The judgment result can be used for two purposes: statistical reporting and feedback regulation.
[0075] FEC_DDR_BW_CTRL.bw_hard_en is the enable flag for feedback control. When valid, the hardware is automatically controlled, and the judgment result of the BRP module is used for feedback and actual control of the BRP module's read and write behavior to DDR, abandoning DDR soft bit read (read DDR bandwidth controller) and abandoning DDR soft bit write (write DDR bandwidth controller). When this register is invalid, the software can query BUS_MON_MODEwr_mon_status and BUS_MON_MODE.rd_monstatus. The previous module actively discards the off-chip retransmission TB stored in DDR and directly feeds back NACK.
[0076] FEC_DDR_BWCTRL.wr_cycle_num, TIME_COUNTER.wr_time_cnter are used to configure the bandwidth of the write controller; wr_cycle num refers to the bandwidth threshold for read and write operations allowed by the write bandwidth decision within wr_time_cnter; wr_time_cnter refers to the time used for a write bandwidth decision statistic, which actually represents the number of 1MHz clock counts, and the value is equal to the duration in microseconds.
[0077] FEC_DDR_BWCTRL.rd_cycle_num,TIME_COUNTER.rd_time_cnter configures the bandwidth of the read controller; rd_cycle_num refers to the bandwidth threshold of the read and write operations allowed by the read bandwidth decision within rd_time_cnter; wr_time_cnter refers to the time used for a read bandwidth decision statistic, which actually represents the number of 1MHz clock counts, and the value is equal to the duration in microseconds.
[0078] In this embodiment, the bandwidth limitation function controls reading and writing separately, and the control method varies according to different scenarios.
[0079] In one embodiment, the bandwidth threshold is determined based on the time used to determine the access bandwidth once and the number of operations to access the DDR. It is known that wr_cycle_num or rd_cycle_num represents the number of read / write operations, and one operation will read / write 64 bits, i.e., 8 bytes of data. Therefore, the bandwidth threshold calculation formula provided by the parameters is as follows:
[0080] Upper threshold = (cycle_num / time_cnter)*8MBps;
[0081] Wherein, time_cnter indicates the time taken to access bandwidth judgment statistics once; cycle_num indicates the number of operations to access DDR.
[0082] BUS_MON_MODE.wr_mon_sr_sel[1:0], selects the buckle pulse of the write DDR bandwidth controller; refers to the type of operation that needs to be counted for write bandwidth judgment, the 0th bit indicates whether to count the number of read operations, and the 1st bit indicates whether to count the number of write operations.
[0083] BUS_MON_MODE.rd_mon_sr_sel[1:0], selects the buckle pulse of the read DDR bandwidth controller; refers to the type of operation that needs to be counted for read bandwidth judgment, the 0th bit indicates whether to count the number of read operations, and the 1st bit indicates whether to count the number of write operations.
[0084] Therefore, cycle_num in the bandwidth threshold calculation formula may be the number of read or write operations, or the sum of the number of read and write operations, depending on the mon_sr_sel configuration corresponding to the judgment process. The calculated bandwidth rate can be understood as the bandwidth occupied by read or write, or the total bandwidth occupied by read and write.
[0085] Case 1 of failure to write DDR bandwidth: When bandwidth limit is set, when the write DDR bandwidth reaches the threshold, the ITI_AXI bus needs to stop writing data and does not update the CB memory (storage area). For example, the first processing module sets a write bandwidth limit, and in response to the failure of the write operation corresponding to the write request of the first processing module and the DDR access bandwidth reaches the bandwidth threshold, the ITI_AXI bus is controlled to stop writing data. In this embodiment, by monitoring the data flow on the ITI_AXI bus and stopping data transmission when the bandwidth limit is reached, this control mechanism ensures that the bandwidth capacity of the DDR will not be exceeded, preventing possible overflow or data loss.
[0086] Case 2 of failure to write DDR bandwidth: When the current CB is being processed, even if the bandwidth is insufficient at this time, the CB will continue to be written to completion, and will be re-judged before the start of the next CB. For this CB, only cyclic redundancy check CRC processing is performed, and it is not written back, and the CB memory will not be updated. For example, the first processing module sets a write bandwidth limit. In response to the DDR access bandwidth of the first processing module reaching the bandwidth threshold and the first processing module is processing the current code block, the ITI_AXI bus is controlled to continue writing the code block to the DDR, and stops writing back and updating the storage area of the code block. In this embodiment, if the current CB is being processed, the writing of this CB will continue to be completed. This is to ensure the integrity and consistency of the data and avoid data corruption caused by interruptions. The CB memory is not updated in order to maintain the consistency and stability of the memory.
[0087] Failure to read DDR bandwidth: When bandwidth limit is set, and the DDR read bandwidth reaches the bandwidth threshold, the ITI_AXI bus needs to stop reading back data. If the data of the next CB exists in DDR, the DDR will not be read, and no merging will be performed. If there is internal storage space, there will be no impact. For example, the first processing module sets a read bandwidth limit. In response to the failure of the read operation corresponding to the read request of the first processing module and the usage of the DDR access bandwidth reaches the bandwidth threshold, the ITI_AXI bus is controlled to stop the read back data operation of the DDR to ensure data security and system stability.
[0088] In one embodiment, in step 103, when the DDR access bandwidth of the first processing module reaches the bandwidth threshold and the access to the DDR is not completed, the priority reduction level of the first processing module is set according to experience. For example, each time it is reduced by one level, if there are two second processing modules initiating access requests to access the DDR, the priorities of the first processing module and the two second processing modules are: second processing module a, first processing module, second processing module b. For example, each time it is reduced by two levels, if there are two second processing modules initiating access requests to access the DDR, the priorities of the first processing module and the two second processing modules are: second processing module a, second processing module b, first processing module.
[0089] In one embodiment, when the DDR access bandwidth of the first processing module reaches the bandwidth threshold and the access to the DDR is not completed in step 103, the priority reduction level of the first processing module is determined according to the remaining processing volume of the current code block being processed by the first processing module, and the reduction level is positively correlated with the remaining processing volume. In this embodiment, adjusting the priority of the first processing module according to the actual application scenario can further improve the utilization rate of the bandwidth.
[0090] In one embodiment, in step 103, when the DDR access bandwidth of the first processing module reaches the bandwidth threshold and the access to the DDR is not completed, the QoS value of the bus is reduced according to experience.
[0091] In one embodiment, in step 103, when the DDR access bandwidth of the first processing module reaches the bandwidth threshold and the first processing module is processing the current code block, the reduction amount of the QoS value is determined according to the remaining processing amount of the code block; the remaining processing amount is positively correlated with the reduction amount. In this embodiment, adjusting the priority of the first processing module according to the actual application scenario can further improve the utilization rate of the bandwidth.
[0092] When designing a bus system, the bandwidth assessment must first meet the needs of all processing modules / master concurrent scenarios, and secondly, consider how to balance the access needs of processing modules / masters when these processing modules / masters initiate various requests at the same time to adapt to the limited available resources of the bus interconnection. This involves many issues, such as 1. High-priority processing modules / masters may occupy the bus bandwidth for a long time, and other transmissions may not get enough bandwidth, and their transmission delays are difficult to guarantee; 2. Even if some transmissions have the highest priority, due to the bus architecture and the different data buffers on each transmission path; high-priority transmissions may be blocked outside the arbitration module by low-priority sequential transmissions, resulting in the inability to transmit priority information to the lower-level network.
[0093] In this embodiment, a QoS dynamic control mechanism is introduced in the bandwidth optimization control. If the "bandwidth share" of the first processing module has not been used up, the QoS is configured with a relatively large value to ensure that the first processing module has a higher priority in accessing the DDR; if the "bandwidth share" has been used up, the QoS is configured with a relatively small value to prevent the first processing module from blocking the second processing module from accessing the DDR. The QoS dynamic control mechanism can ensure that an order is established in a high-speed but chaotic system, making data transmission orderly and controllable, thereby solving the problems of bandwidth waste and congestion.
[0094] It should be noted that:
[0095] (1) Each processing module is an ITI interface, while AWQOS and ARQOS are signals on the AXI bus and need to be controlled on the AXI bus. AWQOS is for write operation priority, and ARQOS is for read operation priority.
[0096] (2) When QoS is low, the number of outstanding (unresolved, unfinished) commands needs to be limited. In one embodiment, the step of lowering the QoS value of the bus also includes: limiting the number of outstanding commands to be less than or equal to 3. If a lot of outstanding commands are sent out when the QoS is set to be low, and when a new time period arrives, there are still many outstanding commands (low QoS) that have not been processed. Obviously, this will reduce the efficiency of the processing module accessing the DDR. For the processing module, HARQ_SWB is outstanding to 1 when writing to DDR, so there is no need to worry about the above problem. But for HARQ_RD, consider limiting the outstanding to 2 to 3 when the QoS is low.
[0097] In one embodiment, the DDR access method further includes: in response to the first processing module accessing the DDR exceeding a preset working time period, the first processing module discards the soft bits of the remaining code blocks. The preset working time period can be set according to actual needs, for example, set to a PDSCH (Physical Downlink Shared Channel) working time period.
[0098] See also Figure 3 In this embodiment, the DDR bandwidth control strategy is implemented through an arbitration mechanism, which specifically includes two parts: bandwidth limitation and time limitation. The bandwidth limitation part is introduced above, and the time limitation (timeout mechanism) part is introduced below.
[0099] Since each PDSCH has a working time period of the processing module, if this working time is exceeded, it will result in the failure to complete the decoding of all CBs in time, thereby obtaining the values of all CB cyclic redundancy checks and TB cyclic redundancy checks and reporting them to the base station. Access to DDR also needs to be limited to the PDSCH working time period (the time for rate matching and LDPC decoding also needs to be subtracted). If this time period is exceeded, the processing module will "discard" the soft bits of the remaining CBs that have not been processed, and record them for relevant processing to reduce resource usage. The BRP mechanism adopted in this embodiment can ensure that even if the soft bits of the remaining CBs are discarded, it will not affect data transmission.
[0100] In addition, there is another option, that is, when a timeout occurs, only an abnormal interrupt notification is generated, but the remaining CB soft bits continue to be transmitted.
[0101] Corresponding to the aforementioned DDR access method embodiments, the present disclosure further provides an embodiment of an arbitrator, which is used to implement the DDR access method provided by any of the aforementioned embodiments.
[0102] The arbiter is applied to a communication chip, the communication chip further comprising a DDR, a first processing module and a second processing module, the first processing module and the second processing module are respectively connected to the DDR via a bus, and the first processing module and the second processing module are respectively preset with a priority for accessing the DDR; the arbiter comprises:
[0103] an allocation module, configured to allocate, to the first processing module, a DDR access bandwidth matching the priority of the first processing module in response to the access request of the first processing module to the DDR;
[0104] a determination module, configured to determine, in response to the access request of the second processing module to the DDR, whether the usage of the DDR access bandwidth of the first processing module reaches a bandwidth threshold;
[0105] A control module is used to reduce the priority of the first processing module and / or reduce the QoS value of the bus in response to the DDR access bandwidth of the first processing module reaching a bandwidth threshold, and reallocate DDR access bandwidth to the first processing module and / or the second processing module.
[0106] Optionally, the determination module is specifically used for:
[0107] Determine whether the usage of the DDR access bandwidth of the first processing module reaches a bandwidth threshold within a time period;
[0108] In response to the DDR access bandwidth of the first processing module reaching a bandwidth threshold, lowering the priority of the first processing module and / or lowering the QoS value of the bus, including:
[0109] In response to the DDR access bandwidth of the first processing module reaching a bandwidth threshold within a time period, the priority of the first processing module is reduced and / or the QoS value of the bus is reduced.
[0110] Optionally, the bandwidth threshold is determined according to the time taken for statistically determining the access bandwidth once and the number of operations for accessing the DDR; wherein the time taken for statistically determining the access bandwidth once and the number of operations for accessing the DDR are obtained through the bus statistics.
[0111] Optionally, the access request is a write request; and the control module is further configured to:
[0112] In response to a write operation corresponding to the write request of the first processing module failing and a usage of the DDR access bandwidth reaching a bandwidth threshold, controlling the bus to stop the write data operation on the DDR;
[0113] Alternatively, in response to the DDR access bandwidth of the first processing module reaching the bandwidth threshold and the first processing module is processing the current code block, the bus is controlled to continue writing the code block into the DDR and stop writing back and stopping updating the storage area of the code block.
[0114] Optionally, the access request is a read request; the control module is further configured to:
[0115] In response to a read operation corresponding to the read request of the first processing module failing and the usage of the DDR access bandwidth reaching a bandwidth threshold, the ITI_AXI bus is controlled to stop the read-back data operation on the DDR.
[0116] Optionally, the control module is further configured to: in response to the DDR access bandwidth of the first processing module reaching the bandwidth threshold and the first processing module is processing a current code block, determine a reduction amount of the QoS value according to a remaining processing amount of the code block; the remaining processing amount is positively correlated with the reduction amount;
[0117] Optionally, the first processing module and the second processing module are connected to the DDR via a set of buses;
[0118] Optionally, after the step of reducing the QoS value of the bus, the control module is further configured to: limit the number of outstanding commands to be less than or equal to 3;
[0119] Optionally, the control module is further configured to: in response to the first processing module accessing the DDR exceeding a preset working time period, discard soft bits of remaining code blocks of the first processing module.
[0120] For the device embodiment, since it basically corresponds to the method embodiment, the relevant parts can refer to the partial description of the method embodiment. The device embodiment described above is only illustrative, wherein the modules described as separate components may or may not be physically separated, and the components as modules may or may not be physical modules, that is, they may be located in one place, or they may be distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the disclosed solution.
[0121] Figure 4 This is a structural diagram of an electronic device shown in an exemplary embodiment of the present disclosure, the electronic device includes a memory, a processor, and a computer program stored in the memory and used to run on the processor, and the processor implements the DDR access method described in any of the above embodiments when executing the computer program. Figure 4 The electronic device 40 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.
[0122] like Figure 4 As shown, the electronic device 40 may be in the form of a general-purpose computing device, for example, it may be a server device. The components of the electronic device 40 may include, but are not limited to: at least one processor 41, at least one memory 42, and a bus 43 connecting different system components (including the memory 42 and the processor 41).
[0123] The bus 43 includes a data bus, an address bus, and a control bus.
[0124] The memory 42 may include a volatile memory, such as a random access memory (RAM) 421 and / or a cache memory 422 , and may further include a read-only memory (ROM) 423 .
[0125] The memory 42 may also include a program tool 425 (or utility) having a set (at least one) of program modules 424, such program modules 424 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.
[0126] The processor 41 executes various functional applications and data processing by running the computer program stored in the memory 42, such as the DDR access method provided in any of the above embodiments.
[0127] The electronic device 40 may also communicate with one or more external devices 44 (e.g., keyboards, pointing devices, etc.). Such communication may be performed via an input / output (I / O) interface 45. Furthermore, the electronic device 40 may also communicate with one or more networks (e.g., local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) via a network adapter 46. As shown, the network adapter 46 communicates with other modules of the electronic device 40 via a bus 43. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 40, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID (disk array) systems, tape drives, and data backup storage systems, etc.
[0128] It should be noted that although several modules / modules or submodules / modules of the electronic device are mentioned in the above detailed description, this division is merely exemplary and not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules / modules described above can be embodied in one module / module. Conversely, the features and functions of one module / module described above can be further divided into multiple modules / modules to be embodied.
[0129] The embodiment of the present disclosure further provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the DDR access method provided by any of the above embodiments is implemented.
[0130] The readable storage medium may include but is not limited to: a portable disk, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical storage device, a magnetic storage device or any suitable combination of the above.
[0131] The embodiment of the present disclosure further provides a computer program product, including a computer program, wherein when the computer program is executed by a processor, the DDR access method described in any one of the above is implemented.
[0132] Among them, the program code for executing the computer program product of the present disclosure can be written in any combination of one or more programming languages, and the program code can be executed completely on the user device, partially on the user device, as an independent software package, partially on the user device and partially on a remote device, or completely on the remote device.
[0133] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, but these changes and modifications all fall within the protection scope of the present disclosure.
Claims
1. A DDR access method, characterized in that: Applied to a communication chip, the communication chip includes a DDR, a first processing module and a second processing module, the first processing module and the second processing module are respectively connected to the DDR through a bus, and the first processing module and the second processing module are respectively preset with a priority for accessing the DDR; the DDR access method includes: In response to the access request of the first processing module to the DDR, allocating a DDR access bandwidth matching the priority of the first processing module to the first processing module; In response to the access request of the second processing module to the DDR, determining whether the usage of the DDR access bandwidth of the first processing module reaches a bandwidth threshold; In response to the DDR access bandwidth of the first processing module reaching a bandwidth threshold, the priority of the first processing module is lowered and / or the QoS value of the bus is lowered, and the DDR access bandwidth is reallocated to the first processing module and / or the second processing module.
2. The DDR access method according to claim 1, characterized in that: Determining whether the usage of the DDR access bandwidth of the first processing module reaches a bandwidth threshold includes: Determine whether the usage of the DDR access bandwidth of the first processing module reaches a bandwidth threshold within a time period; In response to the DDR access bandwidth of the first processing module reaching a bandwidth threshold, lowering the priority of the first processing module and / or lowering the QoS value of the bus, including: In response to the DDR access bandwidth of the first processing module reaching a bandwidth threshold within a time period, the priority of the first processing module is reduced and / or the QoS value of the bus is reduced.
3. The DDR access method according to claim 1, characterized in that: The bandwidth threshold is determined according to the time taken for statistically determining the access bandwidth once and the number of operations for accessing the DDR; wherein the time taken for statistically determining the access bandwidth once and the number of operations for accessing the DDR are obtained through the bus statistics.
4. The DDR access method according to claim 1, characterized in that: The access request is a write request; the DDR access method further includes: In response to a write operation corresponding to the write request of the first processing module failing and a usage of the DDR access bandwidth reaching a bandwidth threshold, controlling the bus to stop the write data operation on the DDR; Alternatively, in response to the DDR access bandwidth of the first processing module reaching the bandwidth threshold and the first processing module is processing the current code block, the bus is controlled to continue writing the code block into the DDR and stop writing back and stopping updating the storage area of the code block.
5. The DDR access method according to claim 1, characterized in that: The access request is a read request; the DDR access method further includes: In response to a read operation corresponding to the read request of the first processing module failing and the usage of the DDR access bandwidth reaching a bandwidth threshold, the ITI_AXI bus is controlled to stop the read-back data operation on the DDR.
6. The DDR access method according to any one of claims 1 to 5, characterized in that: The DDR access method further includes: in response to the first processing module accessing the DDR exceeding a preset working time period, discarding soft bits of remaining code blocks of the first processing module.
7. The DDR access method according to any one of claims 1 to 5, characterized in that: The DDR access method further comprises: in response to the DDR access bandwidth of the first processing module reaching the bandwidth threshold and the first processing module is processing a current code block, determining a reduction amount of the QoS value according to a remaining processing amount of the code block; the remaining processing amount is positively correlated with the reduction amount; And / or, the first processing module and the second processing module are connected to the DDR via a set of buses; And / or, after the step of reducing the QoS value of the bus, the method further includes: limiting the number of outstanding commands to be less than or equal to 3.
8. An arbitrator, characterized in that: Applied to a communication chip, the communication chip further includes a DDR, a first processing module and a second processing module, the first processing module and the second processing module are respectively connected to the DDR through a bus, and the first processing module and the second processing module are respectively preset with a priority for accessing the DDR; the arbitrator includes: an allocation module, configured to allocate, to the first processing module, a DDR access bandwidth matching the priority of the first processing module in response to the access request of the first processing module to the DDR; a determination module, configured to determine, in response to the access request of the second processing module to the DDR, whether the usage of the DDR access bandwidth of the first processing module reaches a bandwidth threshold; A control module is used to reduce the priority of the first processing module and / or reduce the QoS value of the bus in response to the DDR access bandwidth of the first processing module reaching a bandwidth threshold, and reallocate DDR access bandwidth to the first processing module and / or the second processing module.
9. A communication chip, comprising at least one processor, characterized in that: The processor is configured to execute program instructions to perform the DDR access method according to any one of claims 1 to 7.
10. An electronic device comprising a computer program, characterized in that When the computer program is executed by a processor, the DDR access method according to any one of claims 1 to 7 is implemented.