Controller of storage device and instruction scheduling method

Abstract

The invention discloses a controller of a storage device and an instruction scheduling method. According to the controller and the instruction scheduling method, dynamic priority arbitration is introduced through the priority configuration table, so that the CA instructions sent to the CA bus are relatively average and are not sent in a certain instruction type in a heap mode any more, the CA instructions on the CA bus and data transmission on the DQ bus can be better executed in parallel, and therefore the bandwidth utilization rate of the DQ bus is increased.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a controller of a storage device and an instruction scheduling method. Background Art

[0002] Currently, many storage devices, such as USB flash memory, SD card, CF card, SSD, eMMC embedded storage card, UFS device, etc., use flash storage media (especially NAND storage media) as the main storage media, and it has gradually become the mainstream form. Compared with the traditional magnetic media storage, the performance has made a qualitative leap. The traditional flash interface protocol (ONFi or Toggle) used by such storage devices uses the same bus for command / address and data transmission. As the data transmission rate of the flash interface increases, the command / address transmission rate does not change, resulting in an increase in the proportion of command / address transmission time, which in turn leads to a bottleneck in the improvement of the data transmission bandwidth of the flash interface.

[0003] In order to solve the problem of traditional flash memory interface improvement, the new flash memory interface protocol (for example, Separate Command Address, SCA for short) separates the command / address and data transmission and puts them on two different transmission buses for transmission, that is, CA instructions are placed on the command and address (CA) bus for transmission, and DQ instructions (that is, data to be written to or read from the flash memory storage medium) are placed on the data (DATA, also called DQ) bus for transmission.

[0004] As the transmission rate of the DQ bus increases, the time it takes for storage devices to read a unit of data is also decreasing. However, since the CA bus is a low-speed signal, its operating frequency has a maximum limit, and the time required for CA instructions on the CA bus can no longer be shortened by increasing the frequency. When the time required for transmission on the DQ bus is less than the time required for CA instructions on the CA bus, data transmission on the DQ bus will be idle because it needs to wait for the execution of CA instructions on the CA bus. Figure 1 As shown, data transmission G needs to wait for instruction A / B / C / D / G to be executed before it can start to execute; during the execution of instruction G, the DQ bus is idle, resulting in a waste of DQ bus bandwidth. Summary of the invention

[0005] In view of this, an embodiment of the present disclosure provides a controller of a storage device and an instruction scheduling method to solve the above problems.

[0006] According to a first aspect of an embodiment of the present disclosure, a controller of a storage device is provided, wherein the controller is coupled to a plurality of flash memory particles through a CA bus and a DQ bus in a first channel, wherein the first channel further includes a CA control unit coupled to the CA bus and a DQ control unit coupled to the DQ bus, and the controller includes: An instruction cache unit, which caches CA instructions and DQ instructions adapted to the multiple flash memory particles one-to-one through multiple instruction queues; A priority configuration table maintenance unit, used to store a plurality of priority configuration tables corresponding to a plurality of scenarios, wherein the priority configuration table stores an initial amount and a priority balance of a CA instruction used in a corresponding scenario, and the priority configuration table maintenance unit further sets an initial value of the priority balance in each priority configuration table to the initial amount, and when all priority balances in the priority configuration table are equal to zero, resets all priority balances to the initial amount; An arbitration unit is used to obtain the current scene of the controller for multiple CA instructions to be arbitrated, and obtain the priority balance corresponding to each CA instruction in the current scene from the priority balance table, and use the CA instruction with the largest priority balance as the preferred CA instruction of the CA control unit, and subtract 1 from the priority balance corresponding to the CA instruction with the largest priority balance.

[0007] In some embodiments, the multiple scenarios include: random read, random write, continuous read, and continuous write.

[0008] In some embodiments, in each of the multiple scenarios, a CA instruction sequence needs to be executed to complete a read data operation or a write data operation on the flash memory particle, and the priority configuration table maintenance unit sets the initial amount of each CA instruction in the priority configuration table of the corresponding scenario according to the number of each CA instruction in the corresponding CA instruction sequence of the corresponding scenario.

[0009] In some embodiments, the method further includes: a command parser, configured to convert received host commands into CA instructions and DQ instructions adapted to the plurality of flash memory particles, and cache the instructions into the plurality of instruction queues.

[0010] In some embodiments, the system further includes: firmware for determining the current scene of the controller according to a received host command.

[0011] In some embodiments, the priority configuration table maintenance unit further adjusts the initial amount in each priority configuration table according to the bandwidth utilization of the DQ bus in the past period of time.

[0012] In some embodiments, the arbitration unit further determines, for multiple CA instructions to be arbitrated, whether each CA instruction can be executed in parallel with a DQ instruction currently being executed.

[0013] According to a second aspect of an embodiment of the present disclosure, a storage device is provided, comprising: a coupled controller and a flash memory storage medium, the flash memory storage medium being composed of flash memory particles, and the controller being any one of the controllers described above.

[0014] According to a third aspect of an embodiment of the present disclosure, there is provided an instruction scheduling method for a controller of a storage device, wherein the controller is coupled to a plurality of flash memory particles through a CA bus and a DQ bus in a first channel, wherein the first channel further comprises a CA control unit coupled to the CA bus and a DQ control unit coupled to the DQ bus, wherein the instruction scheduling method comprises: Taking out a plurality of instructions from a plurality of instruction queues respectively, the plurality of instruction queues respectively corresponding to the instructions cached and adapted to the plurality of flash memory particles under the first channel; Obtaining the current scene of the controller, and selecting a priority configuration table according to the current scene, wherein a plurality of priority configuration tables correspond to a plurality of scenes; Retrieve the priority balance of each CA instruction to be arbitrated from the selected priority configuration table; comparing the priority balances of the CA instructions to be arbitrated, and taking the CA instruction with the largest priority balance as the preferred CA instruction of the CA control unit; Subtract 1 from the priority balance corresponding to the CA instruction with the largest priority balance in the selected priority configuration table; and When the priority balances of each CA instruction in the priority configuration table are all 0, the priority balances of each CA instruction are reset to the initial amount.

[0015] In some embodiments, the instruction scheduling method further includes: adjusting the initial quota in each priority configuration table according to the bandwidth utilization rate of the DQ bus in the past period of time.

[0016] The disclosed embodiment introduces dynamic priority arbitration through a priority configuration table, so that the various CA instructions sent to the CA bus are more evenly distributed, rather than a certain type of instruction being sent in a cluster. This allows the CA instructions on the CA bus and the data transmission on the DQ bus to be better executed in parallel, thereby improving the bandwidth utilization of the DQ bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which: Figure 1It is a schematic diagram of the CA bus and the DQ bus executing the CA instruction and the DQ instruction respectively; Figure 2 is a schematic block diagram of a host system; Figure 3 is a schematic diagram of the structure of a controller of a storage device provided by an embodiment of the present disclosure; Figure 4A and Figure 4B An example of the structure of a priority configuration table is given; Figure 5 An example of a priority configuration table for random reads designed according to an embodiment of the present disclosure is given; Figure 6 An example of a priority configuration table for continuous writing designed according to an embodiment of the present disclosure is given; Figure 7 An example diagram of random read CA instruction and DQ instruction executed on CA bus and DQ bus respectively is given; Figure 8 A flow chart of an instruction scheduling method provided by an embodiment of the present disclosure is given. DETAILED DESCRIPTION

[0018] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0019] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present invention without the description of these details. In order to avoid confusing the essence of the present invention, known methods, processes, flows, components and circuits are not described in detail.

[0020] Unless the context clearly requires otherwise, the words "include", "comprising" and the like throughout the specification and claims should be interpreted as inclusive rather than exclusive or exhaustive; that is, as "including but not limited to". In the description of the present invention, it should be understood that the terms "first", "second", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0021] Figure 2 is a schematic block diagram of an exemplary host system 100. The host system 100 is, for example, a personal computer, a notebook computer, or a server.

[0022] The host system 100 includes a host device 110 (e.g., a computer system including a main processor and a memory) and a storage device. The host device 110 may issue a host command to the storage device so that the storage device manages the data stored in the storage device according to the command. For example, the host device 110 may be communicatively connected to the storage device (e.g., through the host interface 121) and issue various commands (e.g., READ, WRITE, UNMAP, REASSIGNBLOCK, TRIM, etc.) to the storage device. The storage device may store, update, read and / or otherwise manage host data according to the address range prompted by the command. Once the command is executed, the storage device may transmit a response to the host device 110, indicating that the command has been successfully completed.

[0023] The storage device is composed of a controller 120 and a storage medium 130. The controller 120 parses the host command and converts the host command into an instruction adapted to the storage medium 130, then executes the instruction and feeds back the instruction result to the host device 110. The controller 120 is composed of various hardware and software, such as a (micro)processor, a cache unit such as SRAM and DRAM, and an interface circuit, and the software is a series of software programs that complete management functions, including but not limited to data reading and writing, bad block management, wear leveling, garbage collection, power failure recovery, and write balancing technology.

[0024] The storage medium 130 is used to store data. There are multiple channels (such as CH0 and CH1) between the controller 120 and the storage medium 130, and the controller 120 and the storage medium 130 exchange data through each channel.

[0025] At present, the mainstream storage medium 130 is a flash memory storage medium (especially a NAND storage medium). Usually, each channel (such as CH0 or CH1 in the figure) is coupled to N (N is 2, 4, 8, etc.) flash memory particles, and the controller 120 needs to operate the corresponding flash memory particles through each channel. When the SCA protocol is used as the flash memory interface protocol, each channel includes two buses: a DQ bus and a CA bus. The controller 120 executes a DQ instruction through the DQ bus to write data to or read data from the flash memory particles, and executes a CA instruction through the CA bus to perform command / address operations on the flash memory particles.

[0026] Referring to the background art, in order to fully utilize the transmission bandwidth of the DQ bus, it is necessary to execute the CA instruction as much as possible when data is being transmitted on the DQ bus. Figure 3 A schematic structural diagram of an improved controller 120 based on this concept provided in an embodiment of the present disclosure is given.

[0027] like Figure 3As shown, the controller 120 includes a host interface 201, a command parser 202, an instruction cache unit 203, an arbitration unit 204, a data path 205, a priority configuration table maintenance unit 206, a CA control unit 207, and a DQ control unit 208. For the convenience of description, only the data paths through the same channel (e.g. Figure 1 CH0 in the channel is coupled to the flash memory particles DIE0 to DIEn of the controller 120. The channel includes a CA control unit 207, a DQ control unit 208, a CA bus 11 and a DQ bus 12. The CA control unit 207 is coupled to the flash memory particles DIE0 to DIEn through the CA bus 11, and the DQ control unit 208 is coupled to the flash memory particles DIE0 to DIEn through the DQ bus 12.

[0028] The host interface 201 is used to receive host commands from the host device 110 and to transmit data with the host device 110. The host command is, for example, a write command to write data to the flash storage medium 130, a read command to read data from the flash storage medium, a query command to check the execution status of the write command or the read command, etc. The interface protocol adopted by the host interface 201 determines the various command types and formats. For example, when UPIU (UFS Protocol Information Units) is adopted as the interface protocol, the transmitted UPIU packet is composed of multiple parts such as a header and a data payload. The header provides information such as the interaction type, length, and attributes, and the data payload provides the specific content of the command or data.

[0029] The command parser 202 parses the received host command, converts it into instructions that are compatible with the flash memory particles, and stores the instructions in the instruction cache unit 203. Flash memory particles of different products support different instruction sets. For example, for data write operations, different flash memory particle products have different instruction formats, so the command parser 202 is required to convert the received host command. The command parser 202 can convert one host command into multiple instructions that are compatible with the flash memory particles, or multiple host commands into multiple instructions that are compatible with the flash memory particles. The embodiment of the present disclosure does not specifically limit the correspondence between the host command and the number of instructions that are compatible with the flash memory particles.

[0030] Based on the SCA protocol, the command parser 202 divides the instructions for operating the flash memory particles via the CA bus 11 and the DQ bus 12 into CA instructions and DQ instructions, and caches the CA instructions and DQ instructions in the instruction cache unit 203. CA instructions are generally operation instructions related to the configuration of the flash memory particles, such as instructions for reading the status of the flash memory particles and instructions for modifying the status of the registers on the flash memory particles. DQ instructions are generally instructions for actual data transmission between the flash memory particles, such as writing data to the flash memory particles or reading data from the flash memory particles.

[0031] In some embodiments, the instruction cache unit 203 includes multiple first-in-first-out instruction queues corresponding to multiple flash memory particles, each instruction queue stores CA instructions and DQ instructions for the same flash memory particle. The figure shows (n+1) instruction queues corresponding to flash memory particles DIE0 to DIEn.

[0032] The arbitration unit 204 is used to monitor the working status of the CA control unit 207 and the DQ control unit 208. If the CA control unit 207 is idle, the CA instruction is taken out from multiple instruction queues. If there are multiple CA instructions taken out, it is necessary to arbitrate the multiple CA instructions and send the selected CA instruction to the CA execution unit 207 for execution. If the DQ control unit 207 is idle, a DQ instruction is selected according to similar steps and sent to the DQ control unit 208 through the data path 205 for data transmission. Here, the data path 205 is similar to the data cache unit. The data to be written into the flash memory particles is first placed in the data path 205 and then taken away by the DQ control unit 208. The data read from the flash memory particles is first placed in the data path 205 by the DQ control unit 208 and then transmitted to the host device 110.

[0033] The arbitration performed by the arbitration unit 204 needs to ensure that the selected CA instruction or DQ instruction can be executed in parallel with the currently executed DQ instruction or CA instruction. Due to the limitation of the SCA protocol, some DQ instructions and CA instructions cannot be executed in parallel, so the arbitration unit 204 needs to detect and exclude some instructions that conflict with the currently executed CA instructions and DQ instructions, so as to ensure that the CA instructions or DQ instructions sent to the CA control unit or DQ control unit can be executed in parallel with the currently executed DQ instructions or CA instructions. For example, if the CA instruction is a DQ-relate instruction, it conflicts with the DQ data transmission command of the same LUN (Logical Unit Number), and the two commands cannot be executed at the same time.

[0034] However, if there are multiple CA instructions that can be executed in parallel with the currently executing DQ instruction, the arbitration unit 204 usually makes an arbitration based on the priority of the CA instruction. However, in traditional processing, the priority of each CA instruction is fixed. However, in the embodiment of the present disclosure, the arbitration unit 204 refers to the priority configuration table in the priority configuration table maintenance unit 206 for arbitration. The priority configuration table has a data format as shown in Figure 4A. Since users use hard disks in a relatively regular manner most of the time, they are generally divided into random read, random write, continuous read, continuous write and other scenarios. In these scenarios, the CA instruction sequences used to complete reading or writing data from the flash memory particles are different. Therefore, the following is adopted: Figure 4A The priority configuration table shown provides priority quota query information for different CA instructions in different scenarios. Specifically, each instruction type in each scenario has an initial quota, and the priority balance of each instruction type is counted. The priority balance is equal to the initial quota during initialization. When the priority balance is 0, the priority is the lowest. When the arbitration unit 204 refers to the priority configuration table for arbitration, it first obtains the priority balance of the instruction type corresponding to each CA instruction to be arbitrated in the current scenario by retrieval, and then compares the priority balances corresponding to the various CA instructions to be arbitrated, selects the CA instruction corresponding to the maximum priority balance as the preferred instruction to be sent to the CA execution unit 207, and after the arbitration is completed or the preferred instruction is executed, the corresponding priority balance is subtracted by 1. The priority configuration table maintenance unit also resets all priority balances to the initial quota when all priority balances in the priority configuration table are equal to zero.

[0035] It should be pointed out that the arbitration unit 204 needs to obtain the current scene of the controller in order to determine the priority configuration table adapted to the current scene. Therefore, the controller 120 should also include a functional module for determining the current scene of the controller based on the currently received host command or other information. The functional module can be implemented as firmware (of course not limited to this).

[0036] It should also be noted that although Figure 4A A plurality of priority configuration tables are provided, each of which corresponds to a corresponding scene. However, it is also possible to store the priority configuration tables in the following manner: Figure 4B Organizational priority configuration table shown.

[0037] The following describes the embodiments of the present disclosure by taking random reading and continuous writing as examples.

[0038] In the random read scenario, the data that the host needs to obtain is randomly stored in different flash memory particles. The read data operation executes basically the same CA instruction sequence, which includes: Read status, read the flash memory status, used to determine whether the flash memory particles are ready and whether a read operation command can be sent; Read, that is, send a read operation command Read status: Read the N flash status to determine whether it is ready or not. DATA OUT: Send a command to make NAND ready to start data transmission Read transfer: Perform data transfer.

[0039] The first four CA instructions are executed by the CA line, and the fifth is a DQ instruction for data transmission on the DQ bus (transmission start and end commands need to be sent on the CA bus). For the same flash memory particle, the above CA instruction sequence must be executed sequentially.

[0040] Figure 5 An example of a priority configuration table for random reads designed according to an embodiment of the present disclosure is given. According to this example, if the arbitration unit 204 currently arbitrates the three CA instructions Read status, data out and Read, then Read status and data out have the same priority, and Read has the lowest priority.

[0041] In the scenario of continuous writing, the CA instructions that need to be sent to complete a data write include: 4 Program pages, 4 Program confirms, and 7 Read statuses. Therefore, in this priority configuration table, the initial quotas of these CA instructions are configured as 4 / 4 / 7 respectively. Figure 6 An example of a priority configuration table for continuous writing designed according to an embodiment of the present disclosure is given. According to this example, if the arbitration unit 204 currently arbitrates the three CA instructions Program page, Program confirm and Read status, Program page has the highest priority, and Read status has the same priority as Program confirm.

[0042] In the above example, the initial amount of each CA instruction in the priority configuration table is set according to the number of CA instructions in the CA instruction sequence corresponding to the read / write operation in the random read and continuous write scenarios, that is, the initial amount of each CA instruction in the priority configuration table is equal to the number of CA instructions in the CA instruction sequence corresponding to the read / write operation, and can also be set in multiples. This setting method can be extended to random write and continuous read scenarios. Finally, similar Figure 7 The execution effect, Figure 7A schematic diagram of the random read CA instruction and DQ instruction executed on the CA bus and DQ bus is given. Figure 7 It can be seen that the CA instruction, Read status, Read and DATA OUT, which mark the start or end of DQ transmission, are executed alternately. The CA instruction executed on the CA bus can basically be executed in parallel with the data transmission on the DQ bus, so that the bandwidth utilization of the DQ bus is relatively high.

[0043] It should be understood that the initial quota of each instruction in the priority configuration table plays a key role in the execution order of CA instructions on the CA bus. In order to better maintain the quota, the priority configuration table maintenance unit 206 can also count the bandwidth utilization of the DQ bus in the past period of time. When the bandwidth utilization is not good, adjust the initial quota in the priority configuration table to improve the bandwidth utilization of the subsequent DQ bus.

[0044] Accordingly, the embodiment of the present disclosure also provides an instruction scheduling method, which can be used in a controller of a storage device to implement arbitration logic for distributing CA instructions to a CA control unit, and the controller is coupled to multiple flash memory particles through a first channel. The instruction scheduling method can be implemented as a combination of one or more of a software program, firmware, and hardware logic. The flowchart of the instruction scheduling method is shown in FIG. Figure 8 shown.

[0045] In step S801 , a plurality of CA instructions to be arbitrated are received.

[0046] In step S802, a priority configuration table is selected according to the current scenario.

[0047] In step S803, the priority balance of each CA instruction is retrieved from the selected priority configuration table.

[0048] In step S804, the priority balances of the various CA instructions are compared, and the CA instruction with the largest priority balance is taken as the preferred CA instruction.

[0049] In step S805, the priority balance corresponding to the CA instruction with the largest priority balance in the selected priority configuration table is reduced by 1.

[0050] In step S806, when the priority balance of each CA instruction in the priority configuration table is 0, the priority balance of each CA instruction is reset to the initial amount.

[0051] According to this embodiment, first design Figure 4AAs shown, multiple priority configuration tables corresponding to multiple scenarios are provided, each priority configuration table stores the initial amount and priority balance of the CA instruction of the corresponding scenario, and then for multiple CA instructions to be arbitrated, a priority configuration table is selected according to the current scenario, and the priority balance of each CA instruction to be arbitrated is obtained from the selected priority configuration table, and the priority balances of the multiple CA instructions to be arbitrated are compared, and the CA instruction with the largest priority balance is the preferred CA instruction. If the instruction can be executed in parallel with the DQ instruction currently being executed by the DQ control unit of the controller, it can be sent to the CA control unit in the controller for execution, and then the priority balance corresponding to the CA instruction in the selected priority configuration table is subtracted by 1, and when the priority balances of all CA instructions in a certain priority configuration table are 0, the priority balances of all CA instructions in the priority configuration table are reset to the initial amount.

[0052] As a preferred embodiment, the instruction scheduling method further includes: setting the initial quota corresponding to each CA instruction in multiple priority configuration tables according to the number of each CA instruction in the CA instruction sequence corresponding to the read / write operation in each scenario.

[0053] As a preferred embodiment, the instruction scheduling method further includes: counting bandwidth utilization of the DQ bus in the past period of time, and when the bandwidth utilization is poor, adjusting the initial quota in the priority configuration table to improve the bandwidth utilization of subsequent DQ buses.

[0054] In summary, the controller of the storage device provided by the embodiments of the present disclosure and the instruction scheduling method applied to the controller introduce dynamic priority arbitration through a priority configuration table, and through the initial quota design of the priority configuration table, the various CA instructions sent to the CA bus are relatively evenly distributed, and a certain type of instruction is no longer sent in a cluster. In this way, in the SCA mode, the CA instructions on the CA bus and the data transmission on the DQ bus can be better executed in parallel, thereby improving the bandwidth utilization of the DQ bus.

[0055] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A controller of a storage device, wherein the controller is coupled to a plurality of flash memory particles through a CA bus and a DQ bus in a first channel, wherein the first channel further comprises a CA control unit coupled to the CA bus and a DQ control unit coupled to the DQ bus, wherein the controller comprises: An instruction cache unit, which caches CA instructions and DQ instructions adapted to the multiple flash memory particles one-to-one through multiple instruction queues; A priority configuration table maintenance unit, used to store a plurality of priority configuration tables corresponding to a plurality of scenarios, wherein the priority configuration table stores an initial amount and a priority balance of a CA instruction used in a corresponding scenario, and the priority configuration table maintenance unit further sets an initial value of the priority balance in each priority configuration table to the initial amount, and when all priority balances in the priority configuration table are equal to zero, resets all priority balances to the initial amount; An arbitration unit is used to obtain the current scene of the controller for multiple CA instructions to be arbitrated, and obtain the priority balance corresponding to each CA instruction in the current scene from the priority balance table, and use the CA instruction with the largest priority balance as the preferred CA instruction of the CA control unit, and subtract 1 from the priority balance corresponding to the CA instruction with the largest priority balance.

2. The controller according to claim 1, wherein: The multiple scenarios include: random reading, random writing, continuous reading and continuous writing.

3. The controller according to claim 1, wherein: In each of the multiple scenarios, a CA instruction sequence needs to be executed to complete a read data operation or a write data operation on the flash memory particle, and the priority configuration table maintenance unit sets the initial amount of each CA instruction in the priority configuration table of the corresponding scenario according to the number of each CA instruction in the corresponding CA instruction sequence of the corresponding scenario.

4. The controller according to claim 1, further comprising: The command parser is used to convert the received host command into CA instructions and DQ instructions adapted to the multiple flash memory particles, and cache them into the multiple command queues.

5. The controller according to claim 1, further comprising: The firmware is used to determine the current scene of the controller according to the received host command.

6. The controller according to claim 1, wherein: The priority configuration table maintenance unit further adjusts the initial quota in each priority configuration table according to the bandwidth utilization of the DQ bus in the past period of time.

7. The controller according to claim 1, wherein: The arbitration unit further determines, for a plurality of CA instructions to be arbitrated, whether each CA instruction can be executed in parallel with a DQ instruction currently being executed.

8. A storage device, comprising: A coupled controller and a flash memory storage medium, wherein the flash memory storage medium is composed of flash memory particles, and the controller is the controller according to any one of claims 1 to 7.

9. A method for scheduling instructions, for a controller of a storage device, wherein the controller is coupled to a plurality of flash memory particles via a CA bus and a DQ bus in a first channel, wherein the first channel further comprises a CA control unit coupled to the CA bus and a DQ control unit coupled to the DQ bus, wherein the method for scheduling instructions comprises: Taking out a plurality of instructions from a plurality of instruction queues respectively, wherein the plurality of instruction queues respectively correspond to the instructions of the plurality of flash memory particles cached and adapted to the first channel; Obtaining the current scene of the controller, and selecting a priority configuration table according to the current scene, wherein a plurality of priority configuration tables correspond to a plurality of scenes; Retrieve the priority balance of each CA instruction to be arbitrated from the selected priority configuration table; comparing the priority balances of the CA instructions to be arbitrated, and taking the CA instruction with the largest priority balance as the preferred CA instruction of the CA control unit; Subtract 1 from the priority balance corresponding to the CA instruction with the largest priority balance in the selected priority configuration table; and When the priority balances of each CA instruction in the priority configuration table are all 0, the priority balances of each CA instruction are reset to the initial amount.

10. The instruction scheduling method according to claim 9, further comprising: The initial quota in each priority configuration table is adjusted according to the bandwidth utilization of the DQ bus in the past period of time.

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