Interrupt upper half distributed management method, device, system, equipment and medium

Abstract

The invention provides an interrupt upper half distributed management method, device, system, equipment and medium, and is characterized in that a processor runs a peripheral drive program and interrupts a lower half kernel thread; and the peripheral drive program allocates a direct read-write memory area to the interrupt controller, allocates an interrupt mark to the peripheral device, registers an interrupt lower half processing function, and establishes a mapping relationship between the stored interrupt lower half processing function and the interrupt mark. The interrupt controller receives an interrupt message sent by the external equipment, extracts an interrupt mark, and writes the interrupt mark and a new cache tail pointer position into a cache entry; the interrupt lower half kernel thread determines whether interrupt exists or not according to the cache tail pointer position and the cache head pointer position in the cache entry; and under the condition that the interrupt exists, querying a mapping relationship between the interrupt lower half processing function and the interrupt mark based on the interrupt mark, determining a target interrupt lower half processing function, and performing interrupt processing by utilizing the target interrupt lower half processing function.

Description

Technical Field

[0001] The present disclosure relates to the field of interrupt processing, and discloses an interrupt upper half distributed management method, device, system, equipment, and medium. Background Art

[0002] In order to improve the responsiveness and performance of the system, the interrupt processing process is usually divided into the top half and the bottom half. The top half and the bottom half are two important stages in the interrupt processing process. Through collaboration and division of labor, they jointly achieve efficient processing of interrupt events.

[0003] In the current interrupt handling solution, both the upper and lower halves of the interrupt need to be completed in the processor, which results in the occupation of processor resources and is not conducive to improving the efficiency of interrupt handling. The processing capability for concentrated interrupt bursts is weak. Summary of the invention

[0004] The present disclosure at least provides a method, apparatus, system, device, and medium for distributed management of the upper half of an interrupt to improve interrupt processing efficiency and solve the problem of processor resource occupation.

[0005] According to one aspect of the present disclosure, there is provided a method for distributed management of an interrupt upper half, comprising:

[0006] The processor runs a peripheral driver and an interrupt lower half kernel thread; wherein the peripheral driver is used to allocate a directly readable and writable memory area to the interrupt controller, allocate an interrupt tag to the external device, the interrupt tag is used to uniquely identify the corresponding external device, and register an interrupt lower half processing function, establish a mapping relationship between the interrupt lower half processing function and the interrupt tag, and store the mapping relationship in a relationship table;

[0007] The interrupt controller receives an interrupt message sent by an external device, wherein the interrupt message includes an interrupt flag of the external device; wherein the interrupt controller includes an interrupt upper half processing module and a tail pointer counter; the tail pointer counter is used to store a cache tail pointer position;

[0008] The interrupt controller uses the interrupt upper half processing module to extract the interrupt flag in the interrupt message, determines a new cache tail pointer position according to the cache tail pointer position, and writes the interrupt flag and the new cache tail pointer position into the cache entry of the directly readable and writable memory area;

[0009] The interrupt lower-half kernel thread obtains the cache head pointer position of the directly readable and writable memory area, and obtains a cache entry from the directly readable and writable memory area according to the cache head pointer position; reads the cache tail pointer position in the cache entry, and determines whether there is an interrupt according to the cache head pointer position and the cache tail pointer position; if there is an interrupt, reads the interrupt flag in the cache entry, and queries the relationship table based on the extracted interrupt flag to determine a target interrupt lower-half processing function, and uses the target interrupt lower-half processing function to perform interrupt processing.

[0010] In a possible implementation, after determining a new cache tail pointer position according to the cache tail pointer position, the interrupt upper half processing module is further configured to update the cache tail pointer position to the new cache tail pointer position.

[0011] In a possible implementation, the interrupted lower-half kernel thread stores a cache head pointer position of the directly readable and writable memory area.

[0012] In a possible implementation manner, the interrupt controller stores a mapping table of interrupt flags and directly readable and writable memory areas;

[0013] Before writing the interrupt flag and the new cache tail pointer position into the cache entry of the directly readable and writable memory area, the method further includes:

[0014] The interrupt upper half processing module searches the interrupt flag and the directly readable and writable memory area mapping table in combination with the interrupt flag, and locates the directly readable and writable memory area.

[0015] In a possible implementation manner, determining whether there is an interruption according to the cache head pointer position and the cache tail pointer position includes:

[0016] In the case where the cache head pointer position is not the same as the cache tail pointer position, it is determined that there is an interrupt to be processed.

[0017] In a possible implementation manner, obtaining the cache head pointer position of the directly readable and writable memory area includes:

[0018] The cache head pointer position of the directly readable and writable memory area is obtained from the head pointer counter of the processor.

[0019] According to another aspect of the present disclosure, there is provided an interrupt upper half distributed management device, comprising a processor, an interrupt controller, and a directly readable and writable memory area;

[0020] The processor is used to run a peripheral driver and an interrupt lower half kernel thread; wherein the peripheral driver is used to allocate a directly readable and writable memory area to an interrupt controller, allocate an interrupt tag to an external device, the interrupt tag is used to uniquely identify the corresponding external device, and register an interrupt lower half processing function, establish a mapping relationship between the interrupt lower half processing function and the interrupt tag, and store the mapping relationship in a relationship table;

[0021] The interrupt controller is used to receive an interrupt message sent by an external device, wherein the interrupt message includes an interrupt flag of the external device; wherein the interrupt controller includes an interrupt upper half processing module and a tail pointer counter; the tail pointer counter is used to store a cache tail pointer position; and, using the interrupt upper half processing module to extract the interrupt flag in the interrupt message, determine a new cache tail pointer position according to the cache tail pointer position, and write the interrupt flag and the new cache tail pointer position into the cache entry of the directly readable and writable memory area;

[0022] The interrupt lower half kernel thread in the processor is used to obtain the cache head pointer position of the directly readable and writable memory area, and obtain a cache entry from the directly readable and writable memory area according to the cache head pointer position; read the cache tail pointer position in the cache entry, and determine whether there is an interrupt according to the cache head pointer position and the cache tail pointer position; if there is an interrupt, read the interrupt flag in the cache entry, and query the relationship table based on the extracted interrupt flag to determine the target interrupt lower half processing function, and use the target interrupt lower half processing function to perform interrupt processing.

[0023] According to another aspect of the present disclosure, there is provided an interrupt upper half distributed management system, comprising:

[0024] A processor as described in any one of the above items;

[0025] An interrupt controller as described in any one of the above items;

[0026] Any of the above-mentioned directly readable and writable memory areas;

[0027] The external device is used to send an interrupt message to the interrupt controller.

[0028] According to another aspect of the present disclosure, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory, wherein the processor implements any of the above methods when executing the computer program.

[0029] According to another aspect of the present disclosure, a computer-readable storage medium is provided, wherein a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, any of the above-mentioned methods is implemented.

[0030] In the interrupt upper half distributed management method, device, system, equipment, and medium disclosed in the present invention, the processor runs a peripheral driver and an interrupt lower half kernel thread; wherein the peripheral driver is used to allocate a directly readable and writable memory area to the interrupt controller, allocate an interrupt tag to the external device, the interrupt tag is used to uniquely identify the corresponding external device, and register the interrupt lower half processing function, establish a mapping relationship between the storage interrupt lower half processing function and the interrupt tag, and store the mapping relationship in a relationship table. The interrupt controller receives an interrupt message sent by an external device, wherein the interrupt message includes the interrupt tag of the external device; wherein the interrupt controller includes an interrupt upper half processing module and a tail pointer counter; the tail pointer counter is used to store the cache tail pointer position. The interrupt controller uses the interrupt upper half processing module to extract the interrupt tag in the interrupt message, determines a new cache tail pointer position according to the cache tail pointer position, and writes the interrupt tag and the new cache tail pointer position into the cache entry of the directly readable and writable memory area. The interrupt lower half kernel thread obtains the cache head pointer position of the directly readable and writable memory area, and obtains a cache entry from the directly readable and writable memory area according to the cache head pointer position; reads the cache tail pointer position in the cache entry, and determines whether there is an interrupt according to the cache head pointer position and the cache tail pointer position; if there is an interrupt, reads the interrupt flag in the cache entry, and queries the relationship table based on the extracted interrupt flag to determine the target interrupt lower half processing function, and uses the target interrupt lower half processing function to perform interrupt processing. The technical solution disclosed in the present invention utilizes an interrupt controller to unload the processing operations of the interrupt upper half of the processor, which not only reduces the data processing pressure of the processor, but also improves the interrupt processing efficiency, and can quickly process concentrated interrupts, effectively improving the interrupt processing capability and scenario adaptability.

[0031] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

[0033] Figure 1 is a flow chart of a method for distributing management of the upper half of an interruption according to an embodiment of the present disclosure;

[0034] Figure 2 is a schematic diagram of the structure of the upper half of the distributed management system for interruption according to an embodiment of the present disclosure;

[0035] Figure 3 is a schematic diagram of a cache entry according to an embodiment of the present disclosure;

[0036] Figure 4 is a schematic diagram of the structure of the upper half distributed management device for interruption according to an embodiment of the present disclosure;

[0037] Figure 5 is a schematic structural diagram of an electronic device according to the present disclosure. DETAILED DESCRIPTION

[0038] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0039] The present disclosure provides a method, device, system, equipment and medium for distributed management of the upper half of an interrupt in view of the problems of low interrupt processing efficiency and serious occupation of processor resources in the current interrupt processing scheme. In the present disclosure, the processor runs a peripheral driver and an interrupt lower half kernel thread; wherein the peripheral driver is used to allocate a directly readable and writable memory area to the interrupt controller, allocate an interrupt mark for the external device, the interrupt mark is used to uniquely identify the corresponding external device, and register the lower half of the interrupt processing function, establish a mapping relationship between the lower half of the interrupt processing function and the interrupt mark, and store the mapping relationship in a relationship table. The interrupt controller receives an interrupt message sent by an external device, wherein the interrupt message includes the interrupt mark of the external device; wherein the interrupt controller includes an upper half of the interrupt processing module and a tail pointer counter; the tail pointer counter is used to store the cache tail pointer position. The interrupt controller extracts the interrupt mark in the interrupt message using the upper half of the interrupt processing module, determines a new cache tail pointer position according to the cache tail pointer position, and writes the interrupt mark and the new cache tail pointer position into the cache entry of the directly readable and writable memory area. The interrupt lower half kernel thread obtains the cache head pointer position of the directly readable and writable memory area, and obtains a cache entry from the directly readable and writable memory area according to the cache head pointer position; reads the cache tail pointer position in the cache entry, and determines whether there is an interrupt according to the cache head pointer position and the cache tail pointer position; if there is an interrupt, reads the interrupt flag in the cache entry, and queries the relationship table based on the extracted interrupt flag to determine the target interrupt lower half processing function, and uses the target interrupt lower half processing function to perform interrupt processing. The technical solution disclosed in the present invention utilizes an interrupt controller to unload the processing operations of the interrupt upper half of the processor, which not only reduces the data processing pressure of the processor, but also improves the interrupt processing efficiency, and can quickly process concentrated interrupts, effectively improving the interrupt processing capability and scenario adaptability.

[0040] The technical solution of the present disclosure is described below through specific embodiments.

[0041] like Figure 1 As shown, it is a flowchart of the upper half of the interrupt distributed management method of this embodiment. The execution subject of this embodiment is a computing device or component with data processing capability. The specific method of this embodiment may include the following steps:

[0042] S110, the processor runs a peripheral driver and an interrupt lower-half kernel thread; wherein the peripheral driver is used to allocate a directly readable and writable memory area to the interrupt controller, allocate an interrupt tag to the external device, the interrupt tag is used to uniquely identify the corresponding external device, and register an interrupt lower-half processing function, establish a mapping relationship between the interrupt lower-half processing function and the interrupt tag, and store the mapping relationship in a relationship table.

[0043] The above-mentioned directly readable and writable memory area is Direct Memory Access (DMA). Here, the interrupt controller corresponds to the DMA. After the processor allocation is completed, the interrupt controller can directly perform read and write operations in the DMA.

[0044] The interrupt flag is used by the program running in the processor to distinguish the interrupt source, that is, to distinguish the external device that caused the interrupt.

[0045] After the processor assigns an interrupt flag to the external device, the interrupt flag may be sent to the corresponding external device through the communication component.

[0046] S120, the interrupt controller receives an interrupt message sent by an external device, wherein the interrupt message includes an interrupt flag of the external device; wherein the interrupt controller includes an interrupt upper half processing module and a tail pointer counter; the tail pointer counter is used to store a cache tail pointer position.

[0047] After determining a new cache tail pointer position according to the cache tail pointer position, the interrupt upper half processing module is further used to update the cache tail pointer position to the new cache tail pointer position, that is, to update the value of the tail pointer counter.

[0048] S130, the interrupt controller uses the interrupt upper half processing module to extract the interrupt flag in the interrupt message, determines a new cache tail pointer position according to the cache tail pointer position, and writes the interrupt flag and the new cache tail pointer position into the cache entry of the directly readable and writable memory area.

[0049] In some embodiments, the bottom-half kernel thread is interrupted to store a cache head pointer position of the directly readable and writable memory area.

[0050] In some embodiments, the interrupted bottom-half kernel thread may obtain the cache head pointer position of the directly readable and writable memory area from the head pointer counter of the processor.

[0051] S140, the interrupt lower-half kernel thread obtains the cache head pointer position of the directly readable and writable memory area, and obtains a cache entry from the directly readable and writable memory area according to the cache head pointer position; reads the cache tail pointer position in the cache entry, and determines whether there is an interrupt according to the cache head pointer position and the cache tail pointer position; if there is an interrupt, reads the interrupt flag in the cache entry, and queries the relationship table based on the extracted interrupt flag to determine the target interrupt lower-half processing function, and uses the target interrupt lower-half processing function to perform interrupt processing.

[0052] In some embodiments, the interrupt controller stores a mapping table between interrupt flags and directly readable and writable memory areas. In this case, before writing the interrupt flag and the new cache tail pointer position into the cache entry of the directly readable and writable memory area, the following steps need to be performed:

[0053] The interrupt upper half processing module searches the interrupt flag and the directly readable and writable memory area mapping table in combination with the interrupt flag, and locates the directly readable and writable memory area.

[0054] In some embodiments, judging whether there is an interruption according to the cache head pointer position and the cache tail pointer position can be implemented by the following steps:

[0055] When the cache head pointer position is different from the cache tail pointer position, it is determined that there is an interrupt to be processed; when the cache head pointer position is the same as the cache tail pointer position, it is determined that there is no interrupt to be processed.

[0056] In some embodiments, Figure 2 As shown in the figure, in the upper half of the interrupt distributed management solution, the processor CPU runs the peripheral driver and the bottom half of the interrupt kernel thread. The peripheral driver mainly completes the initialization of the external device and only focuses on interrupt-related work. The specific initialization tasks are as follows:

[0057] 1. Initialize the external device interrupt related configuration and assign an interrupt tag to the external device. The interrupt tag is globally unique and is used by the interrupt processing program to distinguish the interrupt source.

[0058] 2. Allocate a memory area (i.e., the above-mentioned directly readable and writable memory area) that can be DMA (Direct Memory Access) to the interrupt controller, so that the interrupt controller can write the interrupt message into the memory area.

[0059] 3. Register the interrupt lower half processing function, establish a mapping relationship between the interrupt lower half processing function and the interrupt flag, and then use the interrupt lower half kernel thread to call the registered interrupt lower half processing function to perform interrupt processing.

[0060] The external device sends an interrupt message to the interrupt controller, and the interrupt message includes an interrupt flag of the interrupt device.

[0061] The interrupt controller includes an interrupt upper half processing module Top Half, an interrupt flag and a DMA-capable memory area mapping table.

[0062] The interrupt controller is used to complete the following operations:

[0063] 1. After receiving the interrupt message from the external device, the interrupt upper half processing module Top Half queries the interrupt mark and DMA-enabled memory area mapping table through the interrupt mark carried by the external device interrupt message to find the corresponding DMA-enabled memory.

[0064] 2. The interrupt upper half processing module Top Half allocates a memory Buffer for the interrupt flag and Buffertail count (i.e., the new cache tail pointer position) through the DMA write driver.

[0065] 3. After the top half processing module Top Half completes DMA writing to the memory buffer (i.e., writing the interrupt mark and the new cache tail pointer position to the allocated memory buffer), the Buffertail count is updated, that is, updated to the new cache tail pointer position.

[0066] Bottom Half is a task that runs on the operating system and can be scheduled for execution by the kernel task scheduling mechanism. It mainly completes the following operations:

[0067] 1. Record the Bufferhead count (i.e., the cache head pointer position), and read the cache entry Entry in the DMA-capable memory area according to the recorded Bufferhead count.

[0068] 2. Compare the Buffer head count and Buffer tail count recorded by itself to determine whether there is an interruption. If there is an interruption, obtain the interruption mark from the Entry.

[0069] 3. Query the relationship table between the interrupt flag and the lower half interrupt processing function, find the corresponding lower half interrupt processing function, and use the queried lower half interrupt processing function to perform interrupt processing.

[0070] like Figure 3As shown, the composition of the cache entry Entry includes the interrupt flag of the external device, the Buffertail count in the interrupt controller (ie, the cache tail pointer position), and other messages; other messages can be customized according to specific application scenarios and are not limited in this disclosure.

[0071] Based on the same inventive concept, the present disclosure provides an interrupt upper half distributed management device, the steps performed by the components of the device are the same or similar to the above method, so similar parts are not repeated. Figure 4 As shown, the upper half interrupt distributed management device of this embodiment includes a processor 410 , an interrupt controller 420 , and a directly readable and writable memory area 430 .

[0072] The processor 410 is used to run the peripheral driver and the interrupt lower half kernel thread; wherein the peripheral driver is used to allocate a directly readable and writable memory area to the interrupt controller, allocate an interrupt tag to the external device, the interrupt tag is used to uniquely identify the corresponding external device, and register the interrupt lower half processing function, establish a mapping relationship between the interrupt lower half processing function and the interrupt tag, and store the mapping relationship in a relationship table.

[0073] The interrupt controller 420 is used to receive an interrupt message sent by an external device, wherein the interrupt message includes an interrupt flag of the external device; wherein the interrupt controller includes an interrupt upper half processing module and a tail pointer counter; the tail pointer counter is used to store a cache tail pointer position; and, using the interrupt upper half processing module to extract the interrupt flag in the interrupt message, determine a new cache tail pointer position according to the cache tail pointer position, and write the interrupt flag and the new cache tail pointer position into the cache entry of the directly readable and writable memory area.

[0074] The interrupt lower half kernel thread in the processor 410 is used to obtain the cache head pointer position of the directly readable and writable memory area, and obtain a cache entry from the directly readable and writable memory area according to the cache head pointer position; read the cache tail pointer position in the cache entry, and determine whether there is an interrupt according to the cache head pointer position and the cache tail pointer position; if there is an interrupt, read the interrupt flag in the cache entry, and query the relationship table based on the extracted interrupt flag to determine the target interrupt lower half processing function, and use the target interrupt lower half processing function to perform interrupt processing.

[0075] Based on the same inventive concept, the present disclosure provides an interrupt upper half distributed management system, the steps performed by the components of the system are the same or similar to the above method, so similar parts are not repeated. Specifically, the interrupt upper half distributed management system includes:

[0076] A processor of any of the above embodiments; an interrupt controller of any of the above embodiments; a directly readable and writable memory area of ​​any of the above embodiments; and an external device for sending an interrupt message to the interrupt controller.

[0077] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device and a computer-readable storage medium.

[0078] Figure 5 A schematic block diagram of an example electronic device 500 that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0079] like Figure 5 As shown, the device 500 includes a computing unit 510, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 520 or a computer program loaded from a storage unit 580 into a random access memory (RAM) 530. In the RAM 530, various programs and data required for the operation of the device 500 can also be stored. The computing unit 510, the ROM 520, and the RAM 530 are connected to each other via a bus 540. An input / output (I / O) interface 550 is also connected to the bus 540.

[0080] A number of components in the device 500 are connected to the I / O interface 550, including: an input unit 560, such as a keyboard, a mouse, etc.; an output unit 570, such as various types of displays, speakers, etc.; a storage unit 580, such as a disk, an optical disk, etc.; and a communication unit 590, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 590 allows the device 500 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0081] The computing unit 510 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 510 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 510 performs the various methods and processes described above. For example, in some embodiments, any of the above methods may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 580. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 500 via ROM520 and / or communication unit 590. When the computer program is loaded into RAM530 and executed by the computing unit 510, one or more steps of any of the methods described above may be performed. Alternatively, in other embodiments, the computing unit 510 may be configured to perform any of the methods described above in any other appropriate manner (e.g., by means of firmware).

[0082] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0083] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0084] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0085] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0086] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0087] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0088] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0089] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A method for distributing the upper half of an interrupt, characterized in that: include: The processor runs a peripheral driver and an interrupt lower half kernel thread; wherein the peripheral driver is used to allocate a directly readable and writable memory area to the interrupt controller, allocate an interrupt tag to the external device, the interrupt tag is used to uniquely identify the corresponding external device, and register an interrupt lower half processing function, establish a mapping relationship between the interrupt lower half processing function and the interrupt tag, and store the mapping relationship in a relationship table; The interrupt controller receives an interrupt message sent by an external device, wherein the interrupt message includes an interrupt flag of the external device; wherein the interrupt controller includes an interrupt upper half processing module and a tail pointer counter; the tail pointer counter is used to store a cache tail pointer position; The interrupt controller uses the interrupt upper half processing module to extract the interrupt flag in the interrupt message, determines a new cache tail pointer position according to the cache tail pointer position, and writes the interrupt flag and the new cache tail pointer position into the cache entry of the directly readable and writable memory area; The interrupt lower-half kernel thread obtains the cache head pointer position of the directly readable and writable memory area, and obtains a cache entry from the directly readable and writable memory area according to the cache head pointer position; reads the cache tail pointer position in the cache entry, and determines whether there is an interrupt according to the cache head pointer position and the cache tail pointer position; if there is an interrupt, reads the interrupt flag in the cache entry, and queries the relationship table based on the extracted interrupt flag to determine a target interrupt lower-half processing function, and uses the target interrupt lower-half processing function to perform interrupt processing.

2. The method according to claim 1, characterized in that After determining the new cache tail pointer position according to the cache tail pointer position, the interrupt upper half processing module is further used to update the cache tail pointer position to the new cache tail pointer position.

3. The method according to claim 1, characterized in that The interrupt lower-half kernel thread stores the cache head pointer position of the directly readable and writable memory area.

4. The method according to claim 1, characterized in that: The interrupt controller stores an interrupt flag and a mapping table of directly readable and writable memory areas; Before writing the interrupt flag and the new cache tail pointer position into the cache entry of the directly readable and writable memory area, the method further includes: The interrupt upper half processing module searches the interrupt flag and the directly readable and writable memory area mapping table in combination with the interrupt flag, and locates the directly readable and writable memory area.

5. The method according to claim 1, characterized in that The determining whether there is an interruption according to the cache head pointer position and the cache tail pointer position includes: In the case where the cache head pointer position is not the same as the cache tail pointer position, it is determined that there is an interrupt to be processed.

6. The method according to claim 1, characterized in that The obtaining of the cache head pointer position of the directly readable and writable memory area comprises: The cache head pointer position of the directly readable and writable memory area is obtained from the head pointer counter of the processor.

7. An interrupt upper half distributed management device, characterized in that: Includes processor, interrupt controller, and directly readable and writable memory area; The processor is used to run a peripheral driver and an interrupt lower half kernel thread; wherein the peripheral driver is used to allocate a directly readable and writable memory area to an interrupt controller, allocate an interrupt tag to an external device, the interrupt tag is used to uniquely identify the corresponding external device, and register an interrupt lower half processing function, establish a mapping relationship between the interrupt lower half processing function and the interrupt tag, and store the mapping relationship in a relationship table; The interrupt controller is used to receive an interrupt message sent by an external device, wherein the interrupt message includes an interrupt flag of the external device; wherein the interrupt controller includes an interrupt upper half processing module and a tail pointer counter; the tail pointer counter is used to store a cache tail pointer position; and, using the interrupt upper half processing module to extract the interrupt flag in the interrupt message, determine a new cache tail pointer position according to the cache tail pointer position, and write the interrupt flag and the new cache tail pointer position into the cache entry of the directly readable and writable memory area; The interrupt lower-half kernel thread in the processor is used to obtain the cache head pointer position of the directly readable and writable memory area, and obtain a cache entry from the directly readable and writable memory area according to the cache head pointer position; read the cache tail pointer position in the cache entry, and determine whether there is an interrupt according to the cache head pointer position and the cache tail pointer position; if there is an interrupt, read the interrupt flag in the cache entry, and query the relationship table based on the extracted interrupt flag to determine the target interrupt lower-half processing function, and use the target interrupt lower-half processing function to perform interrupt processing.

8. An interrupt upper half distributed management system, characterized in that: include: The processor according to any one of claims 1 to 6; The interrupt controller according to any one of claims 1 to 6; The directly readable and writable memory area as claimed in any one of claims 1 to 6; The external device is used to send an interrupt message to the interrupt controller.

9. An electronic device comprising a memory, a processor and a computer program stored in the memory, wherein the processor implements the method according to any one of claims 1 to 6 when executing the computer program.

10. A computer-readable storage medium, wherein a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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