Cache architecture optimization method and device of multi-chip integration system and storage medium

Abstract

The invention relates to a cache architecture optimization method and device for a multi-chip integration system and a storage medium, and the method comprises the steps: obtaining an architecture topological graph of the multi-chip integration system; the architecture topological graph comprises a storage hierarchy graph and a network topological graph; the storage hierarchy graph is a hierarchy connection graph of a cache subsystem of the multi-chip integration system; the network topological graph is a core particle connection graph of the multi-core particle integrated system; constructing a system performance model based on the architecture topological graph; and solving the system performance model to obtain a target cache parameter, and generating a target cache architecture graph based on the target cache parameter and the storage hierarchy graph. According to the method and the device, the problem that the architecture of the cache subsystem in the multi-chip particle integrated system is difficult to achieve optimal optimization is solved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a cache architecture optimization method, device and storage medium for a multi-chip integrated system. Background Art

[0002] Multi-chip integration technology is a technology that integrates multiple chips with specific functions through semiconductor technology to create high-performance, multi-functional chip integration technology. This technology breaks the area limitation of single-chip manufacturing and achieves higher integration and computing power. Multi-chip integrated system (chiplet) refers to the manufacturer dividing different functional modules (such as processor core, cache, memory controller, I / O interface, etc.) into multiple smaller chips according to system performance requirements on a single chip, and combining them through advanced packaging technology.

[0003] In a multi-chip integrated system, a multi-level cache structure can be used to optimize the performance of the cache subsystem. In the related art, there are two main types of architectural designs for cache subsystems based on multi-chips. One type is similar to chips designed by chip manufacturers such as Inter and AMD, which are designed to support a wide range of computing tasks and applications, from simple office software to complex scientific calculations and games. This architectural design is not optimized for any specific application, but provides a balanced performance to meet the needs of most users. Therefore, for specific or non-general applications, the designed architecture may not achieve optimal performance. The other type is the cache subsystem architectural parameters obtained through design space exploration, but the existing design space exploration has the following problems: there are fewer cache parameters that are not targeted at multi-chip integrated systems or based on multi-chip integrated systems, and the types of chips are limited.

[0004] Currently, no effective solution has been proposed for the problem that the architecture of the cache subsystem in the multi-chip integrated system in the related technology is difficult to achieve optimal optimization. Summary of the invention

[0005] The embodiments of the present application provide a cache architecture optimization method, device and storage medium for a multi-chip integrated system, so as to at least solve the problem in the related art that it is difficult to achieve optimal optimization for the architecture of the cache subsystem in the multi-chip integrated system.

[0006] In a first aspect, an embodiment of the present application provides a cache architecture optimization method for a multi-chip integrated system, the method comprising:

[0007] Acquire an architecture topology diagram of the multi-chip integrated system; the architecture topology diagram includes a storage hierarchy diagram and a network topology diagram; the storage hierarchy diagram is a hierarchical connection diagram of a cache subsystem of the multi-chip integrated system; the network topology diagram is a chip connection diagram of the multi-chip integrated system;

[0008] Based on the architecture topology diagram, construct a system performance model;

[0009] The system performance model is solved to obtain target cache parameters, and a target cache architecture diagram is generated based on the target cache parameters and the storage hierarchy diagram.

[0010] In some embodiments, constructing a system performance model based on the architecture topology diagram includes:

[0011] Based on the storage hierarchy diagram in the architecture topology diagram, model the miss rate of the cache subsystem to generate a miss rate model, and based on the network topology diagram in the architecture topology diagram, model the network delay time of the multi-chip integrated system to generate a delay model;

[0012] The system performance model is constructed according to the miss rate model and the delay model.

[0013] In some embodiments, modeling the miss rate of the cache subsystem based on the storage hierarchy diagram in the architecture topology diagram to generate a miss rate model includes:

[0014] Based on the storage hierarchy diagram, determine a cache hierarchy node set of the cache subsystem; the cache hierarchy node set is a set of upper-layer cache nodes of the current node included in the cache hierarchy structure in the cache subsystem;

[0015] Based on the cache level node set, the miss rate of the cache subsystem is modeled to generate the miss rate model.

[0016] In some embodiments, modeling the network delay time of the multi-chip integrated system based on the network topology diagram in the architecture topology diagram to generate a delay model includes:

[0017] Based on the network topology diagram, determining the node position relationship between the starting node and the destination node in the multi-core integrated system;

[0018] In a case where the node position relationship indicates that the start node and the destination node are located in the same chiplet, generating a first delay model according to the chiplet intra-chip delay in the multi-chiplet integrated system;

[0019] In a case where the node position relationship indicates that the start node and the destination node are located in different chiplets, generating a second delay model according to chiplet intra-chip delay and chiplet inter-chip delay in the multi-chiplet integrated system;

[0020] The delay model includes the first delay model and the second delay model.

[0021] In some embodiments, the different core-grains include a first core-grain and a second core-grain, the first core-grain is the core-grain where the start node is located, and the second core-grain is the core-grain where the destination node is located; generating a second delay model according to the intra-chip delay of the core-grain and the inter-chip delay of the core-grain in the multi-core integrated system includes:

[0022] Determining a first interface node in the first core-grain and a second interface node in the second core-grain;

[0023] Based on the network topology graph, a first path, a second path and a third path are calculated; the first path is a path between the starting node in the first core particle and the first interface node, the second path is a path between the destination node in the second core particle and the second interface node, and the third path is a path between the first interface node and the second interface node;

[0024] The chip intra-chip delay is obtained based on the first path and the second path, the chip inter-chip delay is obtained based on the third path, and a second delay model is generated according to the chip intra-chip delay and the chip inter-chip delay.

[0025] In some embodiments, constructing the system performance model according to the miss rate model and the delay model includes:

[0026] According to the miss rate model and the delay model, the cache miss rate and cache delay time of each cache level in the cache subsystem are obtained, and according to the cache delay time, the average delay time between adjacent cache levels in the core particle is calculated;

[0027] The system performance model is constructed according to the cache miss rate and the average delay time.

[0028] In some embodiments, solving the system performance model to obtain target cache parameters includes:

[0029] Acquire a preset architectural area of ​​the cache subsystem, and determine an area constraint condition that the architectural area of ​​the cache subsystem is smaller than the preset architectural area;

[0030] Acquire a preset architecture power consumption of the cache subsystem, and determine a power consumption constraint condition that the architecture power consumption of the cache subsystem is less than the preset architecture power consumption;

[0031] Based on the area constraint condition and the power consumption constraint condition, the system performance model is solved to obtain the target cache parameter.

[0032] In some embodiments, solving the system performance model to obtain target cache parameters includes:

[0033] Based on the system performance model, construct a root node according to the architecture topology diagram;

[0034] Starting from the root node, determining the branch value range of each layer of sub-nodes layer by layer based on the architecture topology diagram, and constructing a search tree layer by layer according to the branch value range; the search tree includes the root node and each layer of sub-nodes;

[0035] The tree nodes are traversed in the search tree, and the target cache parameters are obtained by solving.

[0036] In a second aspect, an embodiment of the present application provides a cache architecture optimization device for a multi-chip integrated system, including:

[0037] An acquisition module is used to acquire an architecture topology diagram of the multi-chip integrated system; the architecture topology diagram includes a storage hierarchy diagram and a network topology diagram; the storage hierarchy diagram is a hierarchical connection diagram of a cache subsystem of the multi-chip integrated system; the network topology diagram is a chip connection diagram of the multi-chip integrated system;

[0038] A model building module, used to build a system performance model based on the architecture topology diagram;

[0039] A generation module is used to solve the system performance model to obtain target cache parameters, and generate a target cache architecture diagram based on the target cache parameters and the storage hierarchy diagram.

[0040] In a third aspect, an embodiment of the present application provides a storage medium having a computer program stored thereon, which, when executed by a processor, implements the cache architecture optimization method of the multi-chip integrated system as described in the first aspect above.

[0041] Compared with the related art, the cache architecture optimization method, device and storage medium of the multi-chip integrated system provided in the embodiments of the present application obtain the architecture topology diagram of the multi-chip integrated system; the architecture topology diagram includes a storage hierarchy diagram and a network topology diagram; the storage hierarchy diagram is a hierarchical connection diagram of the cache subsystem of the multi-chip integrated system; the network topology diagram is a chip connection diagram of the multi-chip integrated system; based on the architecture topology diagram, a system performance model is constructed; the system performance model is solved to obtain target cache parameters, and based on the target cache parameters and the storage hierarchy diagram, a target cache architecture diagram is generated.

[0042] Based on this, by designing a configurable cache hierarchy (such as resizable first-level cache and second-level cache), cache resource allocation can be dynamically adjusted according to the needs of the application to improve system performance. This makes it possible to model the cache subsystem based on the multi-chip integrated system and design corresponding cache subsystem architectures for different types of applications, solving the problem that the architecture of the cache subsystem in the multi-chip integrated system is difficult to achieve optimal optimization. At the same time, the cache subsystem based on the multi-chip integrated system has more relevant parameters, which can meet the current needs for exploring the design space of the cache subsystem.

[0043] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0045] Figure 1 It is a hardware structure block diagram of a terminal of a cache architecture optimization method of a multi-chip integrated system according to an embodiment of the present application;

[0046] Figure 2 is a flow chart of a cache architecture optimization method for a multi-chip integrated system according to an embodiment of the present application;

[0047] Figure 3 is a schematic diagram of a storage hierarchy diagram according to an embodiment of the present application;

[0048] Figure 4 is a schematic diagram of a network topology diagram according to an embodiment of the present application;

[0049] Figure 5 is a flow chart of another cache architecture optimization method for a multi-chip integrated system according to an embodiment of the present application;

[0050] Figure 6 It is a structural block diagram of a cache architecture optimization device for a multi-chip integrated system according to an embodiment of the present application. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. Based on the embodiments provided in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application. In addition, it can also be understood that although the efforts made in this development process may be complex and lengthy, for ordinary technicians in the field related to the contents disclosed in the present application, some changes such as design, manufacturing or production based on the technical contents disclosed in the present application are only conventional technical means, and should not be understood as insufficient contents disclosed in the present application.

[0052] Reference to "embodiments" in this application means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those of ordinary skill in the art that the embodiments described in this application may be combined with other embodiments without conflict.

[0053] Unless otherwise defined, the technical terms or scientific terms involved in this application should be understood by people with ordinary skills in the technical field to which this application belongs. The words "one", "a", "a", "the" and the like involved in this application do not indicate a quantitative limitation, and may represent the singular or plural. The terms "include", "comprise", "have" and any of their variations involved in this application are intended to cover non-exclusive inclusions; for example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units that are not listed, or may also include other steps or units inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application refers to greater than or equal to two. "And / or" describes the association relationship of associated objects, indicating that there can be three relationships, for example, "A and / or B" can represent: A exists alone, A and B exist at the same time, and B exists alone. The terms "first", "second", "third" and the like involved in the present application are merely used to distinguish similar objects and do not represent a specific ordering of the objects.

[0054] The method embodiment provided in this embodiment can be executed in a terminal, a computer or a similar computing device. Taking running on a terminal as an example, Figure 1 1 is a hardware structure block diagram of a terminal of a cache architecture optimization method for a multi-chip integrated system according to an embodiment of the present application. Figure 1 As shown, the terminal may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data. Optionally, the terminal may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above terminal. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown.

[0055] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the cache architecture optimization method of the multi-core integrated system in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0056] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (Radio Frequency, referred to as RF) module, which is used to communicate with the Internet wirelessly.

[0057] This embodiment provides a cache architecture optimization method for a multi-chip integrated system. Figure 2 is a flow chart of a cache architecture optimization method for a multi-chip integrated system according to an embodiment of the present application. Figure 2 As shown, the process includes the following steps:

[0058] Step S210, obtaining an architecture topology diagram of the multi-chip integrated system; the architecture topology diagram includes a storage hierarchy diagram and a network topology diagram; the storage hierarchy diagram is a hierarchical connection diagram of a cache subsystem of the multi-chip integrated system; and the network topology diagram is a chip connection diagram of the multi-chip integrated system.

[0059] Specifically, the above storage hierarchy graph G1(V,E) is an undirected graph, which refers to the storage hierarchy graph of the cache subsystem of the multi-core integrated system. ijk ∈V can represent a CPU core, a cache unit, or a memory unit. Its subscript i represents the number of the node in the core particle, and j represents the cache level where the node is located; when j = 0, it means that the current node is a CPU core, and when 0 <j<h k When j=h k When , it means that the current node is a memory unit; k represents the number of the node in the core particle. ijk,mno (v ijk ,v mno )∈E represents v ijk and v mno The connectivity between (e.g., between the core and cache, between two levels of cache units, or between cache and memory). If v ijk and v mno If it is reachable between ijk,mno (v ijk ,v mno )=1, otherwise it is 0.

[0060] For example, see Figure 3 The multi-chiplet integrated system shown in the figure includes chiplet 1 (Chiplet1), chiplet 2 (Chiplet2) and chiplet 3 (Chiplet3); wherein chiplet 1 and chiplet 2 respectively include CPU, L1 cache (L1 cache), L2 cache (L2 cache) and L3 cache (L3 cache), and chiplet 3 includes L1 cache. Each level includes cache nodes, such as V 101 It represents the first node in the core particle, located in the 0th level cache (i.e., CPU core), and the core particle is core particle 1. According to the connection relationship between the cache levels in each core particle, the storage hierarchy diagram of the cache subsystem in the multi-core integrated system is determined.

[0061] On the other hand, the network topology graph G2(N,C) is an undirected graph, which refers to the connection relationship between core particles and the connection relationship within core particles in the multi-core integrated system. pq ∈N is a node of the system, which consists of core, cache and router. Its subscript p represents the number of the node in the core particle, and q represents the number of the core particle. p,q,r,s (np,q ,n r,s )∈C represents the adjacent node n p,q and n r,s Connectivity between r,s In a multi-chip integrated system, pq adjacent nodes; similarly, its subscript r represents the number of the node in the core particle, and s represents the number of the core particle. p,q and n r,s If there is a connection between p,q,r,s (n p,q ,n r,s )=1, otherwise it is 0.

[0062] For example, see Figure 4 In the multi-core integrated system shown in the figure, core 1, core 2 and core 3 respectively include system nodes, such as n 11 、n 21 etc. represent the first node and the second node in core particle 1. According to the connection relationship between each core particle and within the core particle, the network topology diagram of the multi-core particle integration system is determined.

[0063] Step S220: construct a system performance model based on the architecture topology diagram.

[0064] Specifically, according to the application requirements of the multi-chip integrated system, the performance indicators that need to be evaluated are determined, such as throughput, response time, power consumption, etc. And based on the storage hierarchy diagram and network topology diagram in the above architecture topology diagram, a data model of system performance is established; this model can reflect the interaction and influence between the various components of the cache subsystem in the multi-chip integrated system, as well as the relationship between performance indicators and cache parameters.

[0065] It should also be noted that in this step, necessary constraints such as cache size, bandwidth limitation, power consumption budget, etc. may be introduced according to the actual situation of the multi-chip integrated system.

[0066] Step S230, solving the system performance model to obtain target cache parameters, and generating a target cache architecture diagram based on the target cache parameters and the storage hierarchy diagram.

[0067] Among them, according to the complexity of the system performance model and the solution requirements, a suitable solution method is selected, such as branch and bound method, dynamic programming, simulated annealing algorithm, etc. The system performance model is solved using the selected solution method to find a cache parameter combination that meets the constraints and has the best performance indicators.

[0068] Optionally, in the above process, the obtained target cache parameters are also verified to ensure that they can meet the performance and constraint requirements of the system in actual applications.

[0069] Optionally, the system performance model can be a performance model that is an average instruction per clock (IPC) model. According to the IPC model, the IPC parameters of the multi-chip integrated system can be calculated, that is, the number of instructions that the multi-chip integrated system can execute in each clock cycle. The IPC parameters can be used to evaluate the performance of the multi-chip integrated system.

[0070] Next, based on the target cache parameters obtained, update the cache hierarchy and parameter settings in the storage hierarchy diagram, and use graphical tools or professional software to draw the target cache architecture diagram based on the updated storage hierarchy diagram, and finally obtain the optimal architecture parameters of the cache subsystem of the multi-chip integrated system. Through the above steps, the target cache architecture diagram is optimized to ensure that it has good performance and scalability in practical applications, and the architecture optimization of the cache subsystem in the multi-chip integrated system is achieved. In addition, the above modeling does not restrict the structure within the chip, and multiple chip types can be arbitrarily combined, and the structure inside each chip is also different.

[0071] The cache architecture optimization method of a multi-chip integrated system provided in an embodiment of the present application models the storage hierarchy of the cache subsystem of the multi-chip integrated system and the network topology of the multi-chip integrated system, and builds a performance model based on the acquired storage hierarchy diagram and network topology diagram to solve the cache parameters; by designing a configurable cache hierarchy (such as a first-level cache and a second-level cache with adjustable size), the cache resource allocation can be dynamically adjusted according to the needs of the application to improve the system performance, so that the corresponding cache subsystem architecture can be designed for different types of applications based on the cache subsystem modeling of the multi-chip integrated system, which solves the problem that the architecture of the cache subsystem in the multi-chip integrated system is difficult to achieve optimal optimization; at the same time, the cache subsystem based on the multi-chip integrated system has many related parameters, which can meet the current needs for exploring the design space of the cache subsystem.

[0072] In some of the embodiments, a cache architecture optimization method for a multi-chip integrated system is also provided. Figure 5 FIG. 1 is a flow chart of another cache architecture optimization method for a multi-chip integrated system according to an embodiment of the present application. Figure 5 As shown, the process includes Figure 2 The steps S210 and S230 shown in the figure further include the following steps:

[0073] Step S510, based on the storage hierarchy diagram in the architecture topology diagram, the miss rate of the cache subsystem is modeled to generate a miss rate model, and based on the network topology diagram in the architecture topology diagram, the network delay time of the multi-chip integrated system is modeled to generate a delay model.

[0074] Specifically, relevant parameters of the cache subsystem are extracted from the storage hierarchy diagram, such as cache size, cache hierarchy, cache strategy, etc. According to system characteristics and requirements, a suitable miss rate model is selected, such as a model based on access frequency, a model based on working set, etc. The extracted parameters are input into the miss rate model, and the initial conditions and boundary conditions of the model are set to generate a miss rate model of the cache subsystem.

[0075] In addition, relevant network parameters are extracted from the network topology diagram, such as network bandwidth, delay, topology structure, etc. According to network characteristics and requirements, a suitable delay model is selected, such as a queue-based model, a flow-based model, etc. The extracted parameters are input into the delay model, and the initial conditions and boundary conditions of the model are set to generate a network delay time model for the multi-chip integrated system.

[0076] Step S520: construct a system performance model according to the miss rate model and the delay model.

[0077] In this step, the miss rate model and the delay model are integrated together to form a complete system performance model.

[0078] Through the above steps S510 to S520, an accurate and efficient system performance model can be constructed to provide strong support for performance evaluation and optimization of the actual system.

[0079] In some embodiments, the above-mentioned modeling of the miss rate of the cache subsystem based on the storage hierarchy diagram in the architecture topology diagram to generate the miss rate model may also include the following steps:

[0080] Based on the storage hierarchy diagram, determine the cache hierarchy node set of the cache subsystem; the cache hierarchy node set is the set of upper-level cache nodes of the current node contained in the cache hierarchy structure in the cache subsystem; based on the cache hierarchy node set, model the miss rate of the cache subsystem to generate a miss rate model.

[0081] In this step, the memory hierarchy graph G1(V,E) can be used to model the miss rate of the cache subsystem of the multi-chip integrated system. The cache parameters involved in the modeling include parameters related to the cache miss rate of each level in the cache subsystem, such as cache size, cache line size, cache associativity, etc.

[0082] Specifically, according to the given storage hierarchy graph G1(V,E), node v ijk (0 <j≤h ε The missing rate of M(v ijk ).definition Is the cache hierarchy containing v ijkThe set of upper cache nodes (i.e., the cache level node set mentioned above). Then, based on the cache level node set, the miss rate modeling formula is expanded into a multi-parameter, polynomial form, with no restriction on the end, and the cache correlation coefficient and polynomial order are both defined specifically for the core particles, thereby establishing a miss rate model. For example, v ijk The cache miss rate of is modeled as:

[0083]

[0084] In the above formula, M(v ijk ) represents the cache miss rate (i.e., the miss rate), a, b, c, a i 、b i and c i are the cache correlation coefficients for modeling the miss rate in corek, α, β, γ, α i , β i and γ i is the polynomial order for modeling the missing rate in core particle k, cs(v ijk ) is the cache size, cl(v ijk ) is the cache line size, as(v ijk ) is the cache associativity; n α is the total number of core particles.

[0085] In the prior art, the missing rate modeling usually directly targets the attributes of a single node and its upper-level nodes, without emphasizing the interaction or global impact between parameters. Parameter collection and organization rely on explicit traversal of node paths, which is a complicated process. In addition, the fitting order limit during modeling results in a relatively fixed number and complexity of parameters.

[0086] In comparison, the present application, through the above-mentioned embodiments, directly uses the defined cache parameters for modeling, and at the same time, through the collection of upper-level cache nodes to which the expression node belongs, uniformly considers the cumulative effect of cache node attributes at all levels and upper-level node parameters, thereby combining with the above-defined storage hierarchy diagram and its nodes to express the hierarchical relationship of the overall multi-chip integrated system, making the modeling clearer and more concise; and, the embodiments of the present application expand the miss rate modeling formula into a multi-parameter, polynomial form without limiting the order, and the cache correlation coefficient and polynomial order in the modeling formula are specifically defined for the chip, thereby also improving the flexibility of miss rate modeling.

[0087] In some embodiments, the network delay time of the multi-chip integrated system is modeled based on the network topology diagram in the architecture topology diagram to generate a delay model, which may also include the following steps:

[0088] Step S511, based on the network topology diagram, determining the node position relationship between the start node and the destination node in the multi-chip integrated system.

[0089] In this embodiment, the network topology diagram can be used to model the network delay time of the multi-chip integrated system, and D(n p,q ,n r,s ) is defined as node n p,q To node n r,s The transmission delay of y (n p,q ,n r,s )={n p,q ,n x,y ,…,n r,s} is defined as slave node n p,q to n r,s The set of all nodes in the path, where n p,q is Γ1,n r,s is Γ n ,The path length is l. Through the path set, all nodes in the path are described uniformly, making the modeling more systematic.

[0090] When considering the delay between two nodes, it is necessary to discuss whether they are located on the same core particle. Specifically, when calculating the delay, traverse each node on the core particle in the multi-core integrated system as the starting node to calculate the delay between the starting node and other nodes, and determine whether the starting node and other nodes as the destination node are on the same core particle, so that different delay models can be used in the subsequent steps.

[0091] Step S512, when the node position relationship indicates that the start node and the destination node are located in the same chiplet, the chiplet intra-chip delay in the multi-chiplet integrated system is obtained according to the network topology diagram, and a first delay model is generated based on the chiplet intra-chip delay.

[0092] Among them, if the two nodes n involved in calculating the delay p,q and n r,s (Node n can be p,q as the starting node, and node n r,s As the destination node) on the same small chip, so that q = s, the delay is only the delay within the chiplet of the multi-chip integrated system, and the delay model is modeled as follows:

[0093]

[0094] In the above formula, c p,q,r,q Used to represent node n p,q and n r,s For any p, there is a path that makes p greater than or equal to 1 and less than or equal to |R q| holds; for any q, there is a condition that makes it greater than or equal to 1 and less than or equal to m; for any r, there is a condition that makes r greater than or equal to 1 and less than or equal to |R q |+d q Established. Among them, |R q | is the number of cores in the qth coreparticle, m is the number of coreparticles, and dq is the number of D2D communication interfaces in the coreparticle.

[0095] Step S513, when the node position relationship indicates that the starting node and the destination node are located in different chiplets, the chiplet intra-chip delay and the chiplet inter-chip delay in the multi-chiplet integrated system are obtained according to the network topology diagram, and a second delay model is generated based on the chiplet intra-chip delay and the chiplet inter-chip delay; wherein the delay model includes a first delay model and a second delay model.

[0096] If node n p,q and n r,s On different cores, if q≠s, the delay is the sum of the intra-core delay and inter-core delay of the multi-core integrated system. The corresponding delay model is determined by judging whether the adjacent nodes are on the same core, thereby more accurately describing the communication delay characteristics of the multi-core integrated system.

[0097] Optionally, in some embodiments, the different core particles include a first core particle and a second core particle; in other words, it can be determined that the two nodes currently involved in calculating the delay, the start node and the destination node, are located on the first core particle and the second core particle, respectively; wherein the first core particle is the core particle where the start node is located, and the second core particle is the core particle where the destination node is located. The second delay model is generated based on the intra-core delay and inter-core delay in the multi-core integrated system, and can also include the following steps:

[0098] Determine a first interface node in a first core particle and a second interface node in a second core particle; calculate a first path, a second path and a third path based on a network topology diagram; the first path is a path between a starting node in the first core particle and a first interface node, the second path is a path between a destination node in the second core particle and a second interface node, and the third path is a path between the first interface node and the second interface node; obtain a core particle intra-chip delay based on the first path and the second path, obtain a core particle inter-chip delay based on the third path, and generate a second delay model based on the core particle intra-chip delay and the core particle inter-chip delay.

[0099] Wherein, when it is detected that the current adjacent node is located in different core particles based on the node position relationship determined above, the different core particles are distinguished into a first core particle and a second core particle. p' is defined as a D2D (Die-to-Die) interface node on the first core particle (i.e., the first interface node mentioned above), and r' is defined as a D2D interface node located on the second core particle (i.e., the second interface node mentioned above). For example, refer to Figure 3 or Figure 4 , each chiplet is provided with one or more D2D interfaces, which are used for data communication between different chiplets. The number of D2D interfaces of each chiplet should not exceed four, that is, the number of D2D interfaces is di,i = {1, ..., 4}; for the jth chiplet, the index of the D2D interface can be defined as: n |Rj|+1，j , ..., n |Rj|+di，j ; |Rj| represents the number of cores of core particle j. Then the first interface node and the second interface node are nodes located on the first core particle and the second core particle respectively, and communicate with the node on the other core particle through the D2D interface. Among them, the first interface node p` satisfies p`∈Γ y (n p,q ,n r,s ), the second interface node r` satisfies r`∈Γ y (n p,q ,n r,s ).

[0100] For example, one of the delay models established based on the first path, the second path, and the third path is shown in the following formula:

[0101]

[0102] In the above formula, |R s | is the number of cores in the sth core. The first term is the path between each node in the first core and the first interface node (i.e., the first path), the second term is the path between the first interface node and the second interface node (i.e., the third path), and the third term is the path between each node in the second core and the second interface node (i.e., the second path). It can be seen that the sum of the first term and the third term is the calculation formula for the delay within the core, and the second term is the calculation formula for the delay between cores. By adding the delay within the core and the delay between cores, a delay model can be established when adjacent nodes are located in different cores.

[0103] Through the above embodiments, intra-chip delay and inter-chip delay are distinguished, and relevant delay models are defined respectively, and the delay composition of intra-chip path and cross-chip path is described in detail; at the same time, p` and r` are innovatively introduced to represent inter-chip D2D interface nodes, and the delay accumulation of intra-chip path and cross-chip path is calculated respectively, so as to more accurately describe the delay characteristics of inter-chip communication.

[0104] In some embodiments, the system performance model is constructed according to the miss rate model and the delay model, and the following steps may also be included:

[0105] According to the miss rate model and the delay model, the cache miss rate and cache delay time of each level of cache in the cache subsystem are obtained, and according to the cache delay time, the average delay time between adjacent cache levels in the core particle is calculated; according to the cache miss rate and the average delay time, the system performance model is constructed.

[0106] Specifically, y(j) is defined as a switch quantity, which is used to determine the coefficient relationship in the system performance modeling formula, and the detailed description is as follows:

[0107]

[0108] Assuming that there are at most three cache levels in the cache subsystem, the above system performance model formula is defined as follows:

[0109]

[0110] In the above formula, CPI(v i0k ) is the number of cycles per instruction (CPI) under ideal conditions assuming no cache misses, H(v ijk ) is the hit time of the j-th cache of core k, M(v ijk ) is the miss rate of the j-th cache of core k, The average delay between adjacent j-1-level and j-level caches in core k, n α is the total number of core particles, |R k | is the number of cores in corek, and T is the time to access memory.

[0111] More specifically, in order to estimate the average delay between adjacent caches, it is necessary to calculate the point-to-point delay between two nodes in the chip-to-chip and chip-to-chip interconnection systems based on the delay model and combined with the above flow theory. The calculation formula for the average delay is as follows:

[0112]

[0113] in, is from node n p,q To node n r,s flow rate, c=1,…,g.

[0114] Through the above embodiments, a system performance model is generated based on the miss rate model and the delay model, and the average delay between adjacent cache levels is introduced into the performance model. By optimizing the data flow path and strategy between cache levels, the delay in data access can be reduced and the response speed of the system can be improved. After introducing the average delay between adjacent cache levels, the hit rate under different cache strategies can be more accurately evaluated, which is beneficial to the architectural optimization of the cache subsystem.

[0115] In some embodiments, solving the system performance model to obtain the target cache parameters may further include the following steps:

[0116] Obtain a preset architectural area of ​​the cache subsystem, and determine an area constraint condition that the architectural area of ​​the cache subsystem is less than the preset architectural area; obtain a preset architectural power consumption of the cache subsystem, and determine a power consumption constraint condition that the architectural power consumption of the cache subsystem is less than the preset architectural power consumption; solve a system performance model based on the area constraint condition and the power consumption constraint condition to obtain target cache parameters.

[0117] Specifically, the architectural area formula for the cache subsystem based on a multi-chip integrated system is the cumulative area of ​​each component. The area modeling of the multi-chip system is as follows:

[0118]

[0119] Among them, A1(v ijk ) is the area of ​​the core, A2(v ijk ) is the area of ​​memory, A3(v ijk ) is the area of ​​the router.

[0120] On the other hand, the architectural power consumption formula of the cache subsystem based on the multi-chip integrated system is the cumulative power consumption of each component. The power consumption of the multi-chip system is modeled as follows:

[0121]

[0122] Among them, P1(v ijk ) is the power consumption of the core, P2(v ijk ) is the power consumption of the memory, P3(v ijk ) is the power consumption of the router.

[0123] Through the performance, power and area model, under the constraints of area and power, the storage hierarchy graph G1(V, E) and network topology graph G2(N, C) of the cache subsystem of the multi-chip integrated system are solved to achieve the best performance of the cache subsystem of the multi-chip integrated system, thereby maximizing IPC. The architectural area of ​​the multi-chip system is smaller than the constrained area A T , the power of the multi-chip system architecture is lower than the constraint power P T. Then the optimization problem can be defined as follows:

[0124] maxIPC(G1,G2)

[0125] stA(G1,G2)≤A T

[0126] P(G1,G2)≤P T

[0127] Through the above embodiments, the area and power consumption constraint performance models can be used to more accurately predict and evaluate the impact of different design schemes on circuit performance, area and power consumption: based on the area constraint performance model, a more compact circuit layout can be designed to reduce the circuit area, and the power consumption constraint performance model helps to reduce the power consumption of the circuit; therefore, by defining the optimization problem through the area and power consumption constraint performance model, the performance and reliability of the cache subsystem can be significantly improved.

[0128] In some embodiments, solving the system performance model to obtain the target cache parameters may further include the following steps:

[0129] Based on the system performance model, a root node is constructed according to the architecture topology diagram; starting from the root node, the branch value range of each layer of sub-nodes is determined layer by layer based on the architecture topology diagram, and a search tree is constructed layer by layer according to the branch value range; the search tree includes the root node and each layer of sub-nodes; the tree nodes are traversed in the search tree, and the target cache parameters are solved.

[0130] Specifically, since the design space of the cache subsystem of the multi-chip integrated system is large, the problem defined has high complexity. In order to effectively solve the above problem, a branch and bound algorithm is used to solve it. In this algorithm, a search tree is used, in which the tree node τ i The definition is as follows:

[0131]

[0132] Among them, G1, G2, …, G j is the adjacency matrix abstracted from G1(V,E), which represents the connection relationship between nodes; |R1|,|R2|,…,|R j | is the core particle R1, R2, ..., R j The number of cores in; c1,c2,…,c j is the number of cores in the multi-core integrated system; h1,h2,…,h j is the maximum number of cache levels in each core; w1,w2,…,w j are cache-related parameters, including cache size, cache line size, associativity, etc.; t1, t2, …, t jIt is the network topology of G2, including Mesh, Ring, Crossbar, etc.

[0133] Starting from the root node, based on the storage hierarchy diagram and network topology diagram in the architecture topology diagram, the value range of each layer of the sub-node branch is gradually determined layer by layer, and a search tree is constructed. Specifically, from layer 0 to layer 1c, the root node branches into j sub-nodes, corresponding to the adjacency matrix G1, G2, …, G j From layer 1c to layer 2c, the branching of child nodes is based on CPI (v i0k ) is in the range of {0,1}; for nodes from the 2c layer to the 3c layer, the branching of the child nodes is based on cs(v ijk ), that is, {256kB, 512kB, 1MB, 2MB, 4MB, 8MB, 16MB}, indicating the power of 2; for nodes from the 3c layer to the 4c ​​layer, the branching of the child nodes is based on cl(v ijk ) is in the range of {16,32}; for nodes from layer 4c to layer 5c, the branching of child nodes is based on as(v ijk ), that is, {1,2,4}. For nodes from layer 5c to layer 6c, the branching of child nodes is based on the number of cores in each core particle |R i |, the value range is {4,8,16}; for nodes from layer 6c to layer 7c, the branching of child nodes is based on the number of core particles, the value range is {32,64,128}; for nodes from layer 7c to layer 8c, the branching of child nodes is based on the maximum cache level h i , the value range is {2,3,4}; for nodes from layer 8c to layer 9c, the branching of the child nodes is based on the network topology t of the network topology graph G2 in the multi-core integrated system i , which consists of six specific topologies represented by the values ​​{0,1,2,3,4,5}.

[0134] It should also be noted that in the above process of building a search tree and traversing tree nodes, a pruning algorithm for the search tree is also provided:

[0135] In the detection tree nodes, the feasible solution is less than the preset current maximum value or does not meet the preset constraints. The tree nodes to be pruned are detected, and pruning is performed on the branch where the detected tree nodes to be pruned are located to obtain an updated search tree; the tree nodes are traversed in the updated search tree to obtain the target cache parameters.

[0136] Specifically, for optimal pruning, the pruning process can be: when the node τ currently being searched i is a leaf node, and the feasible solution obtained by the current node is still less than the current maximum value, the pruning operation is performed. For infeasible pruning, the pruning process can be: when the currently searched node τi The above constraints are not met, that is, A(G1,G2)≤A T Or P(G1,G2)≤P T By the above method, the branches in the search tree that do not meet the constraints and other conditions are pruned, which is conducive to speeding up the search process.

[0137] Through the above embodiments, a solution method for solving optimization problems using branch and bound is provided, and a method for constructing a hierarchical and step-by-step refined search tree is provided in the algorithm, thereby ensuring that the search tree can comprehensively and systematically search for architectural configurations, which is conducive to quickly and accurately finding the optimal architectural configuration parameters.

[0138] It should be noted that the steps shown in the above process or the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0139] This embodiment also provides a cache architecture optimization device for a multi-chip integrated system, which is used to implement the above-mentioned embodiments and preferred implementation modes, and will not be repeated here. As used below, the terms "module", "unit", "sub-unit", etc. can be a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0140] Figure 6 is a structural block diagram of a cache architecture optimization device for a multi-chip integrated system according to an embodiment of the present application, such as Figure 6 As shown, the device includes: an acquisition module 61, a model building module 62 and a generation module 63; wherein:

[0141] The acquisition module 61 is used to acquire an architecture topology diagram of the multi-chip integrated system; the architecture topology diagram includes a storage hierarchy diagram and a network topology diagram; the storage hierarchy diagram is a hierarchical connection diagram of a cache subsystem of the multi-chip integrated system; and the network topology diagram is a chip connection diagram of the multi-chip integrated system;

[0142] A model building module 62 is used to build a system performance model based on the architecture topology diagram;

[0143] The generation module 63 is used to solve the system performance model, obtain the target cache parameters, and generate a target cache architecture diagram based on the target cache parameters and the storage hierarchy diagram.

[0144] It should be noted that the above-mentioned modules can be either functional modules or program modules, and can be implemented by software or hardware. For modules implemented by hardware, the above-mentioned modules can be located in the same processor; or the above-mentioned modules can be located in different processors in any combination. Each module can be either a functional module or a program module, and can be implemented by software or hardware. For specific examples in this embodiment, reference can be made to the examples described in the above-mentioned embodiments and optional implementations, and will not be repeated in this embodiment.

[0145] This embodiment further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0146] Optionally, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0147] Optionally, in this embodiment, the processor may be configured to perform the following steps through a computer program:

[0148] S1, obtain the architecture topology diagram of the multi-chip integrated system; the architecture topology diagram includes a storage hierarchy diagram and a network topology diagram; the storage hierarchy diagram is a hierarchical connection diagram of the cache subsystem of the multi-chip integrated system; the network topology diagram is a chip connection diagram of the multi-chip integrated system.

[0149] S2, builds a system performance model based on the architecture topology diagram.

[0150] S3, solves the system performance model to obtain the target cache parameters, and generates a target cache architecture diagram based on the target cache parameters and the storage hierarchy diagram.

[0151] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementation modes, and this embodiment will not be described in detail here.

[0152] In addition, in combination with the cache architecture optimization method of the multi-chip integrated system in the above embodiment, the embodiment of the present application can provide a storage medium for implementation. The storage medium stores a computer program; when the computer program is executed by the processor, any cache architecture optimization method of the multi-chip integrated system in the above embodiment is implemented.

[0153] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0154] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0155] Those skilled in the art should understand that the technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0156] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A cache architecture optimization method for a multi-chip integrated system, characterized in that: The method comprises: Acquire an architecture topology diagram of the multi-chip integrated system; the architecture topology diagram includes a storage hierarchy diagram and a network topology diagram; the storage hierarchy diagram is a hierarchical connection diagram of a cache subsystem of the multi-chip integrated system; the network topology diagram is a chip connection diagram of the multi-chip integrated system; Based on the architecture topology diagram, construct a system performance model; The system performance model is solved to obtain target cache parameters, and a target cache architecture diagram is generated based on the target cache parameters and the storage hierarchy diagram.

2. The cache architecture optimization method according to claim 1, characterized in that: The constructing of a system performance model based on the architecture topology diagram includes: Based on the storage hierarchy diagram in the architecture topology diagram, model the miss rate of the cache subsystem to generate a miss rate model, and based on the network topology diagram in the architecture topology diagram, model the network delay time of the multi-chip integrated system to generate a delay model; The system performance model is constructed according to the miss rate model and the delay model.

3. The cache architecture optimization method according to claim 2, characterized in that: The step of modeling the miss rate of the cache subsystem based on the storage hierarchy diagram in the architecture topology diagram to generate a miss rate model includes: Based on the storage hierarchy diagram, determine a cache hierarchy node set of the cache subsystem; the cache hierarchy node set is a set of upper-layer cache nodes of the current node included in the cache hierarchy structure in the cache subsystem; Based on the cache level node set, the miss rate of the cache subsystem is modeled to generate the miss rate model.

4. The cache architecture optimization method according to claim 2, characterized in that: The step of modeling the network delay time of the multi-chip integrated system based on the network topology diagram in the architecture topology diagram to generate a delay model includes: Based on the network topology diagram, determining the node position relationship between the starting node and the destination node in the multi-core integrated system; In a case where the node position relationship indicates that the start node and the destination node are located in the same chiplet, generating a first delay model according to the chiplet intra-chip delay in the multi-chiplet integrated system; In a case where the node position relationship indicates that the start node and the destination node are located in different chiplets, generating a second delay model according to chiplet intra-chip delay and chiplet inter-chip delay in the multi-chiplet integrated system; The delay model includes the first delay model and the second delay model.

5. The cache architecture optimization method according to claim 4, characterized in that: The different core particles include a first core particle and a second core particle, the first core particle is the core particle where the starting node is located, and the second core particle is the core particle where the destination node is located; the generating a second delay model according to the intra-core delay and inter-core delay in the multi-core integrated system includes: Determining a first interface node in the first core-grain and a second interface node in the second core-grain; Based on the network topology graph, a first path, a second path and a third path are calculated; the first path is a path between the starting node in the first core particle and the first interface node, the second path is a path between the destination node in the second core particle and the second interface node, and the third path is a path between the first interface node and the second interface node; The chip intra-chip delay is obtained based on the first path and the second path, the chip inter-chip delay is obtained based on the third path, and a second delay model is generated according to the chip intra-chip delay and the chip inter-chip delay.

6. The cache architecture optimization method according to claim 2, characterized in that: The constructing the system performance model according to the miss rate model and the delay model includes: Obtaining cache miss rates and cache delay times of caches at each level in the cache subsystem according to the miss rate model and the delay model, and calculating average delay times between adjacent cache levels in the core particle according to the cache delay times; The system performance model is constructed according to the cache miss rate and the average delay time.

7. The cache architecture optimization method according to claim 1, characterized in that: Solving the system performance model to obtain target cache parameters includes: Acquire a preset architectural area of ​​the cache subsystem, and determine an area constraint condition that the architectural area of ​​the cache subsystem is smaller than the preset architectural area; Acquire a preset architecture power consumption of the cache subsystem, and determine a power consumption constraint condition that the architecture power consumption of the cache subsystem is less than the preset architecture power consumption; Based on the area constraint condition and the power consumption constraint condition, the system performance model is solved to obtain the target cache parameter.

8. The cache architecture optimization method according to any one of claims 1 to 7, characterized in that: Solving the system performance model to obtain target cache parameters includes: Based on the system performance model, construct a root node according to the architecture topology diagram; Starting from the root node, determining the branch value range of each layer of sub-nodes layer by layer based on the architecture topology diagram, and constructing a search tree layer by layer according to the branch value range; the search tree includes the root node and each layer of sub-nodes; The tree nodes are traversed in the search tree, and the target cache parameters are obtained by solving.

9. A cache architecture optimization device for a multi-chip integrated system, characterized in that: include: An acquisition module, used to acquire an architecture topology diagram of the multi-chip integrated system; The architecture topology diagram includes a storage hierarchy diagram and a network topology diagram; The storage hierarchy diagram is a hierarchy connection diagram of the cache subsystem of the multi-chip integrated system; the network topology diagram is a chip connection diagram of the multi-chip integrated system; A model building module, used to build a system performance model based on the architecture topology diagram; A generation module is used to solve the system performance model to obtain target cache parameters, and generate a target cache architecture diagram based on the target cache parameters and the storage hierarchy diagram.

10. A storage medium, characterized in that: The storage medium stores a computer program, wherein the computer program is configured to execute the cache architecture optimization method for a multi-chip integrated system according to any one of claims 1 to 8 when running.

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