Integrated circuit coupling failure analysis method and device based on neural network

Abstract

The invention particularly relates to an integrated circuit coupling failure analysis method based on a neural network. The method comprises the following steps: constructing a ring oscillator circuit; inputting a preset stress condition into a failure analysis model based on a neural network, and obtaining threshold voltage degradation amount prediction data output by the model; wherein the failure analysis model is used for predicting threshold voltage degradation of the PMOS device; the stress condition data is matched with the ring oscillator circuit; configuring the threshold voltage degradation amount prediction data to a grid electrode of a key transistor in a ring oscillator circuit, and obtaining corresponding circuit frequency degradation data; and performing data comparison on the circuit frequency degradation data and preset verification data to obtain a first data comparison result, and generating coupling failure analysis data based on the first data comparison result. According to the method, an analysis model for coupling failure of the NBTI and the HCD of the PMOS transistor is established, so that errors of data analysis are reduced, and the application range is widened.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a neural network-based integrated circuit coupling failure analysis method and device, a storage medium, a computer program product, and an electronic device. Background Art

[0002] In related technologies, modern integrated circuits face a complex environment where multiple failure mechanisms coexist. Considering the actual working conditions of transistors in integrated circuits, this complex external stress poses challenges to the coupled failure simulation of circuits: first, traditional physical models are relatively complex and difficult to apply to existing simulators; second, it is difficult for simulators to directly access device ports in the circuit to extract device electrical parameter degradation and then correlate it with circuit performance changes; third, when the circuit is working, the stress conditions of the device in the circuit will change dynamically with the degradation of the device itself, which requires a lot of computing resources; fourth, the time for simulating degradation simulation. In fact, it is impossible for simulators to perform transient and degradation simulation tasks for several years.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] The present invention provides a method and device for analyzing coupled failure of integrated circuits based on a neural network, a storage medium, a computer program product, and an electronic device, which can realize the analysis of the coupled failure mechanism of NBTI effect and HCD effect, thereby overcoming the defects existing in the prior art to a certain extent.

[0005] Other features and advantages of the present invention will become apparent from the following detailed description, or may be learned in part by practice of the present invention.

[0006] According to a first aspect of the present invention, a method for analyzing coupling failure of integrated circuits based on a neural network is provided, the method comprising:

[0007] Build a ring oscillator circuit;

[0008] Inputting a preset stress condition into a failure analysis model based on a neural network to obtain threshold voltage degradation prediction data output by the model; wherein the failure analysis model is used to predict threshold voltage degradation of a PMOS device; and the stress condition data matches the ring oscillator circuit;

[0009] Configuring the threshold voltage degradation amount prediction data to the gate of a key transistor in a ring oscillator circuit to obtain corresponding circuit frequency degradation data;

[0010] The circuit frequency degradation data is compared with preset verification data to obtain a first data comparison result, and coupling failure analysis data is generated based on the first data comparison result.

[0011] In some exemplary embodiments, the method further comprises:

[0012] adding a target voltage excitation source to the ring oscillator circuit and acquiring corresponding initial circuit performance data; wherein the target voltage excitation source matches the stress condition data;

[0013] The initial circuit performance data is compared with the circuit frequency degradation data to obtain a second data comparison result, and coupling failure analysis data is generated based on the first data comparison result and the second data comparison result.

[0014] In some exemplary embodiments, the preset stress condition includes: stress voltage, duty cycle, time and frequency.

[0015] In some exemplary embodiments, the method further comprises: pre-training the failure analysis model, comprising:

[0016] Constructing a sample data set, wherein the sample data set includes: NBTI effect coupling failure data and HCD effect coupling failure data;

[0017] The sample data is used to perform back-propagation training on a failure analysis model based on a long short-term memory neural network to obtain the failure analysis model; wherein a loss function is constructed based on the difference between the true value and the predicted value of the threshold voltage, the monotonically increasing trend of the threshold voltage, and the boundary constraint of the threshold voltage.

[0018] In some exemplary embodiments, when constructing the sample data set, the method further includes:

[0019] Based on the gate voltage of the PMOS transistor, the degradation value of the failure threshold voltage of the NBTI effect and the degradation value of the failure threshold voltage of the HCD effect are combined to obtain combined sample data; and the combined sample data is configured as the sample data set.

[0020] In some exemplary embodiments, the method further comprises:

[0021] Create a new library;

[0022] Calling an editor tool of the Cadence Virtuoso tool to compile the trained failure analysis model to obtain a corresponding failure analysis model file;

[0023] A source file corresponding to the failure analysis model file is constructed and saved in the new library.

[0024] According to a second aspect of the present invention, there is provided an integrated circuit coupling failure analysis device based on a neural network, comprising:

[0025] Circuit simulation module for building ring oscillator circuits;

[0026] A first data calculation module, used to input a preset stress condition into a failure analysis model based on a neural network, and obtain threshold voltage degradation prediction data output by the model; wherein the failure analysis model is used to predict the threshold voltage degradation of the PMOS device; and the stress condition data matches the ring oscillator circuit;

[0027] A second data calculation module, configured to configure the threshold voltage degradation amount prediction data to the gate of the key transistor in the ring oscillator circuit to obtain corresponding circuit frequency degradation data;

[0028] The data analysis module is used to compare the circuit frequency degradation data with preset verification data to obtain a first data comparison result, and generate coupling failure analysis data based on the first data comparison result.

[0029] According to a third aspect of the present invention, there is provided a storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the above-mentioned neural network-based integrated circuit coupling failure analysis method.

[0030] According to a fourth aspect of the present invention, there is provided an electronic device, comprising:

[0031] Processor; and

[0032] A memory, configured to store executable instructions of the processor;

[0033] Wherein, the processor is configured to implement the above-mentioned neural network-based integrated circuit coupling failure analysis method by executing the executable instructions.

[0034] According to a fifth aspect of the present invention, there is provided a computer program product having a computer program stored thereon, which implements the above-mentioned neural network-based integrated circuit coupling failure analysis method when the computer program is executed by a processor.

[0035] The neural network-based integrated circuit coupling failure analysis method provided by the embodiment of the present invention obtains threshold voltage degradation prediction data corresponding to preset stress conditions by using a trained failure analysis model, and then inputs the threshold voltage degradation prediction data into a pre-built ring oscillator circuit, thereby obtaining corresponding circuit frequency degradation data, and then compares the circuit frequency degradation data with preset verification data, thereby obtaining coupling failure analysis data. By pre-training a neural network-based failure analysis model, the coupling failure of the NBTI effect and the HCD effect can be accurately estimated, and the reliability analysis of the integrated circuit under the coupling failure mechanism is realized.

[0036] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and together with the specification are used to explain the principles of the present invention. Obviously, the accompanying drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0038] Figure 1 A schematic diagram schematically illustrates a method for analyzing coupling failure of an integrated circuit based on a neural network according to an exemplary embodiment of the present invention;

[0039] Figure 2 A schematic diagram schematically illustrates a calculation process of an LSTM model of an exemplary embodiment of the present invention;

[0040] Figure 3 A schematic diagram schematically illustrates an error histogram of a neural network model according to an exemplary embodiment of the present invention;

[0041] Figure 4 A schematic diagram schematically illustrates a comparison between a predicted value output by a model and a true value according to an exemplary embodiment of the present invention;

[0042] Figure 5 A schematic diagram schematically illustrates a failure analysis model framework of an exemplary embodiment of the present invention;

[0043] Figure 6 A schematic diagram schematically illustrates a flow chart of a method for analyzing coupling failure of integrated circuits based on a neural network according to an exemplary embodiment of the present invention;

[0044] Figure 7 A schematic diagram schematically illustrates an integrated circuit coupling failure analysis device based on a neural network according to an exemplary embodiment of the present invention;

[0045] Figure 8 The figure schematically shows the composition of an electronic device in an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0046] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present invention will be more comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0047] In addition, the accompanying drawings are only schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0048] In the related art, the analysis method of integrated circuit coupling failure is too complex in physical model, resulting in low simulation efficiency when applied to simulation software, and the simulation accuracy and speed do not match. In addition, the analysis mode in some existing technologies is too simplified, the addition mode will lead to large errors and the unified model needs to extract more parameters, and the direct addition mode of threshold voltage changes caused by various failure mechanisms cannot characterize the failure physics; in addition, most solutions are not versatile and can only be used on specific circuit types. There will be relatively large limitations in practical applications, and the prediction results will have large errors.

[0049] In view of the shortcomings and deficiencies of the prior art, this exemplary embodiment provides an integrated circuit coupling failure analysis method based on a neural network. Figure 1 As shown, the integrated circuit coupling failure analysis method based on neural network may specifically include the following steps:

[0050] Step S11, constructing a ring oscillator circuit;

[0051] Step S12, inputting the preset stress condition into the failure analysis model based on the neural network, and obtaining the threshold voltage degradation prediction data output by the model; wherein the failure analysis model is used to predict the threshold voltage degradation of the PMOS device; and the stress condition data matches the ring oscillator circuit;

[0052] Step S13, configuring the threshold voltage degradation amount prediction data to the gate of the key transistor in the ring oscillator circuit to obtain corresponding circuit frequency degradation data;

[0053] Step S14: performing data comparison between the circuit frequency degradation data and preset verification data to obtain a first data comparison result, and generating coupling failure analysis data based on the first data comparison result.

[0054] Below, each step of the neural network-based integrated circuit coupling failure analysis method in this example implementation will be described in more detail with reference to the accompanying drawings and embodiments.

[0055] In this example implementation, the method includes: pre-training the failure analysis model, including:

[0056] Step S21, constructing a sample data set, wherein the sample data set includes: NBTI effect coupling failure data and HCD effect coupling failure data;

[0057] Step S22, using the sample data to perform back-propagation training on the failure analysis model based on the long short-term memory neural network to obtain the failure analysis model; wherein a loss function is constructed based on the difference between the true value and the predicted value of the threshold voltage, the monotonically increasing trend of the threshold voltage, and the boundary constraint of the threshold voltage.

[0058] Specifically, the NBTI failure models based on reaction-diffusion theory include:

[0059]

[0060] in, represents the degradation value of the threshold voltage under NBTI failure, V g represents the gate voltage of the PMOS transistor, c represents the duty cycle, and t represents the stress time; the parameters a, b, c, and c1 are fitting parameters obtained based on the data of the published paper.

[0061] The HCD failure model based on energy-driven theory can be expressed as:

[0062]

[0063] in, represents the degradation value of the threshold voltage under HCD failure, V g Represents the gate voltage of the PMOS transistor, V d represents the drain voltage of the PMOS transistor, t represents the stress time; the parameters d, e, f, g, and h are fitting parameters obtained based on the data of the published paper.

[0064] Specifically, NBTI effect coupled failure data and HCD effect coupled failure data can be collected from public data sources to build a sample data set. For example, the experimental data in the paper can be used as sample data.

[0065] Exemplarily, when constructing the sample data set, the method further includes: combining the degradation value of the failure threshold voltage of the NBTI effect and the degradation value of the failure threshold voltage of the HCD effect based on the gate voltage of the PMOS transistor to obtain combined sample data; and configuring the combined sample data as the sample data set.

[0066] Specifically, in order to construct a data set that includes the coupled failure of NBTI and HCD effects, two formulas are considered that contain the common parameter V g , the above two formulas can be combined. Consider that the coupling of BTI and HCD effects is through V g The coupled failure model based on the physical model is as follows:

[0067]

[0068] Based on the failure physical model, the NBTI and HCD effect coupled aging data set is constructed, which can provide the corresponding characteristic parameters as training sample data. Among them, considering the influence of stress voltage, duty cycle, time and frequency on threshold voltage degradation, the characteristic parameters of the data set can be extracted as stress voltage, duty cycle, time and frequency, and the degradation of threshold voltage is the target value.

[0069] For example, a failure analysis model is established based on a recurrent neural network (RNN) and a long short-term memory neural network (LSTM). The basic formula of the LSTM neural network includes:

[0070]

[0071] Among them, W i , W g , Wf, W o and b i , b g , b f、 b o are the weights and biases of the input gate, memory gate, forget gate, and output gate, respectively. t 、f t , o t are the signals of the input gate, forget gate, memory gate and output gate, x t represents input data, C t Stores temporary memory.

[0072] refer to Figure 2 As shown, in a single a block at time t, when it gives a 1 signal, it means that the input data successfully enters the stream, otherwise it returns 0 to the stream. ft decides whether to store the data in the stream into the memory cell. If the signal is 1, the current value in the memory cell will be updated to the data in the stream, or keep the default value. t has a similar function that returns the result if signal is 1. Then, h t and C t At time (t+1), it is connected to the next A block. The network topology used here is a LSTM layer and several fully connected layers. After the network is trained and tuned, the parameters are stored in the model file.

[0073] In order to increase the accuracy of the neural network model and make it more realistic, we consider using PINN (Physics informed Neural Network) to optimize the established LSTM network. The principle of PINN is to optimize the loss function of the neural network. The basic loss function only considers the error between the predicted value and the true value, which is one-sided. For aging, the degradation of the threshold voltage is a monotonically increasing value, and it is a degradation greater than 0, so the PINN method is used to increase the comprehensiveness of the neural network loss function. The formula of the neural network loss function based on the PINN method includes:

[0074]

[0075] Among them, α, β, and γ represent the weights of the items, Y i represents the true value, Represents the predicted value, and ReLU represents the activation function.

[0076] For the neural network loss function, the first term is the basic loss function definition, which represents the difference between the target value and the predicted value; the second term indicates that the predicted value generally presents a monotonically increasing trend, because the change in threshold voltage is increasing; the third term represents the boundary constraint, because the change in threshold voltage is positive, which can improve the performance of the determination coefficient and estimation error. The error analysis is as follows: Figure 3 As shown, the comparison between the predicted value and the true value is as follows Figure 4 shown.

[0077] The data set of the present invention is constructed based on coupled failure data and a basic failure model. The neural network is trained with a data set containing NBTI and HCD coupled failures, and the trained neural network has the characteristics of coupled failures. In terms of model accuracy, the simulation results of the present invention are significantly improved compared with the direct addition mode, reducing reliability prediction errors.

[0078] Exemplarily, the method further includes:

[0079] Step S31, creating a new library;

[0080] Step S32, calling an editor tool of the Cadence Virtuoso tool to compile the trained failure analysis model to obtain a corresponding failure analysis model file;

[0081] Step S33, constructing a source file corresponding to the failure analysis model file and saving it in the new library.

[0082] Specifically, after the training of the failure analysis model is completed, it can be converted into a SPICE simulation model. For example, the SPICE tool can be used to create a new library, the Editor tool of Cadence Virtuoso can be called, and the failure analysis model can be compiled using the Verilog-A language to obtain the corresponding degradation model file, which is then converted into a Symbol file and saved in the newly created library.

[0083] For example, in step S11, the ring oscillator circuit can be constructed by using SPICE tools and calling components in a specific process library through a Schematic Editor tool, and configuring and adjusting design parameters such as device size. The ring oscillator circuit can adopt a conventional circuit structure.

[0084] Exemplarily, in step S12, preset stress conditions are input into a failure analysis model based on a neural network to obtain threshold voltage degradation prediction data output by the model; wherein the failure analysis model is used to predict threshold voltage degradation of a PMOS device; and the stress condition data matches the ring oscillator circuit.

[0085] Exemplarily, the preset stress conditions include: stress voltage, duty cycle, time and frequency.

[0086] Specifically, refer to Figure 5 As shown, the failure analysis model can be called, and the preset stress conditions can be input into the failure analysis model to obtain the threshold voltage degradation amount prediction data output by the model.

[0087] By using a neural network model to perform degradation simulation on key PMOS transistors, detailed degradation values ​​of the threshold voltage are obtained depending on the transistor workload and the operating conditions throughout the life cycle, characterizing the threshold voltage degradation under field working conditions. Coupled failure data analysis at the transistor level is achieved.

[0088] Exemplarily, in step S13, the threshold voltage degradation amount prediction data is configured to the gate of a key transistor in the ring oscillator circuit to obtain corresponding circuit frequency degradation data.

[0089] Specifically, the model output threshold voltage degradation prediction data can be configured as gate data of key transistors in the ring oscillator circuit, and the coupling failure simulation of the ring oscillator circuit can be carried out in a SPICE tool to obtain corresponding circuit frequency degradation data.

[0090] By using the equivalent voltage source method to inject the threshold voltage degradation determination into the gate of the key PMOS transistor in the circuit for circuit degradation simulation, the reliability degradation data of the circuit caused by coupling failure under actual working conditions can be obtained.

[0091] By applying the threshold voltage degradation curve of the corresponding circuit under actual working conditions obtained by the neural network model to the ring oscillator circuit, the neural network model and circuit-level simulation are combined to realize the integrated circuit coupling failure analysis based on neural network.

[0092] Exemplarily, in step S14, the circuit frequency degradation data is compared with preset verification data to obtain a first data comparison result, and coupling failure analysis data is generated based on the first data comparison result.

[0093] Specifically, the preset verification data may be circuit frequency degradation data corresponding to the preset stress condition data. After obtaining the current circuit frequency degradation data, it may be compared with the preset verification data to obtain a first data comparison result, which may be used as coupling failure analysis data to analyze the degradation trend.

[0094] In some exemplary embodiments, the method further comprises:

[0095] Step S15, adding a target voltage excitation source to the ring oscillator circuit and acquiring corresponding initial circuit performance data; wherein the target voltage excitation source matches the stress condition data;

[0096] Step S16: Compare the initial circuit performance data with the circuit frequency degradation data to obtain a second data comparison result, and generate coupling failure analysis data based on the first data comparison result and the second data comparison result.

[0097] Specifically, for the ring oscillator circuit, a voltage excitation source matching the preset stress condition can be added to it in the ADE environment to perform circuit simulation, thereby realizing the initial simulation of the circuit and obtaining the corresponding initial circuit performance data. By performing initial simulation on the initial circuit without fault injection, the electrical characteristics of the key PMOS transistor in the actual working circuit can be collected, thereby facilitating the failure simulation of the transistor based on the actual working voltage of the simulated circuit. Circuit-level coupled failure data analysis is realized.

[0098] Specifically, the initial circuit performance data may be circuit frequency data under initial conditions. Afterwards, the circuit frequency data under initial conditions may be synchronously compared with the circuit frequency degradation data to obtain a frequency degradation data comparison result of the ring oscillator circuit. Furthermore, the two data comparison results may be integrated to generate final coupling failure analysis data.

[0099] The model of this scheme can be directly applied to tube-level failure analysis. It also links the actual working conditions of the circuit with the tube-level failure simulation to form a systematic analysis method, which further improves the simulation efficiency and accuracy.

[0100] The method provided in the embodiment of the present invention is referred to Figure 6 As shown in the figure, by analyzing the coupling failure behavior of integrated circuits, the whole simulation process including device-level failure simulation and circuit-level failure simulation is reasonably disassembled, and the analysis method of integrated circuit coupling failure is realized by constructing a failure simulation model and a circuit simulation method based on a neural network. For the failure analysis model, a data set of NBTI and HCD coupling failures for PMOS transistors is constructed as a training sample and a model is trained, and a data set that can characterize the NBTI and HCD coupling failure mechanisms is established. According to the constructed data set, the constructed LSTM neural network is trained, and the neural network model is optimized by the PINN method to improve the accuracy of the prediction results and meet the actual physical requirements. The constructed failure analysis model based on a neural network establishes the voltage stress of the key transistor corresponding to the actual working conditions of the circuit, applies the voltage stress to the model, obtains detailed failure information, injects the circuit sensitive unit to carry out coupling failure simulation, and obtains the circuit coupling failure information.

[0101] The present invention aims at the problem that the current integrated circuit coupling failure analysis method is missing and the method is not mature enough. It proposes an integrated circuit coupling failure analysis method, establishes an analysis model for PMOS transistor NBTI and HCD coupling failure based on neural network, develops a series of technical innovations such as a circuit simulation method based on neural network, and improves the accuracy of long-term prediction compared with traditional methods, simplifies formula derivation and calculation process, reduces errors and increases the scope of application. It can solve the problem of integrated circuit simulation under multiple failure problems and provide a new technical method for further promoting the reliability prediction of integrated circuits.

[0102] It should be noted that the above figures are only schematic illustrations of the processes included in the method according to an exemplary embodiment of the present invention, and are not intended to be limiting. It is easy to understand that the processes shown in the above figures do not indicate or limit the time sequence of these processes. In addition, it is also easy to understand that these processes can be performed synchronously or asynchronously, for example, in multiple modules.

[0103] For further reference, Figure 7 As shown, in the embodiment of this example, a neural network-based integrated circuit coupling failure analysis device 70 is also provided, comprising:

[0104] A circuit simulation module 701 is used to construct a ring oscillator circuit;

[0105] A first data calculation module 702 is used to input a preset stress condition into a failure analysis model based on a neural network to obtain threshold voltage degradation prediction data output by the model; wherein the failure analysis model is used to predict threshold voltage degradation of a PMOS device; and the stress condition data matches the ring oscillator circuit;

[0106] A second data calculation module 703 is used to configure the threshold voltage degradation amount prediction data to the gate of the key transistor in the ring oscillator circuit to obtain corresponding circuit frequency degradation data;

[0107] The data analysis module 704 is used to perform data comparison between the circuit frequency degradation data and preset verification data to obtain a first data comparison result, and generate coupling failure analysis data based on the first data comparison result.

[0108] It should be noted that, although several modules or units of the equipment for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to an embodiment of the present invention, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into being embodied by multiple modules or units.

[0109] Figure 8 A schematic diagram of an electronic device suitable for implementing an embodiment of the present invention is shown.

[0110] It should be noted that Figure 8 The electronic device 1000 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present invention.

[0111] like Figure 8 As shown, the electronic device 1000 includes a central processing unit (CPU) 1001, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 1002 or the program loaded from the storage part 1008 to the random access memory (RAM) 1003. In the RAM 1003, various programs and data required for system operation are also stored. The CPU 1001, ROM 1002 and RAM 1003 are connected to each other through a bus 1004. An input / output (I / O) interface 1005 is also connected to the bus 1004.

[0112] The following components are connected to the I / O interface 1005: an input section 1006 including a keyboard, a mouse, etc.; an output section 1007 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 1008 including a hard disk, etc.; and a communication section 1009 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 1009 performs communication processing via a network such as the Internet. A drive 1010 is also connected to the I / O interface 1005 as needed. A removable medium 1011, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 1010 as needed, so that a computer program read therefrom is installed into the storage section 1008 as needed.

[0113] In particular, according to an embodiment of the present invention, the process described below with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present invention includes a computer program product, which includes a computer program carried on a storage medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication part 1009, and / or installed from a removable medium 1011. When the computer program is executed by a central processing unit (CPU) 1001, various functions defined in the system of the present application are executed.

[0114] It should be noted that the storage medium shown in the embodiment of the present invention may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present invention, a computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with an instruction execution system, device or device. In the present invention, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any storage medium other than computer-readable storage media, which may send, propagate, or transmit programs for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the storage medium may be transmitted using any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0115] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present invention. In this regard, each box in the flow chart or block diagram can represent a module, a program segment, or a part of a code, and the above-mentioned module, program segment, or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flow chart, and the combination of the boxes in the block diagram or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0116] The units involved in the embodiments of the present invention may be implemented by software or hardware, and the units described may also be arranged in a processor. The names of these units do not, in some cases, limit the units themselves.

[0117] It should be noted that, as another aspect, the present application also provides a storage medium, which can be included in an electronic device; or it can exist independently without being installed in the electronic device. The above storage medium carries one or more programs, and when the above one or more programs are executed by an electronic device, the electronic device implements the method described in the following embodiments. For example, the electronic device can implement the following Figure 1 The individual steps of the method are shown.

[0118] In one embodiment, the present application provides a computer program product, including a computer program, which implements the steps in the above-mentioned method embodiments when executed by a processor.

[0119] In addition, the above-mentioned figures are only schematic illustrations of the processes included in the method according to an exemplary embodiment of the present invention, and are not intended to be limiting. It is easy to understand that the processes shown in the above-mentioned figures do not indicate or limit the time sequence of these processes. In addition, it is also easy to understand that these processes can be performed synchronously or asynchronously, for example, in multiple modules.

[0120] Other embodiments of the invention will readily occur to those skilled in the art after considering the specification and practicing the invention herein. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art that are not disclosed by the present invention. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the claims.

[0121] It should be understood that the present invention is not limited to the exact construction that has been described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A method for analyzing coupling failure of integrated circuits based on neural networks, characterized in that: The method comprises: Build a ring oscillator circuit; Inputting a preset stress condition into a failure analysis model based on a neural network to obtain threshold voltage degradation prediction data output by the model; wherein the failure analysis model is used to predict threshold voltage degradation of a PMOS device; and the stress condition data matches the ring oscillator circuit; Configuring the threshold voltage degradation amount prediction data to the gate of a key transistor in a ring oscillator circuit to obtain corresponding circuit frequency degradation data; The circuit frequency degradation data is compared with preset verification data to obtain a first data comparison result, and coupling failure analysis data is generated based on the first data comparison result.

2. The method according to claim 1, characterized in that: The method further comprises: adding a target voltage excitation source to the ring oscillator circuit and acquiring corresponding initial circuit performance data; wherein the target voltage excitation source matches the stress condition data; The initial circuit performance data is compared with the circuit frequency degradation data to obtain a second data comparison result, and coupling failure analysis data is generated based on the first data comparison result and the second data comparison result.

3. The method according to claim 1, characterized in that The preset stress conditions include: stress voltage, duty cycle, time and frequency.

4. The method according to claim 1, characterized in that: The method further includes: pre-training the failure analysis model, including: Constructing a sample data set, wherein the sample data set includes: NBTI effect coupling failure data and HCD effect coupling failure data; The sample data is used to perform back-propagation training on a failure analysis model based on a long short-term memory neural network to obtain the failure analysis model; wherein a loss function is constructed based on the difference between the true value and the predicted value of the threshold voltage, the monotonically increasing trend of the threshold voltage, and the boundary constraint of the threshold voltage.

5. The method according to claim 4, characterized in that When constructing the sample data set, the method further includes: Based on the gate voltage of the PMOS transistor, the degradation value of the failure threshold voltage of the NBTI effect and the degradation value of the failure threshold voltage of the HCD effect are combined to obtain combined sample data; and the combined sample data is configured as the sample data set.

6. The method according to claim 4, characterized in that The method further comprises: Create a new library; Calling an editor tool of the Cadence Virtuoso tool to compile the trained failure analysis model to obtain a corresponding failure analysis model file; A source file corresponding to the failure analysis model file is constructed and saved in the new library.

7. An integrated circuit coupling failure analysis device based on a neural network, characterized in that: The device comprises: Circuit simulation module for building ring oscillator circuits; A first data calculation module, used to input a preset stress condition into a failure analysis model based on a neural network, and obtain threshold voltage degradation prediction data output by the model; wherein the failure analysis model is used to predict the threshold voltage degradation of the PMOS device; and the stress condition data matches the ring oscillator circuit; A second data calculation module, configured to configure the threshold voltage degradation amount prediction data to the gate of the key transistor in the ring oscillator circuit to obtain corresponding circuit frequency degradation data; The data analysis module is used to compare the circuit frequency degradation data with preset verification data to obtain a first data comparison result, and generate coupling failure analysis data based on the first data comparison result.

8. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the neural network-based integrated circuit coupling failure analysis method according to any one of claims 1 to 6 is implemented.

9. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the neural network-based integrated circuit coupling failure analysis method according to any one of claims 1 to 6 is implemented.

10. An electronic device, characterized in that: include: processor; as well as A memory, configured to store executable instructions of the processor; The processor is configured to execute the neural network-based integrated circuit coupling failure analysis method according to any one of claims 1 to 6 by executing the executable instructions.

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