Graphics processor, graphics drawing method, chip and electronic device

Abstract

The application discloses a graphics processor, a graphics drawing method, a chip and an electronic device, and belongs to the chip field. The graphics processor comprises a geometry processing pipeline, which is used for realizing the functions of an upscaling shader and a mesh shader; the geometry processing pipeline comprises a first task generation pipeline, which is used for creating an upscaling shader thread group; a shader execution unit, which is used for running the upscaling shader thread group to obtain upscaling shading results and a second drawing instruction; a task control unit, which is used for inputting the second drawing instruction into the second task generation pipeline; the second task generation pipeline, which is used for creating a mesh shader thread group based on the second drawing instruction; the shader execution unit, which is used for running the mesh shader thread group to obtain mesh shading results based on the upscaling shading results; and the task control unit, which is used for outputting the mesh shading results. The application provides a geometry processing pipeline supporting a mesh shader and an upscaling shader.

Description

Technical Field

[0001] This application relates to the field of chips, and in particular to a graphics processor, a graphics drawing method, a chip, and an electronic device. Background Technology

[0002] The Graphics Processing Unit (GPU) provides the VTG rendering pipeline. The geometry processing pipeline in the VTG pipeline consists of vertex shaders, tessellation shaders (including shell shaders, tessellation stages, and domain shaders), and geometry shaders. In the VTG rendering pipeline, vertex shaders and geometry shaders are processed serially, which limits the efficiency of parallel computation and can easily lead to performance bottlenecks.

[0003] The graphics processor in the related technology also provides a mesh shading rendering pipeline, in which the geometry processing pipeline includes an amplification shader (optional) and a mesh shader. The mesh shader can process multiple vertices and fragments in parallel, improving the performance of the graphics processor. Summary of the Invention

[0004] This application provides a graphics processor, a graphics drawing method, a chip, and an electronic device. This application also provides a geometry processing pipeline that supports magnifying shaders and mesh shaders, or supports mesh shaders.

[0005] According to one aspect of this application, a graphics processor is provided, which includes a geometry processing pipeline for implementing the functions of an amplification shader and a mesh shader; the geometry processing pipeline includes a first task generation pipeline, a second task generation pipeline, a shader execution unit, and a task control unit.

[0006] The first task generation pipeline is used to create an amplified shader thread group based on the first drawing instruction; the shader execution unit is used to run the amplified shader thread group to obtain the amplified shading result and the second drawing instruction; the task control unit is used to input the second drawing instruction into the second task generation pipeline.

[0007] The second task generation pipeline is used to create a mesh shader thread group based on the second drawing instruction and input the mesh shader thread group into the shader execution unit; the shader execution unit is used to run the mesh shader thread group and obtain the mesh shading result based on the magnified shading result; the task control unit is used to output the mesh shading result to the pipeline after the geometry processing pipeline.

[0008] According to one aspect of this application, a graphics processor is provided, which includes a geometry processing pipeline for implementing the functions of a mesh shader; the geometry processing pipeline includes a third task generation pipeline, a shader execution unit, and a task control unit;

[0009] The third task generation pipeline is used to create a mesh shader thread group based on the third drawing instruction, input the mesh shader thread group into the shader execution unit, and send the mesh task information corresponding to the mesh shader thread group to the task control unit.

[0010] The shader execution unit is used to run the mesh shader thread group and obtain the mesh shading results; the task control unit is used to obtain the mesh shading results according to the instructions of the mesh task information and output the mesh shading results to the pipeline after the geometry processing pipeline.

[0011] According to one aspect of this application, a graphics rendering method is provided, the method being applied to a graphics processor, the graphics processor including a geometry processing pipeline for implementing the functions of an amplification shader and a mesh shader; the geometry processing pipeline includes a first task generation pipeline, a second task generation pipeline, a shader execution unit, and a task control unit; the method includes:

[0012] The first task generation pipeline creates an amplified shader thread group based on the first drawing instruction; the shader execution unit runs the amplified shader thread group to obtain the amplified shading result and the second drawing instruction; the task control unit inputs the second drawing instruction into the second task generation pipeline.

[0013] The second task generation pipeline creates a mesh shader thread group based on the second drawing instruction; the shader execution unit runs the mesh shader thread group and obtains the mesh shading result based on the magnified shading result; the task control unit outputs the mesh shading result to the pipeline after the geometry processing pipeline.

[0014] According to one aspect of this application, a graphics rendering method is provided, the method being applied to a graphics processor, the graphics processor including a geometry processing pipeline for implementing the functionality of a mesh shader; the geometry processing pipeline includes a third task generation pipeline, a shader execution unit, and a task control unit; the method includes:

[0015] The third task generation pipeline creates a mesh shader thread group based on the third drawing instruction, inputs the mesh shader thread group into the shader execution unit, and sends the mesh task information corresponding to the mesh shader thread group to the task control unit.

[0016] The shader execution unit runs the mesh shader thread group to obtain the mesh shading results; the task control unit obtains the mesh shading results according to the instructions of the mesh task information and outputs the mesh shading results to the pipeline after the geometry processing pipeline.

[0017] According to one aspect of this application, a chip is provided, the chip including the above-described graphics processor.

[0018] According to one aspect of this application, a server is provided, the server including the above-described graphics processor.

[0019] According to one aspect of this application, an electronic device is provided, which includes the aforementioned graphics processor.

[0020] The beneficial effects of the technical solutions provided in this application include at least the following:

[0021] This application provides a geometry processing pipeline supporting both a magnifying shader and a mesh shader. Furthermore, it provides a resource scheduling scheme within this pipeline. In this application, the task control unit schedules the second drawing instructions output by the magnifying shader and the mesh shading results output by the mesh shader, improving the orderliness of the scheduling. Moreover, the geometry processing pipeline designed in this application is programmable, comprising a first task generation pipeline, a second task generation pipeline, a task execution unit, and a task control unit. This rich hardware configuration enhances programming flexibility and improves the overall throughput of the graphics processor. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of a geometry processing pipeline provided in one embodiment of this application.

[0024] Figure 2 This is a schematic diagram of a geometry processing pipeline provided in one embodiment of this application.

[0025] Figure 3 This is a schematic diagram of a geometry processing pipeline provided in one embodiment of this application.

[0026] Figure 4 This is a schematic diagram of a geometry processing pipeline provided in one embodiment of this application.

[0027] Figure 5 This is a schematic diagram of a geometry processing pipeline provided in one embodiment of this application.

[0028] Figure 6 This is a schematic diagram of a geometry processing pipeline provided in one embodiment of this application.

[0029] Figure 7 This is a schematic diagram of the drawing result of a mesh shader provided in one embodiment of this application.

[0030] Figure 8 This is a schematic diagram of the drawing result of a mesh shader provided in another embodiment of this application.

[0031] Figure 9 This is a schematic diagram of a data block of a map provided in one embodiment of this application.

[0032] Figure 10 This is a schematic diagram of additional attribute segmentation provided in one embodiment of this application.

[0033] Figure 11 This is a schematic diagram of a quantity indication segment provided in one embodiment of this application.

[0034] Figure 12 This is a flowchart of a method for parsing and rendering results during the rasterization stage, provided in one embodiment of this application.

[0035] Figure 13 This is a structural block diagram of an electronic device provided in one embodiment of this application.

[0036] Figure 14 This is a schematic diagram of the structure of a server provided in one embodiment of this application. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0038] First, some terms used in the embodiments of this application will be introduced:

[0039] The geometry processing pipeline consists of two main parts: the geometry processing pipeline and the pixel processing pipeline. The geometry processing pipeline primarily processes the geometric coordinates and shape of the graphics, while the pixel processing pipeline mainly performs pixel operations on the graphics. In the VTG rendering pipeline proposed in DX11.3, the geometry processing pipeline includes vertex shaders, tessellation shaders (including hull shaders, tessellation stages, and domain shaders), and geometry shaders. In the mesh shading rendering pipeline proposed in DX12, the geometry processing pipeline includes amplification shaders and mesh shaders.

[0040] In the geometry processing pipeline of the VTG rendering pipeline, after receiving a drawing command, the initial drawing data first enters the vertex shader. The vertex shader performs coordinate transformations of the vertices. The vertex shader processes data on a vertex-by-vertex basis. After processing by the vertex shader, the data enters the tessellation shader, which is an optional shader. In the tessellation shader, the shell shader performs the pre-calculation process for tessellation. The tessellation parameters output by the shell shader enter the tessellation stage, which calculates the new vertices after tessellation based on the tessellation parameters. The domain shader adjusts and calculates the coordinates of the new vertices. The domain shader inputs all vertices into the geometry shader, which performs addition, deletion, and modification operations on the vertices. The geometry shader is also an optional shader.

[0041] In the geometry processing pipeline of the mesh shading rendering pipeline, the magnifying shader amplifies the received rendering data to generate more rendering data. The magnifying shader is an optional shader. After obtaining all the rendering data, the mesh shader processes the rendering data of the entire mesh. The mesh shader can process the entire mesh data at once, thereby achieving large-scale geometry data generation and processing.

[0042] Figure 1 This is a schematic diagram of a geometry processing pipeline 100 provided in an exemplary embodiment of this application. Figure 1 The geometry processing pipeline 100 shown is used to implement the functions of the magnifying shader and the mesh shader. The geometry processing pipeline 100 includes a first task generation pipeline 110, a task control unit 120, a second task generation pipeline 130, and a shader execution unit 140.

[0043] The first task generation pipeline 110 generates an amplification shader thread group based on a first drawing instruction. The first drawing instruction instructs the generated thread group to implement the functionality of the amplification shader. The amplification shader thread group can also be called an amplification shader task. The amplification shader thread group is a thread group used to implement the functionality of the amplification shader. The first task generation pipeline 110 sends the amplification shader thread group to the shader execution unit 140 and sends the amplification task information corresponding to the amplification shader thread group to the task control unit 120. The amplification task information is the relevant information of the amplification shader thread group.

[0044] Shader execution unit 140 runs the amplified shader thread group to obtain amplified shading results and a second drawing instruction. The second drawing instruction indicates the number of mesh shader thread groups to be derived, and the amplified shading result characterizes the drawing result produced by the amplified shader. It is worth noting that the first drawing instruction is an instruction input by the user in the shader program, and the second drawing instruction is an instruction output by the amplified shader thread group during runtime. In this application, the first drawing instruction input by the user specifies the number of amplified shader thread groups to be generated, and the second drawing instruction output by shader execution unit 140 specifies the number of mesh shader thread groups to be generated.

[0045] The task control unit 120, based on the received amplification task information, acquires a second drawing instruction and inputs the second drawing instruction into the second task generation pipeline 130. The amplification task information includes information such as the instruction format and storage location of the second drawing instruction. The task control unit 120 can acquire the second drawing instruction according to the amplification task information. In this embodiment, an amplification shader processing pipeline is provided to implement the function of the amplification shader. The amplification shader processing pipeline includes a first task generation pipeline 110, a task control unit 120, and a shader execution unit 140.

[0046] The second task generation pipeline 130 creates a mesh shader thread group based on a second drawing instruction. This second drawing instruction instructs the generated thread group to implement the functionality of the mesh shader. The mesh shader thread group, also known as a mesh shader task, is a group of threads used to implement the mesh shader's functionality. The second task generation pipeline 130 inputs the mesh shader thread group into the shader execution unit 140 and sends the corresponding mesh task information to the task control unit 120. This mesh task information contains relevant information about the mesh shader thread group.

[0047] Shader execution unit 140 is used to run the mesh shader thread group to obtain the mesh shading result based on the magnified shading result. The mesh shading result is used to characterize the drawing result produced by the mesh shader. When running the mesh shader thread group, it is necessary to obtain the mesh shading result based on the generated magnified shading result. The generation of the mesh shading result depends on the magnified shading result.

[0048] The task control unit 120, according to the instructions in the mesh task information, acquires the mesh shading result and outputs the mesh shading result to the pipeline following the geometry processing pipeline. The mesh task information includes information such as the storage format and storage location of the mesh shading result, and the task control unit 120 can acquire the mesh shading result according to the instructions in the mesh task information. In this embodiment, a mesh shader processing pipeline is provided to implement the functions of the mesh shader. The mesh shader processing pipeline includes a second task generation pipeline 130, a task control unit 120, and a shader execution unit 140.

[0049] In one embodiment, the hardware units on the first task generation pipeline 110 and the second task generation pipeline 130 are different, meaning the two pipelines are completely independent. In another embodiment, the hardware units on the first task generation pipeline 110 and the second task generation pipeline 130 are partially the same, meaning the two generation pipelines share some hardware units.

[0050] In one embodiment, the mesh shading result output by the task control unit 120 enters the pixel processing pipeline. The pixel processing pipeline includes a rasterization stage, a pixel shader, and an output blending section. Optionally, the pixel processing pipeline can be a pixel processing pipeline using tile rendering, a tile-based pixel processing pipeline with deferred rendering, etc.; the tile-based pixel processing pipeline aims to divide the entire image into multiple small blocks (called "tiles"), and then process these tiles one by one to improve rendering efficiency and performance; the pixel processing pipeline with deferred rendering is used to separate the rendering of geometric information from lighting calculation, which can handle lighting in complex scenes more efficiently. That is, the geometry processing pipeline provided in this application is applicable to any type of pixel processing pipeline, meaning that the geometry processing pipeline provided in this application has broad applicability.

[0051] In summary, this application provides a geometry processing pipeline that supports both a magnifying shader and a mesh shader. Furthermore, it provides a resource scheduling scheme within this pipeline. In this application, the task control unit schedules the second drawing instructions output by the magnifying shader and the mesh shading results output by the mesh shader, improving the orderliness of the scheduling. Moreover, the geometry processing pipeline designed in this application is programmable, comprising a first task generation pipeline, a second task generation pipeline, a task execution unit, and a task control unit. This rich hardware configuration enhances programming flexibility and improves the overall throughput of the graphics processor.

[0052] Figure 2 This illustration shows a schematic diagram of a geometry processing pipeline 100 provided in an exemplary embodiment of this application. Figure 2 The geometry processing pipeline 100 shown is used to implement the functions of the magnifying shader and the mesh shader. The geometry processing pipeline 100 includes a first task generation pipeline 110, a task control unit 120, a second task generation pipeline 130, and a shader execution unit 140. The first task generation pipeline 110 includes a first task generation unit 111, a magnifying shader unit 112, and a shader task construction unit 113. The second task generation pipeline 130 includes a second task generation unit 131, a mesh shader unit 132, and a shader task construction unit 113.

[0053] For the first task generation pipeline 110

[0054] The first task generation unit 111 creates a first thread group based on a first drawing instruction and sends the first thread group to the magnification shader unit 112. The first thread group is the thread group specified by the first drawing instruction for implementing the function of the magnification shader. Illustratively, the first drawing instruction includes three 32-bit parameters. For example, if the first drawing instruction includes parameters (4, 3, 2), then the first task generation unit 111 will generate 4*3*2 = 24 first thread groups. The first drawing instruction specifies that the generated 24 first thread groups are used to implement the function of the magnification shader. Optionally, each first thread group includes at least two threads. Optionally, each of the at least two threads is used to process one or more meshes. A mesh refers to the geometric structure of a 3D model, typically composed of vertices, edges, and faces; or, multiple threads in the at least two threads are used together to process one or more meshes. This application does not limit this.

[0055] The amplification shading unit 112 adds first resource requirement information to the first thread group to obtain a second thread group; the second thread group is then sent to the shader task construction unit 113. The first resource requirement information refers to the resources required to run the amplification shader thread group. Optionally, the first resource requirement information includes the storage location of the second drawing instructions, the instruction format, the storage format of the amplification shading results, the storage location of the amplification shading results, the address of the temporary storage space used when running the amplification shader thread group, the address of the result storage space, and other resource request information. Optionally, the first resource requirement information includes mesh load packet request information, where the mesh load packet is a load packet used to hold the amplification shading results.

[0056] The shader task construction unit 113 allocates resources to the second thread group based on the first resource requirement information, and uses the resource-allocated second thread group as the amplified shader thread group. The shader task construction unit 113 then sends the amplified shader thread group to the shader execution unit 140. The shader task construction unit 113 also sends the amplified task information corresponding to the amplified shader thread group to the task control unit 120; the amplified task information is the resource information allocated by the shader task construction unit 113 to the second thread group.

[0057] For the second task generation pipeline 130

[0058] The second task generation unit 131 is used to create a third thread group based on the second drawing instruction and send the third thread group to the mesh shading unit. The third thread group is the thread group specified by the second drawing instruction for implementing the function of the mesh shader. Illustratively, the second drawing instruction includes three 32-bit parameters. For example, if the second drawing instruction includes parameters (6, 3, 2), then the second task generation unit 131 will generate 6 * 3 * 2 = 36 third thread groups. The second drawing instruction specifies that the generated 36 third thread groups are used to implement the function of the mesh shader. Optionally, each third thread group includes at least two threads. Optionally, each of the at least two threads is used to process one or more meshes, or multiple threads in the at least two threads are used together to process one or more meshes; this application does not limit this.

[0059] Mesh shading unit 132 is used to add second resource requirement information to the third thread group to obtain a fourth thread group; and send the fourth thread group to shader task construction unit 113. The second resource requirement information refers to the resources required to run the first thread group. Optionally, the second resource requirement information includes resource request information such as the storage format of the mesh shading result, the storage location of the mesh shading result, the address of the temporary storage space used when running the mesh shader thread group, and the address of the result storage space.

[0060] The shader task construction unit 113 is used to allocate resources to the fourth thread group based on the second resource requirement information, and to designate the resource-allocated fourth thread group as the mesh shader thread group. The shader task construction unit 113 sends the mesh shader thread group to the shader execution unit 140. The shader task construction unit 113 also sends the mesh task information corresponding to the mesh shader thread group to the task control unit 120; the mesh task information is the information about the resources allocated by the shader task construction unit 113 to the fourth thread group.

[0061] In the above embodiments, the first task generation pipeline 110 and the second task generation pipeline 130 each have their own task generation unit and a shading unit for requesting resources, as well as a shared shader task construction unit 113. The sharing of the shader task construction unit 113 saves hardware usage and reduces the hardware density on the graphics processor. Furthermore, in addition to allocating resources to the thread group, the shader task construction unit 113 also sends resource information, i.e., task information, to the task control unit 120, facilitating the task control unit 120 to perform scheduling using the task information. That is, this application provides a method for generating task information, allowing the task control unit 120 to better schedule the second drawing instructions and mesh shading results using the task information. Moreover, each task generation pipeline provided in this application has its own task generation unit and a shading unit for requesting resources. The task generation unit and the shading unit for requesting resources are programmable hardware, meaning that the abundant hardware units in this application improve programming flexibility.

[0062] Figure 3 A schematic diagram of a geometry processing pipeline 100 provided in another exemplary embodiment of this application is shown. Figure 3 The geometry processing pipeline 100 shown implements the functions of an amplification shader and a mesh shader. The geometry processing pipeline 100 includes an amplification shader processing pipeline, a task control unit 120, and a mesh shader processing pipeline. The amplification shader processing pipeline includes a first task generation pipeline 110, a shader execution unit 140, a result storage unit 150, and a temporary storage unit 160. The first task generation pipeline 110 includes a first task generation unit 111, an amplification shader unit 112, and a shader task construction unit 113.

[0063] The mesh shader processing pipeline includes a second task generation pipeline 130, a shader execution unit 140, a result storage unit 150, and a temporary storage unit 160. The second task generation pipeline 130 includes a second task generation unit 131, a mesh shading unit 132, and a shader task construction unit 113.

[0064] For amplification shader processing pipelines

[0065] The relevant descriptions of the first task generation pipeline 110 and the shader execution unit 140 can be found above, and will not be repeated here.

[0066] The result storage unit 150 is used to store at least one of the magnified shading result output by the shader execution unit 140 and the second drawing instruction. Optionally, the result storage unit 150 is used to store the second drawing instruction, and the task control unit 120 retrieves the second drawing instruction from the result storage unit 150 according to the indication of the magnification task information, and sends the second drawing instruction to the second task generation unit 131.

[0067] Temporary storage unit 160 is used to temporarily store data read and written by shader execution unit 140 when executing the amplified shader thread group. Optionally, temporary storage unit 160 is used to store the amplified shading results output by shader execution unit 140. Optionally, temporary storage unit 160 is on-chip storage space of graphics processor. Optionally, temporary storage unit 160 can also be off-chip storage space of graphics processor. In one embodiment, the mesh payload allocated by shader task construction unit 113 is located in temporary storage unit 160. The mesh payload is a temporary payload used to contain the amplified shading results output by shader execution unit 140. When shader execution unit 140 runs the mesh shader thread group, it obtains the amplified shading results from temporary storage unit 160. Shader execution unit 140 relies on the amplified shading results when generating mesh shading results by running mesh shader thread group.

[0068] For mesh shader processing pipeline

[0069] The relevant descriptions of the second task generation pipeline 130 and the shader execution unit 140 can be found above, and will not be repeated here.

[0070] The result storage unit 150 is used to store the mesh shading results output by the shader execution unit 140. The task control unit 120 retrieves the mesh shading results from the result storage unit 150 according to the instructions of the mesh task information, and outputs the mesh shading results to the pipeline after the geometry processing pipeline 100.

[0071] Temporary storage unit 160 is used to temporarily store data read and written by the shader execution unit 140 when executing the mesh shader thread group. Optionally, temporary storage unit 160 is on-chip storage space of the graphics processor. Optionally, temporary storage unit 160 can also be off-chip storage space of the graphics processor.

[0072] In this embodiment, the amplification shader processing pipeline and the mesh shader processing pipeline share the result storage unit 150 and the temporary storage unit 160. Sharing the result storage unit 150 and the temporary storage unit 160 saves hardware usage and reduces the hardware density on the graphics processor. Furthermore, this application divides the hardware into the result storage unit 150 and the temporary storage unit 160 to better serve the shader execution unit 140. The temporary storage unit 160 stores intermediate data output by the shader execution unit 140, and the result storage unit 150 stores the result data output by the shader execution unit 140.

[0073] In this embodiment, the mesh payload is a temporary payload allocated by the first task generation pipeline 110, specifically, a temporary payload allocated by the shader task construction unit 113. The mesh payload is used to hold the amplified shading results. Since the mesh payload is a temporary payload, it needs to be released promptly after the amplified shading results are used to avoid the accumulation of mesh payloads and the occupation of storage space.

[0074] In one embodiment, the second task generation pipeline 130 is further configured to add an end flag to the last mesh task information corresponding to the last mesh shader thread group, and the task control unit 120 clears the mesh load packet when the end flag is detected.

[0075] The task control unit 120 detects the end flag, indicating that the shader execution unit 140 has run to the last mesh shader thread group. When the last mesh shader thread group finishes running, it means that the amplified shading results have been used up, and then the mesh load pack can be released and the amplified shading results can be cleared.

[0076] In one embodiment, based on Figure 2 The geometry processing pipeline 100 shown includes a second task generation pipeline 130 comprising a second task generation unit 131, a mesh shading unit 132, and a shader task construction unit 113. The second task generation unit 131 adds an end flag (Lsat flag) to the last group of third threads; the mesh shading unit 132 transmits the end flag, and the shader task construction unit 113 adds an end flag to the last mesh task information corresponding to the last group of third threads. The task control unit 120 clears the mesh payload upon detecting the end flag.

[0077] It is understandable that the second drawing instruction sent by the task control unit 120 to the second task generation unit 131 contains the number of mesh shader thread groups to be generated. Therefore, the second task generation unit 131 can know which group of third thread groups is the last group of third thread groups. Thus, the second task generation unit 131 can add an end marker to the last group of third thread groups.

[0078] In this application, an end flag is added to the last mesh shader thread group. When the task control unit 120 detects the end flag, it can promptly control the release of the mesh load packet. Compared to the related technologies that use reference counting to release the amplified shading result, this method is simpler to operate and less prone to errors. Related technologies use reference counting to manage the output of the amplified shader (i.e., the amplified shading result). These technologies require additional storage space to store a reference counter, which records the number of times the amplified shading result is referenced. An atomic instruction is used to subtract this reference count, and the mesh load packet is released when the subtraction result is zero. The hardware design of these related technologies is relatively complex. In contrast, this application can directly add an end flag to the data stream without storing a reference counter, resulting in a simpler overall hardware design.

[0079] Figure 4 This application illustrates a geometry processing pipeline 100 provided in an exemplary embodiment. Figure 4 The geometry processing pipeline 100 is used to implement the functions of the mesh shader. The geometry processing pipeline 100 includes a third task generation pipeline 410, a task control unit 120, and a shader execution unit 140.

[0080] The third task generation pipeline 410 creates mesh shader thread groups based on third drawing instructions. These third drawing instructions specify the number of mesh shader thread groups to be generated, each also referred to as a mesh shader task. The third task generation pipeline 410 inputs the mesh shader thread groups into the shader execution unit 140 and sends the corresponding mesh task information to the task control unit 120. This mesh task information contains relevant information about the mesh shader thread groups. Optionally, the third drawing instructions are instructions entered by the user into the shader program.

[0081] Shader execution unit 140 is used to run the mesh shader thread group to obtain the mesh shading result.

[0082] The task control unit 120, according to the instructions in the mesh task information, acquires the mesh shading result and outputs the mesh shading result to the pipeline following the geometry processing pipeline. The mesh task information contains information such as the storage format and storage location of the mesh shading result, and the task control unit 120 can acquire the mesh shading result according to the instructions in the mesh task information.

[0083] In one embodiment, the mesh shading result output by the task control unit 120 enters the pixel processing pipeline. The pixel processing pipeline includes a rasterization stage, a pixel shader, and an output blending section. Optionally, the pixel processing pipeline can be a pixel processing pipeline using tile rendering, a tile-based pixel processing pipeline with deferred rendering, etc., that is, the geometry processing pipeline provided in this application is applicable to any type of pixel processing pipeline, meaning that the geometry processing pipeline provided in this application has broad applicability.

[0084] In summary, this application provides a geometry processing pipeline that supports mesh shaders. Furthermore, it provides a resource scheduling scheme within this pipeline. In this application, the mesh shading results output by the mesh shader are scheduled by the task control unit, improving the orderliness of the scheduling. Moreover, the geometry processing pipeline designed in this application is programmable, containing a third task generation pipeline, a task execution unit, and a task control unit. This rich hardware configuration enhances programming flexibility and improves the overall throughput of the graphics processor.

[0085] Furthermore, in comparison Figure 1 and Figure 4 The geometry processing pipeline shown can be seen to support two modes simultaneously: mesh shader only, magnified shader, and mesh shader. The shader execution unit 140 and task control unit 120 in this application can support both modes simultaneously.

[0086] Figure 5 This application illustrates a geometry processing pipeline provided in an exemplary embodiment. Figure 5 The geometry processing pipeline 100 shown is used to implement the functions of a mesh shader. The geometry processing pipeline 100 includes a third task generation pipeline 410, a task control unit 120, and a shader execution unit 140. The third task generation pipeline 410 includes a first task generation unit 111, an amplified shading unit 112, a second task generation unit 131, a mesh shading unit 132, and a shader task construction unit 113.

[0087] The first task generation unit 111 is used to create a fifth thread group based on the third drawing instruction and send the fifth thread group to the amplification shading unit 112. The fifth thread group is the thread group specified by the third drawing instruction to implement the function of the mesh shader. Illustratively, the third drawing instruction includes three 32-bit parameters. For example, if the third drawing instruction includes parameters (6, 3, 2), then the first task generation unit 111 will generate 6 * 3 * 2 = 36 fifth thread groups. The third drawing instruction specifies that the generated 36 fifth thread groups are used to implement the function of the mesh shader. Optionally, each fifth thread group includes at least two threads. Optionally, each of the at least two threads is used to process one or more meshes. A mesh refers to the geometric structure of a 3D model, usually composed of vertices, edges, and faces; or, multiple threads in the at least two threads are used together to process one or more meshes. This application does not limit this.

[0088] The amplified coloring unit 112 is used to pass through the fifth thread group to the second task generation unit 131;

[0089] The second task generation unit 131 is used to pass the fifth thread group to the mesh coloring unit 132.

[0090] Mesh shading unit 132 is used to add third resource requirement information to the fifth thread group to obtain a sixth thread group; and send the sixth thread group to shader task construction unit 113; the third resource requirement information refers to the resources required to run the fifth thread group. Optionally, the third resource requirement information includes the storage format of the mesh shading result, the storage location of the mesh shading result, the address of the temporary storage space used when running the mesh shader thread group, the address of the result storage space, and other resource request information.

[0091] The shader task construction unit 113 is used to allocate resources to the sixth thread group based on the third resource requirement information, and to use the resource-allocated sixth thread group as the mesh shader thread group. The shader task construction unit 113 sends the mesh task information corresponding to the mesh shader thread group to the task control unit 120. The mesh task information is the information of the resources allocated by the shader task construction unit 113 to the sixth thread group.

[0092] In the above embodiments, comparison Figure 2 and Figure 5 The geometry processing pipeline shown can be seen to support two modes simultaneously: mesh shader only, magnifying shader, and mesh shader. The first task generation unit 111, magnifying shader unit 112, second task generation unit 131, and mesh shader unit 132 in this application can support both modes simultaneously.

[0093] Figure 6This application illustrates a geometry processing pipeline provided in an exemplary embodiment. Figure 6 The geometry processing pipeline 100 shown is used to implement the function of a mesh shader. The geometry processing pipeline 100 includes a first task generation unit 111, an amplified shading unit 112, a second task generation unit 131, a mesh shading unit 132, a shader task construction unit 113, a task control unit 120, a shader execution unit 140, a result storage unit 150, and a temporary storage unit 160.

[0094] The result storage unit 150 is used to store the mesh shading results output by the shader execution unit 140. The temporary storage unit 160 is used to temporarily store data read and written by the shader execution unit 140 when executing the mesh shader thread group. Other details have been described above and will not be repeated here.

[0095] In the above embodiments, comparison Figure 3 and Figure 6 The illustrated geometry processing pipeline shows that the pipeline provided in this application can simultaneously support two modes: mesh shader only, magnifying shader, and mesh shader. The result storage unit 150 and temporary storage unit 160 in this application can simultaneously support both modes. Furthermore, this application divides the hardware into the result storage unit 150 and the temporary storage unit 160 to better serve the shader execution unit 140. The temporary storage unit 160 is used to store intermediate data output by the shader execution unit 140, and the result storage unit 150 is used to store the result data output by the shader execution unit 140.

[0096] In one embodiment, for both the mesh shader-only and mesh shader-plus-mesh-shader modes, the stored mesh shading results can have the same or different formats. In either of these modes, the layout of the mesh shading results corresponding to at least one mode can be as follows.

[0097] In the following text, the mesh coloring result is also referred to as the drawing result.

[0098] The drawing results (meshlet) include metadata for various primitive types. For example... Figure 7 As shown, Figure 7A schematic diagram of the drawing result is shown. The drawing result includes a vertex data area 710 and a graph data area 720. The vertex data area 710 includes vertex attributes of a plurality of vertices, which may include zero vertices, one vertex, or multiple vertices (at least two vertices). The graph data area 720 includes a plurality of graph data blocks 721, which correspond one-to-one with a plurality of primitives. Each graph data block 721 is used to store the primitive attributes of the current primitive. Or, the i-th graph data block 721 is used to store the primitive attributes of the i-th primitive. In one embodiment, graph data blocks indicating the same primitive type in the plurality of graph data blocks will be grouped together. For example, in the plurality of graph data blocks, the first graph data block is used to store point type graph data, the middle graph data block is used to store line type graph data, and the last graph data block is used to store triangle type graph data.

[0099] In one embodiment, the vertex data area 710 and the graph data area 720 are concatenated. In this case, the data format of the drawing result can be fully expressed using three parameters: the base address, the size of the vertex data area 710, and the size of the graph data area 720. The base address refers to the starting address of the vertex data area 710. When an external component wants to access the drawing result, it only needs these three parameters to access the target data. For example, when accessing the vertex data area 710, it only needs to start accessing from the base address; when accessing the graph data area 720, it only needs to start accessing from the base address plus the size of the vertex data area 710.

[0100] In another embodiment, the graph data area 720 may also be located before the vertex data area 710.

[0101] In one embodiment, such as Figure 8 As shown, the graph data area 720 includes multiple data blocks 721 and a quantity indicator segment 722. The quantity indicator segment 722 is used to indicate the quantity of several vertices in the vertex data area 710 and the quantity of multiple primitives in the graph data area 720. Optionally, the quantity indicator segment 722 is located at the end of the graph data area 720. In this case, if an external component wants to access the quantity indicator segment 722, it only needs to add the size of the vertex data area 710 and the size of the graph data area 720 to the base address, and then subtract the size of the quantity indicator segment 722 (which is a fixed value, optionally 32 bits).

[0102] Optionally, the quantity indicator segment 722 can also be located in the header of the vertex data area 710. In this case, if an external component wants to access the quantity indicator segment 722, it only needs to access it starting from the base address; if an external component wants to access the vertex attribute part in the vertex data area 710, it only needs to add the size of the quantity indicator segment 722 (which is a fixed value, optionally 32 bits) to the base address.

[0103] Optionally, the quantity indicator segment 722 can also be located at the head of the graph data area 720. In this case, if an external component wants to access the quantity indicator segment 722, it only needs to start accessing from the base address plus the size of the vertex data area 710. If an external component wants to access the primitive attribute part in the graph data area 720, it only needs to add the base address plus the size of the vertex data area 710 plus the size of the quantity indicator segment 722 (which is a fixed value, optionally 32 bits).

[0104] In one embodiment, each graph data block includes the index value of the vertices that make up the current graph element in the vertex data area 710, the graph element type of the current graph element (including any one of point, line, and triangle), whether it supports specifying the point size, fill mode, etc., which will be described in detail below.

[0105] In related technologies, definitions of meshlets output by mesh shaders are provided. However, these definitions are complex, involving as many as four data segments, which complicates meshlet allocation and access. This application provides a two-segment layout for rendering results, which is simpler. With only two segments, hardware allocation of resources for the rendering results is straightforward. Furthermore, the entire layout can be fully expressed using only the three parameters mentioned above (base address, vertex data area size, and graph data area size), simplifying hardware access to the rendering results.

[0106] Image data block

[0107] Based on the above introduction, the graph data area contains multiple graph data blocks, each graph data block corresponds to a graph element, and each graph data block is used to contain the graph element attributes of a graph element.

[0108] Figure 9This illustration shows a schematic diagram of a map data block provided in an exemplary embodiment of this application. The map data block includes a topology attribute segment and multiple other attribute segments (attribute segment 0, attribute segment 1 to attribute segment N). The topology attribute segment includes a first index segment, a second index segment, a third index segment, and an additional attribute segment. In one embodiment, the topology attribute segment and any one of the multiple other attribute segments are of the same size, for example, all 32 bits. Optionally, the first index segment, the second index segment, the third index segment, and the additional attribute segment are all of the same size, for example, all 8 bits.

[0109] In one embodiment, the additional attribute segment includes a type segment that holds the type identifier of the current primitive. The additional attribute segment also includes an indication segment for other topological information, which will be described below.

[0110] When the primitive type corresponding to the primitive data block is a point, the first index segment is used to store the index value of the first vertex of the current primitive in the vertex data area, and the type segment is used to store the point's type identifier. Optionally, the first index segment contains 8 bits. In this case, the first index segment can index 256 vertices. For the current DirectX and Vulkan specifications, using 8 bits to represent each index value is sufficient. At this time, the values ​​in the second and third index segments are invalid. Optionally, the point's type identifier can be stored using 2 bits, for example, using 0 and 1 to identify the point type.

[0111] When the primitive type corresponding to the primitive data block is line, the first and second index segments of the three index segments are used to store the index values ​​of the first and second vertices of the current primitive in the vertex data area, respectively. The type segment is used to store the line type identifier. Optionally, both the first and second index segments contain 8 bits. In this case, each of the two index segments can index 256 vertices, and the value on the third index segment is invalid. Optionally, the line type identifier can be stored using 2 bits, for example, using 10 bits to identify the line type.

[0112] When the primitive type corresponding to the primitive data block is triangle, the first, second, and third index segments of the three index segments are used to store the index values ​​of the first, second, and third vertices of the current primitive in the vertex data area, respectively. The type segment is used to store the triangle type identifier. Optionally, the first, second, and third index segments each contain 8 bits, in which case each of the three index segments can index 256 vertices. Optionally, the triangle type identifier can be stored in 2 bits, for example, using 11 to identify the triangle type.

[0113] It should be noted that the above example uses 8 bits per index segment. In practice, when expansion is needed to indicate more vertices, the 32-bit topological attribute segment can be divided into three 10-bit index segments, with the additional two bits used to hold the type identifier. In this case, each index segment can index 1024 vertices. Furthermore, if 1024 vertices are still insufficient to exhaust all vertices in the vertex index area, the next other attribute segment can be used (i.e.,...). Figure 9 Attribute segment 0), or the next two other attribute segments (i.e. Figure 9 The attribute segments are divided into 0 and 1, and each attribute segment is 32 bits in size. In this case, the first two or the first three 32 bits will be used to represent the topology of the primitive.

[0114] In summary, each primitive data block includes a type segment, which allows the user to specify the primitive type to be output in the shader program; and each primitive data block includes three index segments, which allow the user to specify the vertex index values ​​to be output in the shader program.

[0115] Additional attribute segmentation

[0116] Based on the above description, each graphic data block contains a topology attribute segment, which includes one additional attribute segment and three index segments. The additional attribute segment contains at least one of the following: a type segment (indicating the type of the current graphic element), a first indicator segment (indicating whether a specified point size is supported), and a second indicator segment (indicating the fill mode of the current graphic element). The fill mode includes any one of point fill, line fill, and solid fill. This application does not limit the distribution of the type segment, the first indicator segment, and the second indicator segment in the additional attribute segment; one possible distribution will be described below.

[0117] like Figure 10 As shown, Figure 10 A schematic diagram of an additional attribute segment is shown, in which the type segment, the second indicator segment, and the first indicator segment are concatenated in ascending order of bit position. In one embodiment, the size of the additional attribute segment is 8 bits. The type segment includes the first two bits from right to left, i.e., bits [0:1]. In this case, two bits can encode the three primitive types: point, line, and triangle. The second indicator segment includes bits [2:4]. Three bits can encode the fill mode of the current primitive. For example, bit [2] indicates whether it is a point fill, bit [3] indicates whether it is a line fill, and bit [4] indicates whether it is a solid fill. The first indicator segment includes bit [5]. A value of 0 on bit [5] indicates that the current primitive does not support the specified point size, and a value of 1 indicates that the current primitive supports the specified point size.

[0118] For the first indicator segment, if the first indicator segment indicates that the current graphic element supports the size of the specified point, then Figure 6 Among the multiple other attribute segments shown, one attribute segment is used to indicate the size of a point. For example, the first other attribute segment after the topology attribute segment is used to store the point size. In one embodiment, if the current primitive type is a point, the first indicator segment indicates that the current primitive supports a specified point size. The point size refers to the number of pixels occupied by vertices on the primitive; for example, a vertex occupies 30 pixels.

[0119] For the second indicator segment, if the current element type is a point, the second indicator segment will specify the fill mode of the current element within the range including point fill mode; if the current element type is a line, the second indicator segment will specify the fill mode of the current element within the range including point fill mode and line fill mode; if the current element type is a triangle, the second indicator segment will specify the fill mode of the current element within the range including point fill mode, line fill mode and solid fill mode.

[0120] In summary, the additional attribute segment includes a first indicator segment, which allows the user to specify the output point size on the shader program; and the additional attribute segment includes a second indicator segment, which allows the user to specify the output fill mode on the shader program.

[0121] Quantity indicator segmentation

[0122] Based on the above introduction, there are quantity indicator segments within the graph data data area. These segments indicate the quantity of several vertices in the vertex data area and the quantity of multiple primitives in the graph data data area. The quantity indicator segments include vertex quantity segments and primitive quantity segments. This application does not limit the distribution of the vertex quantity segments and primitive quantity segments within the quantity indicator segments; one distribution will be described below.

[0123] like Figure 11 As shown, the primitive count segment and vertex count segment in the quantity indicator segment are concatenated from low to high bits. In one embodiment, the quantity indicator segment contains 32 bits, where the high 16 bits are used to express the number of vertices in the vertex data area and the low 16 bits are used to express the number of primitives in the primitive data area. According to the DirectX and Vulkan specifications, both actually only require 8 bits.

[0124] In one embodiment, the primitive count segment and the vertex count segment are concatenated from low to high bit order, where the high 16 bits represent the number of vertices in the vertex data area and the low 16 bits represent the number of primitives in the primitive data area. In another embodiment, the vertex count segment and the primitive count segment are concatenated from low to high bit order, where the high 16 bits represent the number of primitives in the primitive data area and the low 16 bits represent the number of vertices in the vertex data area.

[0125] In another embodiment, the high 8 bits of the lower 16 bits are used to express the number of vertices in the vertex data area, and the low 8 bits are used to express the number of vertices in the graph data area. The reverse is also true.

[0126] In another embodiment, the high 8 bits of the high 16 bits are used to express the number of vertices in the vertex data area, and the low 8 bits are used to express the number of vertices in the graph data area. The reverse is also true.

[0127] In summary, the segmentation of quantity indicators makes it easier for the hardware to obtain the number of vertices and primitives.

[0128] Figure 12 The flowchart illustrates the method for resolving and rendering results in the rasterization stage, which is a pipeline following the geometry processing pipeline. The rasterization stage will proceed according to... Figure 12 The method shown parses the drawing results. Figure 12 The method for resolving and rendering results during the rasterization stage, as shown, includes the following steps:

[0129] Step 1201: Calculate the starting position of the quantity indicator segment based on the base address, the size of the vertex data area and the graph data area;

[0130] The task control unit sends relevant information about the rendering results to the rasterization stage. This information includes the base address. The rasterization stage can calculate the starting position of the quantity indicator segment 722 based on the base address, the fixed size of the vertex data area 710, and the fixed size of the graph data area 720.

[0131] Step 1202: Obtain the quantity indication segment from the result storage unit;

[0132] In the above embodiment, the drawing result is stored in the result storage unit 150, and the rasterization stage will obtain the quantity indicator segment 722 from the result storage unit 150 according to the starting address of the quantity indicator segment 722.

[0133] Step 1203: Calculate the starting position of the graph data area based on the base address and the size of the vertex data area;

[0134] The rasterization stage can calculate the starting position of the image data area 720 based on the base address and the size of the fixed vertex data area 710.

[0135] Step 1204: Access each data block of the image data in sequence according to the size and number of image elements;

[0136] The rasterization stage can access each map data block in the map data area 720 sequentially based on the fixed size of the map data block and the number of map elements known from the quantity indicator segment 722.

[0137] Step 1205: Obtain the topological attribute segments in the graph data block;

[0138] For each graph data block, the rasterization stage obtains the first attribute segment in each graph data block, and the first attribute segment in each graph data block is fixed as the topology attribute segment.

[0139] Step 1206: Based on the topological attributes, segment the graph and access the vertices that constitute the current primitive.

[0140] Each primitive's topology attribute segment contains three index segments: the first index segment, the second index segment, and the third index segment. Each index segment corresponds to a vertex. During the rasterization stage, the vertex data constituting the current primitive can be accessed in the vertex data area 710 based on the three index segments.

[0141] In the above embodiments, a process for parsing mesh shading results (drawing results) in the rasterization stage is provided. The rasterization stage will further perform related operations based on the parsed mesh shading results. Through the geometric processing pipeline and the layout structure of the mesh shading results provided in this application, the rasterization stage can accurately and orderly parse the mesh shading results, and the parsing process is less prone to errors.

[0142] Figure 13 A structural block diagram of an electronic device 1300 provided in an exemplary embodiment of this application is shown. Optionally, the electronic device 1300 includes a graphics processor provided in an embodiment of this application.

[0143] Optionally, the electronic device can be a portable mobile terminal, such as a smartphone, tablet, MP3 player (Moving Picture Experts Group Audio Layer III), MP4 player (Moving Picture Experts Group Audio Layer IV), laptop, or desktop computer. The electronic device 1300 may also be referred to as a user device, portable terminal, laptop terminal, desktop terminal, or other names. Typically, the electronic device 1300 includes a processor 1301 and a memory 1302.

[0144] Processor 1301 may include one or more processing cores, such as a 4-core processor, a 13-core processor, etc. Processor 1301 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). Processor 1301 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 1301 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content required to be displayed on the screen. In some embodiments, processor 1301 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0145] The memory 1302 may include one or more computer-readable storage media, which may be non-transitory. The memory 1302 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices.

[0146] In some embodiments, the electronic device 1300 may optionally include: a peripheral device interface 1303 and at least one peripheral device. Those skilled in the art will understand that... Figure 13The structure shown does not constitute a limitation on the electronic device 1300, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0147] This application also provides a chip that includes a graphics processor as described in the embodiments above.

[0148] This application also provides a graphics card that includes a graphics processor as described in the embodiments above.

[0149] This application also provides a server that includes a graphics processor as described in the embodiments above.

[0150] Figure 14 The diagram illustrates the structure of a server provided in an exemplary embodiment of this application. The server 1400 includes a plurality of graphics processors 1401, and at least one of the graphics processors 1401 includes the graphics processor described in the above-described embodiments of this application.

[0151] This application also provides a computing cluster, which includes multiple servers, at least one of which includes a graphics processor as described in the above embodiments.

Claims

1. A graphics processor, characterized in that, The graphics processor includes a geometry processing pipeline for implementing the functions of an amplification shader and a mesh shader; the geometry processing pipeline includes a first task generation pipeline, a second task generation pipeline, a shader execution unit, and a task control unit; The first task generation pipeline is used to create an amplification shader thread group based on a first drawing instruction; the shader execution unit is used to run the amplification shader thread group to obtain the amplification shading result and the second drawing instruction. The task control unit is used to input the second drawing instruction into the second task generation pipeline; The second task generation pipeline is used to create a mesh shader thread group based on the second drawing instruction; The shader execution unit is used to run the mesh shader thread group and obtain the mesh shading result based on the amplified shading result; the task control unit is used to output the mesh shading result to the pipeline after the geometry processing pipeline; The task control unit is further configured to clear the mesh load packet when an end flag corresponding to the last mesh task information of the last mesh shader thread group is detected. The mesh load packet is used to contain the amplified shader result output by the shader execution unit.

2. The graphics processor according to claim 1, characterized in that, The first task generation pipeline includes a first task generation unit, an amplified shading unit, and a shader task construction unit; The first task generation unit is configured to create a first thread group based on the first drawing instruction and send the first thread group to the magnification shader unit. The first thread group is a thread group specified by the first drawing instruction for implementing the function of the magnification shader. The amplified shader unit is used to add first resource requirement information to the first thread group to obtain a second thread group; and send the second thread group to the shader task construction unit. The shader task construction unit is used to allocate resources to the second thread group based on the first resource requirement information, and to use the second thread group after resource allocation as the amplified shader thread group.

3. The graphics processor according to claim 1, characterized in that, The second task generation pipeline includes a second task generation unit, a mesh shading unit, and a shader task construction unit; The second task generation unit is used to create a third thread group based on the second drawing instruction, and send the third thread group to the mesh shading unit. The third thread group is a thread group specified by the second drawing instruction for implementing the function of the mesh shader. The mesh shading unit is used to add second resource requirement information to the third thread group to obtain a fourth thread group; and send the fourth thread group to the shader task construction unit. The shader task construction unit is used to allocate resources to the fourth thread group based on the second resource requirement information, and to use the resource-allocated fourth thread group as the mesh shader thread group.

4. The graphics processor according to any one of claims 1 to 3, characterized in that, The geometry processing pipeline also includes a result storage unit; The result storage unit is used to store at least one of the magnified shading result, the second drawing instruction, and the mesh shading result output by the shader execution unit.

5. The graphics processor according to any one of claims 1 to 3, characterized in that, The geometry processing pipeline also includes a temporary storage unit; The temporary storage unit is used to temporarily store the data read and written by the shader execution unit when executing the amplified shader thread group and the mesh shader thread group.

6. The graphics processor according to claim 5, characterized in that, The temporary storage unit is used to store the amplified shading result output by the shader execution unit.

7. The graphics processor according to any one of claims 1 to 3, characterized in that, The second task generation pipeline is also used to add the end flag to the last mesh task information corresponding to the last mesh shader thread group; The grid load pack is a temporary load pack allocated by the first task generation pipeline.

8. The graphics processor according to claim 3, characterized in that, The third thread group consists of multiple groups, and the mesh task information is the resource information allocated by the shader task construction unit to the fourth thread group; The second task generation unit is used to add an end flag to the last group of third threads; The shader task construction unit is used to add the end flag to the last mesh task information corresponding to the last group of the third thread group. The task control unit is further configured to clear the mesh load packet upon detecting the end flag. The mesh load packet is a temporary load packet allocated by the shader task construction unit and is used to contain the amplified shading result output by the shader execution unit.

9. The graphics processor according to any one of claims 1 to 3, characterized in that, The mesh coloring result includes a vertex data area and a graph data area; The vertex data area includes the vertex attributes of several vertices; The graph data area includes multiple graph data blocks, each graph data block corresponding to a multiple graph element. Each graph data block includes the graph element attributes of the current graph element.

10. The graphics processor according to claim 9, characterized in that, Each graph data block includes a topology attribute segment and multiple other attribute segments; The topology attribute segment includes three index segments; the three index segments are used to accommodate the index values ​​of the vertices of the current primitive in the vertex data area.

11. The graphics processor according to claim 9, characterized in that, The graph data area further includes a quantity indicator segment, which is used to indicate the number of vertices in the vertex data area and the number of primitives in the graph data area.

12. A graphics processor, characterized in that, The graphics processor includes a geometry processing pipeline for implementing the functions of a mesh shader; the geometry processing pipeline includes a third task generation pipeline, a shader execution unit, and a task control unit; The third task generation pipeline is used to create a mesh shader thread group based on the third drawing instruction; input the mesh shader thread group into the shader execution unit; and send the mesh task information corresponding to the mesh shader thread group to the task control unit. The shader execution unit is used to run the mesh shader thread group to obtain the mesh shader result; The task control unit is configured to obtain the mesh shading result according to the instruction of the mesh task information, and output the mesh shading result to the pipeline after the geometry processing pipeline; The task control unit is further configured to clear the mesh load packet when an end flag corresponding to the last mesh task information of the last mesh shader thread group is detected. The mesh load packet is used to contain the amplified shader result output by the shader execution unit.

13. The graphics processor according to claim 12, characterized in that, The third task generation pipeline also includes a first task generation unit, an amplified shading unit, a second task generation unit, a mesh shading unit, and a shader task construction unit; The first task generation unit is used to create a fifth thread group based on the third drawing instruction and send the fifth thread group to the magnification shading unit. The fifth thread group is a thread group specified by the third drawing instruction to implement the function of the mesh shader. The amplification and coloring unit is used to pass the fifth thread group to the second task generation unit; The second task generation unit is used to pass the fifth thread group to the mesh coloring unit; The mesh coloring unit is used to add third resource requirement information to the fifth thread group to obtain the sixth thread group; The sixth thread group is sent to the shader task construction unit; The shader task construction unit is used to allocate resources to the sixth thread group based on the third resource requirement information, and to use the resource-allocated sixth thread group as the mesh shader thread group.

14. The graphics processor according to claim 12 or 13, characterized in that, The geometry processing pipeline also includes a result storage unit; the result storage unit is used to store the mesh shading result output by the shader execution unit.

15. The graphics processor according to claim 12 or 13, characterized in that, The geometry processing pipeline also includes a temporary storage unit; the temporary storage unit is used to temporarily store data read and written by the shader execution unit when executing the mesh shader thread group.

16. The graphics processor according to claim 12 or 13, characterized in that, The mesh coloring result includes a vertex data area and a graph data area; The vertex data area includes the vertex attributes of several vertices; The graph data area includes multiple graph data blocks, each graph data block corresponding to a multiple graph element. Each graph data block includes the graph element attributes of the current graph element.

17. The graphics processor according to claim 16, characterized in that, Each graph data block includes a topology attribute segment and multiple other attribute segments; The topology attribute segment includes three index segments; the three index segments are used to accommodate the index values ​​of the vertices of the current primitive in the vertex data area.

18. The graphics processor according to claim 16, characterized in that, The graph data area further includes a quantity indicator segment, which is used to indicate the number of vertices in the vertex data area and the number of primitives in the graph data area.

19. A method for drawing graphics, characterized in that, The method is applied to a graphics processing unit (GPU), which includes a geometry processing pipeline for implementing the functions of an amplification shader and a mesh shader. The geometry processing pipeline includes a first task generation pipeline, a second task generation pipeline, a shader execution unit, and a task control unit. The method includes: The first task generation pipeline creates an amplification shader thread group based on a first drawing instruction; the shader execution unit runs the amplification shader thread group to obtain an amplification shading result and a second drawing instruction; the task control unit inputs the second drawing instruction into the second task generation pipeline. The second task generation pipeline creates a mesh shader thread group based on the second drawing instruction; the shader execution unit runs the mesh shader thread group and obtains a mesh shading result based on the magnified shading result; the task control unit outputs the mesh shading result to the pipeline after the geometry processing pipeline; the task control unit is also used to clear the mesh payload bag when the end flag corresponding to the last mesh task information corresponding to the last mesh shader thread group is detected, the mesh payload bag being used to contain the magnified shading result output by the shader execution unit.

20. A method for drawing graphics, characterized in that, The method is applied to a graphics processing unit (GPU), which includes a geometry processing pipeline for implementing the functionality of a mesh shader. The geometry processing pipeline includes a third task generation pipeline, a shader execution unit, and a task control unit. The method includes: The third task generation pipeline creates a mesh shader thread group based on the third drawing instruction, inputs the mesh shader thread group into the shader execution unit, and sends the mesh task information corresponding to the mesh shader thread group to the task control unit. The shader execution unit runs the mesh shader thread group to obtain the mesh shading result; the task control unit obtains the mesh shading result according to the instruction of the mesh task information and outputs the mesh shading result to the pipeline after the geometry processing pipeline; the task control unit is also used to clear the mesh payload bag when the end flag corresponding to the last mesh task information corresponding to the last mesh shader thread group is detected, the mesh payload bag is used to contain the magnified shading result output by the shader execution unit.

21. A chip, characterized in that, The chip includes a graphics processor as described in any one of claims 1 to 18.

22. A server, characterized in that, The server includes a graphics processor as described in any one of claims 1 to 18.

23. An electronic device, characterized in that, The electronic device includes a graphics processor as described in any one of claims 1 to 18.

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