Gate drive circuit and display panel

Abstract

The invention discloses a gate drive circuit and a display panel, the gate drive circuit comprises a multi-stage cascaded gate drive unit, the gate drive unit comprises a first output unit used for outputting a first pulse signal, the first pulse signal is a normal high-potential low-potential pulse, the second output unit is used for outputting a second pulse signal, the first output unit is used for outputting a second pulse signal, and the second output unit is used for outputting a third pulse signal. The second output unit is used for outputting a second pulse signal, and the second pulse signal is a pulse width modulation signal accompanied by the high-potential pulse; the first control unit is connected with the control end of the first output unit and used for controlling the first output unit to output a first pulse signal; and the second control unit is connected with the control end of the second output unit and is used for controlling the second output unit to output a second pulse signal. Through the circuit, the output of the scanning signal and the switching signal is realized.

Description

Technical Field

[0001] The present invention relates to the field of display panels, and in particular to a gate driving circuit and a display panel. Background Art

[0002] With the development of display technology, OLED (Organic Light Emitting Display) products have begun to enter the public eye. Different from LCD products, OLED drives organic light emitting substances to emit light through electric current. According to the saturation current formula: It can be seen that the threshold voltage Vth of the transistor TFT will have a greater impact on the current.

[0003] The common OLED pixel driving circuit includes a reset process operated by the previous scan signal Pscan(n-1), a sampling process operated by the current scan signal Pscan(n), and a light-emitting process controlled by the current switch signal EM(n). Different from LCD, the switch signal achieves the periodic on and off of the circuit by periodically switching the equivalent circuit of the light-emitting process, thereby achieving PWM dimming. Summary of the invention

[0004] The main technical problem solved by the present application is to provide a gate driving circuit and a display panel to realize the output of two signals, a scanning signal and a switching signal.

[0005] To solve the above problems, the present application provides a gate drive circuit, wherein the gate drive circuit includes a multi-stage cascaded gate drive unit, and the gate drive unit includes: a first output unit, used to output a first pulse signal, wherein the first pulse signal is a low-potential pulse with a normal high potential; a second output unit, used to output a second pulse signal, wherein the second pulse signal is a pulse width modulated signal accompanied by a high-potential pulse; a first control unit, connected to the control end of the first output unit, used to control the first output unit to output the first pulse signal; and a second control unit, connected to the control end of the second output unit, used to control the second output unit to output the second pulse signal.

[0006] Among them, the first output unit includes a first sub-output unit and a second sub-output unit; the first sub-output unit is connected to a high-potential signal line, and is used to output a high-potential pulse according to a control signal output by the first control unit; the second sub-output unit is connected to a low-potential signal line, and is used to output a low-potential pulse according to the control signal output by the first control unit.

[0007] Among them, the first control unit includes: a first sub-control unit, connected to the control end of the first sub-output unit, used to output a conduction signal to the first sub-output unit to control the first sub-output unit to output a high-voltage pulse; a low-voltage control unit, connected to the control ends of the first sub-control unit and the second sub-output unit, used to transmit a low-voltage control signal to the control ends of the first sub-control unit and the second sub-output unit, thereby controlling the second sub-output unit and controlling the first sub-output unit through the first sub-control unit; a high-voltage holding unit, connected to the control ends of the first sub-control unit and the second sub-output unit, used to keep the control ends of the first sub-control unit and the second sub-output unit at a high voltage, thereby controlling the output of the first sub-output unit and the second sub-output unit.

[0008] Among them, the first control unit also includes: a first cascade unit, connected to the first output unit of the previous level, for receiving the first pulse signal transmitted by the first output unit of the previous level; a first storage unit, connected to the first cascade unit, for storing the potential signal of the first pulse signal of the previous level; wherein the potential signal includes a high potential and a low potential; a delay control unit, connecting the first storage unit with the control end of the low potential control unit, for transmitting the potential signal stored in the first storage unit to the control end of the low potential control unit to control the on / off of the low potential control unit.

[0009] Wherein, the control ends of the first cascade unit and the delay control unit are connected to a group of control signal lines with opposite pulse phases.

[0010] Wherein, the first sub-control unit includes: a low-potential signal line; a first transistor, the input end of the first transistor is connected to the low-potential signal line, the output end of the first transistor is connected to the control end of the first sub-output unit, the control end of the first transistor is connected to the high-potential holding unit and the low-potential control unit, and is used to control the low-potential signal line to output a conduction signal to the first sub-output unit according to the control signals output by the high-potential holding unit and the low-potential control unit; wherein, the first transistor is an N-type transistor.

[0011] The high potential holding unit includes a high potential signal line and a first resistor, and the high potential signal line is connected to the control ends of the first sub-control unit and the first sub-output unit through the first resistor.

[0012] Wherein, the second output unit includes a third sub-output unit, a fourth sub-output unit and a fifth sub-output unit; the third sub-output unit is connected to the low-potential signal line, and is used to output a low-potential pulse according to the first pulse width control signal; the fourth sub-output unit is connected to the high-potential signal line, and is used to output a high-potential pulse of the pulse width control signal according to the second pulse width control signal; the fifth sub-output unit is connected to the high-potential signal line, and is used to output a high potential according to the control signal output by the second control unit; the first pulse width modulation unit is connected to the control end of the third sub-output unit, and is used to output the first pulse width control signal to the control end of the third sub-output unit; the second pulse width modulation unit is connected to the control end of the fourth sub-output unit, and is used to output the second pulse width control signal to the control end of the fourth sub-output unit; wherein, the first pulse width control signal and the second pulse width control signal are a set of level signals with opposite pulse phases.

[0013] Wherein, the second control unit includes: a first potential control unit, whose input end is connected to the high potential signal line, and whose output end is connected to the control ends of the first pulse width modulation unit, the second pulse width modulation unit and the fifth sub-output unit, and is used to transmit a high potential control signal to the control ends of the first pulse width modulation unit, the second pulse width modulation unit and the fifth sub-output unit; a second potential control unit, whose input end is connected to the low potential signal line, and whose output end is connected to the control ends of the first pulse width modulation unit, the second pulse width modulation unit and the fifth sub-output unit, and is used to transmit a low potential control signal to the control ends of the first pulse width modulation unit, the second pulse width modulation unit and the fifth sub-output unit.

[0014] Wherein, the second control unit also includes: a high potential control unit, connected to the control ends of the first potential control unit and the second potential control unit, and used to control the on / off of the first potential control unit and the second potential control unit; a low potential holding unit, connected to the control ends of the first potential control unit and the second potential control unit and the output end of the high potential control unit, and used to control the control ends of the first potential control unit and the second potential control unit to be at a low potential when the high potential control unit does not output; wherein, the first potential control unit and the second potential control unit include a group of transistors with opposite driving characteristics.

[0015] Among them, the second control unit also includes: a second cascade unit, connected to the second output unit of the previous level, for receiving the second pulse signal output by the second output unit of the previous level; a first storage control unit, connected to the second cascade unit, for transmitting a control signal according to the second cascade unit; a third storage unit, connected to the first storage control unit, for storing the control signal transmitted by the first storage control unit; a second storage control unit, connected to the third storage unit, for controlling the third storage unit to transmit the control signal to the control end of the high potential control unit; a fourth storage unit, connected to the second storage control unit, for storing the control signal transmitted by the second storage control unit; wherein the control ends of the first storage control unit and the second storage control unit are respectively connected to two control signal lines with opposite pulse phases.

[0016] Wherein, the second control unit further includes: a reset signal line connected to the third storage unit, and used to transmit a reset signal to the third storage unit, and then transmit the reset signal to the fourth storage unit.

[0017] The low potential holding unit includes a low potential signal line and a second resistor, and the low potential signal line is connected to the control ends of the first potential control unit and the second potential control unit through the second resistor.

[0018] The second control unit further includes: a reset unit, including a low potential signal line and a third resistor, connected to the input end of the first storage control unit, and used for transmitting a low potential reset signal to the third storage unit and the fourth storage unit.

[0019] To solve the above problem, the present application provides a display panel in a second aspect, wherein the display panel includes the gate driving circuit described in any embodiment of the first aspect.

[0020] The beneficial effect of the present application is that by designing the gate drive circuit, while minimizing the use of input signals, a gate drive circuit can output scanning signals and switching signals to each row of pixel units in sequence to control the light-emitting devices in the surface to emit light, thereby saving circuit expenses and reducing the border width. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 A schematic diagram of the structure of an embodiment of a gate driving circuit provided in the present application; Figure 2 A timing diagram of the first pulse signal and the second pulse signal provided in the present application; Figure 3 A schematic structural diagram of a first specific embodiment of a gate driving unit provided in the present application; Figure 4 A schematic structural diagram of a second specific embodiment of a gate driving unit provided in the present application; Figure 5 A partial structural schematic diagram of a third specific embodiment of a gate driving unit provided in the present application; Figure 6 A partial structural schematic diagram of a fourth specific embodiment of a gate driving unit provided in the present application; Figure 7 A partial structural schematic diagram of a fifth specific embodiment of a gate driving unit provided in the present application; Figure 8 A partial structural schematic diagram of a sixth specific embodiment of a gate driving circuit provided in the present application; Fig. 9 A partial structural schematic diagram of a seventh specific embodiment of the gate driving circuit provided in the present application; Fig.10 A partial structural schematic diagram of an eighth specific embodiment of a gate driving unit provided in the present application; Fig.11 A partial structural schematic diagram of a ninth specific embodiment of a gate driving unit provided in the present application; Fig.12 A partial structural schematic diagram of a tenth specific embodiment of a gate driving unit provided in the present application; Fig.13 A schematic diagram of the circuit structure of a specific embodiment of the gate driving unit provided in this application; Fig.14 A driving timing diagram of a specific embodiment of a gate driving unit provided in the present application; Fig.15 A circuit diagram of the first driving stage of a specific embodiment of a gate driving unit provided in the present application; Fig.16 A circuit diagram of the second driving stage of a specific embodiment of a gate driving unit provided in the present application; Fig.17 A circuit diagram of the third driving stage of a specific embodiment of a gate driving unit provided in the present application; Fig.18 A circuit diagram of a fourth driving stage of a specific embodiment of a gate driving unit provided in the present application; Fig.19A schematic diagram of the structure of an embodiment of a display panel provided in the present application; Fig. 20 This is a structural schematic diagram of an embodiment of a pixel driving circuit provided in the present application.

[0023] The first output unit 10; the second output unit 20; the first control unit 11; the second control unit 21; the first pulse signal Pscan(n); the first pulse signal Pscan(n-1) of the previous stage; the first pulse signal Pscan(n-2) of the previous two stages; the second pulse signal EM(n); the high potential signal line VGH; the low potential signal line VGL; the first sub-control unit 111; the high potential holding unit 113; the low potential control unit 112; the delay control unit 115; the first cascade unit 114; the first sub-output unit 101; the second sub-output unit 102; the third sub-output unit 201; the fourth sub-output unit 202; the fifth sub-output unit 203; the first storage control unit 215; the second storage control unit 216; the low potential holding unit 214; the high potential control unit 213; the first potential control unit 211; the second potential control unit 212; the first pulse width modulation unit 220; the second pulse width modulation unit 230; the cascade control unit 243; the first sub-cascade unit 241; the second sub-cascade unit 242; A first control signal line XCK; a second control signal line CK; a first pulse width control signal PWM-CK; a second pulse width control signal PWM-XCK; a first transistor T1; a second transistor T2; a third transistor T3; a fourth transistor T4; a low potential signal line VGL1; a fifth transistor T5; a high potential signal line VGH1; a sixth transistor T6; a seventh transistor T7; an eighth transistor T8; a ninth transistor T9; a tenth transistor T10; an eleventh transistor T11; a twelfth transistor T12; a thirteenth transistor T13; a fourteenth transistor T14; a fifteenth transistor T15; a sixteenth transistor T16; a seventeenth transistor T17; an eighteenth transistor T18; a nineteenth transistor T19; a twentieth transistor T20; Display panel 100 ; display area 1001 ; non-display area 1002 . DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "said", and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless otherwise clearly indicated above, and "multiple" generally includes at least two, but does not exclude the inclusion of at least one.

[0026] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0027] It should be understood that the terms "include", "comprises" or any other variations used herein are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, the elements defined by the sentence "includes..." do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.

[0028] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back...), such directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0029] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The presence of the phrase at each location in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0030] The present application provides a gate driving circuit, which includes: a plurality of cascaded gate driving units, for details, please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of an embodiment of the gate drive circuit provided by the present application. Figure 1As shown, each gate driving unit GOA at least includes: a first output unit 10 , a second output unit 20 , a first control unit 11 , and a second control unit 21 .

[0031] The first output unit 10 is used to output a first pulse signal Pscan(n), which is a low potential pulse with a normal high potential. The first pulse signal Pscan(n) is a low potential scanning signal used to control the writing of data signals in the display panel.

[0032] The second output unit 20 is used to output a second pulse signal EM(n), which is a pulse width modulation signal accompanied by a high potential pulse. Specifically, the second pulse signal EM(n) is a switching signal that modulates the light emission frequency of the light emitting unit.

[0033] Specifically, the first output unit 10 and the second output unit 20 are both connected to the high potential signal line VGH and the low potential signal line VGL, and the first output unit 10 and the second output unit 20 control the output of the first pulse signal Pscan(n) and the second pulse signal EM(n).

[0034] The first control unit 11 is connected to the control end of the first output unit 10 and is used to control the first output unit 10 to output the first pulse signal Pscan(n).

[0035] The second control unit 21 is connected to the control end of the second output unit 20 and is used to control the second output unit 20 to output the second pulse signal EM(n).

[0036] Please refer to Figure 2 , Figure 2 This is a timing diagram of the first pulse signal and the second pulse signal provided in this application. Figure 2As shown, the first pulse signal Pscan(n) and the second pulse signal EM(n) both include a high potential pulse (high potential voltage) and a low potential pulse (low potential voltage). The duty ratio of the high / low potential in the first pulse signal Pscan(n) and the second pulse signal EM(n) is different, and the timing is also different. In this preferred embodiment, the second pulse signal EM(n) is delayed by one timing / phase from the first pulse signal Pscan(n). Preferably, the pulse frequency of the second pulse signal EM(n) is greater than the pulse frequency of the first pulse signal Pscan(n), specifically, the pulse frequency of the second pulse signal EM(n) is greater than an integer multiple of the pulse frequency of the first pulse signal Pscan(n). As shown in this embodiment, within a timing, the pulse frequency of the second pulse signal EM(n) is 3 times the pulse frequency of the first pulse signal Pscan(n), that is, the three second pulse signals EM(n) have the same timing as one first pulse signal Pscan(n), that is, the comparison is performed within the same phase width.

[0037] Specifically, see Figure 3 , Figure 3 This is a schematic diagram of the structure of the first specific embodiment of the gate driving unit provided in this application. Figure 3 As shown, the first output unit 10 includes a first sub-output unit 101 and a second sub-output unit 102. The first sub-output unit 101 is connected to the high potential signal line VGH, and is used to output a high potential pulse (that is, a high potential level) of the first pulse signal Pscan(n) according to the control signal output by the first control unit 11. The second sub-output unit 102 is connected to the low potential signal line VGL, and is used to output a low potential pulse (low potential level) of the first pulse signal Pscan(n) according to the control signal output by the first control unit 11. The first pulse signal Pscan(n) is a pulse signal formed by alternating high and low potentials.

[0038] In a specific embodiment, the output end of the first control unit 11 is connected to the control end of the first sub-output unit 101 and the second sub-output unit 102 at the same time, and the first sub-output unit 101 and the second sub-output unit 102 include two transistors with opposite driving characteristics. That is, when the first sub-output unit 101 is turned on, the second sub-output unit 102 is turned off, and when the second sub-output unit 102 is turned on, the first sub-output unit 101 is turned off, so that the first control unit 11 controls the first sub-output unit 101 and the second sub-output unit 102 to be turned on alternately, thereby forming an output first pulse signal Pscan(n).

[0039] In a further embodiment, the second output unit 20 includes a third sub-output unit 201 , a fourth sub-output unit 202 , and a fifth sub-output unit 203 .

[0040] The third sub-output unit 201 is connected to the low potential signal line VGL, and is used to output the low potential pulse of the pulse width modulation signal. The fourth sub-output unit 202 is connected to the high potential signal line VGH, and is used to output the high potential pulse of the pulse width modulation signal. The fifth sub-output unit 203 is connected to the high potential signal line VGH, and is used to output the high potential pulse according to the control signal output by the second control unit.

[0041] It should be noted that the second pulse signal EM(n) includes a normal high potential pulse and a high potential pulse and a low potential pulse in a pulse width modulation signal. Specifically, the high potential pulse and the low potential pulse of the pulse width modulation signal refer to the high potential pulse and the low potential pulse in the pulse width modulation stage (light emitting stage). The normal high potential pulse refers to the high potential pulse in the non-light emitting stage.

[0042] In further embodiments, please refer to Figure 4 , Figure 4 This is a schematic diagram of the structure of the second specific embodiment of the gate driving unit provided in this application. Figure 4 As shown, the third sub-output unit 201 and the fourth sub-output unit 202 also include a pulse width modulation unit 210, which is used to output a pulse width modulation control signal so that the third sub-output unit 201 and the fourth sub-output unit 202 are alternately turned on in the light-emitting stage to generate a pulse width modulation signal, and the pulse width modulation signal is at least one group of alternating high-potential pulses and low-potential pulses. In a specific embodiment, the pulse width modulation unit 210 may include a first pulse width modulation unit and a second pulse width modulation unit, please refer to the subsequent specific embodiments. In this specific embodiment, the pulse width modulation unit 210 can also be composed of a modulation unit, outputting an alternating high / low pulse modulation signal to control the third sub-output unit 201 and the fourth sub-output unit 202 to be alternately turned on. At this time, the third sub-output unit 201 and the fourth sub-output unit 202 include two transistors (N-type transistor and P-type transistor) with opposite driving characteristics.

[0043] Furthermore, the pulse width modulation unit 210 in the third sub-output unit 201 and the fourth sub-output unit 202 has the opposite driving characteristics to the fifth sub-output unit 203, that is, when the third sub-output unit 201 and the fourth sub-output unit 202 are working, the fifth sub-output unit 203 is not working, thereby outputting a pulse width modulation signal (light-emitting stage). When the third sub-output unit 201 and the fourth sub-output unit 202 are not working, the fifth sub-output unit 203 is working, and the slave outputs a normal high potential pulse (non-light-emitting stage).

[0044] Further, the first control unit 11 includes a first sub-control unit 111, a high potential holding unit 113, and a low potential control unit 112. Figure 5 , Figure 5This is a partial structural diagram of the third specific embodiment of the gate driving unit provided in this application. Figure 5 As shown, the first sub-control unit 111 is connected to the control end of the first sub-output unit 101, and is used to output a conduction signal to the control end of the first sub-output unit 101 to control the first sub-output unit 101 to output a high potential pulse.

[0045] In this specific embodiment, the first sub-control unit 111 also includes a low potential signal line VGL, and the conduction signal is a low potential signal. The first sub-control unit 111 is used to control the transmission of the low potential signal to the control end of the first sub-output unit 101 to control the conduction of the first sub-output unit 101.

[0046] The low-voltage control unit 112 is connected to the control ends of the first sub-control unit 111 and the second sub-output unit 102, and is used to transmit a low-voltage control signal to the control ends of the first sub-control unit 111 and the second sub-output unit 102, thereby controlling the output of the second sub-output unit 102 and controlling the output of the first sub-output unit 101 through the first sub-control unit 111.

[0047] The high potential holding unit 113 is connected to the control ends of the first sub-control unit 111 and the second sub-output unit 102, and is used to keep the control ends of the first sub-control unit 111 and the second sub-output unit 102 at a high potential, thereby controlling the output of the first sub-output unit 101 and the second sub-output unit 102.

[0048] Wherein, the first sub-control unit 111 and the second sub-output unit 102 include a group of transistors with opposite driving characteristics, that is, when the first sub-control unit 111 is turned on, the second sub-output unit 102 is turned off; when the second sub-output unit 102 is turned on, the first sub-control unit 111 is turned off. Wherein, when the first sub-control unit 111 is turned on, the first sub-output unit 101 can be controlled to be turned on. Wherein, the first sub-output unit 101 and the second sub-output unit 102 include transistors with the same driving characteristics, specifically, both are P-type transistors that are turned on at a low potential. It can be understood that the first sub-output unit 101 and the second sub-output unit 102 can also be N-type transistors that are turned on at a high potential, and then each conduction signal or control signal is also a high potential signal.

[0049] In this embodiment, the control terminals of the first sub-control unit 111 and the second sub-output unit 102 are kept at a high potential through the high potential holding unit 113, so that the first sub-output unit 101 is kept normally open and the second sub-output unit 102 is kept normally closed. The control signal (low potential control signal) is transmitted to the control terminals of the first sub-control unit 111 and the second sub-output unit 102 through the low potential control unit 112, so that the first sub-output unit 101 is turned off and the second sub-output unit 102 is turned on, thereby outputting a low potential pulse of the first pulse signal Pscan(n).

[0050] Furthermore, the low potential control unit 112 includes a low potential signal line VGL and a switching transistor. The high potential holding unit 113 includes a high potential signal line VGH and a first resistor R1. The first resistor R1 is a large resistor, and the speed at which the low potential control unit 112 transmits the low potential signal to the control end of the first sub-control unit 111 and the second sub-output unit 102 is greater than the high potential signal transmission speed of the high potential holding unit 113, so that the control of the low potential control unit 112 on the first sub-control unit 111 and the second sub-output unit 102 is superior to the control strength of the high potential holding unit 113. In other embodiments, the high potential holding unit 113 can also be composed of a high potential signal line VGH and a switching transistor, which is not limited here.

[0051] The control end of the low potential control unit 112 is also connected to the cascade unit. Figure 6 , Figure 6 This is a partial structural diagram of the fourth specific embodiment of the gate driving unit provided in this application. Figure 6 As shown, the first control unit 11 further includes a first cascade unit 114, which is connected to the first output unit 10 of the previous stage and is used to receive the first pulse signal Pscan(n-1) transmitted by the first output unit 10 of the previous stage. Specifically, the input end of the first cascade unit 114 is connected to the output end of the first output unit 10 of the previous stage.

[0052] The first storage unit C1 is connected to the first cascade unit 114 and is used to store the potential signal of the previous first pulse signal Pscan(n), wherein the potential signal includes a high potential pulse signal and a low potential pulse signal.

[0053] The delay control unit 115 is arranged at the control end of the first storage unit C1 and the low potential control unit 112, and is used to control the connection between the first storage unit C1 and the control end of the low potential control unit 112, and control the potential signal stored in the first storage unit C1 to be transmitted to the control end of the low potential control unit 112, so as to control the on / off of the low potential control unit 112.

[0054] Specifically, the first plate of the first storage unit C1 is connected to the output end of the first cascade unit 114 and the input end of the delay control unit 115, so as to store the first pulse signal Pscan(n-1) transmitted by the first cascade unit 114 in the previous timing, and transmit the stored first pulse signal Pscan(n-1) to the control end of the low potential control unit 112 through the delay control unit 115 in the next timing. In a specific embodiment, the second plate of the first storage unit C1 is connected to the low potential signal line VGL, and in other embodiments, the second plate of the first storage unit C1 can also be connected to the high potential signal line VGH, or to the ground line, or to the common potential line, which is not limited here.

[0055] In this specific embodiment, the control ends of the first cascade unit 114 and the delay control unit 115 are connected to a group of control signal lines with opposite phases, specifically including a first control signal line XCK and a second control signal line CK. The control signals transmitted by the first control signal line XCK and the second control signal line CK are in opposite phases, so that when the first cascade unit 114 is turned on, the delay control unit 115 is turned off; or, when the first cascade unit 114 is turned off, the delay control unit 115 is turned on. In this specific embodiment, the first cascade unit 114 and the delay control unit 115 include transistors with the same driving characteristics. In other embodiments, the control ends of the first cascade unit 114 and the delay control unit 115 can also be connected to the same control signal line, and the control signal includes a high / low level signal, then the first cascade unit 114 and the delay control unit 115 include a group of transistors with opposite driving characteristics.

[0056] Specifically, in the first stage, the first pulse signal Pscan(n-1) of the previous stage transmits the low potential pulse of the first pulse signal Pscan(n-1) to the first storage unit C1 through the first cascade unit 114. In this stage, the high potential holding unit 113 transmits a high potential signal to the control end of the first sub-control unit 111 and the second sub-output unit 102 to control the first sub-control unit 111 to be turned on, thereby enabling the first sub-control unit 111 to control the first sub-output unit 101 to output the high potential pulse of the first pulse signal Pscan(n).

[0057] In the second stage, the first storage unit C1 transmits the stored low-voltage pulse to the control end of the low-voltage control unit 112 through the delay control unit 115 to control the transistor in the low-voltage control unit 112 to turn on, and then transmits the low-voltage control signal to the control ends of the first sub-control unit 111 and the second sub-output unit 102, so that the transistor in the first sub-control unit 111 is turned off, the second sub-output unit 102 is turned on, and the low-voltage pulse of the first pulse signal Pscan(n) is output.

[0058] Furthermore, the first output unit 10 further includes a second storage unit C2, which is connected to the control end of the second sub-output unit 102 and is used to accelerate the shutdown of the second sub-output unit 102. The second storage unit C2 is a Miller capacitor, which is used as a buffer for the Miller effect, and accelerates the second sub-output unit 102 to quickly shut down after the second stage, thereby ensuring that the light-emitting stage after the second stage can work normally.

[0059] The first electrode plate of the second storage unit C2 is connected to the control end of the second sub-output unit 102, and the second electrode plate is connected to the output end of the second sub-output unit 102. In the second stage, the first electrode plate and the second electrode plate of the second storage unit C2 both store low potentials, and in the light-emitting stage after the second stage, the second electrode plate of the second storage unit C2 is high potential, so that according to the capacitive coupling effect, the first electrode plate of the second storage unit C2 is coupled to a high potential, thereby accelerating the shutdown of the second sub-output unit 102.

[0060] In a specific embodiment, the first sub-control unit 111 includes a low potential signal line VGL and a first transistor T1 that is turned on at a high potential. The input end of the first transistor T1 is connected to the low potential signal line VGL, and the output end is connected to the control end of the first sub-output unit 101, and is used to transmit a low potential turn-on signal to the control end of the first sub-output unit 101. The first transistor T1 is an N-type transistor.

[0061] In another specific embodiment, the first sub-control unit 111 includes a low potential signal line VGL, a first transistor T1 that is turned on at a high potential, and a second transistor T2 that is turned on at a low potential. The second transistor T2 is disposed between the control terminals of the first transistor T1, the control terminal of the second transistor T2 is connected to the output unit of the first transistor T1, receives a low potential signal to turn on, the input terminal of the second transistor T2 is connected to the low potential signal line VGL, and the output terminal is connected to the control terminal of the first sub-output unit 101, and is used to control the low potential signal line VGL to output a turn-on signal to the control terminal of the first sub-output unit 101 according to the control signal output by the first transistor T1. The first transistor T1 is an N-type transistor, and the second transistor T2 is a P-type transistor.

[0062] Please refer to Figure 7 , Figure 7 This is a partial structural diagram of the fifth specific embodiment of the gate driving unit provided in the present application.

[0063] In a specific embodiment, the pulse width modulation unit 210 includes a first pulse width modulation unit 220 and a second pulse width modulation unit 230. The first pulse width modulation unit 220 is connected to the control end of the third sub-output unit 201, and is used to output the first pulse width modulation signal PWM-CK to the control end of the third sub-output unit 201. The second pulse width modulation unit 230 is connected to the control end of the fourth sub-output unit 202, and is used to output the second pulse width modulation signal PWM-XCK to the control end of the fourth sub-output unit 202. Among them, the first pulse width modulation signal PWM-CK and the second pulse width modulation signal PWM-XCK are a group of level signals with opposite pulse phases and the same frequency. That is, when the first pulse width modulation signal PWM-CK controls the third sub-output unit 201 to be turned on, the second pulse width modulation signal PWM-XCK controls the fourth sub-output unit 202 to be turned off; when the first pulse width modulation signal PWM-CK controls the third sub-output unit 201 to be turned off, the second pulse width modulation signal PWM-XCK controls the fourth sub-output unit 202 to be turned on. Among them, the frequency of the first pulse width control signal PWM-CK and the second pulse width control signal PWM-XCK is greater than the frequency of the first pulse signal Pscan(n). Preferably, the pulse frequency of the first pulse width control signal PWM-CK and the second pulse width control signal PWM-XCK is an integer multiple of the pulse frequency of the first pulse signal Pscan(n), specifically an integer multiple greater than 1, which can be 2 times, 3 times, 4 times, etc. So that in the light-emitting stage, the first pulse width control signal PWM-CK and the second pulse width control signal PWM-XCK include at least a group of low level and high level, so that the second pulse signal EM(n) outputs a turn-on signal and a turn-off signal in the light-emitting stage. In this specific embodiment, the third sub-output unit 201 and the fourth sub-output unit 202 include transistors with the same driving characteristics, both of which are P-type transistors.

[0064] The second control unit 21 outputs alternating high potential signals and low potential signals to control the conduction of the first pulse width modulation unit 220 , the second pulse width modulation unit 230 and the fifth sub-output unit 203 , respectively.

[0065] For further information, see Figure 8 , Figure 8 This is a partial structural diagram of the sixth specific embodiment of the gate driving unit provided in this application. Figure 8 As shown, the second control unit 21 at least includes a first potential control unit 211 and a second potential control unit 212 .

[0066] Among them, the input end of the first potential control unit 211 is connected to the high potential signal line VGH, and the output end is connected to the control ends of the first pulse width modulation unit 220, the second pulse width modulation unit 230 and the fifth sub-output unit 203, and is used to transmit a high potential control signal to the control ends of the first pulse width modulation unit 220, the second pulse width modulation unit 230 and the fifth sub-output unit 203 to control the first pulse width modulation unit 220 and the second pulse width modulation unit 230 to be turned on and the fifth sub-output unit 203 to be turned off.

[0067] The input end of the second potential control unit 212 is connected to the low potential signal line VGL, and the output end is connected to the control end of the first pulse width modulation unit 220, the second pulse width modulation unit 230 and the fifth sub-output unit 203, and is used to transmit a low potential control signal to the control end of the first pulse width modulation unit 220, the second pulse width modulation unit 230 and the fifth sub-output unit 203 to control the first pulse width modulation unit 220 and the second pulse width modulation unit 230 to turn off and the fifth sub-output unit 203 to turn on. It should be noted that the on and off here can also refer to the two states of working and not working, that is, the first pulse width modulation unit 220 and the second pulse width modulation unit 230 are working, and the fifth sub-output unit 203 is not working; or the fifth sub-output unit 203 is working, and the first pulse width modulation unit 220 and the second pulse width modulation unit 230 are not working.

[0068] In this specific embodiment, the first pulse width modulation unit 220 and the second pulse width modulation unit 230 include N-type transistors that are turned on at a high potential, and the fifth sub-output unit 203 includes a P-type transistor that is turned on at a low potential. In other embodiments, the first pulse width modulation unit 220 and the second pulse width modulation unit 230 may also include P-type transistors, and the fifth sub-output unit 203 includes an N-type transistor, then the first potential control unit 211 is used to transmit a low potential control signal, and the second potential control unit 212 is used to transmit a high potential control signal.

[0069] See further Fig. 9 , Fig. 9 This is a partial structural diagram of the seventh specific embodiment of the gate driving unit provided in this application. Fig. 9 As shown, the second control unit 21 also includes a high potential control unit 213 and a low potential holding unit 214. The output ends of the high potential control unit 213 and the low potential holding unit 214 are connected to the control ends of the first potential control unit 211 and the second potential control unit 212, and are used to control the first potential control unit 211 to be turned on or the second potential control unit 212 to be turned on.

[0070] In this specific embodiment, the first potential control unit 211 and the second potential control unit 212 include a group of transistors with opposite driving characteristics. It is conceivable that in other embodiments, the control ends of the first potential control unit 211 and the second potential control unit 212 can also be controlled by a pulse signal line, which can be a low potential pulse with a normal high potential or a high potential pulse with a normal low potential, wherein the pulse signal line can be a cascaded first pulse signal line.

[0071] The high potential control unit 213 is used to transmit a high potential signal to the control ends of the first potential control unit 211 and the second potential control unit 212, so as to control the first potential control unit 211 to be turned on and the second potential control unit 212 to be turned off. The low potential holding unit 214 is used to transmit a low potential signal to the control ends of the first potential control unit 211 and the second potential control unit 212, so as to control the first potential control unit 211 to be turned off and the second potential control unit 212 to be turned on.

[0072] When the high potential control unit 213 is not working, the low potential holding unit 214 keeps the control terminals of the first potential control unit 211 and the second potential control unit 212 at a low potential, so that the fifth sub-output unit 203 outputs a normal high potential pulse.

[0073] See further Fig.10 , Fig.10 This is a partial structural diagram of the eighth specific embodiment of the gate driving unit provided in this application. Fig.10 As shown, the second cascade unit 240, the first storage control unit 215, the third storage unit C3, the second storage control unit 216, and the fourth storage unit C4.

[0074] Specifically, the second cascade unit 240 is connected to the output end of the second output unit 20 of the previous level, and is used to receive the second pulse signal EM(n-1) output by the second output unit output 20 of the previous level, and control the transmission of a control signal to the control end of the high potential control unit 213 according to the second pulse signal EM(n-1) output by the second output unit output 20 of the previous level, and the control signal is a high potential voltage.

[0075] The first storage control unit 215 is connected to the second cascade unit 240, and is used to control the transmission of a control signal to the control end of the high potential control unit 213 according to the on / off status of the second cascade unit 240. Specifically, the input end of the first storage control unit 215 is connected to the high potential signal line VGH, and the output end is connected to the third storage unit C3. In this specific embodiment, the input end of the first storage control unit 215 is connected to the high potential signal line VGH through the second cascade unit 240. In other embodiments, the second cascade unit 240 is connected to the control end of the first storage control unit 215, and is used to control the first storage control unit 215 to transmit a control signal to the high potential control unit 213.

[0076] The third storage unit C3 is connected to the output end of the first storage control unit 215 and is used to store the control signal transmitted by the first storage control unit 215 .

[0077] The second storage control unit 216 is connected to the third storage unit C3 and is used to control the third storage unit C3 to transmit a control signal to the control terminal of the high potential control unit 213 .

[0078] It also includes a fourth storage unit C4, which is connected to the output end of the second storage control unit 216 and is used to store the control signal transmitted by the second storage control unit 216 until the next timing cut-off signal (low potential voltage) arrives, thereby ensuring that the high potential control unit 213 is always in the on state before then.

[0079] In this specific embodiment, the control terminals of the first storage control unit 215 and the second storage control unit 216 are respectively connected to two control signal lines (CK and XCK) with opposite pulse phases.

[0080] For further information, please see Fig.11 , Fig.11 This is a partial structural diagram of the ninth specific embodiment of the gate driving unit provided in this application. Fig.11 As shown, the second cascade unit 240 includes a first sub-cascade unit 241 , a second sub-cascade unit 242 , and a cascade control unit 243 .

[0081] Among them, the control end of the first sub-cascade unit 241 is connected to the output end of the first output unit 10 of the upper two levels, and the input end is connected to the output end of the second output unit 20 of the upper level, and is used to control the reception of the second pulse signal EM(n-1) output by the second output unit 20 of the upper level according to the first pulse signal Pscan(n-2) of the upper two levels.

[0082] The control end of the second sub-cascade unit 242 is connected to the output end of the first output unit 10 of the previous level, and the input end is connected to the output end of the second output unit 20 of the previous level, and is used to control the reception of the second pulse signal EM(n-1) output by the second output unit 20 of the previous level according to the first pulse signal Pscan(n-1) of the previous level.

[0083] The control end of the cascade control unit 243 is connected to the output ends of the first sub-cascade unit 241 and the second sub-cascade unit 242, and is used to control the transmission of a control signal to the control end of the high potential control unit 213 according to the second pulse signal EM(n-1) of the previous stage.

[0084] In the above embodiment, the low potential holding unit 214 includes a low potential signal line VGL and a second resistor R2, and the low potential signal line VGL is connected to the control terminals of the first potential control unit 211 and the second potential control unit 212 through the second resistor R2. In other embodiments, it can also be controlled by a transistor, which is not limited here.

[0085] In this specific embodiment, the second control unit 21 also includes a reset signal line CLR, which is connected to the third storage unit C3 and is used to transmit a reset signal to the third storage unit C3, and then transmit a reset signal to the fourth storage unit C4 through the second storage control unit 216, so that the potential stored in the third storage unit C3 and the fourth storage unit C4 is reset.

[0086] In some specific embodiments, the second control unit 21 further includes a reset unit 250, see Fig.12 , Fig.12 This is a partial structural diagram of the tenth specific embodiment of the gate driving unit provided in the present application. The reset unit 250 includes a low potential signal line VGL and a third resistor R3. The reset unit 250 is connected to the input end of the first storage control unit 215 and is used to transmit a low potential reset signal to the third storage unit C3 and the fourth storage unit C4. Specifically, the reset unit 250 is connected to the input end of the first storage control unit 215 and the output end of the cascade control unit 243.

[0087] Specifically, when the first storage control unit 215 is turned on, the high potential stored in the third storage unit C3 is discharged through the first storage control unit 215 and the reset unit 250. When the second storage control unit 216 is turned on, the high potential stored in the fourth storage unit C4 is discharged and reset.

[0088] It should be noted that the reset unit 250 is a low potential reset unit in each level of the gate driving unit. The reset signal line CLR connects all the gate driving units. The reset signal on the reset signal line CLR is arranged in the light-emitting cycle stage of other gate driving units, generally at the Blanking moment. In order to avoid timing conflicts and insufficient thrust caused by placing the reset signal in the Blanking stage, a reset unit 250 is added to each level of the gate driving unit.

[0089] See further Fig.13 , Fig.13 A schematic diagram of the circuit structure of a specific embodiment of the gate driving unit provided in the present application.

[0090] The first sub-control unit 111 includes a first transistor T1 and a second transistor T2. The high potential holding unit 113 includes a first resistor R1. The low potential control unit 112 includes a third transistor T3. The delay control unit 115 includes a fourth transistor T4. The first cascade unit 114 includes a fifth transistor T5. The first sub-output unit 101 includes a sixth transistor T6, and the second sub-output unit 102 includes a seventh transistor T7.

[0091] The third sub-output unit 201 includes an eighth transistor T8. The fourth sub-output unit 202 includes a ninth transistor T9. The fifth sub-output unit 203 includes a tenth transistor T10. The first storage control unit 215 includes an eleventh transistor T11. The second storage control unit 216 includes a twelfth transistor T12. The low potential holding unit 214 includes a second resistor R2. The high potential control unit 213 includes a thirteenth transistor T13. The first potential control unit 211 includes a fourteenth transistor T14. The second potential control unit 212 includes a fifteenth transistor T15. The first pulse width modulation unit 220 includes a sixteenth transistor T16. The second pulse width modulation unit 230 includes a seventeenth transistor T17. The cascade control unit 243 includes an eighteenth transistor T18. The first sub-cascade unit 241 includes a nineteenth transistor T19. The second sub-cascade unit 242 includes a twentieth transistor T20.

[0092] In this specific embodiment, the first transistor T1, the thirteenth transistor T13, the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17, and the eighteenth transistor T18 are N-type transistors, and the other transistors are P-type transistors. In other embodiments, PMOS and NMOS can also be reversed, which is not limited here.

[0093] The present application also provides a driving timing diagram of a gate driving unit. Fig.14 , Fig.14 This is a driving timing diagram of a specific embodiment of the gate driving unit provided in this application. Fig.14 As shown in FIG, the driving stage includes a preparation stage, a reset stage, a sampling stage, and a light-emitting stage. Figure 15~Figure 18 . Fig.15 This is a circuit diagram of the first driving stage of a specific embodiment of the gate driving unit provided in the present application. Fig.16 This is a circuit diagram of the second driving stage of a specific embodiment of the gate driving unit provided in the present application. Fig.17 This is a circuit diagram of the third driving stage of a specific embodiment of the gate driving unit provided in this application. Fig.18 This is a circuit diagram of the fourth driving stage of a specific embodiment of the gate driving unit provided in this application.

[0094] In the preparation stage, the first control signal line XCK is at a low potential, and the second control signal line CK is at a high potential. At this time, the fourth transistor T4 is turned on, and the fifth transistor T5 is turned off. The high potential stored in the first storage unit C1 in the previous cycle passes through the gate of the fourth transistor T4, so that the third transistor T3 is turned off, and the gate of the first transistor T1 and the gate of the sixth transistor T6 are pulled high, so that the first transistor T1 is turned on, and the sixth transistor T6 is turned off. The low potential signal line VGL is transmitted to the gate of the second transistor T2 through the first transistor T1, and the second transistor T2 is controlled to be turned on, and then the low potential signal line VGL passes through the second transistor T2 to the gate of the seventh transistor T7, and the seventh transistor T7 is controlled to be turned on. At this time, the high potential signal line VGH outputs a high potential pulse of the first pulse signal Pscan(n) through the seventh transistor T7.

[0095] At this time, the first pulse signal Pscan(n-2) of the upper two levels is a low potential pulse, and the first pulse signal Pscan(n-1) of the upper level is a high potential pulse. The nineteenth transistor T19 is turned on, and the twentieth transistor T20 is turned off. The high potential pulse of the second pulse signal EM(n-1) of the upper level is applied to the gate of the eighteenth transistor T18 through the nineteenth transistor T19, controlling the eighteenth transistor T18 to turn on. At this time, the high potential of the first control signal line XCK controls the eleventh transistor T11 to turn on, and the high potential signal line VGH passes through the eighteenth transistor T18, and the transmission of the eleventh transistor T11 to the upper plate of the third storage unit C3, thereby storing the high potential pulse signal. At this time, the fourth storage unit C4 stores a low potential signal in the previous cycle, thereby controlling the thirteenth transistor T13 to turn off. At this time, the low potential signal of the low potential signal line VGL passes through the second resistor R2 to the gates of the fourteenth transistor T14 and the fifteenth transistor T15, the fourteenth transistor T14 is turned on, and the fifteenth transistor T15 is turned off. The high potential signal line VGH transmits a high potential signal to the gates of the sixteenth transistor T16, the seventeenth transistor T17 and the tenth transistor T10 through the fourteenth transistor T14, controls the sixteenth transistor T16 and the seventeenth transistor T17 to be turned on, and the tenth transistor T10 to be turned off. The first pulse width modulation signal line PWM-CK transmits a first pulse width modulation signal to the gate of the eighth transistor T8 through the sixteenth transistor T16, and the second pulse modulation signal line PWM-XCK transmits a second pulse width modulation signal to the gate of the ninth transistor T9 through the seventeenth transistor T17. The first pulse width modulation signal and the second pulse width modulation signal control the eighth transistor T8 and the ninth transistor T9 to be turned on alternately, thereby outputting a high / low potential pulse of the second pulse signal EM(n).

[0096] In the reset stage, the first control signal line XCK is at a high potential, and the second control signal line CK is at a low potential. At this time, the fourth transistor T4 is turned off and the fifth transistor T5 is turned on. The first pulse signal Pscan(n-1) of the previous stage is a low potential pulse, and the low potential pulse is transmitted to the first storage unit C1 for storage through the fifth transistor T5. The third transistor T3 remains turned off, and the high potential signal line VGH pulls up the gate of the first transistor T1 and the gate of the sixth transistor T6 through the first resistor R1, so that the first transistor T1 is turned on and the sixth transistor T6 is turned off. The low potential signal line VGL is transmitted to the gate of the second transistor T2 through the first transistor T1, controlling the second transistor T2 to be turned on, and then the low potential signal line VGL is transmitted to the gate of the seventh transistor T7 through the second transistor T2, controlling the seventh transistor T7 to be turned on. At this time, the high potential signal line VGH outputs the high potential pulse of the first pulse signal Pscan(n) through the seventh transistor T7.

[0097] At this time, the first pulse signal Pscan(n-2) of the upper two levels is a high potential pulse, and the first pulse signal Pscan(n-1) of the upper level is a low potential pulse. The nineteenth transistor T19 is turned off, and the twentieth transistor T20 is turned on. The high potential pulse of the second pulse signal EM(n-1) of the upper level is applied to the gate of the eighteenth transistor T18 through the twentieth transistor T20, and the eighteenth transistor T18 is controlled to be turned on. At this time, the low potential of the second control signal line CK controls the twelfth transistor T12 to be turned on, and the high potential pulse stored in the third storage unit C3 is transmitted to the fourth storage unit C4 and the control end of the thirteenth transistor T13 through the twelfth transistor T12, and the thirteenth transistor T13 is controlled to be turned on. The high potential signal line VGH transmits a high potential to the gates of the fourteenth transistor T14 and the fifteenth transistor T15 through the thirteenth transistor T13, and the fourteenth transistor T14 is controlled to be turned off, and the fifteenth transistor T15 is turned on. The low potential signal line VGL transmits a high potential to the gates of the sixteenth transistor T16, the seventeenth transistor T17 and the tenth transistor T10 through the fifteenth transistor T15, controls the sixteenth transistor T16 and the seventeenth transistor T17 to be turned off, and the tenth transistor T10 to be turned on. The high potential signal line VGH outputs a high potential pulse of the second pulse signal EM(n) through the tenth transistor T10.

[0098] In the sampling phase, the first control signal line XCK is at a low potential, and the second control signal line CK is at a high potential. At this time, the fourth transistor T4 is turned on, and the fifth transistor T5 is turned off. The low potential stored in the first storage unit C1 in the previous cycle is transmitted to the gate of the third transistor T3 through the fourth transistor T4, so that the third transistor T3 is turned on. The low potential signal line VGL is transmitted to the gates of the first transistor T1 and the sixth transistor T6 through the third transistor T3, so that the first transistor T1 is turned off and the sixth transistor T6 is turned on. At this time, the low potential signal line VGL outputs a low potential pulse of the first pulse signal Pscan(n) through the sixth transistor T6.

[0099] At this time, the first pulse signal Pscan(n-2) of the upper two levels is a high potential pulse, and the first pulse signal Pscan(n-1) of the upper level is a high potential pulse. The nineteenth transistor T19 is turned off, and the twentieth transistor T20 is turned off. The eighteenth transistor T18 is turned off. At this time, the high potential of the first control signal line XCK controls the eleventh transistor T11 to be turned on, and the low potential signal line VGL is transmitted to the upper board storage of the third storage unit C3 through the third resistor R3 and the eleventh transistor T11, thereby storing the low potential pulse signal. At this time, the fourth storage unit C4 stores a high potential signal in the previous cycle, thereby controlling the thirteenth transistor T13 to be turned on. At this time, the high potential signal line VGH transmits a high potential to the gates of the fourteenth transistor T14 and the fifteenth transistor T15 through the thirteenth transistor T13, controlling the fourteenth transistor T14 to be turned off, and the fifteenth transistor T15 to be turned on. The low potential signal line VGL transmits a high potential to the gates of the sixteenth transistor T16, the seventeenth transistor T17 and the tenth transistor T10 through the fifteenth transistor T15, controls the sixteenth transistor T16 and the seventeenth transistor T17 to be turned off, and the tenth transistor T10 to be turned on. The high potential signal line VGH outputs a high potential pulse of the second pulse signal EM(n) through the tenth transistor T10.

[0100] In the light-emitting stage, the first control signal line XCK is at a high potential, and the second control signal line CK is at a low potential. At this time, the fourth transistor T4 is turned off, the fifth transistor T5 is turned on, and the first pulse signal Pscan(n-1) of the previous stage is a low potential pulse, and the low potential pulse is transmitted to the first storage unit C1 for storage through the fifth transistor T5. The third transistor T3 remains turned off, and the high potential signal line VGH pulls up the gate of the first transistor T1 and the gate of the sixth transistor T6 through the first resistor R1, so that the first transistor T1 is turned on and the sixth transistor T6 is turned off. The low potential signal line VGL is transmitted to the gate of the second transistor T2 through the first transistor T1, controlling the second transistor T2 to be turned on, and then the low potential signal line VGL is transmitted to the gate of the seventh transistor T7 through the second transistor T2, controlling the seventh transistor T7 to be turned on, and at this time, the high potential signal line VGH outputs the high potential pulse of the first pulse signal Pscan(n) through the seventh transistor T7.

[0101] At this time, the first pulse signal Pscan(n-2) of the upper two levels is a high potential pulse, and the first pulse signal Pscan(n-1) of the upper level is a high potential pulse. The nineteenth transistor T19 is turned off, and the twentieth transistor T20 is turned off. The eighteenth transistor T18 is turned off. At this time, the low potential of the second control signal line CK controls the twelfth transistor T12 to be turned on, and the low potential stored in the third storage unit C3 is transmitted to the fourth storage unit C4 and the gate of the thirteenth transistor T13 through the twelfth transistor T12, and the thirteenth transistor T13 is controlled to be turned off. At this time, the low potential signal of the low potential signal line VGL is transmitted to the gate of the fourteenth transistor T14 and the fifteenth transistor T15 through the second resistor R2, the fourteenth transistor T14 is turned on, and the fifteenth transistor T15 is turned off. The high potential signal line VGH transmits a high potential signal to the gates of the sixteenth transistor T16, the seventeenth transistor T17 and the tenth transistor T10 through the fourteenth transistor T14, and controls the sixteenth transistor T16 and the seventeenth transistor T17 to be turned on, and the tenth transistor T10 is turned off. The first pulse width control signal line PWM-CK transmits the first pulse width control signal to the gate of the eighth transistor T8 through the sixteenth transistor T16, and the second pulse modulation signal line PWM-XCK transmits the second pulse width control signal to the gate of the ninth transistor T9 through the seventeenth transistor T17. The first pulse width control signal and the second pulse width control signal control the eighth transistor T8 and the ninth transistor T9 to be alternately turned on, thereby outputting the high / low potential pulses of the second pulse signal EM(n).

[0102] The present application also provides a display panel. Fig.19 , Fig.19 This is a schematic diagram of the structure of an embodiment of a display panel provided by the present application. Fig.19 As shown, the display panel 100 includes a display area 1001 and a non-display area 1002. The non-display area 1002 on one side or opposite sides of the display panel 100 is provided with a gate driving circuit as described in any of the above embodiments, and the gate driving circuit includes a plurality of cascaded gate driving units. The gate driving circuit transmits a first pulse signal Pscan(n) and a second pulse signal EM(n) to each row of pixel units in the display area 1001 in sequence.

[0103] Each pixel unit in the display area 1001 includes a pixel driving circuit. Fig. 20 , Fig. 20A schematic diagram of the structure of an embodiment of a pixel driving circuit provided by the present application. The gate driving circuit sequentially transmits a first pulse signal Pscan(n) and a second pulse signal EM(n) to the pixel driving circuit in each row of pixel units in the display area 1001. In the sampling phase, the first pulse signal Pscan(n) controls the data writing transistor TF2 to write a data signal to the gate of the driving transistor DTFT of the pixel driving circuit; in the light-emitting phase, the second pulse signal EM(n) transmits a switching signal to the switching transistors TF4 and TF5, so that the driving transistor DTFT drives the light-emitting device OLED to emit light.

[0104] The present application designs the above-mentioned gate drive circuit to minimize the use of input signals while allowing a GOA circuit to transmit scan signals and switch signals to the pixel unit, thereby saving circuit expenses and reducing border width.

[0105] The above are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A gate drive circuit, characterized in that: The gate driving circuit includes a multi-stage cascaded gate driving unit, and the gate driving unit includes: A first output unit, configured to output a first pulse signal, wherein the first pulse signal is a low potential pulse with a normal high potential; A second output unit, used to output a second pulse signal, wherein the second pulse signal is a pulse width modulation signal accompanied by a high potential pulse; a first control unit, connected to the control end of the first output unit, and used to control the first output unit to output a first pulse signal; The second control unit is connected to the control end of the second output unit and is used to control the second output unit to output a second pulse signal.

2. The gate driving circuit according to claim 1, characterized in that: The first output unit includes a first sub-output unit and a second sub-output unit; The first sub-output unit is connected to the high-potential signal line and is used to output a high-potential pulse according to the control signal output by the first control unit; The second sub-output unit is connected to the low-potential signal line, and is used to output a low-potential pulse according to the control signal output by the first control unit.

3. The gate driving circuit according to claim 2, characterized in that: The first control unit comprises: The first sub-control unit is connected to the control end of the first sub-output unit, and is used to output a conduction signal to the first sub-output unit to control the first sub-output unit to output a high potential pulse; a low potential control unit connected to the control ends of the first sub-control unit and the second sub-output unit, and configured to transmit a low potential control signal to the control ends of the first sub-control unit and the second sub-output unit, thereby controlling the second sub-output unit and controlling the first sub-output unit through the first sub-control unit; A high potential holding unit is connected to the control ends of the first sub-control unit and the second sub-output unit, and is used to keep the control ends of the first sub-control unit and the second sub-output unit at a high potential, thereby controlling the outputs of the first sub-output unit and the second sub-output unit.

4. The gate driving circuit according to claim 3, characterized in that: The first control unit also includes: A first cascade unit, connected to the first output unit of the previous stage, and configured to receive a first pulse signal transmitted by the first output unit of the previous stage; A first storage unit, connected to the first cascade unit, and used to store a potential signal of the first pulse signal of the previous stage; wherein the potential signal includes a high potential and a low potential; A delay control unit is connected to the first storage unit and the control end of the low potential control unit, and is used to transmit the potential signal stored in the first storage unit to the control end of the low potential control unit to control the on / off of the low potential control unit.

5. The gate driving circuit according to claim 4, characterized in that: Control ends of the first cascade unit and the delay control unit are connected to a group of control signal lines with opposite pulse phases.

6. The gate driving circuit according to claim 3, characterized in that: The first sub-control unit comprises: Low potential signal line; A first transistor, wherein the input end of the first transistor is connected to the low potential signal line, the output end of the first transistor is connected to the control end of the first sub-output unit, the control end of the first transistor is connected to the high potential holding unit and the low potential control unit, and is used to control the low potential signal line to output a conduction signal to the first sub-output unit according to the control signals output by the high potential holding unit and the low potential control unit; wherein the first transistor is an N-type transistor.

7. The gate driving circuit according to claim 3, characterized in that: The high potential holding unit includes a high potential signal line and a first resistor, and the high potential signal line is connected to the control ends of the first sub-control unit and the first sub-output unit through the first resistor.

8. The gate driving circuit according to claim 1, characterized in that: The second output unit comprises: A third sub-output unit is connected to the low potential signal line and is used to output a low potential pulse according to the first pulse width control signal; a fourth sub-output unit, connected to the high potential signal line, and configured to output a high potential pulse of a pulse width control signal according to the second pulse width control signal; a fifth sub-output unit, connected to the high potential signal line, and configured to output a high potential according to the control signal output by the second control unit; a first pulse width modulation unit, connected to the control end of the third sub-output unit, and configured to output the first pulse width modulation signal to the control end of the third sub-output unit; a second pulse width modulation unit, connected to the control end of the fourth sub-output unit, and configured to output the second pulse width modulation signal to the control end of the fourth sub-output unit; The first pulse width control signal and the second pulse width control signal are a set of level signals with opposite pulse phases.

9. The gate driving circuit according to claim 8, characterized in that: The second control unit comprises: A first potential control unit, whose input end is connected to the high potential signal line, and whose output end is connected to the control ends of the first pulse width modulation unit, the second pulse width modulation unit and the fifth sub-output unit, and is used to transmit a high potential control signal to the control ends of the first pulse width modulation unit, the second pulse width modulation unit and the fifth sub-output unit; A second potential control unit, whose input end is connected to the low potential signal line, and whose output end is connected to the control ends of the first pulse width modulation unit, the second pulse width modulation unit and the fifth sub-output unit, is used to transmit a low potential control signal to the control ends of the first pulse width modulation unit, the second pulse width modulation unit and the fifth sub-output unit.

10. The gate driving circuit according to claim 9, characterized in that: The second control unit also includes: A high potential control unit, connected to the control ends of the first potential control unit and the second potential control unit, and used to control the on / off of the first potential control unit and the second potential control unit; a low potential holding unit connected to the control ends of the first potential control unit and the second potential control unit and the output end of the high potential control unit, and configured to control the control ends of the first potential control unit and the second potential control unit to be at a low potential when the high potential control unit does not output; The first potential control unit and the second potential control unit include a group of transistors with opposite driving characteristics.

11. The gate driving circuit according to claim 10, characterized in that: The second control unit also includes: A second cascade unit, connected to the second output unit of the previous stage, and configured to receive a second pulse signal output by the second output unit of the previous stage; a first storage control unit, connected to the second cascade unit, and configured to transmit a control signal according to the second cascade unit; a third storage unit, connected to the first storage control unit, and configured to store the control signal transmitted by the first storage control unit; a second storage control unit, connected to the third storage unit, and used to control the third storage unit to transmit the control signal to the control end of the high potential control unit; a fourth storage unit, connected to the second storage control unit, and configured to store the control signal transmitted by the second storage control unit; Wherein, the control ends of the first storage control unit and the second storage control unit are respectively connected to two control signal lines with opposite pulse phases.

12. The gate driving circuit according to claim 11, characterized in that: The second control unit also includes: A reset signal line is connected to the third storage unit and is used to transmit a reset signal to the third storage unit, and then transmit a reset signal to the fourth storage unit.

13. The gate driving circuit according to claim 10, characterized in that: The low potential holding unit includes a low potential signal line and a second resistor, and the low potential signal line is connected to the control ends of the first potential control unit and the second potential control unit through the second resistor.

14. The gate driving circuit according to claim 11, characterized in that: The second control unit also includes: The reset unit includes a low potential signal line and a third resistor, is connected to the input end of the first storage control unit, and is used to transmit a low potential reset signal to the third storage unit and the fourth storage unit.

15. A display panel, characterized in that: The display panel comprises the gate driving circuit according to any one of claims 1 to 14.

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