Pixel driving circuit and driving method thereof, display substrate and display device

Abstract

The invention discloses a pixel driving circuit, a pixel driving method, a display substrate and a display device. A reset induction sub-circuit, a driving sub-circuit, a node control sub-circuit and a light-emitting control sub-circuit; the driving sub-circuit is configured to provide a driving signal to a third node under the control of the signals of the first node and the second node; the reset induction sub-circuit is configured to provide a reference signal provided by a control signal end for a third node or provide a signal of the first node or the third node for the control signal end under the control of signals of a reset signal end and an induction control signal end; the node control sub-circuit is configured to provide a signal of a data signal end for a first node under the control of a signal of a scanning signal end, and store a voltage difference between the signal of the first node and the signal of a first power supply end; and the light-emitting control sub-circuit is configured to provide the signal of the first power supply end to the second node under the control of the signal of the light-emitting control signal end.

Description

Technical Field

[0001] The present disclosure relates to but is not limited to the field of display technology, and specifically to a pixel driving circuit and a driving method thereof, a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) is an active light-emitting display device with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, and extremely high response speed. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED as the light-emitting device and thin film transistors (TFT) for signal control have become the mainstream products in the current display field.

[0003] At present, the concept of full-screen mobile phones has received widespread attention in the mobile phone market and is also the development direction of future mobile phones. In this full-screen mobile phone, the camera can be hidden so that the front visible area is almost entirely the screen, so that users can get a better display effect. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, the present disclosure provides a pixel driving circuit configured to drive a light-emitting device to emit light, comprising: a reset sensing subcircuit, a driving subcircuit, a node control subcircuit and a light-emitting control subcircuit;

[0006] The driving subcircuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node under the control of the signals of the first node and the second node;

[0007] The reset sensing sub-circuit is electrically connected to the sensing control signal terminal, the reset signal terminal, the control signal terminal, the first node and the third node respectively, and is configured to provide the reference signal provided by the control signal terminal to the third node, or provide the signal of the first node or the third node to the control signal terminal under the control of the signals of the reset signal terminal and the sensing control signal terminal;

[0008] The node control subcircuit is electrically connected to the scan signal terminal, the data signal terminal, the first node and the first power supply terminal respectively, and is configured to provide the signal of the data signal terminal to the first node under the control of the signal of the scan signal terminal, and store the voltage difference between the signal of the first node and the signal of the first power supply terminal;

[0009] The light emitting control subcircuit is electrically connected to the light emitting control signal terminal, the first power supply terminal and the second node respectively, and is configured to provide the signal of the first power supply terminal to the second node under the control of the signal of the light emitting control signal terminal;

[0010] The light emitting device is electrically connected to the third node and the second power supply terminal respectively.

[0011] In an exemplary embodiment, the reset sensing subcircuit includes: a first sensing subcircuit and a second sensing subcircuit;

[0012] The first sensing sub-circuit is electrically connected to the reset signal terminal, the control signal terminal and the third node respectively, and is configured to provide the reference signal provided by the control signal terminal to the third node, or provide the signal of the third node to the control signal terminal, under the control of the signal of the reset signal terminal;

[0013] The second sensing sub-circuit is electrically connected to the sensing control signal terminal, the control signal terminal and the first node respectively, and is configured to provide the signal of the first node to the control signal terminal under the control of the signal of the sensing control signal terminal.

[0014] In an exemplary embodiment, the first sensing subcircuit includes: a first transistor, and the second sensing subcircuit includes: a second transistor;

[0015] The gate electrode of the first transistor is electrically connected to the reset signal terminal, the first electrode of the first transistor is electrically connected to the control signal terminal, and the second electrode of the first transistor is electrically connected to the third node;

[0016] A gate electrode of the second transistor is electrically connected to the sensing control signal terminal, a first electrode of the second transistor is connected to the control signal terminal, and a second electrode of the second transistor is electrically connected to the first node.

[0017] In an exemplary embodiment, the reset sensing subcircuit includes: a first transistor and a second transistor, the driving subcircuit includes: a third transistor, the node control subcircuit includes: a fourth transistor and a capacitor, the capacitor includes: a first plate and a second plate, and the light emitting control subcircuit includes: a fifth transistor;

[0018] The gate electrode of the first transistor is electrically connected to the reset signal terminal, the first electrode of the first transistor is electrically connected to the control signal terminal, and the second electrode of the first transistor is electrically connected to the third node;

[0019] The gate electrode of the second transistor is electrically connected to the sensing control signal terminal, the first electrode of the second transistor is connected to the control signal terminal, and the second electrode of the second transistor is electrically connected to the first node;

[0020] The gate electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node;

[0021] The gate electrode of the fourth transistor is electrically connected to the scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the first node;

[0022] The gate electrode of the fifth transistor is electrically connected to the light emitting control signal terminal, the first electrode of the fifth transistor is connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node;

[0023] The first plate of the capacitor is connected to the first node, and the second plate of the capacitor is electrically connected to the first power supply terminal.

[0024] In an exemplary embodiment, the first transistor, the second transistor, and the fourth transistor are N-type transistors, and the third transistor and the fifth transistor are P-type transistors.

[0025] In a second aspect, the present disclosure further provides a driving method of a pixel driving circuit, which is configured to drive the above-mentioned pixel driving circuit, wherein the pixel driving circuit is arranged in a display substrate, and the working process of the display substrate includes: a display phase and a non-display phase;

[0026] In the display stage and the non-display stage, the driving method of the pixel driving circuit includes:

[0027] The driving subcircuit provides a driving signal to the third node under the control of the signals of the first node and the second node;

[0028] The reset sensing subcircuit provides the reference signal provided by the control signal terminal to the third node, or provides the signal of the first node or the third node to the control signal terminal, under the control of the signals of the reset signal terminal and the sensing control signal terminal;

[0029] The node control subcircuit provides the signal of the data signal terminal to the first node under the control of the signal of the scan signal terminal, and stores the voltage difference between the signal of the first node and the signal of the first power terminal;

[0030] The light emitting control subcircuit provides the signal of the first power supply terminal to the second node under the control of the signal of the light emitting control signal terminal.

[0031] In an exemplary embodiment, the display phase includes: a first reset phase, a first data writing phase, and a light emitting phase;

[0032] The signal of the sensing control signal end in the display stage is an invalid level signal, the signal of the reset signal end in the first reset stage is a valid level signal, and the signal in the first data writing stage and the light emitting stage is an invalid level signal, the signal of the scanning signal end in the first data writing stage is a valid level signal, and the signal in the first reset stage and the light emitting stage is an invalid level signal, the signal of the light emitting control signal end in the light emitting stage is a valid level signal, and the signal in the first reset stage and the first data writing stage is an invalid level signal;

[0033] In the display stage, the driving method of the pixel driving circuit includes:

[0034] In the first reset phase, the reset sensing subcircuit provides the reference signal provided by the control signal terminal to the third node under the control of the signal at the reset signal terminal;

[0035] In the first data writing phase, the node control subcircuit provides the signal of the data signal terminal to the first node under the control of the signal of the scan signal terminal, and stores the voltage difference between the signal of the first node and the signal of the first power terminal;

[0036] In the light-emitting stage, the light-emitting control subcircuit provides the signal of the first power supply end to the second node under the control of the signal of the light-emitting control signal end, and the driving subcircuit provides the driving signal to the third node under the control of the signals of the first node and the second node.

[0037] In an exemplary embodiment, the non-display phase includes: a first sensing phase, the first sensing phase occurs before the display phase, the first sensing phase includes: a second reset phase, a second data writing phase and a first sampling phase;

[0038] The signal of the sensing control signal end in the first sensing stage is an invalid level signal, the signal of the reset signal end in the second reset stage and the first sampling stage is a valid level signal, and the signal in the second data writing stage is an invalid level signal, the signal of the scanning signal end in the second data writing stage is a valid level signal, and the signal in the second reset stage and the first sampling stage is an invalid level signal, the signal of the light emitting control signal end in the first sampling stage is a valid level signal, and the signal in the second reset stage and the second data writing stage is an invalid level signal;

[0039] In the first sensing stage, the driving method of the pixel driving circuit includes:

[0040] In the second reset phase, the reset sensing subcircuit provides the reference signal provided by the control signal terminal to the third node under the control of the signal at the reset signal terminal;

[0041] In the second data writing phase, the node control subcircuit provides the signal of the data signal terminal to the first node under the control of the signal of the scan signal terminal, and stores the voltage difference between the signal of the first node and the signal of the first power terminal;

[0042] In the first sampling stage, the light-emitting control subcircuit provides the signal of the first power supply terminal to the second node under the control of the signal of the light-emitting control signal terminal, the driving subcircuit provides the driving signal to the third node under the control of the signals of the first node and the second node, and the reset sensing subcircuit provides the signal of the third node to the control signal terminal under the control of the signal of the reset signal terminal.

[0043] In an exemplary embodiment, the display substrate further includes: an integrated circuit electrically connected to the pixel driving circuit;

[0044] The integrated circuit acquires the signal of the third node, processes the signal of the third node, and provides the processed signal of the third node to the pixel driving circuit to compensate for the brightness of the light emitting device.

[0045] In an exemplary embodiment, the non-display phase includes: a second sensing phase, the second sensing phase occurs before the display phase, the second sensing phase includes: a third reset phase, a third data writing phase, and a second sampling phase;

[0046] The signal of the reset signal end in the third reset stage is a valid level signal, and the signal in the third data writing stage and the second sampling stage is an invalid level signal, the signal of the scanning signal end in the third data writing stage is a valid level signal, and the signal in the third reset stage and the second sampling stage is an invalid level signal, the signal of the light emitting control signal end in the second sampling stage is a valid level signal, and the signal in the third reset stage and the third data writing stage is an invalid level signal, the signal of the sensing control signal end in the second sampling stage is a valid level signal, and the signal in the third reset stage and the third data writing stage is an invalid level signal;

[0047] In the second sensing stage, the driving method of the pixel driving circuit includes:

[0048] In the third reset stage, the reset sensing subcircuit provides the reference signal provided by the control signal terminal to the third node under the control of the signal of the reset signal terminal;

[0049] In the third data writing phase, the node control subcircuit provides the signal of the data signal terminal to the first node under the control of the signal of the scan signal terminal, and stores the voltage difference between the signal of the first node and the signal of the first power terminal;

[0050] In the second sampling stage, the light-emitting control subcircuit provides the signal of the first power supply terminal to the second node under the control of the signal of the light-emitting control signal terminal, the driving subcircuit provides the driving signal to the third node under the control of the signals of the first node and the second node, and the reset sensing subcircuit provides the signal of the first node to the control signal terminal under the control of the signal of the sensing control signal terminal.

[0051] In an exemplary embodiment, the display substrate further includes: an integrated circuit electrically connected to the pixel driving circuit;

[0052] The integrated circuit acquires the signal of the first node, processes the signal of the first node, and provides the processed signal of the first node to the pixel driving circuit to compensate for the threshold voltage of the driving transistor in the pixel driving circuit.

[0053] In a third aspect, the present disclosure further provides a display substrate, comprising: a substrate, the substrate comprising: a display area and a non-display area surrounding the display area, the display area comprising: a first display area and a second display area, the second display area being located at least on one side of the first display area;

[0054] The first display area includes: a plurality of first sub-pixels, the second display area includes: a plurality of second sub-pixels, and at least one of the first sub-pixels and the second sub-pixels includes: the pixel driving circuit according to any one of claims 1 to 5.

[0055] In an exemplary embodiment, the pixel driving circuit includes: at least one P-type transistor and at least one N-type transistor;

[0056] An orthographic projection of the at least one P-type transistor on the substrate at least partially overlaps with an orthographic projection of the at least one N-type transistor on the substrate.

[0057] In an exemplary embodiment, the transistor includes an active pattern, and an orthographic projection of the active pattern of the at least one N-type transistor on the substrate at least partially overlaps an orthographic projection of the active pattern of the at least one P-type transistor on the substrate.

[0058] In an exemplary embodiment, an orthographic projection of the active pattern of the at least one N-type transistor on the substrate is located within an orthographic projection of the active pattern of the at least one P-type transistor on the substrate.

[0059] In an exemplary embodiment, the display area further includes: at least one first power line;

[0060] The orthographic projection of the first power line on the substrate at least partially overlaps with the orthographic projection of the active pattern of the at least one P-type transistor on the substrate, and the orthographic projection of the first power line on the substrate at least partially overlaps with the orthographic projection of the active pattern of the at least one N-type transistor on the substrate;

[0061] The active pattern of the at least one P-type transistor is located on a side of the first power line close to the substrate, and the active pattern of the at least one N-type transistor is located on a side of the first power line far from the substrate.

[0062] In an exemplary embodiment, the display area further includes: pixel units arranged in an array, at least one light emitting control signal line, at least one reset signal line, at least one scanning signal line, at least one sensing control signal line, at least one data signal line, at least one control signal line and at least one first power supply line, at least one pixel unit includes: at least one sub-pixel arranged along the first direction;

[0063] The at least one pixel unit is electrically connected to the light emitting control signal line, the reset signal line, the scanning signal line, the sensing control signal line, N data signal lines, N control signal lines and N first power lines, respectively, where N is the number of sub-pixels in a pixel unit.

[0064] In an exemplary embodiment, pixel structures of adjacent sub-pixels among the plurality of sub-pixels arranged along the first direction are at least partially symmetrically disposed with respect to a virtual straight line extending along a second direction, and the first direction and the second direction intersect.

[0065] In an exemplary embodiment, the display area further includes: at least one data signal line and at least one control signal line, the data signal line and the control signal line at least partially extending along the second direction;

[0066] The data signal line is electrically connected to a data signal terminal connected to the pixel driving circuit, and the control signal line is electrically connected to a control signal terminal connected to the pixel driving circuit;

[0067] The data signal lines connecting adjacent sub-pixels among the multiple sub-pixels arranged along the first direction are symmetrically arranged relative to the center line of the adjacent sub-pixels, and the control signal lines connecting adjacent sub-pixels among the multiple sub-pixels arranged along the first direction are symmetrically arranged relative to the center line of the adjacent sub-pixels.

[0068] In an exemplary embodiment, the display area further includes: at least one first power line; the first power line at least partially extending along the second direction;

[0069] The first power line is electrically connected to the first power terminal connected to the pixel driving circuit, adjacent first power lines are electrically connected, and the first power lines connected to adjacent sub-pixels in a plurality of sub-pixels arranged along the first direction are symmetrically arranged relative to the midline of the adjacent sub-pixels.

[0070] In an exemplary embodiment, the first power line includes: a first connection line, a second connection line and a plurality of connection blocks, the first connection line and the second connection line are arranged along a first direction and extend along a second direction, the connection block is arranged between the first connection line and the second connection line, and the pixel driving circuit includes: a capacitor, the capacitor includes: a first electrode plate and a second electrode plate;

[0071] The orthographic projection of the connecting block on the substrate at least partially overlaps with the orthographic projection of the first electrode plate on the substrate, and the multiple connecting blocks located between the first connecting line and the second connecting line are arranged along the second direction and are arranged at intervals, and a closed area is formed between adjacent connecting blocks arranged along the second direction and adjacent first connecting lines and second connecting lines.

[0072] In an exemplary embodiment, the display area further includes: at least one light emitting control signal line, at least one reset signal line, at least one scan signal line, and at least one sensing control signal line, wherein at least one of the light emitting control signal line, the reset signal line, the scan signal line, and the sensing control signal line extends at least partially along the first direction;

[0073] The light emitting control signal line is electrically connected to the light emitting control signal terminal connected to the pixel driving circuit, the reset signal line is electrically connected to the reset signal terminal connected to the pixel driving circuit, the scanning signal line is electrically connected to the scanning signal terminal connected to the pixel driving circuit, and the sensing control signal line is electrically connected to the sensing control signal terminal connected to the pixel driving circuit;

[0074] The orthographic projections of the light emitting control signal line, the scanning signal line, the sensing control signal line and the reset signal line connected to at least one sub-pixel on the substrate are arranged in sequence along the second direction;

[0075] The light emitting control signal line is arranged in a different layer from at least one of the reset signal line, the scanning signal line and the sensing control signal line.

[0076] In an exemplary embodiment, it further includes: a driving structure layer disposed on the substrate, the driving structure layer is provided with an anode connection line, a light emitting control signal line, a reset signal line, a scanning signal line, a sensing control signal line, a first power line, a data signal line, a control signal line and the pixel driving circuit, the driving structure layer at least includes: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer and a fourth conductive layer sequentially stacked in a direction away from the substrate, the pixel driving circuit includes: at least one P-type transistor, at least one N-type transistor and a capacitor, the transistor includes: an active pattern, a gate electrode, a first electrode and a second electrode, the capacitor includes: a first electrode plate and a second electrode plate;

[0077] The first semiconductor layer at least includes: the active pattern of the at least one P-type transistor located in at least one sub-pixel;

[0078] The first conductive layer at least includes: the light emitting control signal line, the gate electrode of the at least one P-type transistor located in at least one sub-pixel, and the first plate of the capacitor;

[0079] The second conductive layer at least includes: the first power line, the second electrode plate of the capacitor located in at least one sub-pixel, and the first electrode and the second electrode of the at least one P-type transistor;

[0080] The second semiconductor layer at least includes: an active pattern of the at least one N-type transistor located in at least one sub-pixel;

[0081] The third conductive layer at least includes: the reset signal line, the scan signal line, the sensing control signal line, and a gate electrode, a first electrode, and a second electrode of the at least one N-type transistor located in at least one sub-pixel;

[0082] The fourth conductive layer at least includes: the data signal line, the control signal line, and the anode connection line located in at least one sub-pixel.

[0083] In an exemplary embodiment, at least a portion of at least one of the data signal line and the control signal line is a transparent conductive signal line.

[0084] In an exemplary embodiment, it further includes: a light emitting structure layer located on a side of the driving structure layer away from the substrate, the light emitting structure layer including: a fifth conductive layer and a pixel definition layer sequentially stacked on the substrate, the fifth conductive layer at least including: a first electrode of the light emitting device, the pixel definition layer is provided with a plurality of pixel openings, the pixel openings including: a first pixel opening, a second pixel opening and a third pixel opening;

[0085] The light emitting device comprises: a first light emitting device, a second light emitting device and a third light emitting device, wherein the first light emitting device, the second light emitting device and the third light emitting device emit light of different colors;

[0086] The first pixel opening exposes the first electrode of the first light emitting device, the second pixel opening exposes the first electrode of the second light emitting device, and the third pixel opening exposes the first electrode of the third light emitting device;

[0087] The area of ​​the first pixel opening located in the first display area is smaller than the area of ​​the first pixel opening located in the second display area, the area of ​​the second pixel opening located in the first display area is smaller than the area of ​​the second pixel opening located in the second display area, and the area of ​​the third pixel opening located in the first display area is smaller than the area of ​​the third pixel opening located in the second display area.

[0088] In an exemplary embodiment, the light transmittance of the first display area is greater than the light transmittance of the second display area, and the sub-pixel density of the first display area is less than or equal to the sub-pixel density of the second display area.

[0089] In a fourth aspect, the present disclosure further provides a display device, comprising the above-mentioned display substrate and a photosensitive sensor;

[0090] The orthographic projection of the photosensor on the substrate at least partially overlaps with the first display area.

[0091] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0092] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0093] Figure 1 A schematic diagram of the structure of a pixel driving circuit provided in an embodiment of the present disclosure;

[0094] Figure 2A A schematic structural diagram of a pixel driving circuit provided in an exemplary embodiment;

[0095] Figure 2B is an equivalent circuit diagram of a first inductive subcircuit and a second inductive subcircuit;

[0096] Figure 3 is an equivalent circuit diagram of a pixel driving circuit;

[0097] Figure 4A for Figure 3 The working timing diagram of the pixel driving circuit in the display stage is provided;

[0098] Figure 4B for Figure 3 The working timing diagram of the pixel driving circuit in the first sensing stage is provided;

[0099] Figure 4C for Figure 3 The provided pixel driving circuit operates in the second sensing phase.

[0100] Figure 5A A schematic diagram showing the structure of a substrate;

[0101] Figure 5B for Figure 5A A partial schematic diagram of the first display area;

[0102] Figure 5C for Figure 5A A partial schematic diagram of the second display area;

[0103] Fig. 6A for Figure 5B and Figure 5C Schematic diagram of some film layers in the display substrate provided Figure 1 ;

[0104] Figure 6B for Figure 5B and Figure 5C Schematic diagram 2 of part of the film layer in the provided display substrate;

[0105] Figure 7 is a schematic diagram of a first semiconductor layer pattern;

[0106] Figure 8 is a schematic diagram of a first conductive layer pattern;

[0107] Fig. 9 is a schematic diagram after forming a first conductive layer pattern;

[0108] Fig.10 is a schematic diagram after forming a second insulating layer;

[0109] Fig.11 is a schematic diagram of a second conductive layer pattern;

[0110] Fig.12 is a schematic diagram after forming a second conductive layer pattern;

[0111] Fig.13 is a schematic diagram after forming a third insulating layer;

[0112] Fig.14 is a schematic diagram of a second semiconductor layer pattern;

[0113] Fig.15 is a schematic diagram after forming a second semiconductor layer pattern;

[0114] Fig.16 is a schematic diagram after forming a fourth insulating layer;

[0115] Fig.17 is a schematic diagram of a pattern of a third conductive layer;

[0116] Fig.18 is a schematic diagram after forming a third conductive layer pattern;

[0117] Fig.19 is a schematic diagram after forming the first flat layer;

[0118] Fig. 20 is a schematic diagram of a fourth conductive layer pattern;

[0119] Fig.21 is a schematic diagram after forming a fourth conductive layer pattern;

[0120] Fig. 22 is a schematic diagram after forming the second flat layer;

[0121] Fig.23 is a schematic diagram of a fifth conductive layer pattern;

[0122] Fig.24 is a schematic diagram after forming a fifth conductive layer pattern;

[0123] Fig.25 A schematic diagram after forming a pixel definition layer;

[0124] Fig.26 A cross-sectional view of a display device. DETAILED DESCRIPTION

[0125] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings hereinafter. Note that the embodiments can be implemented in a number of different forms. A person of ordinary skill in the relevant technical field can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0126] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixel units in the display substrate and the number of sub-pixels in each pixel unit are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0127] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0128] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0129] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0130] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0131] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0132] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0133] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0134] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0135] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the materials of the precursors forming the multiple structures arranged in the same layer are the same, and the materials finally formed may be the same or different.

[0136] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0137] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0138] The full-screen display product includes: a translucent display area and a normal display area. In order to ensure the light transmittance of the translucent display area of ​​the full-screen display product, the pixel circuits and pixel openings located in the translucent display area are compressed, which not only results in poor display effect of the display product, but also reduces the life of the display product.

[0139] Figure 1 Schematic diagram of the structure of the pixel driving circuit provided by the embodiment of the present disclosure. Figure 1As shown, the pixel driving circuit provided by the embodiment of the present disclosure is configured to drive the light-emitting device to emit light, and may include: a reset sensing subcircuit, a driving subcircuit, a node control subcircuit and a light-emitting control subcircuit. Among them, the driving subcircuit is electrically connected to the first node N1, the second node N2 and the third node N3, respectively, and is configured to provide a driving signal to the third node N3 under the control of the signals of the first node N1 and the second node N2; the reset sensing subcircuit is electrically connected to the sensing control signal terminal SW-SENSE, the reset signal terminal Reset, the control signal terminal CON, the first node N1 and the third node N3, respectively, and is configured to provide the reference signal provided by the control signal terminal CON to the third node N3 under the control of the signals of the reset signal terminal Reset and the sensing control signal terminal SW-SENSE, or provide the signal of the first node N1 or the third node N3 to the control signal terminal CON. A node control subcircuit is electrically connected to the scan signal terminal Gate, the data signal terminal Data, the first node N1 and the first power supply terminal VDD, respectively, and is configured to provide the signal of the data signal terminal Data to the first node N1 under the control of the signal of the scan signal terminal Gate, and store the voltage difference between the signal of the first node N1 and the signal of the first power supply terminal VDD; a light emitting control subcircuit is electrically connected to the light emitting control signal terminal EM, the first power supply terminal VDD and the second node N2, respectively, and is configured to provide the signal of the first power supply terminal VDD to the second node N2 under the control of the signal of the light emitting control signal terminal EM; a light emitting device is electrically connected to the third node N3 and the second power supply terminal VSS, respectively.

[0140] In an exemplary embodiment, the light emitting device may include a stacked first electrode (anode), an organic light emitting layer and a second electrode (cathode). Exemplarily, the anode of the light emitting device is electrically connected to the third node N3, and the cathode of the light emitting device is electrically connected to the second power supply terminal VSS.

[0141] In an exemplary embodiment, the light emitting device may include a current driven device, and a current light emitting diode may be used, such as a micro light emitting diode (Micro Light Emitting Diode, Micro LED for short) or a mini light emitting diode (Mini Light Emitting Diode, Mini LED for short) or an organic light emitting diode (Organic Light Emitting Diode, OLED for short) or a quantum dot light emitting diode (Quantum Light Emitting Diode, QLED for short). The typical size (e.g., length) of a Micro LED may be less than 100 μm, such as 10 μm to 50 μm. The typical size (e.g., length) of a Mini LED may be about 100 μm to 300 μm, such as 120 μm to 260 μm.

[0142] In an exemplary embodiment, the organic light emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), an emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, the hole blocking layers of all sub-pixels may be a common layer connected together, the light emitting layers of adjacent sub-pixels may have a small overlap, or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap, or may be isolated.

[0143] In an exemplary embodiment, the first power supply terminal VDD continuously provides a high level signal, and the signal of the first power supply terminal VDD is a DC signal.

[0144] In an exemplary embodiment, the second power terminal VSS continuously provides a low level signal, and the signal of the second power terminal VSS is a DC signal.

[0145] In an exemplary embodiment, the reference signal is a low-level signal and a direct current signal. Exemplarily, the voltage of the reference signal may be 0V.

[0146] In an exemplary embodiment, the reset sensing subcircuit provided by the present disclosure can provide a signal of the first node N1 or the third node N3 to the control signal terminal CON, so that the integrated circuit connected to the control signal terminal can obtain a signal of at least one of the first node N1 and the third node N3, and obtain a threshold voltage of the driving transistor according to the signal of the first node, so as to externally compensate the pixel driving circuit according to the threshold voltage, and obtain a compensation voltage according to the signal of the third node and the device aging model, so as to externally compensate the pixel driving circuit according to the compensation voltage.

[0147] In an exemplary embodiment, the difference between the voltage value of the signal at the first power supply terminal VDD and the voltage value of the signal at the first node is equal to the threshold voltage of the threshold transistor. The device aging model is a data processing model stored in the display device where the pixel driving circuit is located.

[0148] In an exemplary embodiment, externally compensating the pixel driving circuit according to the threshold voltage may include: adjusting a signal at the data signal terminal according to the threshold voltage, thereby externally compensating the pixel driving circuit.

[0149] In an exemplary embodiment, externally compensating the pixel driving circuit according to the compensation voltage may include: adjusting a signal at the data signal terminal according to the compensation voltage, thereby externally compensating the pixel driving circuit.

[0150] The pixel driving circuit provided by the embodiment of the present disclosure is configured to drive the light-emitting device to emit light, and includes: a reset sensing subcircuit, a driving subcircuit, a node control subcircuit and a light-emitting control subcircuit; wherein the driving subcircuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node under the control of the signals of the first node and the second node; the reset sensing subcircuit is electrically connected to the sensing control signal terminal, the reset signal terminal, the control signal terminal, the first node and the third node respectively, and is configured to provide the reference signal provided by the control signal terminal to the third node under the control of the signals of the reset signal terminal and the sensing control signal terminal. A reference signal is provided, or a signal of a first node or a third node is provided to a control signal terminal; a node control subcircuit is electrically connected to a scan signal terminal, a data signal terminal, a first node and a first power supply terminal respectively, and is configured to provide a signal of a data signal terminal to the first node under the control of a signal of a scan signal terminal, and store a voltage difference between a signal of the first node and a signal of the first power supply terminal; a light-emitting control subcircuit is electrically connected to a light-emitting control signal terminal, a first power supply terminal and a second node respectively, and is configured to provide a signal of a first power supply terminal to the second node under the control of a signal of a light-emitting control signal terminal; and a light-emitting device is electrically connected to a third node and a second power supply terminal respectively. The control signal terminal in the reset sensing subcircuit in the present disclosure can not only provide a reference signal, but also obtain parameters of a pixel driving circuit (such as a first node and a third node) to compensate for the pixel driving circuit, which can reduce the number of devices in the pixel driving circuit, reduce the area occupied by the pixel driving circuit, and ensure that the pixel driving circuit is not affected by a threshold voltage, thereby avoiding the pixel driving circuit from being compressed when applied to a full-screen display product, improving the display effect of the display product, and improving the display life of the display product.

[0151] In an exemplary embodiment, Figure 2A FIG. 1 is a schematic diagram of a pixel driving circuit provided in an exemplary embodiment. Figure 2AAs shown, the reset sensing subcircuit in the pixel driving circuit may include: a first sensing subcircuit and a second sensing subcircuit. The first sensing subcircuit is electrically connected to the reset signal terminal Reset, the control signal terminal CON and the third node N3, respectively, and is configured to provide the reference signal provided by the control signal terminal CON to the third node N3, or provide the signal of the third node N3 to the control signal terminal CON under the control of the signal of the reset signal terminal Reset; the second sensing subcircuit is electrically connected to the sensing control signal terminal SW-SENSE, the control signal terminal CON and the first node N1, respectively, and is configured to provide the signal of the first node N1 to the control signal terminal CON under the control of the signal of the sensing control signal terminal SW-SENSE.

[0152] In an exemplary embodiment, the first sensing subcircuit may obtain a signal of the third node, ie, an anode voltage of the light emitting device, and may further perform external compensation on the pixel driving circuit.

[0153] In an exemplary embodiment, the second sensing sub-circuit may obtain a signal of the first node, and thus may perform external compensation on the pixel driving circuit.

[0154] In an exemplary embodiment, Figure 2B is the equivalent circuit diagram of the first inductive subcircuit and the second inductive subcircuit. Figure 2B As shown, the first sensing sub-circuit may include: a first transistor T1, and the second sensing sub-circuit may include: a second transistor T2. The gate electrode of the first transistor T1 is electrically connected to the reset signal terminal Reset, the first electrode of the first transistor T1 is electrically connected to the control signal terminal CON, and the second electrode of the first transistor T1 is electrically connected to the third node N3; the gate electrode of the second transistor T2 is electrically connected to the sensing control signal terminal SW-SENSE, the first electrode of the second transistor T2 is connected to the control signal terminal CON, and the second electrode of the second transistor T2 is electrically connected to the first node N1.

[0155] Figure 2B Only an exemplary structure of the first inductive sub-circuit and the second inductive sub-circuit is shown. It is easy for those skilled in the art to understand that the implementation of the first inductive sub-circuit and the second inductive sub-circuit is not limited thereto.

[0156] In an exemplary embodiment, Figure 3 is the equivalent circuit diagram of the pixel driving circuit. Figure 3As shown, the reset sensing subcircuit in the pixel driving circuit includes: a first transistor T1 and a second transistor T2, the driving subcircuit includes: a third transistor T3, the node control subcircuit includes: a fourth transistor T4 and a capacitor C, the capacitor C includes: a first electrode plate and a second electrode plate, and the light emitting control subcircuit includes: a fifth transistor T5. Among them, the gate electrode of the first transistor T1 is electrically connected to the reset signal terminal Reset, the first electrode of the first transistor T1 is electrically connected to the control signal terminal CON, and the second electrode of the first transistor T1 is electrically connected to the third node N3; the gate electrode of the second transistor T2 is electrically connected to the sensing control signal terminal SW-SENSE, the first electrode of the second transistor T2 is connected to the control signal terminal CON, and the second electrode of the second transistor T2 is electrically connected to the first node N1; the gate electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the third transistor T3 is electrically connected to the sensing control signal terminal SW-SENSE. The second electrode of the transistor T3 is electrically connected to the third node N3; the gate electrode of the fourth transistor T4 is electrically connected to the scan signal terminal Gate, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is electrically connected to the first node N1; the gate electrode of the fifth transistor T5 is electrically connected to the light emitting control signal terminal EM, the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the first plate of the capacitor C is connected to the first node N1, and the second plate of the capacitor C is electrically connected to the first power supply terminal VDD.

[0157] According to the characteristics of the transistor, the transistor can be divided into an N-type transistor and a P-type transistor. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages).

[0158] In an exemplary embodiment, the first transistor T1, the second transistor T2 and the fourth transistor T4 are N-type transistors and are metal oxide transistors. In an exemplary embodiment, the N-type transistors may be oxide thin film transistors. The active pattern of the oxide thin film transistors uses oxide semiconductors (Oxide). Oxide thin film transistors have advantages such as low leakage current.

[0159] In an exemplary embodiment, the third transistor T3 and the fifth transistor T5 are P-type transistors. In an exemplary embodiment, the P-type transistors may be low temperature polysilicon transistors.

[0160] In an exemplary embodiment, the first transistor T1 , the second transistor T2 , and the fourth transistor T4 are N-type transistors, which can reduce leakage currents of the first node and the third node and improve the reliability of the pixel driving circuit.

[0161] In an exemplary embodiment, the pixel driving circuit may be disposed in a display substrate, the operation process of the display substrate includes a display phase and a non-display phase, and the operation process of the pixel driving circuit in the non-display phase includes: a first sensing phase and a second sensing phase. The first sensing phase and the second sensing phase occur before the display phase.

[0162] In an exemplary embodiment, the first sensing phase and the second sensing phase may occur simultaneously.

[0163] In an exemplary embodiment, the operation process of the pixel driving circuit in the display stage includes: a first reset stage, a first data writing stage and a light emitting stage. Among them, the control signal terminal provides a reference signal in the display stage, and the signal of the sensing control signal terminal in the display stage is an invalid level signal. The signal of the reset signal terminal in the first reset stage is a valid level signal, and the signal of the first data writing stage and the light emitting stage is an invalid level signal. The signal of the scanning signal terminal in the first data writing stage is a valid level signal, and the signal of the first reset stage and the light emitting stage is an invalid level signal. The signal of the light emitting control signal terminal in the light emitting stage is a valid level signal, and the signal of the first reset stage and the first data writing stage is an invalid level signal.

[0164] In an exemplary embodiment, the operation process of the pixel driving circuit in the first sensing stage includes: a second reset stage, a second data writing stage and a first sampling stage. The control signal terminal provides a reference signal in the second reset stage and the second data writing stage, and obtains the signal of the third node in the first sampling stage. The signal of the sensing control signal terminal in the first sensing stage is an invalid level signal. The signal of the reset signal terminal in the second reset stage and the first sampling stage is a valid level signal, and the signal in the second data writing stage is an invalid level signal. The signal of the scanning signal terminal in the second data writing stage is a valid level signal, and the signal in the second reset stage and the first sampling stage is an invalid level signal. The signal of the light emitting control signal terminal in the first sampling stage is a valid level signal, and the signal in the second reset stage and the second data writing stage is an invalid level signal.

[0165] In an exemplary embodiment, the operation process of the pixel driving circuit in the second sensing stage includes: a third reset stage, a third data writing stage, and a second sampling stage. Among them, the control signal terminal provides a reference signal in the third reset stage and the third data writing stage, and obtains the signal of the first node in the second sampling stage. The signal of the reset signal terminal in the third reset stage is a valid level signal, and the signal in the third data writing stage and the second sampling stage is an invalid level signal. The signal of the scanning signal terminal in the third data writing stage is a valid level signal, and the signal in the third reset stage and the second sampling stage is an invalid level signal. The signal of the light emitting control signal terminal in the second sampling stage is a valid level signal, and the signal in the third reset stage and the third data writing stage is an invalid level signal. The signal of the sensing control signal terminal in the second sampling stage is a valid level signal, and the signal in the third reset stage and the third data writing stage is an invalid level signal.

[0166] In an exemplary embodiment, the first sensing phase and the second sensing phase may occur simultaneously, which means that the first sampling phase and the second sampling phase occur simultaneously, ie, the pixel driving circuit acquires signals of the first node and the third node.

[0167] Figure 4A for Figure 3 The working timing diagram of the pixel driving circuit in the display stage is provided. Figure 3 The working process of the exemplary pixel driving circuit in the display stage illustrates the exemplary embodiments of the present disclosure. Figure 3 The pixel driving circuit includes five transistors (a first transistor T1 to a fifth transistor T5) and a capacitor (capacitor C), the first transistor T1, the second transistor T2 and the fourth transistor T4 are N-type transistors, and the third transistor T3 and the fifth transistor T5 are P-type transistors.

[0168] In an exemplary embodiment, Figure 3 The working process of the provided pixel driving circuit in the display stage may include:

[0169] The first stage A1 is called the first reset stage. The signals of the reset signal terminal Reset and the light-emitting control signal terminal EM are high-level signals, the signals of the sensing control signal terminal SW-SENSE and the scanning signal terminal Gate are low-level signals, and the control signal terminal CON provides a reference signal, wherein Vref is the voltage value of the reference signal. The signal of the reset signal terminal Reset is a high-level signal, the first transistor T1 is turned on, the reference signal of the control signal terminal CON is written into the third node N3, the third node N3, i.e., the anode of the light-emitting device L, is initialized, and the original charge of the third node N3 is cleared. The signal of the light-emitting control signal terminal EM is a high-level signal, the signals of the sensing control signal terminal SW-SENSE and the scanning signal terminal Gate are low-level signals, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off. In this stage, the light-emitting device L does not emit light.

[0170] In the second stage A2, the first data writing stage, the signals of the scanning signal terminal Gate and the light-emitting control signal terminal EM are high-level signals, the signals of the sensing control signal terminal SW-SENSE and the reset signal terminal Reset are low-level signals, the control signal terminal CON provides a reference signal, and the data signal terminal Data outputs a data voltage. The signal of the scanning signal terminal Gate is a high-level signal, the fourth transistor T4 is turned on, and the data voltage of the data signal terminal Data is written into the first node N1. The signal of the light-emitting control signal terminal EM is a high-level signal, the signals of the sensing control signal terminal SW-SENSE and the reset signal terminal Reset are low-level signals, and the first transistor T1, the second transistor T2, and the fifth transistor T5 are turned off. In this stage, the light-emitting device L does not emit light.

[0171] In the third stage A3, i.e., the light-emitting stage, the signals of the scanning signal terminal Gate, the light-emitting control signal terminal EM, the sensing control signal terminal SW-SENSE and the reset signal terminal Reset are low-level signals, and the control signal terminal CON provides a reference signal. The signal of the light-emitting control signal terminal EM is a low-level signal, the fifth transistor T5 is turned on, and the power supply voltage output by the first power supply terminal VDD provides a driving voltage to the anode of the light-emitting device L through the turned-on fifth transistor T5 and the third transistor T3, driving the light-emitting device L to emit light, the signals of the scanning signal terminal Gate, the sensing control signal terminal SW-SENSE and the reset signal terminal Reset are low-level signals, and the first transistor T1, the second transistor T2 and the fourth transistor T4 are turned off. In this stage, the light-emitting device L emits light.

[0172] Figure 4B for Figure 3 The pixel driving circuit provided is a working timing diagram in the first sensing phase. Figure 3 The working process of the exemplary pixel driving circuit in the first sensing stage illustrates an exemplary embodiment of the present disclosure. Figure 3The pixel driving circuit includes five transistors (first transistor T1 to fifth transistor T5) and a capacitor (capacitor C), the first transistor T1, the second transistor T2 and the fourth transistor T4 are N-type transistors, and the third transistor T3 and the fifth transistor T5 are P-type transistors.

[0173] In an exemplary embodiment, Figure 3 The working process of the provided pixel driving circuit in the first sensing stage may include:

[0174] The first stage B1 is called the second reset stage. The signals of the reset signal terminal Reset and the light-emitting control signal terminal EM are high-level signals, the signals of the sensing control signal terminal SW-SENSE and the scanning signal terminal Gate are low-level signals, and the control signal terminal CON provides a reference signal, wherein Vref is the voltage value of the reference signal. The signal of the reset signal terminal Reset is a high-level signal, the first transistor T1 is turned on, the reference signal of the control signal terminal CON is written into the third node N3, the third node N3, i.e., the anode of the light-emitting device L, is initialized, and the original charge of the third node N3 is cleared. The signal of the light-emitting control signal terminal EM is a high-level signal, the signals of the sensing control signal terminal SW-SENSE and the scanning signal terminal Gate are low-level signals, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off.

[0175] In the second stage B2, the second data writing stage, the signals of the scanning signal terminal Gate and the light emitting control signal terminal EM are high level signals, the signals of the sensing control signal terminal SW-SENSE and the reset signal terminal Reset are low level signals, the control signal terminal CON provides a reference signal, and the data signal terminal Data outputs a data voltage. The signal of the scanning signal terminal Gate is a high level signal, the fourth transistor T4 is turned on, and the data voltage of the data signal terminal Data is written into the first node N1. The signal of the light emitting control signal terminal EM is a high level signal, the signals of the sensing control signal terminal SW-SENSE and the reset signal terminal Reset are low level signals, and the first transistor T1, the second transistor T2, and the fifth transistor T5 are turned off.

[0176] In the third stage B3, i.e., the first sampling stage, the signal of the reset signal terminal Reset is a high-level signal, the signals of the scanning signal terminal Gate, the light-emitting control signal terminal EM and the sensing control signal terminal SW-SENSE are low-level signals, the signal of the reset signal terminal Reset is a high-level signal, the first transistor T1 is turned on, the signal of the light-emitting control signal terminal EM is a low-level signal, the fifth transistor T5 is turned on, the power supply voltage output by the first power supply terminal VDD provides a driving voltage to the anode of the light-emitting device L through the turned-on fifth transistor T5 and the third transistor T3, the control signal terminal CON obtains the signal of the third node N3, and samples the signal of the third node N3, the signals of the scanning signal terminal Gate and the sensing control signal terminal SW-SENSE are low-level signals, and the second transistor T2 and the fourth transistor T4 are turned off.

[0177] Figure 4C for Figure 3 The pixel driving circuit provided is a working timing diagram in the second sensing phase. Figure 3 The operation process of the exemplary pixel driving circuit in the second sensing stage illustrates an exemplary embodiment of the present disclosure. Figure 3 The pixel driving circuit includes five transistors (first transistor T1 to fifth transistor T5) and a capacitor (capacitor C), the first transistor T1, the second transistor T2 and the fourth transistor T4 are N-type transistors, and the third transistor T3 and the fifth transistor T5 are P-type transistors.

[0178] In an exemplary embodiment, Figure 3 The operation process of the provided pixel driving circuit in the second sensing phase may include:

[0179] The first stage C1 is called the third reset stage. The signals of the reset signal terminal Reset and the light-emitting control signal terminal EM are high-level signals, the signals of the sensing control signal terminal SW-SENSE and the scanning signal terminal Gate are low-level signals, and the control signal terminal CON provides a reference signal, wherein Vref is the voltage value of the reference signal. The signal of the reset signal terminal Reset is a high-level signal, the first transistor T1 is turned on, the reference signal of the control signal terminal CON is written into the third node N3, the third node N3, i.e., the anode of the light-emitting device L, is initialized, and the original charge of the third node N3 is cleared. The signal of the light-emitting control signal terminal EM is a high-level signal, the signals of the sensing control signal terminal SW-SENSE and the scanning signal terminal Gate are low-level signals, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off.

[0180] In the second stage C2, the third data writing stage, the signals of the scanning signal terminal Gate and the light emitting control signal terminal EM are high level signals, the signals of the sensing control signal terminal SW-SENSE and the reset signal terminal Reset are low level signals, the control signal terminal CON provides a reference signal, and the data signal terminal Data outputs a data voltage. The signal of the scanning signal terminal Gate is a high level signal, the fourth transistor T4 is turned on, and the data voltage of the data signal terminal Data is written into the first node N1. The signal of the light emitting control signal terminal EM is a high level signal, the signals of the sensing control signal terminal SW-SENSE and the reset signal terminal Reset are low level signals, and the first transistor T1, the second transistor T2, and the fifth transistor T5 are turned off.

[0181] In the third stage C3, i.e., the second sampling stage, the signal of the sensing control signal terminal SW-SENSE is a high-level signal, the signals of the scanning signal terminal Gate, the light-emitting control signal terminal EM and the reset signal terminal Reset are low-level signals, the signal of the sensing control signal terminal SW-SENSE is a high-level signal, the second transistor T2 is turned on, the control signal terminal CON obtains the signal of the first node N1, and samples the signal of the first node N1, the signal of the light-emitting control signal terminal EM is a low-level signal, the fifth transistor T5 is turned on, and the power supply voltage output by the first power supply terminal VDD provides a driving voltage to the anode of the light-emitting device L through the turned-on fifth transistor T5 and the third transistor T3, the signals of the scanning signal terminal Gate and the reset signal terminal Reset are low-level signals, and the first transistor T1 and the fourth transistor T4 are turned off.

[0182] The present disclosure also provides a driving method of a pixel driving circuit, which is configured to drive the pixel driving circuit provided by any of the aforementioned embodiments. The pixel driving circuit is arranged in a display substrate, and the working process of the display substrate includes: a display phase and a non-display phase;

[0183] In the display stage and the non-display stage, the driving method of the pixel driving circuit includes:

[0184] The driving subcircuit provides a driving signal to the third node under the control of the signals at the first node and the second node;

[0185] The reset sensing subcircuit provides the reference signal provided by the control signal terminal to the third node, or provides the signal of the first node or the third node to the control signal terminal, under the control of the signal of the reset signal terminal and the sensing control signal terminal;

[0186] The node control subcircuit provides the signal of the data signal terminal to the first node under the control of the signal of the scan signal terminal, and stores the voltage difference between the signal of the first node and the signal of the first power terminal;

[0187] The light emitting control sub-circuit provides the signal of the first power supply terminal to the second node under the control of the signal of the light emitting control signal terminal.

[0188] In an exemplary embodiment, the display phase includes: a first reset phase, a first data writing phase and a light emitting phase; the pixel driving circuit is in the display phase, and the driving method of the pixel driving circuit may include the following steps:

[0189] In the first reset stage, the reset sensing subcircuit provides the reference signal provided by the control signal terminal to the third node under the control of the signal of the reset signal terminal;

[0190] In the first data writing phase, the node control subcircuit provides the signal of the data signal terminal to the first node under the control of the signal of the scan signal terminal, and stores the voltage difference between the signal of the first node and the signal of the first power terminal;

[0191] In the light-emitting stage, the light-emitting control subcircuit provides a signal from the first power supply end to the second node under the control of a signal from the light-emitting control signal end, and the driving subcircuit provides a driving signal to the third node under the control of signals from the first node and the second node.

[0192] In an exemplary embodiment, the non-display phase includes: a first sensing phase, the first sensing phase occurs before the display phase, and the first sensing phase includes: a second reset phase, a second data writing phase, and a first sampling phase.

[0193] In an exemplary embodiment, the pixel driving circuit is in a first sensing stage, and a driving method of the pixel driving circuit may include the following steps:

[0194] In the second reset phase, the reset sensing subcircuit provides the reference signal provided by the control signal terminal to the third node under the control of the signal at the reset signal terminal;

[0195] In the second data writing phase, the node control subcircuit provides the signal of the data signal terminal to the first node under the control of the signal of the scan signal terminal, and stores the voltage difference between the signal of the first node and the signal of the first power terminal;

[0196] In the first sampling stage, the light-emitting control subcircuit provides the signal of the first power supply end to the second node under the control of the signal of the light-emitting control signal end, the driving subcircuit provides the driving signal to the third node under the control of the signals of the first node and the second node, and the reset sensing subcircuit provides the signal of the third node to the control signal end under the control of the signal of the reset signal end.

[0197] In an exemplary embodiment, the display substrate further includes: an integrated circuit electrically connected to the pixel driving circuit. The integrated circuit obtains a signal of the third node, processes the signal of the third node, and provides the processed signal of the third node to the pixel driving circuit to compensate for the brightness of the light-emitting device. The display substrate provided by the present disclosure can perform external compensation on the pixel driving circuit, and can improve the reliability and display effect of the display substrate.

[0198] In an exemplary embodiment, the non-display phase includes: a second sensing phase, the second sensing phase occurs before the display phase, and the second sensing phase includes: a third reset phase, a third data writing phase, and a second sampling phase.

[0199] In an exemplary embodiment, the pixel driving circuit is in the second sensing stage, and the driving method of the pixel driving circuit may include the following steps:

[0200] In the third reset stage, the reset sensing subcircuit provides the reference signal provided by the control signal terminal to the third node under the control of the signal of the reset signal terminal;

[0201] In the third data writing phase, the node control subcircuit provides the signal of the data signal terminal to the first node under the control of the signal of the scan signal terminal, and stores the voltage difference between the signal of the first node and the signal of the first power terminal;

[0202] In the second sampling stage, the light-emitting control subcircuit provides the signal of the first power supply end to the second node under the control of the signal of the light-emitting control signal end, the driving subcircuit provides the driving signal to the third node under the control of the signals of the first node and the second node, and the reset sensing subcircuit provides the signal of the first node to the control signal end under the control of the signal of the sensing control signal end.

[0203] In an exemplary embodiment, the integrated circuit obtains a signal of the first node, processes the signal of the first node, and provides the processed signal of the first node to the pixel driving circuit to compensate for the threshold voltage of the driving transistor in the pixel driving circuit. The display substrate provided by the present disclosure can perform external compensation on the pixel driving circuit, which can improve the reliability and display effect of the display substrate. Exemplarily, the display substrate includes a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit, and the integrated circuit can capture the signal of the first node of the pixel driving circuit in at least one sub-pixel.

[0204] Figure 5A To show the structural diagram of the substrate, Figure 5B for Figure 5A A partial schematic diagram of the first display area in FIG. Figure 5C for Figure 5A Partial schematic diagram of the second display area in FIG. FIG. 5A to FIG. 5CAs shown, the embodiment of the present disclosure further provides a display substrate, including a substrate, the substrate including a display area AA and a non-display area BB, the display area AA including: a first display area A1 and a second display area A2, the second display area A2 is located on at least one side of the first display area A1. The first display area A1 includes: a plurality of first sub-pixels, the second display area A2 includes: a plurality of second sub-pixels, at least one of the first sub-pixel and the second sub-pixel includes: a pixel driving circuit and a light-emitting device. Among them, the pixel driving circuit in the first sub-pixel is the pixel driving circuit provided in any of the aforementioned embodiments, and the implementation effect and implementation principle are not repeated here. Figure 5B and Figure 5C The description is made by taking two rows and six columns of sub-pixels as an example.

[0205] In an exemplary embodiment, the pixel driving circuit in the second sub-pixel may be the pixel driving circuit provided by any of the aforementioned embodiments.

[0206] In an exemplary embodiment, if Figure 5A As shown, the pixel driving circuit 11 in the first sub-pixel is electrically connected to the light-emitting device 13 in the first sub-pixel, and the pixel driving circuit 12 in the second sub-pixel is electrically connected to the light-emitting device 14 in the second sub-pixel.

[0207] In an exemplary embodiment, the display area may be in the shape of a rounded polygon or a circle. When the display area is in the shape of a rounded polygon, the display area may further include: a straight line display border. Figure 5A The description is given below by taking the display area as a rounded rectangle as an example.

[0208] In an exemplary embodiment, the light transmittance of the first display area A1 may be greater than the light transmittance of the second display area A2. The first display area A1 may be a light-transmitting display area, and the second display area A2 may be a normal display area. The light-transmitting display area may display or transmit light.

[0209] In an exemplary embodiment, in a plane parallel to the display substrate, the shape of the first display area may be any one or more of the following: a rectangle, a polygon, a circle, and an ellipse. Figure 5A The description is made by taking a circle as an example. For example, when the shape of the first display area is a circle, the diameter of the circle can be about 3 mm to 5 mm. For another example, when the shape of the first display area is a rectangle, the side length of the rectangle can be about 3 mm to 5 mm.

[0210] In an exemplary embodiment, in a plane parallel to the display substrate, the shape of the first display area A1 may be any one or more of the following: a rectangle, a polygon, a circle, and an ellipse.

[0211] In an exemplary embodiment, the second display area A2 may surround or semi-surround the first display area A1. When the second display area A2 surrounds the first display area A1, the first display area A1 is located in the middle of the second display area A2. When the second display area A2 semi-surrounds the first display area A1, the first display area A1 is disposed at the top edge, that is, disposed along the edge of the second display area A2.

[0212] In an exemplary embodiment, the area of ​​the first display area A1 may be greater than the area of ​​the second display area A2, or the area of ​​the first display area A1 may be equal to the area of ​​the second display area A2, or the area of ​​the first display area A1 may be smaller than the area of ​​the second display area A2. Figure 5A The description is made by taking the example that the area of ​​the first display area is smaller than the area of ​​the second display area.

[0213] In an exemplary embodiment, on a plane parallel to the display substrate, the display substrate may include a plurality of pixel units arranged regularly. Each pixel unit may include 3 sub-pixels, or may include 4 sub-pixels, or may include a plurality of sub-pixels. When the pixel unit includes 3 sub-pixels, the 3 sub-pixels include a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light. When the pixel unit includes 4 sub-pixels, the 4 sub-pixels include a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, a third sub-pixel emitting a third color light, and a fourth sub-pixel emitting a fourth color light.

[0214] In an exemplary embodiment, the pixel unit may include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B.

[0215] In an exemplary embodiment, when a pixel unit includes three sub-pixels, the three rectangular sub-pixels may be arranged in parallel in a horizontal direction, or may be arranged in parallel in a vertical direction.

[0216] In an exemplary embodiment, when a pixel unit includes four sub-pixels, the four sub-pixels included in the pixel unit may be in various shapes and arranged in various ways. The four sub-pixels may be in a rectangular shape and arranged in parallel, from left to right, respectively: R sub-pixel, G sub-pixel, B sub-pixel and G sub-pixel, or the four sub-pixels may be in a pentagonal and hexagonal shape, respectively, and arranged in parallel, with two pentagonal G sub-pixels located in the middle of the pixel unit, and the hexagonal R sub-pixels and the hexagonal B sub-pixels located on both sides of the G sub-pixel.

[0217] In an exemplary embodiment, the sub-pixel density of the first display area A1 is equal to the sub-pixel density of the second display area A2, and the resolution of the first display area is equal to the resolution of the second display area. Among them, resolution (Pixels Per Inch, PPI for short) refers to the number of sub-pixels per unit area, which can be called sub-pixel density. The higher the PPI value, the higher the density at which the picture is displayed, and the richer the details of the picture. That is. In the present disclosure, by adopting a pixel driving circuit that occupies a smaller area, it is possible to avoid compressing the pixel driving circuit in the first display area in a full-screen display product, and the display effect of the display substrate can be improved. The sub-pixel density of the first display area A1 is equal to the sub-pixel density of the second display area A2, which can ensure the display uniformity of the display substrate and improve the display effect of the display substrate.

[0218] In an exemplary embodiment, the sub-pixel density of the first display area A1 may be greater than the sub-pixel density of the second display area A2, and the resolution of the first display area is greater than the resolution of the second display area; alternatively, the sub-pixel density of the first display area A1 may be less than the sub-pixel density of the second display area A2, and the resolution of the first display area is less than the resolution of the second display area.

[0219] In an exemplary embodiment, if Figure 5B and Figure 5C As shown, the pixel structures of adjacent sub-pixels in the plurality of sub-pixels arranged along the first direction D1 are at least partially symmetrically arranged relative to a virtual straight line extending along the second direction D2, and the first direction D1 and the second direction D2 intersect. In an exemplary embodiment, the first direction D1 and the second direction D2 may be perpendicular. The first direction D1 may be a row direction, and the second direction D2 may be a column direction.

[0220] In an exemplary embodiment, the light emitting device includes a first light emitting device, a second light emitting device, and a third light emitting device, the light emitting device includes: a first electrode; the first light emitting device, the second light emitting device, and the third light emitting device emit light of different colors. Figure 5B and Figure 5C The description is made by taking the example that the first light emitting device emits red light, the second light emitting device emits blue light, and the third light emitting device emits green light.

[0221] In an exemplary embodiment, the area of ​​the first electrode AN1-1 of the first light-emitting device located in the first display area A1 may be smaller than the area of ​​the first electrode AN1-2 of the first light-emitting device located in the second display area A2, or the area of ​​the first electrode AN1-1 of the first light-emitting device located in the first display area A1 may be equal to the area of ​​the first electrode AN1-2 of the first light-emitting device located in the second display area A2, or the area of ​​the first electrode AN1-1 of the first light-emitting device located in the first display area A1 may be larger than the area of ​​the first electrode AN1-2 of the first light-emitting device located in the second display area A2.

[0222] In an exemplary embodiment, the area of ​​the first electrode AN2-1 of the second light-emitting device located in the first display area A1 may be smaller than the area of ​​the first electrode AN2-2 of the second light-emitting device located in the second display area A2, or the area of ​​the first electrode AN2-1 of the second light-emitting device located in the first display area A1 may be equal to the area of ​​the first electrode AN2-2 of the second light-emitting device located in the second display area A2, or the area of ​​the first electrode AN2-1 of the second light-emitting device located in the first display area A1 may be larger than the area of ​​the first electrode AN2-2 of the second light-emitting device located in the second display area A2.

[0223] In an exemplary embodiment, the area of ​​the first electrode AN3-1 of the third light-emitting device located in the first display area A1 may be smaller than the area of ​​the first electrode AN2-2 of the third light-emitting device located in the second display area A2, or the area of ​​the first electrode AN3-1 of the third light-emitting device located in the first display area A1 may be equal to the area of ​​the first electrode AN2-2 of the third light-emitting device located in the second display area A2, or the area of ​​the first electrode AN3-1 of the third light-emitting device located in the first display area A1 may be larger than the area of ​​the first electrode AN2-2 of the third light-emitting device located in the second display area A2.

[0224] In an exemplary embodiment, the first electrode may employ a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0225] In an exemplary embodiment, Fig. 6A for Figure 5B and Figure 5C Schematic diagram of some film layers in the provided display substrate Figure 1 , Figure 6B for Figure 5B and Figure 5C Schematic diagram 2 of part of the film layer in the display substrate provided. Fig. 6A and Figure 6BAs shown, the pixel driving circuit includes: at least one P-type transistor and at least one N-type transistor, and the positive projection of the at least one P-type transistor on the substrate at least partially overlaps with the positive projection of the at least one N-type transistor on the substrate. The at least one P-type transistor includes: a third transistor T3 and a fifth transistor T5, and the at least one N-type transistor includes: a first transistor T1, a second transistor T2, and a fourth transistor T4.

[0226] In an exemplary embodiment, if Figure 6B As shown, the transistor includes: an active pattern. The orthographic projection of the active pattern of at least one P-type transistor on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one N-type transistor on the substrate. Exemplarily, the orthographic projection of the active pattern of at least one N-type transistor on the substrate is located within the orthographic projection of the active pattern of at least one P-type transistor on the substrate. Figure 6B The active pattern of at least one N-type transistor includes: an active pattern 11 of a first transistor, an active pattern 21 of a second transistor, and an active pattern 41 of a fourth transistor, and the active pattern of at least one P-type transistor includes: an active pattern 31 of a third transistor and an active pattern 51 of a fifth transistor. The orthographic projection of at least part of the active pattern of at least one P-type transistor in the present disclosure overlaps at least part of the orthographic projection of at least part of the active pattern of at least one N-type transistor on the substrate, which can reduce and further compress the area of ​​the pixel driving circuit, increase the transmittance, and ensure that the active pattern of the N-type transistor is set on a flat structure, which can improve the reliability of the display substrate.

[0227] In an exemplary embodiment, if Figure 6B As shown, the display area may further include: at least one first power line VDDL disposed in the display area. The orthographic projection of the first power line VDDL on the substrate at least partially overlaps with the orthographic projection of at least part of at least one P-type transistor on the substrate, and the orthographic projection of the first power line VDDL on the substrate at least partially overlaps with the orthographic projection of at least part of at least one N-type transistor on the substrate. The first power line VDDL in the present disclosure separates the P-type transistor from the N-type transistor, and since the signal of the first power line VDDL is a constant voltage signal, the first power line in the present disclosure can prevent interference between the signal of the P-type transistor and the signal of the N-type transistor.

[0228] In an exemplary embodiment, if Figure 6B As shown, the active pattern of at least one P-type transistor may be located on a side of the first power line VDDL close to the substrate, and the active pattern of at least one N-type transistor may be located on a side of the first power line VDDL far from the substrate.

[0229] In an exemplary embodiment, if Fig. 6AAs shown, the display area includes: array-arranged pixel units PE, at least one light-emitting control signal line EL, at least one reset signal line RL, at least one scanning signal line GL, at least one sensing control signal line SL, at least one data signal line DL, at least one control signal line CONL and at least one first power line VDDL, and at least one pixel unit includes: at least one sub-pixel arranged along a first direction. Fig. 6A The description is made by taking two rows and two columns of pixel units as an example.

[0230] In an exemplary embodiment, at least one pixel unit is electrically connected to the light emitting control signal line EL, the reset signal line RL, the scanning signal line GL, the sensing control signal line SL, N data signal lines DL, N control signal lines CONL and N first power lines VDDL, respectively, where N is the number of sub-pixels in one pixel unit.

[0231] In an exemplary embodiment, if Fig. 6A As shown, the display area may include: at least one data signal line DL and at least one control signal line CONL, the data signal line DL and the control signal line CONL at least partially extend along the second direction D2, wherein the data signal line DL is electrically connected to the data signal terminal connected to the pixel driving circuit, and the control signal line CONL is electrically connected to the control signal terminal connected to the pixel driving circuit.

[0232] In an exemplary embodiment, if Fig. 6A As shown, the data signal lines DL connecting adjacent sub-pixels among the plurality of sub-pixels arranged along the first direction D1 are symmetrically arranged relative to the center line O of the adjacent sub-pixels, and the control signal lines CONL connecting adjacent sub-pixels among the plurality of sub-pixels arranged along the first direction D1 are symmetrically arranged relative to the center line O of the adjacent sub-pixels.

[0233] In an exemplary embodiment, at least a portion of any one of the data signal line DL and the control signal line CONL is a transparent conductive signal line. At least a portion of any one of the data signal line DL and the control signal line CONL is a transparent conductive signal line, which can further increase the pixel opening, and is more conducive to the under-screen camera effect without affecting the display effect.

[0234] In an exemplary embodiment, if Fig. 6A and Figure 6B As shown, the display substrate may include: at least one first power line VDDL; the first power line VDDL at least partially extends along the second direction D2. The first power line VDDL is electrically connected to the first power terminal connected to the pixel driving circuit, adjacent first power lines VDDL are electrically connected, and the first power lines VDDL connected to adjacent sub-pixels in a plurality of sub-pixels arranged along the first direction D1 are symmetrically arranged relative to the center line O of the adjacent sub-pixels.

[0235] In an exemplary embodiment, if Figure 6B As shown, the first power line VDDL includes: a first connection line VL1, a second connection line VL2 and a plurality of connection blocks CL, the first connection line VL1 and the second connection line VL2 are arranged along the first direction D1 and extend along the second direction D2, the connection block CL is arranged between the first connection line VL1 and the second connection line VL2, and the pixel driving circuit includes: a capacitor, and the capacitor includes: a first electrode plate C1 and a second electrode plate C2. The orthographic projection of the connection block CL on the substrate overlaps with the orthographic projection of the first electrode plate C1 on the substrate at least partially, that is, the connection block CL is reused as the second electrode plate C2 of the capacitor. The plurality of connection blocks CL located between the first connection line VL1 and the second connection line VL2 are arranged along the second direction D2 and are arranged at intervals, and a closed area is formed between the adjacent connection blocks CL arranged along the second direction D2 and the adjacent first connection line VL1 and the second connection line VL2.

[0236] In an exemplary embodiment, the closed area may be a light-transmitting area.

[0237] In an exemplary embodiment, if Fig. 6A As shown, the display area may further include: at least one light-emitting control signal line EL, at least one reset signal line RL, at least one scanning signal line GL and at least one sensing control signal line SL, wherein at least one of the light-emitting control signal line EL, the reset signal line RL, the scanning signal line GL and the sensing control signal line SL extends at least partially along the first direction D1, wherein the light-emitting control signal line EL is electrically connected to the light-emitting control signal terminal connected to the pixel driving circuit, the reset signal line RL is electrically connected to the reset signal terminal connected to the pixel driving circuit, the scanning signal line GL is electrically connected to the scanning signal terminal connected to the pixel driving circuit, and the sensing control signal line SL is electrically connected to the sensing control signal terminal connected to the pixel driving circuit.

[0238] In an exemplary embodiment, if Fig. 6A As shown, the light emitting control signal line EL is arranged at a different layer from at least one of the reset signal line RL, the scanning signal line GL and the sensing control signal line SL.

[0239] In an exemplary embodiment, if Fig. 6A As shown, the orthographic projections of the light emitting control signal line EL, the scanning signal line GL, the sensing control signal line SL and the reset signal line RL connected to at least one sub-pixel on the substrate are arranged in sequence along the second direction;

[0240] In an exemplary embodiment, the display substrate further includes: a driving structure layer disposed on the substrate, the driving structure layer is provided with a light emitting control signal line, a reset signal line, a scanning signal line, a sensing control signal line, a first power line, a data signal line, a control signal line and a pixel driving circuit, the driving structure layer at least includes: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer and a fourth conductive layer stacked in sequence in a direction away from the substrate, the pixel driving circuit includes: at least one P-type transistor, at least one N-type transistor and a capacitor, the transistor includes: an active pattern, a gate electrode, a first electrode and a second electrode, and the capacitor includes: a first electrode plate and a second electrode plate. Among them, at least one P-type transistor may include Figure 3 Among the third transistor and the fifth transistor, at least one N-type transistor may include Figure 3 The first transistor, the second transistor and the fourth transistor in.

[0241] The first semiconductor layer includes at least: an active pattern of at least one P-type transistor located in at least one sub-pixel.

[0242] The first conductive layer at least includes: a light emitting control signal line, a gate electrode of at least one P-type transistor located in at least one sub-pixel, and a first plate of a capacitor.

[0243] The second conductive layer at least includes: a first power line, a second electrode plate of a capacitor located in at least one sub-pixel, and a first electrode and a second electrode of at least one P-type transistor.

[0244] The second semiconductor layer includes at least: an active pattern of at least one N-type transistor located in at least one sub-pixel.

[0245] The third conductive layer at least includes: a reset signal line, a scan signal line, a sensing control signal line, and a gate electrode, a first electrode, and a second electrode of at least one N-type transistor located in at least one sub-pixel.

[0246] The fourth conductive layer at least includes: a data signal line, a control signal line, and an anode connection line located in at least one sub-pixel.

[0247] In an exemplary embodiment, the anode connection line includes a transparent wire. Exemplarily, the transparent wire may be made of indium tin oxide (ITO) or indium zinc oxide (IZO).

[0248] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0249] In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer. The first flexible material layer and the second flexible material layer may be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc. The first inorganic material layer and the second inorganic material layer may be made of silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate, and the semiconductor layer may be made of amorphous silicon (a-Si).

[0250] The display substrate in the present disclosure uses four conductive layers and two semiconductor layers to realize a pixel driving circuit including P-type transistors and N-type transistors, which simplifies the film layer structure of the display substrate, not only maximally saves the space occupied by the pixel driving circuit, but also helps to improve the aperture ratio of the light-transmitting display area.

[0251] In an exemplary embodiment, the driving structure layer may further include: a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a first flat layer, and a second flat layer. The first insulating layer is located between the first semiconductor layer and the first conductive layer, the second insulating layer is located between the first conductive layer and the second conductive layer, the third insulating layer is located between the second conductive layer and the second semiconductor layer, the fourth insulating layer is located between the second semiconductor layer and the third conductive layer, the first flat layer is located between the third conductive layer and the fourth conductive layer, and the second flat layer is located on a side of the fourth conductive layer away from the substrate.

[0252] In an exemplary embodiment, the display substrate may further include: a light emitting structure layer located on a side of the driving structure layer away from the substrate, the light emitting structure layer including: a fifth conductive layer and a pixel definition layer sequentially stacked on the substrate, the fifth conductive layer including at least: a first electrode, the pixel definition layer is provided with a plurality of pixel openings, the pixel openings including: a first pixel opening, a second pixel opening, and a third pixel opening. The first pixel opening exposes the first electrode of the first light emitting device, the second pixel opening exposes the first electrode of the second light emitting device, and the third pixel opening exposes the first electrode of the third light emitting device.

[0253] like Figure 5B and Figure 5C As shown, the area of ​​the first pixel opening PV1-1 located in the first display area A1 is smaller than the area of ​​the first pixel opening PV1-2 located in the second display area A2, the area of ​​the second pixel opening PV2-1 located in the first display area A1 is smaller than the area of ​​the second pixel opening PV2-2 located in the second display area A2, and the area of ​​the third pixel opening PV3-2 located in the first display area A1 is smaller than the area of ​​the third pixel opening PV3-2 located in the second display area A2.

[0254] The display substrate provided in the embodiments of the present disclosure can be applicable to application scenarios such as front-end camera photography and mobile gaming of high-frequency terminal devices.

[0255] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0256] In an exemplary embodiment, taking 12 sub-pixels (2 sub-pixel rows and 6 sub-pixel columns) located in the first display area as an example, the preparation process of the display substrate may include the following operations.

[0257] (1) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: depositing a first semiconductor film on a substrate, patterning the first semiconductor film through a patterning process, and forming a first semiconductor layer pattern covering the substrate, such as Figure 7 As shown, Figure 7 is a schematic diagram of a pattern of a first semiconductor layer.

[0258] In an exemplary embodiment, if Figure 7 As shown, the first semiconductor layer pattern may include at least an active pattern 31 of a third transistor and an active pattern 51 of a fifth transistor located in at least one sub-pixel.

[0259] In an exemplary embodiment, the active pattern 31 of the third transistor and the active pattern 51 of the fifth transistor located in the same sub-pixel are an integral structure connected to each other.

[0260] In an exemplary embodiment, the integrated structure of the active pattern 31 of the third transistor and the active pattern 51 of the fifth transistor of adjacent sub-pixels located in the same row is symmetrical with respect to a center line O of the adjacent sub-pixels extending in the second direction D2.

[0261] In an exemplary embodiment, in the first direction D1, the active pattern 31 of the third transistor of the i-th column sub-pixel is located on a side of the active pattern 51 of the fifth transistor of the i-th column sub-pixel close to the adjacent column sub-pixel. In the second direction D2, the active pattern 31 of the third transistor of the j-th row sub-pixel is located on a side of the active pattern 51 of the fifth transistor of the j-th row sub-pixel close to the j+1-th row sub-pixel.

[0262] In exemplary embodiments, the active pattern 51 of the fifth transistor may have an “I” shape.

[0263] In an exemplary embodiment, the active pattern 31 of the third transistor includes: a first active connection portion 31A, a second active connection portion 31B, and a third active connection portion 31C. The first active connection portion 31A and the third active connection portion 31C are located on a side of the second active connection portion 31B close to the active pattern 51 of the fifth transistor, the first active connection portion 31A is connected to the active pattern 51 of the fifth transistor and the second active connection portion 31B, respectively, and the third active connection portion 31C is connected to the second active connection portion 31B.

[0264] In an exemplary embodiment, the first active connection portion 31A may be shaped like an inverted “Ω”, the second active connection portion 31B may be shaped like an “I”, and the third active connection portion 31C may be shaped like a “I”.

[0265] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region between the first region and the second region. In an exemplary embodiment, the first region 31-1 of the active pattern 31 of the third transistor may serve as the second region 51-2 of the active pattern 51 of the fifth transistor, and the second region 31-2 of the active pattern 31 of the third transistor and the first region 51-1 of the active pattern 51 of the fifth transistor may be separately provided.

[0266] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process, forming a first insulating layer covering the first semiconductor layer pattern and a first conductive layer pattern disposed on the first insulating layer, such as Figure 8 and Fig. 9 As shown, Figure 8 is a schematic diagram of a first conductive layer pattern, Fig. 9 FIG. 2 is a schematic diagram after forming a first conductive layer pattern. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0267] In an exemplary embodiment, if Figure 8 and Fig. 9 As shown, the first conductive layer pattern at least includes: a light emitting control signal line EL, a gate electrode 32 of a third transistor located in at least one sub-pixel, a gate electrode 52 of a fifth transistor, and a first plate C1 of a capacitor.

[0268] In an exemplary embodiment, the shape of the light emission control signal line EL may be a line shape in which the main part extends along the first direction D1, and the light emission control signal line EL in the j-th row of sub-pixels may be located on a side of the first plate C1 of the capacitor of the j-th row of sub-pixels away from the j+1-th row of sub-pixels. The region where the light emission control signal line EL overlaps with the active pattern of the fifth transistor serves as the gate electrode of the fifth transistor T5.

[0269] In an exemplary embodiment, the gate electrode 32 of the third transistor and the first plate C1 of the capacitor in the same sub-pixel are an integrated structure. The shape of the integrated structure of the gate electrode 32 of the third transistor and the first plate C1 of the capacitor may be rectangular, and the corners of the rectangle may be chamfered, and the orthographic projection of the integrated structure of the gate electrode 32 of the third transistor and the first plate C1 of the capacitor on the substrate at least partially overlaps with the orthographic projection of the first active connection portion in the active pattern of the third transistor on the substrate.

[0270] In an exemplary embodiment, the integrated structure of the gate electrode 32 of the third transistor and the first plate C1 of the capacitor of adjacent sub-pixels located in the same row is symmetrical with respect to a center line O of the adjacent sub-pixels extending along the second direction D2.

[0271] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductor processing on the first semiconductor layer, and the first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the third transistor T3 and the fifth transistor T5, and the first semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of ​​the third transistor T3 and the fifth transistor T5 are both conductorized, and the first area 31-1 of the active pattern 31 of the third transistor (also the second area 51-2 of the active pattern 51 of the fifth transistor) can serve as the first electrode 33 of the third transistor (also the second electrode 54 of the fifth transistor).

[0272] (3) Forming a second insulating layer pattern. In an exemplary embodiment, forming the second insulating layer pattern may include: depositing a second insulating film on the substrate on which the aforementioned pattern is formed, patterning the second insulating film using a patterning process to form a second insulating layer covering the first conductive layer, wherein a plurality of vias are provided on the second insulating layer, such as Fig.10 As shown, Fig.10 It is a schematic diagram after forming the second insulating layer.

[0273] In an exemplary embodiment, if Fig.10 As shown, the plurality of via holes at least include: a first via hole V1 and a second via hole V2 located in at least one sub-pixel.

[0274] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the third transistor on the substrate, the first insulating layer in the first via hole V1 is etched away to expose the surface of the second area of ​​the active pattern of the third transistor, and the first via hole V1 is configured to connect the second electrode of the subsequently formed third transistor to the second area of ​​the active pattern of the third transistor through the via hole.

[0275] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fifth transistor on the substrate, the first insulating layer in the second via hole V2 is etched away to expose the surface of the first area of ​​the active pattern of the fifth transistor, and the second via hole V2 is configured to connect a subsequently formed first power line to the first area of ​​the active pattern of the fifth transistor through the via hole.

[0276] (4) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second conductive film on the substrate having the aforementioned pattern, patterning the second conductive film using a patterning process, and forming the second conductive layer pattern on the second insulating layer. Fig.11 and Fig.12 As shown, Fig.11 is a schematic diagram of a second conductive layer pattern, Fig.12It is a schematic diagram after forming the second conductive layer pattern.

[0277] In an exemplary embodiment, the second conductive layer pattern includes at least a first power line VDDL, and a second electrode 34 of a third transistor, a first electrode 53 of a fifth transistor, and a second plate C2 of a capacitor located in at least one sub-pixel.

[0278] In an exemplary embodiment, the first power lines VDDL connected to adjacent sub-pixels among the plurality of sub-pixels arranged along the first direction D1 are symmetrically arranged with respect to the center line O of the adjacent sub-pixels. The second electrodes 34 of the third transistors of adjacent sub-pixels located in the same row are symmetrically arranged with respect to the virtual straight line O extending along the second direction of the adjacent sub-pixels.

[0279] In an exemplary embodiment, adjacent first power lines VDDL are electrically connected. The first power lines VDDL at least partially extend along the second direction D2.

[0280] In an exemplary embodiment, if Fig.11 As shown, the first power line VDDL includes: a first connection line VL1, a second connection line VL2 and a plurality of connection blocks CL, the first connection line VL1 and the second connection line VL2 are arranged along the first direction D1 and extend along the second direction D2, the connection block CL is arranged between the first connection line VL1 and the second connection line VL2, and the pixel driving circuit includes: a capacitor, and the capacitor includes: a first electrode plate C1 and a second electrode plate C2. The positive projection of the connection block CL on the substrate overlaps with the positive projection of the first electrode plate C1 on the substrate at least partially, that is, the connection block CL is reused as the second electrode plate C2 of the capacitor, and the plurality of connection blocks CL located between the first connection line VL1 and the second connection line VL2 are arranged along the second direction D2 and are arranged at intervals. For the same first power line VDDL, a closed area is formed between the adjacent connection blocks CL and the first connection line VL1 and the second connection line VL2.

[0281] In an exemplary embodiment, the overlapped area between the first power line VDDL and the second via is reused as the first electrode of the fifth transistor. The connection block CL is reused as the second plate C2 of the capacitor, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first plate of the capacitor on the substrate.

[0282] In an exemplary embodiment, the outline of the connection block CL may be rectangular. An opening K is provided on the connection block CL, and the shape of the opening K may be rectangular, and may be located in the middle of the connection block CL, so that the connection block CL forms a ring structure. The opening K exposes the second insulating layer covering the first electrode plate, and the orthographic projection of the first electrode plate on the substrate includes the orthographic projection of the opening K on the substrate. In an exemplary embodiment, the opening K is configured to accommodate a fourth via hole formed subsequently, and the fourth via hole is located in the opening K and exposes the first electrode plate 24, so that the second electrode of the fourth transistor formed subsequently (also the second electrode of the second transistor) is connected to the first electrode plate.

[0283] In an exemplary embodiment, the second electrode 34 of the third transistor is separately provided and may be rectangular in shape, which is not limited in the present disclosure. The second electrode 34 of the third transistor may be located in a closed area.

[0284] In an exemplary embodiment, the first power line VDDL is electrically connected to the second region of the active pattern of the fifth transistor through the second via hole. The second electrode 34 of the third transistor is electrically connected to the second region of the active pattern of the third transistor through the first via hole.

[0285] In an exemplary embodiment, since adjacent first power lines VDDL are electrically connected to each other, by forming all the first power lines into an integrated structure connected to each other, it can be ensured that the second plates of multiple capacitors in all sub-pixel rows have the same potential, which is beneficial to improving the uniformity of the display substrate, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0286] (5) Forming a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, patterning the third insulating film using a patterning process to form a third insulating layer covering the second conductive layer, wherein a plurality of via holes are disposed on the third insulating layer, such as Fig.13 shown. Fig.13 It is a schematic diagram after forming the third insulating layer.

[0287] In an exemplary embodiment, if Fig.13 As shown, the via holes on the third insulating layer at least include: a third via hole V3 located in at least one sub-pixel.

[0288] In an exemplary embodiment, the orthographic projection of the third via V3 on the substrate is located within the range of the orthographic projection of the second electrode of the third transistor on the substrate, the third via V3 exposes the surface of the second electrode of the third transistor, and the third via V3 is configured to connect the second area of ​​the active pattern of the first transistor formed subsequently to the second electrode of the third transistor through the via.

[0289] (6) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern may include: depositing a second semiconductor film on the substrate on which the aforementioned pattern is formed, patterning the second semiconductor film through a patterning process, and forming a second semiconductor layer pattern covering the third insulating layer, such as Fig.14 and Fig.15 As shown, Fig.14 is a schematic diagram of a second semiconductor layer pattern, Fig.15 It is a schematic diagram after forming the second semiconductor layer pattern.

[0290] In an exemplary embodiment, if Fig.14 and Fig.15 As shown, the second semiconductor layer pattern may include at least an active pattern 11 of a first transistor, an active pattern 21 of a second transistor, and an active pattern 41 of a fourth transistor located in at least one sub-pixel.

[0291] In an exemplary embodiment, the active pattern 11 of the first transistor and the active pattern 21 of the second transistor located in the same sub-pixel are connected to each other as an integral structure. The active pattern 41 of the fourth transistor may be provided separately.

[0292] In an exemplary embodiment, the first transistor active pattern 11 , the second transistor active pattern 21 , and the fourth transistor active pattern 41 of adjacent sub-pixels located in the same row are symmetrical with respect to a center line O of the adjacent sub-pixels extending in the second direction D2 .

[0293] In an exemplary embodiment, in the first direction D1, the integrated structure of the active pattern 11 of the first transistor and the active pattern 21 of the second transistor of the i-th column sub-pixel is located on a side of the active pattern 41 of the fourth transistor of the i-th column sub-pixel close to the adjacent column sub-pixel. In the second direction D2, the integrated structure of the active pattern 11 of the first transistor and the active pattern 21 of the j-th row sub-pixel is located on a side of the active pattern 41 of the fourth transistor of the j-th row sub-pixel close to the j+1-th row sub-pixel.

[0294] In an exemplary embodiment, the active pattern 21 of the second transistor and the active pattern 41 of the fourth transistor may have an I-shape. The active pattern 11 of the first transistor may have a straight-line shape.

[0295] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region between the first region and the second region. In an exemplary embodiment, the first region 11-1 of the active pattern 11 of the first transistor may serve as the first region 21-1 of the active pattern 21 of the second transistor, and the second region 11-2 of the active pattern 11 of the first transistor, the second region 21-2 of the active pattern 21 of the second transistor, and the first region 41-1 and the second region 41-2 of the active pattern 41 of the fourth transistor may be separately provided.

[0296] In an exemplary embodiment, orthographic projections of the active patterns 11 of the first transistor, 21 of the second transistor, and 41 of the fourth transistor on the substrate at least partially overlap with an orthographic projection of the first power line VDDL on the substrate.

[0297] In an exemplary embodiment, the second region 11 - 2 of the active pattern 11 of the first transistor is connected to the second electrode of the third transistor through a third via hole.

[0298] (7) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second semiconductor layer, wherein a plurality of via holes are disposed on the fourth insulating layer, such as Fig.16 shown. Fig.16 It is a schematic diagram after forming the fourth insulating layer.

[0299] In an exemplary embodiment, if Fig.16 As shown, the via holes on the fourth insulating layer include at least: a fourth via hole V4, a fifth via hole V5, a sixth via hole V6, a seventh via hole V7, an eighth via hole V8 and a ninth via hole V9 located in at least one sub-pixel.

[0300] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the gate electrode of the third transistor (also the first plate of the capacitor) on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the fourth via hole V4 are etched, and the surface of the second electrode of the third transistor is exposed, and the fourth via hole V4 is configured to connect the second electrode of the subsequently formed second transistor (also the second electrode of the fourth transistor) to the gate electrode of the third transistor (also the first plate of the capacitor) through the via hole.

[0301] In an exemplary embodiment, the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the first transistor (also the first area of ​​the active pattern of the second transistor) on the substrate, the fifth via V5 exposes the surface of the first area of ​​the active pattern of the first transistor (also the first area of ​​the active pattern of the second transistor), and the fifth via V5 is configured to connect the first electrode of the subsequently formed first transistor (also the first electrode of the second transistor) to the first area of ​​the active pattern of the first transistor (also the first area of ​​the active pattern of the second transistor) through the via.

[0302] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the first transistor on the substrate, the sixth via V6 exposes the surface of the second area of ​​the active pattern of the first transistor, and the sixth via V6 is configured to connect the second electrode of the subsequently formed first transistor T1 to the second area of ​​the active pattern of the first transistor through the via.

[0303] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the second transistor on the substrate, and the surface of the second area of ​​the active pattern of the second transistor is exposed by the seventh via V7. The seventh via V7 is configured to connect the second electrode of the subsequently formed second transistor (which is also the second electrode of the fourth transistor) to the second area of ​​the active pattern of the second transistor through the via.

[0304] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fourth transistor on the substrate, the eighth via V8 exposes the surface of the first area of ​​the active pattern of the fourth transistor, and the eighth via V8 is configured to connect the first electrode of the subsequently formed fourth transistor to the first area of ​​the active pattern of the fourth transistor through the via.

[0305] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the fourth transistor on the substrate, the ninth via V9 exposes the surface of the second area of ​​the active pattern of the fourth transistor, and the ninth via V9 is configured to connect the second electrode of the subsequently formed second transistor (which is also the second electrode of the fourth transistor) to the second area of ​​the active pattern of the fourth transistor through the via.

[0306] (8) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on the fourth insulating layer, such as Fig.17 and Fig.18 As shown, Fig.17 is a schematic diagram of a pattern of a third conductive layer, Fig.18 It is a schematic diagram after forming the third conductive layer pattern.

[0307] In an exemplary embodiment, if Fig.17 and Fig.18 As shown, the third conductive layer pattern includes at least: a scanning signal line GL, a sensing control signal line SL, a reset signal line RL, and a gate electrode 12, a first electrode 13, and a second electrode 14 of a first transistor located in at least one sub-pixel, a gate electrode 22, a first electrode 23, and a second electrode 24 of a second transistor, and a gate electrode 42, a first electrode 43, and a second electrode 44 of a fourth transistor.

[0308] In an exemplary embodiment, the scanning signal line connected to the j-th row of sub-pixels is located on a side of the sensing control signal line SL connected to the j-th row of sub-pixels close to the j-1-th row of sub-pixels, and the reset signal line RL connected to the j-th row of sub-pixels is located on a side of the sensing control signal line SL connected to the j-th row of sub-pixels close to the j+1-th row of sub-pixels.

[0309] In an exemplary embodiment, the scan signal line GL may be in the shape of a line whose main portion extends along the first direction D1 , and a region where the scan signal line GL overlaps with an active pattern of the fourth transistor of the present subpixel serves as a gate electrode 42 of the fourth transistor.

[0310] In an exemplary embodiment, the sensing control signal line SL may be in the shape of a line whose main portion extends along the first direction D1. The region where the sensing control signal line SL overlaps with the active pattern of the second transistor of the sub-pixel serves as the gate electrode 22 of the second transistor.

[0311] In an exemplary embodiment, the reset signal line RL may be in the shape of a line whose main portion extends along the first direction D1. The area where the reset signal line RL overlaps with the active pattern of the first transistor of the sub-pixel serves as the gate electrode 12 of the first transistor.

[0312] In an exemplary embodiment, the first electrodes 13 and 14 of the first transistor, the first electrodes 23 and 24 of the second transistor, and the first electrodes 43 and 44 of the fourth transistor located in adjacent sub-pixels in the same row are symmetrically arranged with respect to a center line O extending along the second direction D2 of the adjacent sub-pixels.

[0313] In an exemplary embodiment, the first electrode 13 of the first transistor and the first electrode 23 of the second transistor are an integrated structure. The integrated structure of the first electrode 13 of the first transistor and the first electrode 23 of the second transistor is block-shaped and connected to the first region of the active pattern of the first transistor (also the first region of the active pattern of the second transistor) through the fifth via.

[0314] In an exemplary embodiment, the second electrode 14 of the first transistor is separately provided. The second electrode 14 of the first transistor is block-shaped and connected to the second region of the active pattern of the first transistor through a sixth via hole.

[0315] In an exemplary embodiment, the second electrode 24 of the second transistor and the second electrode 44 of the fourth transistor are an integrated structure. The integrated structure of the second electrode 24 of the second transistor and the second electrode 44 of the fourth transistor is strip-shaped and extends along the first direction D1. The integrated structure of the second electrode 24 of the second transistor and the second electrode 44 of the fourth transistor is connected to the gate electrode of the third transistor (also the first electrode plate of the capacitor) through the fourth via hole, connected to the second area of ​​the active pattern of the second transistor through the seventh via hole, and connected to the first area of ​​the active pattern of the fourth transistor through the eighth via hole.

[0316] In an exemplary embodiment, the first electrode 43 of the fourth transistor is separately provided. The first electrode 43 of the fourth transistor is block-shaped and connected to the second region of the active pattern of the fourth transistor through a ninth via hole.

[0317] In an exemplary embodiment, the second electrode 14 of the first transistor is connected to the second electrode of the third transistor through the second electrode of the active pattern of the first transistor.

[0318] In an exemplary embodiment, the scanning signal line GL, the sensing control signal line SL, and the reset signal line RL can be designed with equal width, or can be designed with unequal width, can be straight lines, or can be broken lines, which can not only facilitate the layout of the pixel structure but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.

[0319] (9) Forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a first planar layer covering the third conductive layer pattern, wherein a plurality of vias are disposed on the first planar layer, such as Fig.19 As shown, Fig.19 It is a schematic diagram after forming the first planarization layer.

[0320] In an exemplary embodiment, if Fig.19 As shown, the plurality of via holes at least include: a tenth via hole V10, an eleventh via hole V11, and a twelfth via hole V12 located in at least one sub-pixel.

[0321] In an exemplary embodiment, the orthographic projection of the tenth via V10 on the substrate is located within the range of the orthographic projection of the first electrode of the first transistor (also the first electrode of the second transistor) on the substrate, the tenth via V10 exposes the surface of the first electrode of the first transistor (also the first electrode of the second transistor), and the tenth via V10 is configured to connect a subsequently formed control signal line through the via to the first electrode of the first transistor (also the first electrode of the second transistor).

[0322] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the second electrode of the first transistor on the substrate, the eleventh via hole V11 exposes the surface of the second electrode of the first transistor, and the eleventh via hole V11 is configured to connect a subsequently formed anode connection line to the second electrode of the first transistor through the via hole.

[0323] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the first electrode of the fourth transistor on the substrate, the twelfth via V12 exposes the surface of the first electrode of the fourth transistor, and the twelfth via V12 is configured to connect a subsequently formed data signal line to the first electrode of the fourth transistor through the via.

[0324] (10) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the first planar layer, such as Fig. 20 and Fig.21 As shown, Fig. 20 is a schematic diagram of a fourth conductive layer pattern, Fig.21 It is a schematic diagram after forming the fourth conductive layer pattern.

[0325] In an exemplary embodiment, if Fig. 20 and Fig.21 As shown, the fourth conductive layer pattern at least includes: a data signal line DL, a control signal line CONL, and an anode connection line AL located in at least one sub-pixel.

[0326] In an exemplary embodiment, the shape of the anode connection line AL may be a strip shape in which the main portion extends along the second direction D2, the anode connection line AL is connected to the second electrode of the first transistor through the eleventh via hole, and the anode connection line AL is configured to be connected to the subsequently formed anode. Since the second electrode of the first transistor is also connected to the second electrode of the third transistor, the subsequently formed anode can be connected to the second electrode of the first transistor and the second electrode of the third transistor.

[0327] In an exemplary embodiment, the data signal lines DL connected to adjacent sub-pixels in the same row are symmetrically arranged with respect to a center line O extending along the second direction D2 of the adjacent sub-pixels. The control signal lines CONL connected to adjacent sub-pixels in the same row are symmetrically arranged with respect to a center line O extending along the second direction D2 of the adjacent sub-pixels.

[0328] In an exemplary embodiment, the shape of the data signal line DL may be a zigzag shape with a main portion extending along the second direction D1. The data signal line DL is connected to the first electrode of the fourth transistor through the twelfth via hole.

[0329] In an exemplary embodiment, the control signal line CONL may be in a zigzag shape with a main portion extending along the second direction D1. The control signal line CONL is connected to the first electrode of the first transistor (also the first electrode of the second transistor) through the tenth via hole.

[0330] (11) Forming a second planar layer pattern. In an exemplary embodiment, forming the second planar layer pattern may include: coating a second planar film on the substrate on which the aforementioned pattern is formed, patterning the second planar film using a patterning process to form a second planar layer covering the fourth conductive layer pattern, and providing a plurality of via holes on the second planar layer, such as Fig. 22 As shown, Fig. 22 It is a schematic diagram after forming the second planarization layer.

[0331] In an exemplary embodiment, if Fig. 22 As shown, the plurality of via holes at least include: a thirteenth via hole V13 located in at least one sub-pixel.

[0332] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the anode connecting line on the substrate, the thirteenth via hole V13 exposes the surface of the anode connecting line, and the thirteenth via hole V13 is configured to connect the first electrode of the subsequently formed light-emitting device to the anode connecting line through the via hole.

[0333] At this point, the drive circuit layer is prepared on the substrate. In a plane parallel to the display substrate, the drive circuit layer may include a plurality of circuit units, each of which may include a pixel drive circuit, and the pixel drive circuit is connected to a scanning signal line, a light emitting control signal line, a sensing control signal line, a reset signal line, a first power line, a data signal line, and a control signal line. In a plane perpendicular to the display substrate, the drive circuit layer may be disposed on the substrate, and the substrate may include a first flexible layer, a barrier layer, and a second flexible layer stacked.

[0334] The driving circuit layer may include a first semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a second semiconductor layer, a fourth insulating layer, a third conductive layer, a first planar layer, a fourth conductive layer and a second planar layer, which are sequentially arranged on a substrate.

[0335] In example embodiments, the first semiconductor layer may be an amorphous silicon layer or a polycrystalline silicon layer.

[0336] In an exemplary embodiment, the second semiconductor layer may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0337] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0338] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer.

[0339] In an exemplary embodiment, the first planarization layer and the second planarization layer may employ an organic material such as resin or the like.

[0340] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer is prepared on the driving circuit layer. The preparation process of the light emitting structure layer may include the following operations.

[0341] (12) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer pattern may include: depositing a fifth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fifth conductive film using a patterning process, and forming a fifth conductive layer disposed on the second planar layer, such as Fig.23 and Fig.24 As shown, Fig.23 is a schematic diagram of a fifth conductive layer pattern, Fig.24 It is a schematic diagram after forming the fifth conductive layer pattern.

[0342] In an exemplary embodiment, if Fig.23 and Fig.24 As shown, the fifth conductive layer pattern at least includes: a plurality of first electrodes.

[0343] In an exemplary embodiment, the fifth conductive layer has a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0344] In an exemplary embodiment, the plurality of first electrodes may include a first anode AN1 of a light emitting device emitting a first color light, a second anode AN2 of a light emitting device emitting a second color light, and a third anode AN3 of a light emitting device emitting a third color.

[0345] In an exemplary embodiment, the first anode AN1 and the second anode AN2 are alternately arranged along the first direction D1. The plurality of third anodes AN3 are alternately arranged along the first direction D1. A virtual straight line extending along the second direction D2 passing through the center of the third anode AN3 is located between a virtual straight line extending along the second direction D2 passing through the center of the first anode AN1 and a virtual straight line extending along the second direction D2 passing through the center of the second anode AN2.

[0346] In an exemplary embodiment, the first electrode of the light emitting device is connected to the anode connection line through a thirteenth via hole.

[0347] In an exemplary embodiment, the first electrode may include an anode main body and an anode connection part connected to each other, and the anode connection part is connected to the anode connection line through the thirteenth via hole. The shape of the anode main body may be rectangular, and the corners of the rectangle may be provided with arc-shaped chamfers.

[0348] (13) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer pattern may include: coating a pixel definition film on a substrate formed with the aforementioned pattern, patterning the pixel definition film using a patterning process to form a pixel definition layer, wherein a pixel opening PV is provided on the pixel definition layer of each sub-pixel, and the pixel definition film in the pixel opening PV is removed to expose the first electrode of the sub-pixel, such as Fig.25 As shown, Fig.25 This is a schematic diagram after the pixel definition layer is formed.

[0349] In an exemplary embodiment, an orthographic projection of the pixel opening on the substrate does not overlap with an orthographic projection of the thirteenth via hole on the substrate.

[0350] In an exemplary embodiment, the subsequent preparation process may include: first forming an organic light-emitting layer by an evaporation or inkjet printing process, then forming a cathode on the organic light-emitting layer, and then forming a packaging structure layer, the packaging structure layer may include a stacked first packaging layer, a second packaging layer and a third packaging layer, the first packaging layer and the third packaging layer may be made of inorganic materials, the second packaging layer may be made of organic materials, and the second packaging layer is arranged between the first packaging layer and the third packaging layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0351] Fig.26 is a cross-sectional view of a display device. The present disclosure also provides a display device such as Fig.26 As shown, the display device provided by the embodiment of the present disclosure includes: a display substrate 10 and a light sensor 20. The orthographic projection of the light sensor 20 on the substrate at least partially overlaps with the first display area A1. External ambient light can be incident on the light sensor through the first display area.

[0352] In an exemplary embodiment, the display device may be an organic light-emitting diode (OLED) display device, an active-matrix organic light-emitting diode (AMOLED) display device, a mobile phone, a tablet computer, a flexible display device, a television set, a monitor, or any other product or component having a display function.

[0353] The display substrate may be the display substrate provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be described in detail here.

[0354] In an exemplary embodiment, the area of ​​the positive projection of the light sensor on the substrate may be smaller than or equal to the area of ​​the inscribed circle of the first display area. That is, the size of the area where the light sensor is located may be smaller than or equal to the size of the inscribed circle of the first display area. For example, the size of the area where the light sensor is located is equal to the size of the inscribed circle of the first display area, that is, the shape of the area where the light sensor is located may be circular, and accordingly, the area where the light sensor is located may also be referred to as a light-transmitting hole.

[0355] In an exemplary embodiment, the photosensor may include at least one of a camera module (e.g., a front camera module), a 3D structured light module (e.g., a 3D structured light sensor), a time-of-flight 3D imaging module (e.g., a time-of-flight sensor), an infrared sensing module (e.g., an infrared sensing sensor), etc.

[0356] In an exemplary embodiment, the front camera module is usually enabled when the user takes a selfie or makes a video call, and the display area of ​​the display device displays the image obtained by the selfie for the user to watch. The front camera module includes, for example, a lens, an image sensor, an image processing chip, etc. The optical image of the scene generated by the lens is projected onto the surface of the image sensor (the image sensor includes CCD and CMOS) and converted into an electrical signal, which is converted into a digital image signal after analog-to-digital conversion by the image processing chip, and then processed and output on the display screen.

[0357] The drawings in the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0358] For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness and size of the layer or microstructure are exaggerated. It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or there may be intermediate elements.

[0359] Although the embodiments disclosed in the present disclosure are as above, the contents described are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any technician in the field to which the present disclosure belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the scope of patent protection of the present disclosure shall still be subject to the scope defined in the attached claims.

Claims

1. A pixel driving circuit, configured to drive a light-emitting device to emit light, characterized in that: Including: a reset sensing subcircuit, a driving subcircuit, a node control subcircuit and a light emitting control subcircuit; The driving subcircuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node under the control of the signals of the first node and the second node; The reset sensing sub-circuit is electrically connected to the sensing control signal terminal, the reset signal terminal, the control signal terminal, the first node and the third node respectively, and is configured to provide the reference signal provided by the control signal terminal to the third node, or provide the signal of the first node or the third node to the control signal terminal under the control of the signals of the reset signal terminal and the sensing control signal terminal; The node control subcircuit is electrically connected to the scan signal terminal, the data signal terminal, the first node and the first power supply terminal respectively, and is configured to provide the signal of the data signal terminal to the first node under the control of the signal of the scan signal terminal, and store the voltage difference between the signal of the first node and the signal of the first power supply terminal; The light emitting control subcircuit is electrically connected to the light emitting control signal terminal, the first power supply terminal and the second node respectively, and is configured to provide the signal of the first power supply terminal to the second node under the control of the signal of the light emitting control signal terminal; The light emitting device is electrically connected to the third node and the second power supply terminal respectively.

2. The pixel driving circuit according to claim 1, characterized in that: The reset induction subcircuit comprises: a first induction subcircuit and a second induction subcircuit; The first sensing sub-circuit is electrically connected to the reset signal terminal, the control signal terminal and the third node respectively, and is configured to provide the reference signal provided by the control signal terminal to the third node, or provide the signal of the third node to the control signal terminal, under the control of the signal of the reset signal terminal; The second sensing sub-circuit is electrically connected to the sensing control signal terminal, the control signal terminal and the first node respectively, and is configured to provide the signal of the first node to the control signal terminal under the control of the signal of the sensing control signal terminal.

3. The pixel driving circuit according to claim 2, characterized in that: The first sensing subcircuit includes: a first transistor, and the second sensing subcircuit includes: a second transistor; The gate electrode of the first transistor is electrically connected to the reset signal terminal, the first electrode of the first transistor is electrically connected to the control signal terminal, and the second electrode of the first transistor is electrically connected to the third node; A gate electrode of the second transistor is electrically connected to the sensing control signal terminal, a first electrode of the second transistor is connected to the control signal terminal, and a second electrode of the second transistor is electrically connected to the first node.

4. The pixel driving circuit according to claim 1, characterized in that: The reset sensing subcircuit includes: a first transistor and a second transistor, the driving subcircuit includes: a third transistor, the node control subcircuit includes: a fourth transistor and a capacitor, the capacitor includes: a first plate and a second plate, and the light emitting control subcircuit includes: a fifth transistor; The gate electrode of the first transistor is electrically connected to the reset signal terminal, the first electrode of the first transistor is electrically connected to the control signal terminal, and the second electrode of the first transistor is electrically connected to the third node; The gate electrode of the second transistor is electrically connected to the sensing control signal terminal, the first electrode of the second transistor is connected to the control signal terminal, and the second electrode of the second transistor is electrically connected to the first node; The gate electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node; The gate electrode of the fourth transistor is electrically connected to the scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the first node; The gate electrode of the fifth transistor is electrically connected to the light emitting control signal terminal, the first electrode of the fifth transistor is connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node; The first plate of the capacitor is connected to the first node, and the second plate of the capacitor is electrically connected to the first power supply terminal.

5. The pixel driving circuit according to claim 4, characterized in that: The first transistor, the second transistor and the fourth transistor are N-type transistors, and the third transistor and the fifth transistor are P-type transistors.

6. A driving method for a pixel driving circuit, characterized in that: is configured to drive the pixel driving circuit according to any one of claims 1 to 5, wherein the pixel driving circuit is arranged in a display substrate, and the working process of the display substrate includes: a display phase and a non-display phase; In the display stage and the non-display stage, the driving method of the pixel driving circuit includes: The driving subcircuit provides a driving signal to the third node under the control of the signals of the first node and the second node; The reset sensing subcircuit provides the reference signal provided by the control signal terminal to the third node, or provides the signal of the first node or the third node to the control signal terminal, under the control of the signals of the reset signal terminal and the sensing control signal terminal; The node control subcircuit provides the signal of the data signal terminal to the first node under the control of the signal of the scan signal terminal, and stores the voltage difference between the signal of the first node and the signal of the first power terminal; The light emitting control subcircuit provides the signal of the first power supply terminal to the second node under the control of the signal of the light emitting control signal terminal.

7. The method according to claim 6, characterized in that The display stage includes: a first reset stage, a first data writing stage and a light emitting stage; The signal of the sensing control signal end in the display stage is an invalid level signal, the signal of the reset signal end in the first reset stage is a valid level signal, and the signal in the first data writing stage and the light emitting stage is an invalid level signal, the signal of the scanning signal end in the first data writing stage is a valid level signal, and the signal in the first reset stage and the light emitting stage is an invalid level signal, the signal of the light emitting control signal end in the light emitting stage is a valid level signal, and the signal in the first reset stage and the first data writing stage is an invalid level signal; In the display stage, the driving method of the pixel driving circuit includes: In the first reset phase, the reset sensing subcircuit provides the reference signal provided by the control signal terminal to the third node under the control of the signal at the reset signal terminal; In the first data writing phase, the node control subcircuit provides the signal of the data signal terminal to the first node under the control of the signal of the scan signal terminal, and stores the voltage difference between the signal of the first node and the signal of the first power terminal; In the light-emitting stage, the light-emitting control subcircuit provides the signal of the first power supply end to the second node under the control of the signal of the light-emitting control signal end, and the driving subcircuit provides the driving signal to the third node under the control of the signals of the first node and the second node.

8. The method according to claim 6, characterized in that The non-display stage includes: a first sensing stage, the first sensing stage occurs before the display stage, and the first sensing stage includes: a second reset stage, a second data writing stage and a first sampling stage; The signal of the sensing control signal end in the first sensing stage is an invalid level signal, the signal of the reset signal end in the second reset stage and the first sampling stage is a valid level signal, and the signal in the second data writing stage is an invalid level signal, the signal of the scanning signal end in the second data writing stage is a valid level signal, and the signal in the second reset stage and the first sampling stage is an invalid level signal, the signal of the light emitting control signal end in the first sampling stage is a valid level signal, and the signal in the second reset stage and the second data writing stage is an invalid level signal; In the first sensing stage, the driving method of the pixel driving circuit includes: In the second reset phase, the reset sensing subcircuit provides the reference signal provided by the control signal terminal to the third node under the control of the signal at the reset signal terminal; In the second data writing phase, the node control subcircuit provides the signal of the data signal terminal to the first node under the control of the signal of the scan signal terminal, and stores the voltage difference between the signal of the first node and the signal of the first power terminal; In the first sampling stage, the light-emitting control subcircuit provides the signal of the first power supply terminal to the second node under the control of the signal of the light-emitting control signal terminal, the driving subcircuit provides the driving signal to the third node under the control of the signals of the first node and the second node, and the reset sensing subcircuit provides the signal of the third node to the control signal terminal under the control of the signal of the reset signal terminal.

9. The method according to claim 8, characterized in that The display substrate further comprises: an integrated circuit electrically connected to the pixel driving circuit; The integrated circuit acquires the signal of the third node, processes the signal of the third node, and provides the processed signal of the third node to the pixel driving circuit to compensate for the brightness of the light emitting device.

10. The method according to claim 6, characterized in that The non-display stage includes: a second sensing stage, the second sensing stage occurs before the display stage, and the second sensing stage includes: a third reset stage, a third data writing stage, and a second sampling stage; The signal of the reset signal end in the third reset stage is a valid level signal, and the signal in the third data writing stage and the second sampling stage is an invalid level signal, the signal of the scanning signal end in the third data writing stage is a valid level signal, and the signal in the third reset stage and the second sampling stage is an invalid level signal, the signal of the light emitting control signal end in the second sampling stage is a valid level signal, and the signal in the third reset stage and the third data writing stage is an invalid level signal, the signal of the sensing control signal end in the second sampling stage is a valid level signal, and the signal in the third reset stage and the third data writing stage is an invalid level signal; In the second sensing stage, the driving method of the pixel driving circuit includes: In the third reset stage, the reset sensing subcircuit provides the reference signal provided by the control signal terminal to the third node under the control of the signal of the reset signal terminal; In the third data writing phase, the node control subcircuit provides the signal of the data signal terminal to the first node under the control of the signal of the scan signal terminal, and stores the voltage difference between the signal of the first node and the signal of the first power terminal; In the second sampling stage, the light-emitting control subcircuit provides the signal of the first power supply terminal to the second node under the control of the signal of the light-emitting control signal terminal, the driving subcircuit provides the driving signal to the third node under the control of the signals of the first node and the second node, and the reset sensing subcircuit provides the signal of the first node to the control signal terminal under the control of the signal of the sensing control signal terminal.

11. The method according to claim 10, characterized in that The display substrate further comprises: an integrated circuit electrically connected to the pixel driving circuit; The integrated circuit acquires the signal of the first node, processes the signal of the first node, and provides the processed signal of the first node to the pixel driving circuit to compensate for the threshold voltage of the driving transistor in the pixel driving circuit.

12. A display substrate, characterized in that: The invention comprises: a substrate, the substrate comprising: a display area and a non-display area surrounding the display area, the display area comprising: a first display area and a second display area, the second display area being located at least on one side of the first display area; The first display area includes: a plurality of first sub-pixels, the second display area includes: a plurality of second sub-pixels, and at least one of the first sub-pixels and the second sub-pixels includes: the pixel driving circuit according to any one of claims 1 to 5.

13. The display substrate according to claim 12, characterized in that: The pixel driving circuit includes: at least one P-type transistor and at least one N-type transistor; An orthographic projection of the at least one P-type transistor on the substrate at least partially overlaps with an orthographic projection of the at least one N-type transistor on the substrate.

14. The display substrate according to claim 13, characterized in that: The transistor includes an active pattern, and an orthographic projection of the active pattern of the at least one N-type transistor on the substrate at least partially overlaps with an orthographic projection of the active pattern of the at least one P-type transistor on the substrate.

15. The display substrate according to claim 14, characterized in that: An orthographic projection of the active pattern of the at least one N-type transistor on the substrate is located within an orthographic projection of the active pattern of the at least one P-type transistor on the substrate.

16. The display substrate according to claim 14, characterized in that: The display area further includes: at least one first power line; The orthographic projection of the first power line on the substrate at least partially overlaps with the orthographic projection of the active pattern of the at least one P-type transistor on the substrate, and the orthographic projection of the first power line on the substrate at least partially overlaps with the orthographic projection of the active pattern of the at least one N-type transistor on the substrate; The active pattern of the at least one P-type transistor is located on a side of the first power line close to the substrate, and the active pattern of the at least one N-type transistor is located on a side of the first power line far from the substrate.

17. The display substrate according to claim 12, characterized in that: The display area further comprises: pixel units arranged in an array, at least one light emitting control signal line, at least one reset signal line, at least one scanning signal line, at least one sensing control signal line, at least one data signal line, at least one control signal line and at least one first power supply line, at least one pixel unit comprises: at least one sub-pixel arranged along a first direction; The at least one pixel unit is electrically connected to the light emitting control signal line, the reset signal line, the scanning signal line, the sensing control signal line, N data signal lines, N control signal lines and N first power lines, respectively, where N is the number of sub-pixels in a pixel unit.

18. The display substrate according to claim 17, characterized in that: Pixel structures of adjacent sub-pixels among the plurality of sub-pixels arranged along the first direction are at least partially symmetrically arranged with respect to a virtual straight line extending along a second direction, and the first direction and the second direction intersect.

19. The display substrate according to claim 12, characterized in that: The display area further includes: at least one data signal line and at least one control signal line, wherein the data signal line and the control signal line at least partially extend along the second direction; The data signal line is electrically connected to a data signal terminal connected to the pixel driving circuit, and the control signal line is electrically connected to a control signal terminal connected to the pixel driving circuit; The data signal lines connecting adjacent sub-pixels among the multiple sub-pixels arranged along the first direction are symmetrically arranged relative to the center line of the adjacent sub-pixels, and the control signal lines connecting adjacent sub-pixels among the multiple sub-pixels arranged along the first direction are symmetrically arranged relative to the center line of the adjacent sub-pixels.

20. The display substrate according to claim 12, characterized in that: The display area further includes: at least one first power line; the first power line at least partially extends along the second direction; The first power line is electrically connected to the first power terminal connected to the pixel driving circuit, adjacent first power lines are electrically connected, and the first power lines connected to adjacent sub-pixels in a plurality of sub-pixels arranged along the first direction are symmetrically arranged relative to the midline of the adjacent sub-pixels.

21. The display substrate according to claim 20, characterized in that: The first power line includes: a first connection line, a second connection line and a plurality of connection blocks, the first connection line and the second connection line are arranged along a first direction and extend along a second direction, the connection block is arranged between the first connection line and the second connection line, the pixel driving circuit includes: a capacitor, the capacitor includes: a first plate and a second plate; The orthographic projection of the connecting block on the substrate at least partially overlaps with the orthographic projection of the first electrode plate on the substrate, and the multiple connecting blocks located between the first connecting line and the second connecting line are arranged along the second direction and are arranged at intervals, and a closed area is formed between adjacent connecting blocks arranged along the second direction and adjacent first connecting lines and second connecting lines.

22. The display substrate according to claim 12, characterized in that: The display area further includes: at least one light emitting control signal line, at least one reset signal line, at least one scan signal line and at least one sensing control signal line, wherein at least one of the light emitting control signal line, the reset signal line, the scan signal line and the sensing control signal line at least partially extends along the first direction; The light emitting control signal line is electrically connected to the light emitting control signal terminal connected to the pixel driving circuit, the reset signal line is electrically connected to the reset signal terminal connected to the pixel driving circuit, the scanning signal line is electrically connected to the scanning signal terminal connected to the pixel driving circuit, and the sensing control signal line is electrically connected to the sensing control signal terminal connected to the pixel driving circuit; The orthographic projections of the light emitting control signal line, the scanning signal line, the sensing control signal line and the reset signal line connected to at least one sub-pixel on the substrate are arranged in sequence along the second direction; The light emitting control signal line is arranged in a different layer from at least one of the reset signal line, the scanning signal line and the sensing control signal line.

23. The display substrate according to claim 12, characterized in that: Also includes: A driving structure layer is provided on the substrate, wherein the driving structure layer is provided with an anode connection line, a light emitting control signal line, a reset signal line, a scanning signal line, a sensing control signal line, a first power line, a data signal line, a control signal line and the pixel driving circuit, wherein the driving structure layer at least comprises: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer and a fourth conductive layer stacked in sequence in a direction away from the substrate, wherein the pixel driving circuit comprises: at least one P-type transistor, at least one N-type transistor and a capacitor, wherein the transistor comprises: an active pattern, a gate electrode, a first pole and a second pole, and wherein the capacitor comprises: a first plate and a second plate; The first semiconductor layer at least includes: the active pattern of the at least one P-type transistor located in at least one sub-pixel; The first conductive layer at least includes: the light emitting control signal line, the gate electrode of the at least one P-type transistor located in at least one sub-pixel, and the first plate of the capacitor; The second conductive layer at least includes: the first power line, the second electrode plate of the capacitor located in at least one sub-pixel, and the first electrode and the second electrode of the at least one P-type transistor; The second semiconductor layer at least includes: an active pattern of the at least one N-type transistor located in at least one sub-pixel; The third conductive layer at least includes: the reset signal line, the scan signal line, the sensing control signal line, and a gate electrode, a first electrode, and a second electrode of the at least one N-type transistor located in at least one sub-pixel; The fourth conductive layer at least includes: the data signal line, the control signal line, and the anode connection line located in at least one sub-pixel.

24. The display substrate according to claim 19, characterized in that: At least a portion of at least one of the data signal line and the control signal line is a transparent conductive signal line.

25. The display substrate according to claim 23, characterized in that: Also includes: A light emitting structure layer located on a side of the driving structure layer away from the substrate, the light emitting structure layer comprising: a fifth conductive layer and a pixel definition layer sequentially stacked on the substrate, the fifth conductive layer at least comprising: a first electrode of the light emitting device, the pixel definition layer being provided with a plurality of pixel openings, the pixel openings comprising: a first pixel opening, a second pixel opening and a third pixel opening; The light emitting device comprises: a first light emitting device, a second light emitting device and a third light emitting device, wherein the first light emitting device, the second light emitting device and the third light emitting device emit light of different colors; The first pixel opening exposes the first electrode of the first light emitting device, the second pixel opening exposes the first electrode of the second light emitting device, and the third pixel opening exposes the first electrode of the third light emitting device; The area of ​​the first pixel opening located in the first display area is smaller than the area of ​​the first pixel opening located in the second display area, the area of ​​the second pixel opening located in the first display area is smaller than the area of ​​the second pixel opening located in the second display area, and the area of ​​the third pixel opening located in the first display area is smaller than the area of ​​the third pixel opening located in the second display area.

26. The display substrate according to claim 12, characterized in that: The light transmittance of the first display area is greater than the light transmittance of the second display area, and the sub-pixel density of the first display area is less than or equal to the sub-pixel density of the second display area.

27. A display device, characterized in that: A display substrate and a photosensor as claimed in any one of claims 12 to 26; The orthographic projection of the photosensor on the substrate at least partially overlaps with the first display area.

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