Forgetting type bloom filter structure

Abstract

Various implementations described herein relate to a device having a write circuit that provides data for storage. The apparatus may include a memory circuit that stores the data in a leakage bit cell having a capacitive element that gradually discharges for a predetermined period of time. The apparatus may include a read circuit that enables the leakage bit cell to operate as one or more memory storage elements. The apparatus may include a query circuit that identifies a match between query data and output data provided by the read circuit.

Description

Background Art

[0001] This section is intended to provide information relevant to understanding the various technologies described herein. As the title of this section implies, this is a discussion of related art and should in no way be considered prior art. Generally speaking, related art may or may not be considered prior art. Therefore, it should be understood that any statement in this section should be understood in this sense and is not intended to be any admission of prior art.

[0002] In some modern circuit architectures, Bloom filters are configured to perform approximate membership queries (AMQs). One feature is that Bloom filters allow simple checks on whether an element is a member of a data set described by a Bloom filter. In such cases, AMQ returns one of two results: a) definitely not in the data set, or b) possibly in the data set. However, some operations on Bloom filters are generally difficult to implement and have a certain degree of complexity to implement. For example, once a member is submitted to a data set, it may be quite difficult to remove the added member from the data set in the following cases: not rebuilding the entire data set, or not maintaining a large amount of overhead when managing the access history of the data set. Therefore, this may complicate the construction of an adaptive structure that only filters the most recent elements. Although some progress has been made to achieve counting of Bloom filters, this usually requires adding counters for each bit, which may complicate Bloom filters and reduce their desirability as AMQ algorithms, especially for physical implementations in some modern computing systems. Therefore, there is a need for an efficient Bloom filter design that improves integration schemes and techniques to thereby enhance the performance of Bloom filters and related circuits by providing efficient and effective bit cell design schemes and techniques for various memory-based Bloom filter applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The present invention describes various technical implementations with reference to the accompanying drawings. It should be understood that the accompanying drawings illustrate various implementations described herein and are not intended to limit the embodiments described herein.

[0004] Figures 1A to 1C Various diagrams associated with a bit cell structure in a first configuration are illustrated according to various implementations described herein.

[0005] Figure 2 A diagram illustrating a forgetful memory array (FMA) structure according to various implementations described herein.

[0006] Figure 3 A diagram illustrating an oblivious Bloom filter core according to various implementations described herein is illustrated.

[0007] Figure 4A diagram illustrating an oblivious Bloom filter core according to various implementations described herein is illustrated.

[0008] FIG. 5A to FIG. 5C Various diagrams associated with a bit cell structure in a second configuration are illustrated according to various implementations described herein.

[0009] Figure 6 A diagram illustrating a forgetful memory array (FMA) structure according to various implementations described herein.

[0010] Figure 7 A diagram illustrating an oblivious Bloom filter core with flushing according to various implementations described herein is illustrated.

[0011] Figure 8 Process diagrams associated with bitcell structures in various configurations are illustrated according to various implementations described herein.

[0012] Fig. 9 A diagram illustrating a matching output architecture according to various implementations described herein.

[0013] FIG. 10A to FIG. 10C Various diagrams associated with a bit cell structure in a third configuration are illustrated according to various implementations described herein.

[0014] Fig.11 Schematic diagrams illustrating destructive read bitcell structures according to various implementations described herein. DETAILED DESCRIPTION

[0015] Various specific implementations described herein relate to oblivious Bloom filter schemes and techniques for memory applications in various circuit-related designs. In addition, in some specific implementations, the oblivious Bloom filter schemes and techniques described herein compensate for the lack of obliviousness in the Bloom filter by changing the storage method of the Bloom filter itself. Therefore, the various oblivious Bloom filter schemes and techniques described herein provide a capacitive storage element that is ground-referenced or, in some cases, positive supply voltage-referenced. For example, when the capacitive storage element leaks to ground, the capacitive storage element slowly decays or discharges, and any "1" bit gradually decreases to "0". In this way, the Bloom filter "forgets" over time.

[0016] Generally speaking, this leakage discharge technique cannot be implemented using DRAM cells because, in DRAM cells, reads are destructive. One reason for using a non-DRAM implementation is that a failed match should not cause a refresh. In addition, since DRAM reads are destructive, they must be accompanied by a corresponding rewrite; however, in some cases, the rewrite operation may result in an undesired refresh.

[0017] Thus, various oblivious Bloom filter schemes and techniques described herein utilize memory element circuits that store data in leaky bit cells having capacitive elements that gradually discharge over a predetermined period of time.

[0018] Various specific implementations of oblivious Bloom filter schemes and techniques for memory-based applications will now be described herein with reference to the accompanying drawings.

[0019] Figures 1A to 1C Various diagrams associated with a bit cell structure in a first configuration according to a specific implementation as described herein are illustrated. Specifically, Figure 1A A simplified conceptual diagram 100A showing a bit cell structure 104A in a first configuration, Figure 1B A transistor-level diagram 100B of a bit cell structure 104B in a first configuration is shown, and in addition, Figure 1C An operational waveform diagram 100C of the bitcell structure 104C in a first configuration is shown.

[0020] In various implementations, the bitcell architecture may be used to fabricate memory circuits having various integrated circuit (IC) components that may be arranged and / or coupled together as an assembly or some combination of parts that provide a physical circuit design, structure, and / or application. In various cases, methods of designing, providing, and fabricating the bitcell architecture as an integrated device may involve using the various circuit components and / or related structures described herein to implement various techniques associated therewith. Additionally, the bitcell architecture may be integrated with various circuits and / or related components on a single chip, and additionally, the bitcell architecture may be implemented in various embedded devices for automotive, mobile phone, computer, server, and / or Internet of Things (IoT) based applications, including various circuits associated therewith, such as, for example, remote sensor nodes.

[0021] like Figure 1A As shown, the bit cell architecture 104A can be implemented as an oblivious memory device having a leaky bit cell (BC) having at least one capacitive element, such as, for example, a capacitor (C). In addition, the bit cell architecture 104A can include one or more inputs, such as, for example, input data (D) and a reset (RST), and at least one output, such as, for example, output data (Q). In some applications, the input data (D) can refer to inverted input data (D-not), and in addition, the output data can refer to inverted output data (Q-not).

[0022] like Figure 1BAs shown, the bit cell architecture 104B may have a plurality of stages, including a first stage (Stage_1), a second stage (Stage_2), and a third stage (Stage_3), which are arranged and coupled together in a first configuration so as to thereby function as a forgetful memory device with a leaky bit cell (BC) (e.g., as shown in FIG. 1 ). Figure 1A ), the leakage bit cell having at least one capacitive element, such as, for example, a capacitor (C).

[0023] In some implementations, the first stage (Stage_1) may refer to a write element or write circuit stage of a leaky bit cell, wherein the write circuit stage (Stage_1) provides data for storage in the second stage (Stage_2). Additionally, in some applications, the first stage (Stage_1) may include one or more transistors, such as, for example, transistors (T1, T2) coupled together in series between a supply voltage (VDD) and a ground (VSS or GND). As shown, transistor (T1) is coupled between a supply voltage (VDD) and a node (n1), and transistor (T2) is coupled between node (n1) and ground (VSS or GND). Additionally, input data (D-not) is coupled to the gate of transistor (T1), and additionally, an input reset (RST) is coupled to the gate of transistor (T2). Additionally, transistor (T1) may be a P-type transistor, and transistor (T2) may be an N-type transistor; however, other configurations may be used.

[0024] In some implementations, the second stage (Stage_2) may refer to a memory element or memory circuit stage of a leakage bit cell, wherein the memory circuit stage (Stage_2) stores data received from the first stage (Stage_1) in at least one capacitive element (such as, for example, a capacitor (C)), which gradually discharges over a predetermined time period. Additionally, in various applications, the capacitor (C) may have a decay time that is determined by the size of the capacitor (C), the self-leakage current of the capacitor (C), and / or the leakage current of the connected transistors (such as, for example, one or more of the transistors (T1, T2, T3)). Thus, the leakage bit cell may be referred to as a capacitive bit cell having a capacitive element (such as, for example, a capacitor (C)) that gradually discharges over the time period by slowly leaking the stored charge over the time period. Additionally, the capacitor (C) may be coupled between the node (n1) or the node (Vc) and ground (VSS or GND), wherein the node (Vc) refers to the voltage potential of the capacitor (C) at the node (n1).

[0025] In some cases, the capacitive element or capacitor (C) may be referenced to ground (VSS or GND) so that the capacitive element or capacitor (C) slowly leaks to ground (VSS or GND) such that the leaking bit cell is configured to forget the data storage value of the leaking bit cell during the period of time. In other cases, such as Fig. 10B As shown, the capacitive element or capacitor (C) may be referenced to a supply voltage (VDD) so that the capacitive element or capacitor (C) slowly leaks to the supply voltage (VDD) so that the leakage bit cell is configured to forget the data storage value of the leakage bit cell during the period of time. Therefore, in various cases, the leakage bit cell may be provided with a capacitive storage element that is ground (VSS or GND) referenced or supply voltage (VDD) referenced (corresponding to the positive voltage supply (VDD)).

[0026] In some implementations, the third stage (Stage_3) can refer to a read element or read circuit stage of the leakage bit cell, wherein the read circuit stage (Stage_3) enables the leakage bit cell to operate as one or more memory storage elements. In some cases, the read element can refer to a non-destructive read element of the leakage bit cell, wherein the non-destructive read circuit enables the leakage bit cell to operate as a non-destructive memory storage element without performing a destructive read operation that causes a refresh operation. In addition, in some other cases, the read element can refer to a read element as described in reference to Fig.11 The destructive read element described in the bit cell structure 1104 in FIG.

[0027] Additionally, in some applications, the third stage (Stage_3) may include one or more transistors, such as, for example, a transistor (T3) coupled between a supply voltage (VDD) and an output node (Q-not). As shown, the output of transistor (T1) is coupled to the gate of transistor (T3) at node (n1), and additionally, the output of transistor (T3) is coupled to the output node (Q-not). In some cases, transistor (T3) may be a P-type transistor; however, in other cases, other configurations may be used to achieve similar results.

[0028] like Figure 1CAs shown, the operation waveform diagram 100C of the bit cell structure 104A, 104B in the first configuration shows the input data signal (D-not), the Vc signal at the node (n1), the output data signal (Q-not) and the reset signal (RST). As shown, in the time period (t0 to t1), when the reset signal (RST) is deactivated, the input data signal (D-not) triggers the Vc signal at the node (n1) and the output signal (Q-not) is inverted to low, wherein the Vc signal slowly decays or discharges to time (t1). Therefore, when the input data signal (D-not) is high, the Vc signal is triggered to be high, then slowly decays or discharges, and the output signal (Q-not) is low.

[0029] In addition, in the time period (t1 to t2), when the reset signal (RST) is deactivated, the input data signal (D-not) triggers the Vc signal at the node (n1) to be high and the output signal (Q-not) is inverted from low to high at time (t2), wherein the Vc signal slowly decays or discharges to time (t3). In addition, in the time period (t2 to t3), the input data signal (D-not) is low, while the Vc signal at the node (n1) slowly decays or discharges to time (t3), and the output signal (Q-not) remains high during the period when the Vc signal slowly decays or discharges to time (t3).

[0030] In addition, in the time period (t3 to t4), when the reset signal (RST) is deactivated, the input data signal (D-not) triggers the Vc signal at the node (n1) to be high and the output signal (Q-not) is inverted from high to low at time (t3), wherein the Vc signal slowly decays or discharges to time (t4). In addition, at time (t4 and>t4), upon activation and / or triggering of the reset signal (RST) from low to high, the input data signal (D-not) is low, the Vc signal at the node (n1) drops to low, and the output signal (Q-not) rises from low to high.

[0031] Figure 2 A schematic layout diagram 200 of a forgetful memory array (FMA) structure 204 is illustrated in accordance with various implementations described herein.

[0032] In various implementations, the FMA structure 204 may be used to fabricate a memory circuit having various integrated circuit (IC) components that may be arranged and / or coupled together as an assembly or some combination of parts that provide a physical circuit design, structure, and / or application. In various cases, methods of designing, providing, and fabricating the FMA structure 204 as an integrated device may involve using the various circuit components and / or related structures described herein to implement various techniques associated therewith. Additionally, the FMA structure 204 may be integrated with various circuits and / or related components on a single chip, and additionally, the FMA structure 204 may be implemented in various embedded devices for automotive, mobile phone, computer, server, and / or Internet of Things (IoT) based applications (including various circuits associated therewith, such as, for example, remote sensor nodes).

[0033] like Figure 2 As shown, the FMA structure 204 can be as follows Figure 1B The illustrated approach is implemented as an oblivious Bloom filter having an array (BC0, BC1, ..., BCn-1) of leaky bit cells, wherein each leaky bit cell has at least one capacitive element, such as at least one capacitor (C). Thus, the oblivious memory array (FMA) structure 204 may be implemented as an oblivious Bloom filter having one or more leaky bit cells as oblivious memory cells, the one or more leaky bit cells including a capacitive element (C) that gradually discharges over a period of time. In addition, the FMA structure 204 may include one or more inputs, such as, for example, input data (D0, D1, ..., Dn-1), a write enable input (W) and a reset input (RST), and output data (Q0, Q1, ..., Qn-1). In some applications, the output data (Q0, Q1, ..., Qn-1) may refer to inverted output data (Q0-not, Q1-not, ..., Qn-1-not).

[0034] In some implementations, the FMA structure 204 may include logic gates, such as, for example, NAND logic gates (L0, L1, Ln-1), which receive input data (D0, D1, ..., Dn-1), receive a write enable input (W), and then provide inverted input data (D0-not, D1-not, ..., Dn-1-not) to corresponding leakage bit cells (BC0, BC1, ..., BCn-1). For example, each NAND logic gate (L0, L1, Ln-1) receives corresponding input data (D0, D1, ..., Dn-1), receives a write enable input (W), and then provides corresponding inverted input data (D0-not, D1-not, ..., Dn-1-not) to corresponding leakage bit cells (BC0, BC1, ..., BCn-1) in the oblivious memory array (FMA) structure 204. In addition, each corresponding leakage bit cell (BC0, BC1,…, BCn-1) receives corresponding inverted input data (D0-not, D1-not,…, Dn-1-not), receives a reset input (RST), and provides corresponding inverted output data (Q0-not, Q1-not,…, Qn-1-not) as an output from the FMA structure 204.

[0035] Figure 3 A schematic diagram 300 illustrating an oblivious Bloom filter core 304 according to various implementations described herein.

[0036] In various specific implementations, the oblivious Bloom filter core 304 may be used to fabricate a memory circuit having various integrated circuit (IC) components that may be arranged and / or coupled together as an assembly or some combination of parts that provide a physical circuit design, structure, and / or application. In various cases, methods of designing, providing, and fabricating the oblivious Bloom filter core 304 as an integrated device may involve using the various circuit components and / or related structures described herein to implement various techniques associated therewith. Additionally, the oblivious Bloom filter core 304 may be integrated with various circuits and / or related components on a single chip, and the oblivious Bloom filter core 304 may be implemented in various embedded devices for automotive, mobile phone, computer, server, and / or IoT-based applications, including, for example, remote sensor nodes.

[0037] like Figure 3 As shown, the oblivious Bloom filter core 304 may be as follows Figure 1B The method shown is used Figure 2The oblivious Bloom filter core 304 may be implemented as an oblivious Bloom filter having an array of leaky bit cells (BC0, BC1, ..., BCn-1) as an array of oblivious memory cells, wherein each leaky bit cell has at least one capacitive element, such as at least one capacitor (C). Therefore, the oblivious Bloom filter core 304 may be implemented as an oblivious Bloom filter having an array of leaky bit cells as an array of oblivious memory cells, the array of leaky bit cells including capacitive elements (C) that are gradually discharged over a period of time. In addition, the oblivious Bloom filter core 304 may include one or more inputs, such as, for example, input data (D: D0, D1, ..., Dn-1), a write enable input (W, coupled to E) and a reset input (RST), as well as output data (Q-not: Q0-not, Q1-not, ..., Qn-1-not).

[0038] In some implementations, the oblivious Bloom filter core 304 may include multi-input logic gates, such as, for example, an AND gate (LX), an XOR gate (LY), and an OR gate (LZ). For example, the AND gate (LX) may receive output data (Q-not: Q0-not, Q1-not, ..., Qn-1-not) at an inverting input, receive a query input (Qu) at a non-inverting input, and provide an output to the XOR gate (LY). Additionally, the XOR gate (LY) may receive an output from the AND gate (LX), receive a query input (Qu), and provide an output to the OR gate (LZ). Additionally, the OR gate (LZ) may receive an output from the XOR gate (LY) and provide a matching output (M-not) as an output from the oblivious Bloom filter core 304. In some applications, the logic gates (LX, LY, LZ) refer to a query circuit that identifies a match between query data (input Qu) and output data (Q-not: Q0-not, Q1-not,…, Qn-1-not) provided by a read element or read circuit stage of the forgetful Bloom filter core 304.

[0039] In some applications, upon receiving a query input (Qu), the query circuit (LX, LY, LZ) may invert a data bit of the output data (Q-not) and then mask the inverted data bit of the output data (Q-not) to isolate the inverted data bit of the output data (Q-not) having a high logic state. After isolating the inverted data bit, the query circuit (LX, Ly, LZ) may XOR the masked inverted data bit with the data bit of the query input (Qu) (e.g., through LY) to generate the queried output data. If there is a match between the data bit of the stored input data and the data bit of the queried output data, the query circuit (LX, LY, LZ) may assert a match signal (M-not). Otherwise, if there is a mismatch between the data bit of the stored input data and the data bit of the queried output data, the query circuit (LX, LY, LZ) may be configured to assert a mismatch signal with the M signal.

[0040] Figure 4 A diagram 400 is illustrated of an oblivious bloom filter core 404 with a hash function according to various implementations described herein.

[0041] like Figure 4 As shown, the oblivious bloom filter core 404 is available Figure 3 The FBF core 304 is implemented by a data hash circuit for write operations and a query hash circuit for query operations. In some applications, the data hash circuit has a hash function block (H10, ..., H1k-1) that receives a data input (D) and then provides a hash data input to a corresponding decoder block (decoder 1 (0), ..., decoder 1 (k-1)), which then provides the decoded hash data to a logic device (LD) (such as, for example, an OR gate), which then provides the write data to the D input of the FBF core 304. Additionally, in some applications, the query hash circuit has a hash function block (H20, ..., H2k-1) that receives a query input (Q) and provides the hashed query input to a corresponding decoder block (decoder2(0), ..., decoder2(k-1)), which then provides the decoded hashed query input to a logic device (LQ) (such as, for example, an OR gate), which then provides the query data to the Qu input of the FBF core 304. Additionally, the oblivious Bloom filter core 404 includes other inputs, such as, for example, write enable (W) and reset (RST), and the oblivious Bloom filter core 404 includes at least one output, including, for example, a match output (M-not).

[0042] In some implementations, the data query hash functions (H10, ..., H1k-1 and H20, ..., H2k-1) may be configured to write data bits or query data bits in the leaky bit cells of the FBF core 304. In various applications, hash functions are important for Bloom filters, and examples of hash functions may include, but are not limited to, non-cryptographic hash functions. In addition, various other examples of hash functions may include one or more of the following: (including, for example) CRC, FNV1, and SHA. Hash functions may also be used to implement various logic-based filters, including, for example, XOR filters.

[0043] FIG. 5A to FIG. 5C Various diagrams associated with a bit cell structure in a second configuration according to various implementations described herein are illustrated. Specifically, Figure 5A A simplified conceptual diagram 500A showing a bit cell structure 504A in a second configuration, Figure 5B A transistor-level diagram 500B shows a bit cell structure 504B in a second configuration, and Figure 5C Operational waveform diagram 500C of a bitcell structure 504C in a second configuration is shown.

[0044] In various implementations, the bitcell architecture may be used to fabricate memory circuits having various integrated circuit (IC) components that may be arranged and / or coupled together as an assembly or some combination of parts that provide a physical circuit design, structure, and / or application. In various cases, methods of designing, providing, and fabricating the bitcell architecture as an integrated device may involve using the various circuit components and / or related structures described herein to implement various techniques associated therewith. Additionally, the bitcell architecture may be integrated with various circuits and / or related components on a single chip, and additionally, the bitcell architecture may be implemented in various embedded devices for automotive, mobile phone, computer, server, and / or Internet of Things (IoT) based applications, including various circuits associated therewith, such as, for example, remote sensor nodes.

[0045] like Figure 5A As shown, the bit cell architecture 504A can be implemented as an oblivious memory device with a leaky bit cell (BC) having at least one capacitive element, such as, for example, a capacitor (C). In addition, the bit cell architecture 504A can include one or more inputs, such as, for example, input data (D), refresh (R), and reset (RST), and at least one output, such as, for example, output data (Q). In various applications, the input data (D) refers to the inverted input data (D-not), the refresh (R) refers to the inverted refresh (R-not), and in addition, the output data can refer to the inverted output data (Q-not).

[0046] like Figure 5B As shown, the bit cell architecture 504B may have a plurality of stages, including a first stage (Stage_1), a second stage (Stage_2), and a third stage (Stage_3), which are arranged and coupled together in a second configuration to thereby function as a forgetful memory device with a leaky bit cell (BC) (e.g., as shown in FIG. Figure 5A ), the leakage bit cell having at least one capacitive element, such as, for example, a capacitor (C).

[0047] In some implementations, the first stage (Stage_1) may refer to a write element or write circuit stage of a leaky bit cell, wherein the write circuit stage (Stage_1) provides data for storage in the second stage (Stage_2). In addition, in some applications, the first stage (Stage_1) may include one or more transistors, such as, for example, transistors (T1, T2, T4) coupled together in series between a supply voltage (VDD) and a ground (VSS or GND). As shown, transistor (T1) is coupled between the supply voltage (VDD) and a node (n1), and transistor (T2) is coupled between the node (n1) and the ground (VSS or GND). In addition, transistor (T4) is coupled between the supply voltage (VDD) and the node (n1). In addition, input data (D-not) is coupled to the gate of transistor (T1), refresh (R-not) is coupled to the gate of transistor (T4), and in addition, input reset (RST) is coupled to the gate of transistor (T2). Additionally, the transistors (T1, T4) may be P-type transistors, and additionally, the transistor (T2) may be an N-type transistor; however, various other configurations may be used.

[0048] In some specific implementations, the second stage (Stage_2) may refer to a memory element or memory circuit stage of a leakage bit cell, wherein the memory circuit stage (Stage_2) stores data received from the first stage (Stage_1) in at least one capacitive element (such as, for example, a capacitor (C)), which gradually discharges over a predetermined time period. Additionally, in various applications, the capacitor (C) may have a decay time that is determined by the size of the capacitor (C), the self-leakage current of the capacitor (C), and / or the leakage current of the connected transistors (such as, for example, one or more of the transistors (T1, T2, T4)). Thus, the leakage bit cell may be referred to as a capacitive bit cell having a capacitive element (such as, for example, a capacitor (C)) that gradually discharges over the time period by slowly leaking the stored charge over the time period. Additionally, the capacitor (C) may be coupled between the node (n1) or the node (Vc) and ground (VSS or GND), wherein the node (Vc) refers to the voltage potential of the capacitor (C) at the node (n1).

[0049] In some cases, the capacitive element or capacitor (C) may be referenced to ground (VSS or GND) so that the capacitive element or capacitor (C) slowly leaks to ground (VSS or GND) such that the leaking bit cell is configured to forget the data storage value of the leaking bit cell during the period of time. In other cases, such as Fig. 10B As shown, the capacitive element or capacitor (C) may be referenced to a supply voltage (VDD) so that the capacitive element or capacitor (C) slowly leaks to the supply voltage (VDD) so that the leakage bit cell is configured to forget the data storage value of the leakage bit cell during the period of time. Therefore, in various cases, the leakage bit cell may be provided with a capacitive storage element that is ground (VSS or GND) referenced or supply voltage (VDD) referenced (corresponding to the positive voltage supply (VDD)).

[0050] In some implementations, the third stage (Stage_3) can refer to a read element or read circuit stage of a leakage bit cell, wherein the read circuit stage (Stage_3) enables the leakage bit cell to operate as one or more memory storage elements. In some cases, the read element can refer to a non-destructive read element of the leakage bit cell, wherein the non-destructive read circuit enables the leakage bit cell to operate as a non-destructive memory storage element. In other cases, the read element can refer to a read element as described in reference to Fig.11 The destructive read element described in the bit cell structure 1104 in FIG.

[0051] Additionally, in some applications, the third stage (Stage_3) may include a Schmitt trigger (ST1) coupled between the node (n1) and the output node (Q-not). Thus, the input of the Schmitt trigger (ST1) is coupled to the node (n1), and the output of the Schmitt trigger (ST1) is coupled to the output node (Q-not). Thus, the non-destructive read element, circuit, and / or stage (Stage_3) may be implemented using a Schmitt trigger.

[0052] like Figure 5C As shown, the operation waveform diagram 500C of the bit cell structure 504A, 504B in the second configuration shows the input data signal (D-not), the Vc signal at the node (n1), the output data signal (Q-not), the refresh signal (R-not) and the reset signal (RST). As shown in the figure, in the time period (t0 to t1), during the period when the reset signal (RST) is activated to high, the input data signal (D-not) is low, the Vc signal at the node (n1) is low, the output data signal (Q-not) is high, and the refresh signal (R-not) is high.

[0053] In addition, in the time period (t1 to t2), when the reset signal (RST) is deactivated, the input data signal (D-not) triggers the Vc signal to be high at the node (n1) and the output signal (Q-not) is inverted to be low, wherein the Vc signal slowly decays or discharges to the time (t2 and t3). Therefore, when the input data signal (D-not) is high, the Vc signal is triggered to be high, then slowly decays or discharges, and the output signal (Q-not) is low. In addition, in the time period (t2 to t3), the input data signal (D-not) is low, while the Vc signal at the node (n1) continues to slowly decay or discharge to the time (t3), and the output signal (Q-not) is inverted to be high during the slow decay or discharge of the Vc signal from the time (t2) to the time (t3).

[0054] In addition, in the time period (t3 to t4), the input data signal (D-not) triggers the Vc signal to be high at the node (n1) and the output signal (Q-not) is inverted from high to low at time (t3), and the reset signal (RST) is deactivated, wherein the Vc signal slowly decays or discharges to time (t4). In addition, at time (t4 and>t4), refresh (R-not low) is activated, and the input data signal (D-not) is low, the Vc signal at the node (n1) rises to high, then slowly decays or discharges, and the output signal (Q-not) remains low.

[0055] Figure 6A diagram 600 illustrating a forgetful memory array (FMA) structure 604 in accordance with various implementations described herein.

[0056] In various implementations, the FMA structure 604 may be used to fabricate a memory circuit having various integrated circuit (IC) components that may be arranged and / or coupled together as an assembly or some combination of parts that provide a physical circuit design, structure, and / or application. In various cases, methods of designing, providing, and fabricating the FMA structure 604 as an integrated device may involve using the various circuit components and / or related structures described herein to implement various techniques associated therewith. Additionally, the FMA structure 604 may be integrated with various circuits and / or related components on a single chip, and additionally, the FMA structure 604 may be implemented in various embedded devices for automotive, mobile phone, computer, server, and / or Internet of Things (IoT) based applications (including various circuits associated therewith, such as, for example, remote sensor nodes).

[0057] like Figure 6 As shown, the FMA structure 604 can be as follows Figure 5B The illustrated approach is implemented as an oblivious Bloom filter having an array of leaky bit cells (BC0, BC1, ..., BCn-1), wherein each leaky bit cell has at least one capacitive element, such as at least one capacitor (C). Thus, the oblivious memory array (FMA) structure 604 may be implemented as an oblivious Bloom filter having one or more leaky bit cells as oblivious memory cells, the one or more leaky bit cells including a capacitive element (C) that is gradually discharged over a period of time. In addition, the FMA structure 604 may include one or more inputs, such as, for example, input data (D0, D1, ..., Dn-1), function data (F0, F1, ..., Fn-1), a write enable input (W), a refresh input (R), and a reset input (RST), and output data (Q0, Q1, ..., Qn-1). In some applications, the output data (Q0, Q1, ..., Qn-1) may refer to inverted output data (Q0-not, Q1-not, ..., Qn-1-not).

[0058] In some implementations, the FMA structure 604 may include a data logic gate, such as, for example, a NAND logic gate (LD0, LD1, LDn-1), which receives input data (D0, D1, ..., Dn-1), receives a write enable input (W), and then provides the inverted input data (D0-not, D1-not, ..., Dn-1-not) to the data input (D-not) of the corresponding leakage bit cell (BC0, BC1, ..., BCn-1). For example, as shown, each NAND logic gate (LD0, LD1, LDn-1) receives the corresponding input data (D0, D1, ..., Dn-1), receives the write enable input (W), and then provides the corresponding inverted input data (D0-not, D1-not, ..., Dn-1-not) to the corresponding leakage bit cell (BC0, BC1, ..., BCn-1) in the FMA structure 604.

[0059] In some implementations, the FMA structure 604 may have function logic gates, such as, for example, NAND logic gates (LF0, LF1, LFn-1), which receive function data (F0, F1, ..., Fn-1), receive a refresh input (R), and then provide inverted function data (F0-not, F1-not, ..., Fn-1-not) to the refresh input (R-not) of the corresponding leakage bit cell (BC0, BC1, ..., BCn-1). For example, as shown, each NAND logic gate (LF0, LF1, LFn-1) receives corresponding function data (F0, F1, ..., Fn-1), receives a refresh input (R), and then provides corresponding inverted function data (F0-not, F1-not, ..., Fn-1-not) to the corresponding leakage bit cell (BC0, BC1, ..., BCn-1) in the FMA structure 604.

[0060] In addition, in some specific implementations, such as Figure 6 As shown in , each corresponding leakage bit cell (BC0, BC1,…, BCn-1) receives corresponding inverted input data (D0-not, D1-not,…, Dn-1-not) at the data input (D-not), receives corresponding inverted function data (F0-not, F1-not,…, Fn-1-not) at the refresh input (R-not), receives a reset input (RST), and then provides corresponding inverted output data (Q0-not, Q1-not,…, Qn-1-not) as output from the FMA structure 604.

[0061] Figure 7 Diagram 700 is illustrated of a forgetful Bloom filter core 704 with flushing according to various implementations described herein.

[0062] In various specific implementations, the oblivious Bloom filter core 704 can be used to make memory circuits having various integrated circuit (IC) components that can be arranged and / or coupled together as an assembly or some combination of parts that provide a physical circuit design, structure, and / or application. In various cases, methods of designing, providing, and making the oblivious Bloom filter core 704 as an integrated device can involve using the various circuit components and / or related structures described herein to implement various technologies associated therewith. In addition, the oblivious Bloom filter core 704 can be integrated with various circuits and / or related components on a single chip, and the oblivious Bloom filter core 704 can be implemented in various embedded devices for automotive, mobile phone, computer, server, and / or IoT-based applications (including, for example, remote sensor nodes).

[0063] like Figure 7 As shown, the oblivious Bloom filter core 704 may be as follows Figure 5B The method shown is used Figure 6 The oblivious Bloom filter core 704 may be implemented as an oblivious Bloom filter having an array of leaky bit cells (BC0, BC1, ..., BCn-1) as an array of oblivious memory cells, wherein each leaky bit cell has at least one capacitive element, such as at least one capacitor (C). Therefore, the oblivious Bloom filter core 704 may be implemented as an oblivious Bloom filter having an array of leaky bit cells as an array of oblivious memory cells, the array of leaky bit cells including a capacitive element (C) that is gradually discharged over a period of time. In addition, the oblivious Bloom filter core 704 may include one or more inputs, such as, for example, input data (D: D0, D1, ..., Dn-1), function data (F: F0, F1, ..., Fn-1), a write enable input (W), a reset input (RST), and a refresh input (R), and output data (Q-not: Q0-not, Q1-not, ..., Qn-1-not).

[0064] In some implementations, the oblivious Bloom filter core 704 may include multi-input logic gates, such as, for example, an AND gate (LX), an XOR gate (LY), and an OR gate (LZ). For example, the AND gate (LX) may receive output data (Q-not: Q0-not, Q1-not, ..., Qn-1-not) at an inverting input, receive a query input (Qu) at a non-inverting input, and provide an output to the XOR gate (LY). Additionally, the XOR gate (LY) may receive an output from the AND gate (LX), receive a query input (Qu), and provide an output to the OR gate (LZ). Additionally, the OR gate (LZ) may receive an output from the XOR gate (LY) and provide a matching output (M-not) as an output from the oblivious Bloom filter core 704. In some applications, the logic gates (LX, LY, LZ) refer to a query circuit that identifies a match between query data (input Qu) and output data (Q-not: Q0-not, Q1-not,…, Qn-1-not) provided by a read element or read circuit stage of the forgetful Bloom filter core 704.

[0065] In some applications, upon receiving a query input (Qu), the query circuit (LX, LY, LZ) may invert a data bit of the output data (Q-not) and then mask the inverted data bit of the output data (Q-not) to isolate the inverted data bit of the output data (Q-not) having a high logic state. After isolating the inverted data bit, the query circuit (LX, Ly, LZ) may XOR the masked inverted data bit with the data bit of the query input (Qu) (e.g., through LY) to generate the queried output data. If there is a match between the data bit of the stored input data and the data bit of the queried output data, the query circuit (LX, LY, LZ) may assert a match signal (M-not). Otherwise, if there is a mismatch between the data bit of the stored input data and the data bit of the queried output data, the query circuit (LX, LY, LZ) may be configured to assert a mismatch signal with the M signal.

[0066] Additionally, in some applications, the match output signal (M-not) may be provided to the refresh input (R) of the FMA structure 704 via an inverter (inv). For example, the match output signal (M-not) is provided to the input of the inverter (inv), which then provides the refresh signal (R) as a feedback signal to the refresh input (R) of the FMA structure 704.

[0067] Figure 8 A diagram illustrating a method 800 for using a bitcell structure in various configurations according to various implementations described herein.

[0068] It should be understood that even though method 800 indicates a particular order in which operations are to be performed, in some cases, specific portions of the operations may be performed in a different order and on a different system. In other cases, additional operations and / or steps may be added to and / or omitted from method 800. In addition, method 800 may be implemented in hardware and / or software. If implemented in hardware, method 800 may be implemented using various components and / or circuits, such as those described in detail in the accompanying drawings. Figures 1A to 7 As described. In addition, if implemented in software, the method 800 may be implemented with a program and / or software instruction process configured to provide oblivious Bloom filter schemes, techniques, and applications, as described herein. In addition, if implemented in software, instructions related to implementing the method 800 may be stored in a memory (such as a database). In addition, in various cases, a computer or other type of computing device with a processor and a memory may be configured to perform the method 800.

[0069] In various specific implementations, method 800 may refer to a method for designing, providing, making, and / or manufacturing oblivious Bloom filter schemes and techniques as an integrated system, device, and / or circuit that involves using circuit components and related structures as described herein to implement various schemes and techniques associated therewith. In addition, various oblivious Bloom filter schemes and techniques may be integrated with computing circuits and related components on a single chip, and oblivious Bloom filter schemes and techniques may be implemented in embedded systems for various electronic devices, mobile phones, and IoT applications (including remote sensor nodes).

[0070] At block 810, method 800 may provide data for storage via a first circuit (such as, for example, a write element or write circuit stage), such as Figure 1B and Figure 5B Thus, in some applications, the first circuit may include a write circuit, and the data may be provided to a second circuit (such as, for example, a memory circuit) for storage by the write circuit. At block 820, the method 800 may store the data in a second circuit having a leaky bit cell, the leaky bit cell having a capacitive element (such as, for example, a memory element or a memory circuit stage) that is gradually discharged over a period of time, such as Figure 1B and Figure 5BAs shown. Therefore, in some applications, the second circuit may include a memory circuit, and data may be stored in the memory circuit having a leaky bit cell, the leaky bit cell including a capacitive element (e.g., a capacitor) that gradually discharges during the time period. In addition, each capacitive element may be referenced to a supply voltage (VDD) or ground (VSS or GND) so that each capacitive element leaks (or decays or discharges) slowly, so that each leaky bit cell is configured to forget the data storage value of each leaky bit cell during the time period.

[0071] At block 830, method 800 may enable the leakage bit cell to operate as one or more memory storage elements via a third circuit (such as, for example, a read element or read circuit stage), such as Figure 1B and Figure 5B Thus, in some applications, the third circuit may include a non-destructive read circuit that enables each leaky bit cell to operate as a non-destructive memory storage element without undergoing a destructive read operation that causes a refresh operation. Additionally, at block 840, method 800 may use a query circuit to identify a match between the query data and output data provided by a third circuit (such as, for example, a read element or a read circuit stage), such as Figure 3 to Figure 4 and Figure 7 In addition, in various applications, the method may be performed by an oblivious Bloom filter having one or more leaky bit cells as oblivious memory cells, the one or more leaky bit cells comprising a capacitive element that is gradually discharged within the time period.

[0072] Fig. 9 A simplified diagram 900 is illustrated of a matching output architecture 904 according to various implementations described herein.

[0073] In various implementations, the matching output architecture 904 may be used to fabricate an oblivious memory circuit having various integrated circuit (IC) components that may be arranged and / or coupled together as an assembly or some combination of parts that provide physical circuit design, structure, and application. In various cases, methods of designing, providing, and fabricating the matching output architecture 904 as an integrated device may involve using the various circuit components and / or related structures described herein to implement various techniques associated therewith. Additionally, the matching output architecture 904 may be integrated with circuits and / or related components on a single chip, and the matching output architecture 904 may be implemented in various embedded devices for use and application in automotive, mobile phone, computer, server, and / or IoT-based applications (including, for example, remote sensor nodes).

[0074] like Fig. 9As shown, the matching output architecture 904 can be implemented as a forgetful memory device with a leaky bit cell having a capacitive element, such as, for example, a capacitor (C). In addition, the matching output architecture 904 can use one or more inputs, such as, for example, a write input and a query input, and in addition, the matching output architecture 904 can provide at least one output, such as, for example, a matching output, based on the write input and / or the query input in various operating applications.

[0075] like Fig. 9 As shown, the matching output architecture 904 may include multiple circuits or stages having various elements, including a write circuit 910, a memory circuit 914 having a capacitive element (e.g., a capacitor), a non-destructive read circuit 918, and a query check circuit 922, which are arranged and coupled together so as to thereby operate as an oblivious memory device having a leaky bit cell having a capacitive element.

[0076] In some implementations, write circuit 910 may refer to a write element or a write circuit stage that provides write data from a write input to memory circuit 914 for storage in a capacitive element of a leaky bit cell. Additionally, in some implementations, memory circuit 914 may refer to a memory element or a memory circuit stage that stores write data received from write circuit 910 in a capacitive element (such as, for example, a capacitor) that gradually discharges over a predetermined period of time.

[0077] In some implementations, the non-destructive read circuit 918 can refer to a read element or a read circuit stage that enables a leaky bit cell to operate as a memory storage element. In some applications, the read element can refer to a non-destructive read element having a leaky bit cell. Additionally, in some cases, the read circuit 918 can include a Schmitt trigger circuit. Thus, the read circuit 918 can be implemented as a non-destructive read circuit so as to enable the leaky bit cell to operate as a non-destructive memory storage element without performing a destructive read operation that can cause a refresh operation. However, in some other applications, the read element can be as described herein below with reference to Fig.11 The bit cell structure 1104 in the embodiment of the present invention is implemented as a destructive read element. Therefore, in various applications, the read circuit 918 can be referred to as a non-destructive read circuit or a destructive read circuit.

[0078] In some implementations, the query circuit 922 may refer to a query element or query circuit stage that identifies a match between query data from a query input and output data provided by the non-destructive read circuit 918. Additionally, the query circuit 922 may receive a query input and subsequently identify a match between the query data in the query input and the output data of the matching output provided by the non-destructive read circuit 918. Additionally, in some cases, upon receiving the query input, the query circuit 922 may identify one or more matches between data bits of the stored input data and data bits of the output data having a high logic state. Additionally, in response to identifying a match, one or more bits representing the output data identified by the match are written back to the leaking bit cell, which may be implemented as a refresh operation.

[0079] In some implementations, upon receiving a query input, the query circuit 922 may be configured to invert data bits of the output data and then mask the inverted data bits of the output data so as to isolate the inverted data bits of the output data having a high logic state. Additionally, after isolating the inverted data bits, the query circuit 922 may perform a logic operation (e.g., an XOR operation) on the masked inverted data bits and the data bits of the query input to produce the queried output data (such as, for example, in the form of a matched output). In some applications, if there is a match between the data bits of the stored input data and the data bits of the queried output data, the query circuit 922 asserts a match signal. Otherwise, in other applications, if there is a mismatch between the data bits of the stored input data and the data bits of the queried output data, the query circuit 922 may be configured to assert a mismatch signal.

[0080] FIG. 10A to FIG. 10C Various diagrams associated with a bitcell structure in a third configuration are illustrated according to various implementations as described herein.

[0081] Specifically, Fig. 10A 1000A shows a bit cell structure 1004A in a third configuration, Fig. 10B A transistor-level diagram 1000B is shown of a bit cell structure 1004B in a third configuration, and Fig. 10C Operational waveform diagram 1000C of a bitcell structure 1004C in a third configuration is shown.

[0082] In various implementations, the bitcell architecture may be used to fabricate memory circuits having various integrated circuit (IC) components that may be arranged and / or coupled together as an assembly or some combination of parts that provide a physical circuit design, structure, and / or application. In various cases, methods of designing, providing, and fabricating the bitcell architecture as an integrated device may involve using the various circuit components and / or related structures described herein to implement various techniques associated therewith. Additionally, the bitcell architecture may be integrated with various circuits and / or related components on a single chip, and additionally, the bitcell architecture may be implemented in various embedded devices for automotive, mobile phone, computer, server, and / or Internet of Things (IoT) based applications, including various circuits associated therewith, such as, for example, remote sensor nodes.

[0083] like Fig. 10A As shown, the bit cell architecture 1004A can be implemented as a forgetful memory device having a leaky bit cell (BC) having at least one capacitive element, such as, for example, a capacitor (C). In addition, the bit cell architecture 1004A can have one or more inputs, such as, for example, input data (D) and reset (RST), and outputs, such as, for example, output data (Q). In some cases, reset (RST) can refer to an inverted reset (RST-not).

[0084] like Fig. 10B As shown, the bit cell architecture 1004B may include a plurality of stages, including a first stage (Stage_1), a second stage (Stage_2), and a third stage (Stage_3), which are arranged and coupled together in a third configuration to thereby function as a forgetful memory device with a leaky bit cell (BC) (e.g., as shown in FIG. Fig. 10A ), the leakage bit cell having at least one capacitive element, such as, for example, a capacitor (C).

[0085] In some implementations, the first stage (Stage_1) may refer to a write element or write circuit stage of a leaky bit cell, wherein the write circuit stage (Stage_1) provides data for storage in the second stage (Stage_2). Additionally, in some applications, the first stage (Stage_1) may include one or more transistors, such as, for example, transistors (T1, T2) coupled together in series between a supply voltage (VDD) and a ground (VSS or GND). As shown, transistor (T1) is coupled between the supply voltage (VDD) and a node (n1), and transistor (T2) is coupled between the node (n1) and the ground (VSS or GND). Additionally, an input reset (RST-not) is coupled to the gate of transistor (T1), and input data (D) is coupled to the gate of transistor (T2). Additionally, transistor (T1) may be a P-type transistor, and transistor (T2) may be an N-type transistor; however, other configurations may be used.

[0086] In some specific implementations, the second stage (Stage_2) may refer to a memory element or memory circuit stage of a leakage bit cell, wherein the memory circuit stage (Stage_2) stores data received from the first stage (Stage_1) in at least one capacitive element (such as, for example, a capacitor (C)), which gradually discharges over a predetermined time period. In addition, in various applications, the capacitor (C) may have a decay time, which is determined by the size of the capacitor (C), the self-leakage current of the capacitor (C), and / or the leakage current of the connected transistor (such as, for example, one or more of the transistors (T1, T2, T5)). Therefore, the leakage bit cell may be referred to as a capacitive bit cell, which has a capacitive element (such as, for example, a capacitor (C)) that gradually discharges over the time period by slowly leaking the stored charge over the time period. In addition, the capacitor (C) may be coupled between a supply voltage (VDD) and a node (n1) or a node (Vc), wherein the node (Vc) refers to the voltage potential of the capacitor (C) at the node (n1).

[0087] In some cases, the capacitive element or capacitor (C) may be referenced to a supply voltage (VDD) so that the capacitive element or capacitor (C) slowly leaks the supply voltage (VDD) such that the leaking bit cell is configured to forget the data storage value of the leaking bit cell during the period of time. In other cases, such as Figure 1B and Figure 5BAs shown, the capacitive element or capacitor (C) may be referenced to ground (VSS or GND) so that the capacitive element or capacitor (C) slowly leaks to ground (VSS or GND) so that the leakage bit cell is configured to forget the data storage value of the leakage bit cell during the period of time. Therefore, in various cases, the leakage bit cell may be provided with a capacitive storage element that is supply voltage (VDD) referenced (corresponding to the positive voltage supply (VDD)) or may be ground (VSS or GND) referenced.

[0088] In some implementations, the third stage (Stage_3) can refer to a read element or read circuit stage of the leakage bit cell, wherein the read circuit stage (Stage_3) enables the leakage bit cell to operate as one or more memory storage elements. In some cases, the read element can refer to a non-destructive read element of the leakage bit cell, wherein the non-destructive read circuit enables the leakage bit cell to operate as a non-destructive memory storage element without performing a destructive read operation that causes a refresh operation. In addition, in some other cases, the read element can refer to a read element as described in reference to Fig.11 The destructive read element described in the bit cell structure 1104 in FIG.

[0089] Additionally, in some applications, the third stage (Stage_3) may include one or more transistors, such as, for example, a transistor (T5) coupled between the output node (Q-not) and ground (VSS or GND). As shown, the output of transistor (T1) is coupled to the gate of transistor (T5) at node (n1), and additionally, the input of transistor (T5) is coupled to the output node (Q-not). In some cases, transistor (T5) may be an N-type transistor; however, in other cases, other configurations may be used to achieve similar results.

[0090] like Fig. 10C As shown, the operation waveform diagram 1000C of the bit cell structure 1004A, 1004B in the third configuration shows the input data signal (D), the Vc signal at the node (n1), the output data signal (Q) and the reset signal (RST-not). As shown, in the time period (t0 to t1), during the period when the reset signal (RST-not) is activated high, the input data signal (D) is low, the Vc signal at the node (n1) is low, and the output data signal (Q) is high.

[0091] In addition, in the time period (t1 to t2), when the reset signal (RST-not) switches from low to high, the input data signal (D) remains low, the Vc signal inverts from low to high, and the output signal (Q) inverts from high to low.

[0092] In addition, in the time period (t2 to t3), when the reset signal (RST-not) is set to high, the input data signal (D) triggers the Vc signal at the node (n1) from high to low, and the output signal (Q) is inverted to high, wherein the Vc signal is slowly charged to high until time (t4). Therefore, when the input data signal (D) switches to high, the Vc signal is triggered to low, then slowly charged to high, and the output signal (Q) is high during time (t2 to t3). In addition, in the time period (t3 to t4), the data signal (D) remains low, and the Vc signal continues to be charged to high until time (t4), and the output signal (Q) is inverted from high to low, while the reset signal (RST-not) remains high.

[0093] In addition, in the time period (t4 to t5), the input data signal (D) triggers the Vc signal at the node (n1) to be low, and the output signal (Q) is inverted from low to high at time (t4), while the reset signal (RST-NOT) remains high, wherein the Vc signal is slowly charged to time (t5). In addition, in the time period (t5 to t6), the input data signal (D) remains low, while the Vc signal at the node (n1) continues to be charged to time (t6), and the output signal (Q) remains high during the period when the Vc signal is charged to time (t6).

[0094] In addition, in the time period (t6 to t7), the input data signal (D) triggers the Vc signal at the node (n1) to be low, and the output signal (Q) remains high until time (t7), while the reset signal (RST-not) remains high, wherein the Vc signal is slowly charged until time (t8). In addition, in the time period (t7 to t8), the input data signal (D) remains low, while the Vc signal at the node (n1) continues to be charged until time (t8), and the output signal (Q) is inverted from high to low at time (t7) while the Vc signal is charged until time (t8).

[0095] Fig.11 Diagram 1100 illustrating a destructive read bitcell structure 1104 according to various implementations described herein.

[0096] In some implementations, the bitcell structure 1104 may be used to fabricate a memory circuit having various integrated circuit (IC) components that are arranged and / or coupled together as an assembly or some combination of parts that provide a physical circuit design, structure, and / or application. In some cases, methods of designing, providing, and fabricating the bitcell structure 1104 as an integrated device may involve using the various circuit components and / or related structures described herein to implement various techniques associated therewith. Additionally, the bitcell structure 1104 may be integrated with various circuits and / or related components on a single chip, and additionally, the bitcell structure 1104 may be implemented in various embedded devices for automotive, mobile phone, computer, server, and / or Internet of Things (IoT) based applications (including various circuits associated therewith, such as, for example, remote sensor nodes).

[0097] like Fig.11 As shown, the bit cell structure 1104 can be implemented as a destructive read bit cell structure having, for example, at least one capacitive element, such as, for example, a capacitor (C). In addition, the bit cell structure 1104 can include one or more inputs, such as, for example, input data (D), write enable (W), and refresh (R), and at least one output, such as, for example, output data (Q). In addition, the bit cell structure 1104 can include transistors (T6, T7), wherein the transistor (T6) is coupled between the input data (D) and an input of a buffer (B1) at a node (nB), the input of the buffer being coupled between the transistor (T6) and the output (Q). In addition, the transistor (T7) can be coupled in series with the capacitor (C) between the node (nB) and ground (VSS or GND). In addition, the write enable (W) can be coupled to the gate of the transistor (T6). Additionally, the bit cell structure 1104 may include a logic gate (LWR), such as, for example, an OR gate, that receives a write enable (W), receives a refresh signal (R), and then provides an output signal to the gate of the transistor (T7).

[0098] Reference has been made in detail to various specific implementations, examples of which are shown in the accompanying drawings and diagrams. In the following specific description, many specific details are set forth to provide a thorough understanding of the disclosure provided herein. However, the disclosure provided herein may be practiced without these specific details. In some other cases, well-known methods, procedures, components, circuits, and networks are not described in detail so as not to unnecessarily obscure the details of the embodiments.

[0099] Various implementations of a device having a write circuit that provides data for storage are described herein. The device may include a memory circuit that stores the data in a leaky bit cell having a capacitive element that gradually discharges over a predetermined period of time. The device may include a read circuit that enables the leaky bit cell to operate as one or more memory storage elements. The device may include a query circuit that identifies a match between query data and output data provided by the read circuit.

[0100] Various implementations of a method are described herein. The method may provide data for storage via a first circuit. The method may store the data in a second circuit having a leaky bit cell having a capacitive element that gradually discharges over a period of time. The method may enable the leaky bit cell to operate as one or more memory storage elements via a third circuit. The method may use a query circuit to identify a match between the query data and output data provided by the third circuit.

[0101] Various implementations of a device having a memory circuit are described herein that stores input data in a leaky bit cell having a capacitive element that gradually discharges over a period of time. The device may include a read circuit that enables the leaky bit cell to operate as one or more memory storage elements. Additionally, the device may further include a query circuit that identifies a match between the query data and the output data provided by the read circuit.

[0102] It should also be understood that although the terms "first", "second", etc. may be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. The first element and the second element are both elements, but they are not considered to be the same element.

[0103] The terms used in the description of the present disclosure provided herein are for the purpose of describing a specific implementation, and are not intended to limit the disclosure provided herein. As used in the disclosure provided herein and the description of the appended claims, the singular forms "one", "a kind of" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. As used herein, the term "and / or" refers to and encompasses any and all possible combinations of one or more of the associated listed items. In addition, when used in this specification, the terms "include", "comprise" and / or "contain" can specify the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other various features, integers, steps, operations, elements, parts and / or their groups.

[0104] As used herein, the term "if" may be interpreted to mean "when" or "at" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined that..." or "if [the condition or event] is detected" may be interpreted to mean "upon determining..." or "in response to determining..." or "upon detecting [the condition or event]," or "in response to detecting [the condition or event]," depending on the context. The terms "up" and "down"; "upper" and "lower"; "upwardly" and "downwardly"; "below" and "above"; and other similar terms indicating relative positions above or below a given point or element may be used in conjunction with some specific implementations of the various techniques described herein.

[0105] While the foregoing is directed to various specific implementations of the related art described herein, other and additional specific implementations are contemplated based on the disclosure herein, which may be determined by the appended claims.

[0106] Although the subject matter is described herein in language specific to structural features and / or methodological acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as exemplary forms of implementing the claims.

Claims

1. A device, comprising: a write circuit that provides data for storage; a memory circuit that stores the data in a leaky bit cell having a capacitive element that gradually discharges over a predetermined period of time; read circuitry that enables the leakage bit cell to operate as one or more memory storage elements; and A query circuit identifies a match between query data and output data provided by the read circuit. 2 . The apparatus of claim 1 , wherein the read circuit is a non-destructive read circuit or a destructive read circuit.

3. The apparatus of claim 1 , wherein each capacitive element is referenced to a supply voltage or a ground voltage so that each capacitive element leaks slowly such that each leakage bit cell is configured to forget a data storage value of said each leakage bit cell during said time period.

4. The apparatus of claim 1, wherein the read circuit is a non-destructive read circuit that enables the leakage bit cell to operate as a non-destructive memory storage element without performing a destructive read operation that causes a refresh operation.

5. The apparatus of claim 1, wherein the apparatus is an oblivious Bloom filter having one or more leaky bit cells as oblivious memory cells, the one or more leaky bit cells comprising the capacitive element that is gradually discharged over the time period.

6. A method comprising: providing data for storage via a first circuit; storing the data in a second circuit having a leaky bit cell having a capacitive element that gradually discharges over a period of time; enabling the leakage bit cell to operate as one or more memory storage elements via a third circuit; and A query circuit is used to identify a match between the query data and the output data provided by the third circuit.

7. The method of claim 6, wherein the first circuit comprises a write circuit, wherein the data is provided to a memory circuit for storage by the write circuit.

8. The method of claim 6, wherein the second circuit comprises a memory circuit, and wherein the data is stored in the memory circuit having the leakage bit cell including the capacitive element that is gradually discharged within the time period.

9. The method of claim 6, wherein each capacitive element is referenced to a supply voltage or ground so that each capacitive element leaks slowly such that each leakage bit cell is configured to forget the data storage value of each leakage bit cell during the time period.

10. The method of claim 6, wherein the third circuit comprises a non-destructive read circuit that enables each leakage bit cell to operate as a non-destructive memory storage element without performing a destructive read operation that causes a refresh operation.

11. The method of claim 6, wherein the method is performed by an oblivious Bloom filter having one or more leaky bit cells as oblivious memory cells, the one or more leaky bit cells comprising the capacitive element that is gradually discharged within the time period.

12. A device, comprising: a memory circuit that stores input data in a leaky bit cell having a capacitive element that gradually discharges over a period of time; read circuitry that enables the leakage bit cell to operate as one or more memory storage elements; and A query circuit identifies a match between query data and output data provided by the read circuit.

13. The device according to claim 12, further comprising: A write circuit provides data to the memory circuit for storage.

14. The apparatus of claim 12, wherein the read circuit is a non-destructive read circuit or a destructive read circuit.

15. The device according to claim 12, further comprising: One or more hash functions configured to write or query data bits in the leaky bit cells.

16. The apparatus of claim 12, wherein the read circuit is a non-destructive read circuit that enables each leakage bit cell to operate as a non-destructive memory storage element without performing a destructive read operation that causes a refresh operation.

17. The apparatus of claim 12, wherein the read circuit comprises a Schmitt trigger circuit.

18. The apparatus of claim 12, wherein: The query circuit receives a query input and subsequently identifies a match between the query data and the output data provided by the read circuit, and When receiving the query input, the query circuit identifies a match between a data bit of the stored input data and a data bit of the output data having a high logic state.

19. The apparatus of claim 18, wherein in response to identifying a match, one or more bits representing the output data identified by the match are written back into the leak bit cell.

20. The apparatus of claim 18, wherein: When receiving the query input, the query circuit inverts a data bit of the output data and then masks the inverted data bit of the output data so as to isolate the inverted data bit of the output data having a high logic state, After isolating the inverted data bit, the query circuit performs XOR on the masked inverted data bit and the query input data bit to generate the query output data, The query circuit asserts a match signal if there is a match between the data bits of the stored input data and the data bits of the queried output data, and asserts a mismatch signal if there is a mismatch between the data bits of the stored input data and the data bits of the queried output data.

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