Memory circuit
By designing a direct data transmission mechanism between memory cells in memory circuits, the problems of long data transmission time and large number of pins in traditional memory circuits are solved, and more efficient data transmission and lower cost are achieved.
Patent Information
- Application Number
- CN202410208480.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-10-31
- Filing Date
- 2024-02-26
- Publication Date
- 2025-05-02
AI Technical Summary
In traditional memory circuits, data transmission between memory cells needs to be transferred through the controller, resulting in a long transmission time, and multiple pins need to be added for each additional memory cell, which increases the cost.
A memory circuit is designed in which data can be directly transmitted between memory units. By reconfiguring the connection method between the control pin and the memory unit, the step of data needing to be stored first in the controller's temporary storage and then transmitted is avoided.
Direct data transmission between memory cells is realized, which shortens transmission time, reduces the number of required pins, and reduces the cost of the system.
Smart Images
Figure CN119920286A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of memory, and in particular to a memory circuit, and in particular to a memory circuit in which data can be directly transmitted between memories. Background Art
[0002] Figure 1 shows a conventional memory circuit. Figure 1 A controller 10 and a memory circuit 20 are shown. The memory circuit 20 includes six control pins 21-26 and two memory cells 27 and 28, wherein the control pins 21-23 are respectively connected to the control terminal 271, the input terminal 272 and the output terminal 273 of the memory cell 27, and the control pins 24-26 are respectively connected to the control terminal 281, the input terminal 282 and the output terminal 283 of the memory cell 28. The controller 10 includes six control pins 11-16 respectively connected to the control pins 21-26. The controller 10 sends control signals C1 and C2 through the control pins 11 and 14 to enable the memory cells 27 and 28. The controller 10 sends read commands R1 and R2 through the control pins 12 and 15 to enable the memory cells 27 and 28 to send data. The controller 10 can also send write commands W1 and W2 through the control pins 12 and 15 to enable the memory cells 27 and 28 to store data. The control pin 13 of the controller 10 can send data to the control pin 23 of the memory circuit 20, or receive data from the control pin 23 of the memory circuit 20. The control pin 16 of the controller 10 can send data to the control pin 26 of the memory circuit 20, or receive data from the control pin 26 of the memory circuit 20.
[0003] When the data D1 of the memory cell 27 is to be written into the memory cell 28, the controller 10 sends a control signal C1 through the control pin 11 to enable the memory cell 27, and sends a read command R1 to the memory cell 27 through the control pin 12, so that the memory cell 27 outputs the data D1 to the controller 10 through the control pin 23. The controller 10 stores the data D1 from the memory cell 27 in a register (not shown) inside the controller 10. After storing the data D1, the controller 10 sends a control signal C2 through the control pin 14 to enable the memory cell 28, and sends a write command W1 and the data D1 to the memory cell 28 through the control pins 15 and 16, respectively, so that the memory cell 28 stores the data D1. In other words, the controller 10 must first store the data D1 of the memory cell 27 in the register inside the controller 10 before transmitting it from the controller 10 to the memory cell 28.
[0004] Similarly, when the data D2 of the memory unit 28 is to be written into the memory unit 27 , the controller 10 first stores the data D2 of the memory unit 28 in a register within the controller 10 and then transmits the data D2 from the controller 10 to the memory unit 27 .
[0005] When data is to be transmitted between the memory cells 27 and 28 in the conventional memory circuit 20, the data must be transmitted through the controller 10, which results in a longer time required to complete the data transmission between the memory cells 27 and 28. Figure 1 As shown, for each memory unit, the controller 10 and the memory circuit 20 need to configure three pins to achieve read and write operations. Therefore, for each additional memory unit, the controller 10 and the memory circuit 20 need to add three pins, resulting in increased costs. Figure 2 As shown, when a memory unit 32 is added to the memory circuit 20, the memory circuit 20 needs to add three control pins 29-31 respectively connected to the control end 321, input end 322 and output end 323 of the memory unit 32, and the controller 10 also needs to add three control pins 17-19 respectively connected to the control pins 29-31 of the memory circuit 20. Summary of the invention
[0006] The object of the present invention is to provide a memory circuit in which data can be directly transmitted between memories.
[0007] According to the present invention, a memory circuit includes a first control pin, a second control pin, a first memory unit and a second memory unit. The first control pin and the second control pin are used to connect a controller. The first memory unit has a first input terminal and a first output terminal, wherein the first input terminal is connected to the first control pin, and the first output terminal is connected to the second control pin. The second memory unit has a second input terminal and a second output terminal, wherein the second input terminal is connected to the second control pin and the first output terminal, and the second output terminal is connected to the first control pin and the first input terminal.
[0008] In one embodiment, when the first data of the first memory unit is to be written into the second memory unit, the controller will send a read instruction and a write instruction to the first control pin and the second control pin respectively, and the first memory unit will send the first data from the first output end to the second input end according to the read instruction, and the second memory unit will store the first data on the second input end according to the write instruction.
[0009] In one embodiment, when the second data of the second memory unit is to be written into the first memory unit, the controller sends a read instruction and a write instruction to the second control pin and the first control pin respectively, and the second memory unit sends the second data from the second output end to the first input end according to the read instruction, and the first memory unit stores the second data on the first input end according to the write instruction.
[0010] In one embodiment, the memory circuit further includes a third control pin and a third memory unit. The third control pin is used to connect to the controller. The third memory unit has a third input terminal and a third output terminal, wherein the third input terminal is connected to the third control pin, a fourth output terminal of the first memory unit and a fifth output terminal of the second memory unit, and the third output terminal is connected to the first control pin, the first input terminal and the second output terminal.
[0011] In one embodiment, when the second data of the second memory unit is to be written into the third memory unit, the controller first sends a read instruction and a write instruction to the second control pin and the first control pin respectively, and the second memory unit sends the second data from the second output end to the first input end according to the read instruction, and the first memory unit stores the second data on the first input end according to the write instruction; after the second data is stored in the first memory unit, the controller then sends the read instruction and the write instruction to the first control pin and the third control pin respectively, and the first memory unit sends the second data from the fourth output end to the third input end according to the read instruction, and the third memory unit stores the second data on the third input end according to the write instruction.
[0012] The memory units of the memory circuit of the present invention can directly transmit data to each other, so as to shorten the data transmission time. In addition, the memory circuit of the present invention requires fewer pins, so as to reduce the cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.
[0014] Figure 1 A conventional memory circuit having two memory cells is shown.
[0015] Figure 2 A conventional memory circuit with three memory cells is shown.
[0016] Figure 3 A first embodiment of the memory circuit of the present invention is shown.
[0017] Figure 4 A second embodiment of the memory circuit of the present invention is shown.
[0018] Explanation of symbols:
[0019] 10: controller, 11: control pin, 12: control pin, 13: control pin, 14: control pin, 15: control pin, 16: control pin, 17: control pin, 18: control pin, 19: control pin, 20: memory circuit, 21: control pin, 22: control pin, 23: control pin, 24: control pin, 25: control pin, 26: control pin, 27: memory unit, 271: control end, 272: input end, 273: output end, 28: memory unit, 281: control end, 282: input end, 283: output end, 29: control pin, 30: control pin, 31: control pin, 32: memory unit, 321: control end, 322: input end, 323: output end;
[0020] 40: controller, 41: control pin, 42: control pin, 43: control pin, 50: memory circuit, 51: control pin, 52: control pin, 53: control pin, 54: memory unit, 541: control end, 542: input end, 543: output end, 55: memory unit, 551: control end, 552: input end, 553: output end;
[0021] 60: controller, 61: control pin, 62: control pin, 63: control pin, 64: control pin, 70: memory circuit, 71: control pin, 72: control pin, 73: control pin, 74: control pin, 75: memory unit, 751: control end, 752: input end, 753: output end, 754: output end, 76: memory unit, 761: control end, 762: input end, 763: output end, 764: output end, 77: memory unit, 771: control end, 772: input end, 773: output end. DETAILED DESCRIPTION
[0022] Figure 3 A first embodiment of the memory circuit of the present invention is shown. Figure 3A controller 40 and a memory circuit 50 are shown. The memory circuit 50 includes three control pins 51-53 and two memory cells 54 and 55, wherein the control pin 51 is connected to the control terminals 541 and 551 of the memory cells 54 and 55, the control pin 52 is connected to the input terminal 542 of the memory cell 54 and the output terminal 553 of the memory cell 55, and the control pin 53 is connected to the output terminal 543 of the memory cell 54 and the input terminal 552 of the memory cell 55. The controller 40 includes three control pins 41-43 connected to the control pins 51-53 of the memory circuit 50 respectively. The controller 40 sends a control signal C through the control pin 41 to enable the memory cells 54 and 55. The controller 40 sends a read command R and a write command W through the control pins 42 and 43 to enable the memory cells 54 and 55 to send or write data.
[0023] When the first data D1 of the memory unit 54 is to be written into the memory unit 55, the controller 40 sends a control signal C via the control pin 41 to enable the memory units 54 and 55, and sends a read command R and a write command W to the control pins 52 and 53 of the memory circuit 50 via the control pins 42 and 43, respectively. When the input terminal 542 of the memory unit 54 receives the read command R from the control pin 52, the memory unit 54 sends the first data D1 from the output terminal 543 to the input terminal 552 of the memory unit 55 according to the read command R. When the input terminal 552 of the memory unit 55 receives the write command W from the control pin 53, the memory unit 55 stores the first data D1 provided to the input terminal 552 by the memory unit 54 according to the write command W.
[0024] When the second data D2 of the memory unit 55 is to be written into the memory unit 54, the controller 40 sends a control signal C via the control pin 41 to enable the memory units 54 and 55, and sends a write command W and a read command R to the control pins 52 and 53 of the memory circuit 50 via the control pins 42 and 43, respectively. When the input terminal 552 of the memory unit 55 receives the read command R from the control pin 53, the memory unit 55 sends the second data D2 from the output terminal 553 to the input terminal 542 of the memory unit 54 according to the read command R. When the input terminal 542 of the memory unit 54 receives the write command W from the control pin 52, the memory unit 54 stores the second data D2 provided to the input terminal 542 by the memory unit 55 according to the write command W.
[0025] The memory units 54 and 55 of the memory circuit 50 of the present invention can directly transmit data without first storing it in the register of the controller 40, so the data transmission time is shorter. Figure 1 Compared with the memory circuit 20 of the present invention, the memory circuit 50 of the present invention can reduce the number of pins and thus has a lower cost.
[0026] Figure 4 A second embodiment of the memory circuit of the present invention is shown. Figure 4 A controller 60 and a memory circuit 70 are shown. The memory circuit 70 includes four control pins 71-74 and three memory units 75-77, wherein the control pin 71 is connected to the control terminals 751, 761 and 771 of the three memory units 75, 76 and 77, the control pin 72 is connected to the input terminal 752 of the memory unit 75, the output terminal 763 of the memory unit 76 and the output terminal 773 of the memory unit 77, the control pin 73 is connected to the output terminal 753 of the memory unit 75 and the input terminal 762 of the memory unit 76, and the control pin 74 is connected to the output terminal 754 of the memory unit 75, the output terminal 764 of the memory unit 76 and the input terminal 772 of the memory unit 77. The controller 60 includes four control pins 61-64 respectively connected to the control pins 71-74 of the memory circuit 70. The controller 60 sends a control signal C through the control pin 61 to enable the memory units 75-77. The controller 60 sends a read command R and a write command W via the control pins 72 ˜ 74 to enable the memory units 75 ˜ 77 to send out or write data.
[0027] When the first data D1 of the memory unit 75 is to be written into the memory unit 76, the controller 60 sends a control signal C via the control pin 61 to enable the memory units 75-77, and sends a read command R and a write command W to the control pins 72 and 73 of the memory circuit 70 via the control pins 62 and 63, respectively. When the input terminal 752 of the memory unit 75 receives the read command R from the control pin 72, the memory unit 75 sends the first data D1 from the output terminal 753 to the input terminal 762 of the memory unit 76 according to the read command R. When the input terminal 762 of the memory unit 76 receives the write command W from the control pin 73, the memory unit 76 stores the first data D1 provided to the input terminal 762 by the memory unit 75 according to the write command W.
[0028] When the first data D1 of the memory unit 75 is to be written into the memory unit 77, the controller 60 sends a control signal C via the control pin 61 to enable the memory units 75-77, and sends a read command R and a write command W to the control pins 72 and 74 of the memory circuit 70 via the control pins 62 and 64, respectively. When the input terminal 752 of the memory unit 75 receives the read command R from the control pin 72, the memory unit 75 sends the first data D1 from the output terminal 754 to the input terminal 772 of the memory unit 77 according to the read command R. When the input terminal 772 of the memory unit 77 receives the write command W from the control pin 74, the memory unit 77 stores the first data D1 provided by the memory unit 75 to the input terminal 772 according to the write command W.
[0029] When the second data D2 of the memory unit 76 is to be written into the memory unit 75, the controller 60 sends a control signal C via the control pin 61 to enable the memory units 75-77, and sends a write command W and a read command R to the control pins 72 and 73 of the memory circuit 70 via the control pins 62 and 63, respectively. When the input terminal 762 of the memory unit 76 receives the read command R from the control pin 73, the memory unit 76 sends the second data D2 from the output terminal 763 to the input terminal 752 of the memory unit 75 according to the read command R. When the input terminal 752 of the memory unit 75 receives the write command W from the control pin 72, the memory unit 75 stores the second data D2 provided by the memory unit 76 to the input terminal 752 according to the write command W.
[0030] When the second data D2 of the memory unit 76 is to be written into the memory unit 77, the controller 60 sends a control signal C via the control pin 61 to enable the memory units 75-77, and sends a read command R and a write command W to the control pins 73 and 74 of the memory circuit 70 via the control pins 63 and 64, respectively. When the input terminal 762 of the memory unit 76 receives the read command R from the control pin 73, the memory unit 76 sends the second data D2 from the output terminal 764 to the input terminal 772 of the memory unit 77 according to the read command R. When the input terminal 772 of the memory unit 77 receives the write command W from the control pin 74, the memory unit 77 stores the second data D2 provided by the memory unit 76 to the input terminal 772 according to the write command W.
[0031] The second data D2 of the memory cell 76 can also be written into the memory cell 77 in another way. When the second data D2 of the memory cell 76 is to be written into the memory cell 77, the controller 60 sends a control signal C through the control pin 61 to enable the memory cells 75-77, and then writes the second data D2 into the memory cell 77 in two stages. In the first stage, the controller 60 sends a write command W and a read command R to the control pins 72 and 73 of the memory circuit 70 through the control pins 62 and 63, respectively. When the input terminal 762 of the memory cell 76 receives the read command R from the control pin 73, the memory cell 76 sends the second data D2 from the output terminal 763 to the input terminal 752 of the memory cell 75 according to the read command R. When the input terminal 752 of the memory cell 75 receives the write command W from the control pin 72, the memory cell 75 stores the second data D2 provided to the input terminal 752 by the memory cell 76 according to the write command W. The second stage is performed after the memory cell 75 stores the second data D2. In the second stage, the controller 60 sends a read command R and a write command W to the control pins 72 and 74 of the memory circuit 70 via the control pins 62 and 64, respectively. When the input terminal 752 of the memory unit 75 receives the read command R from the control pin 72, the memory unit 75 sends the second data D2 from the output terminal 754 to the input terminal 772 of the memory unit 77 according to the read command R. When the input terminal 772 of the memory unit 77 receives the write command W from the control pin 74, the memory unit 77 stores the second data D2 provided to the input terminal 772 by the memory unit 75 according to the write command W. In the method of transmitting the second data D2 from the memory unit 76 to the memory unit 77 using two stages, the output terminal 764 of the memory unit 76 can be omitted.
[0032] When the third data D3 of the memory unit 77 is to be written into the memory unit 75, the controller 60 sends a control signal C via the control pin 61 to enable the memory units 75-77, and sends a write command W and a read command R to the control pins 72 and 74 of the memory circuit 70 via the control pins 62 and 64, respectively. When the input terminal 772 of the memory unit 77 receives the read command R from the control pin 74, the memory unit 77 sends the third data D3 from the output terminal 773 to the input terminal 752 of the memory unit 75 according to the read command R. When the input terminal 752 of the memory unit 75 receives the write command W from the control pin 72, the memory unit 75 stores the third data D3 provided by the memory unit 77 to the input terminal 752 according to the write command W.
[0033] When the third data D3 of the memory cell 77 is to be written into the memory cell 76, the controller 60 sends a control signal C via the control pin 61 to enable the memory cells 75-77, and then writes the third data D3 into the memory cell 76 through two stages. In the first stage, the controller 60 sends a write command W and a read command R to the control pins 72 and 74 of the memory circuit 70 via the control pins 62 and 64, respectively. When the input terminal 772 of the memory cell 77 receives the read command R from the control pin 74, the memory cell 77 sends the third data D3 from the output terminal 773 to the input terminal 752 of the memory cell 75 according to the read command R. When the input terminal 752 of the memory cell 75 receives the write command W from the control pin 72, the memory cell 75 stores the third data D3 provided by the memory cell 77 to the input terminal 752 according to the write command W. The second stage is performed after the memory cell 75 stores the second data D2. In the second stage, the controller 60 sends a control signal C via the control pin 61 to enable the memory units 75-77, and sends a read command R and a write command W to the control pins 72 and 73 of the memory circuit 70 via the control pins 62 and 63, respectively. When the input terminal 752 of the memory unit 75 receives the read command R from the control pin 72, the memory unit 75 sends the third data D3 from the output terminal 753 to the input terminal 762 of the memory unit 76 according to the read command R. When the input terminal 762 of the memory unit 76 receives the write command W from the control pin 73, the memory unit 76 stores the third data D3 provided by the memory unit 75 to the input terminal 762 according to the write command W.
[0034] In another embodiment, if the memory unit 77 adds an output terminal (not shown) connected to the input terminal 762 of the memory unit 76, the third data D3 of the memory unit 77 can also be directly transmitted to the memory unit 76 without passing through the memory unit 75. Specifically, the controller 60 sends a write command W and a read command R through the control pins 63 and 64, respectively. When the input terminal 772 of the memory unit 77 receives the read command R, the memory unit 77 sends the third data D3 from the newly added output terminal to the input terminal 762 of the memory unit 76 according to the read command R. When the input terminal 762 of the memory unit 76 receives the write command W, the memory unit 76 stores the third data D3 provided by the memory unit 77 to the input terminal 762 according to the write command W.
[0035] The memory units 75-77 of the memory circuit 70 of the present invention can directly transmit data without first storing it in the register of the controller 60, thereby shortening the data transmission time. Figure 2 Compared with the memory circuit 20 of the present invention, the memory circuit 70 of the present invention can reduce the number of pins and thus has a lower cost.
[0036] exist Figure 3 and Figure 4 In the embodiment of the present invention, only a memory circuit with two memory cells and a memory circuit with three memory cells are shown, but the present invention is not limited thereto. The number of memory cells in the memory circuit may be more than four. A person skilled in the art can Figure 3 and Figure 4 The teachings of the present invention can be used to infer the connection method of more than four memory cells.
[0037] The above description is only an embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as above by the embodiment, it is not used to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes or modifications to equivalent embodiments of equivalent changes by using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.
Claims
1. A memory circuit, characterized in that: The memory circuit comprises: A first control pin, used for connecting to a controller; A second control pin, used for connecting to the controller; a first memory unit having a first input terminal and a first output terminal, wherein the first input terminal is connected to the first control pin, and the first output terminal is connected to the second control pin; and A second memory unit has a second input terminal and a second output terminal, wherein the second input terminal is connected to the second control pin and the first output terminal, and the second output terminal is connected to the first control pin and the first input terminal.
2. The memory circuit according to claim 1, wherein: When the first data of the first memory unit is to be written into the second memory unit, the controller will send a read instruction and a write instruction to the first control pin and the second control pin respectively. The first memory unit sends the first data from the first output end to the second input end according to the read instruction, and the second memory unit stores the first data on the second input end according to the write instruction.
3. The memory circuit according to claim 1, wherein: When the second data of the second memory unit is to be written into the first memory unit, the controller sends a read instruction and a write instruction to the second control pin and the first control pin respectively, and the second memory unit sends the second data from the second output end to the first input end according to the read instruction, and the first memory unit stores the second data on the first input end according to the write instruction.
4. The memory circuit according to claim 1, wherein: The memory circuit further includes: a third control pin, used to connect to the controller; and A third memory unit has a third input terminal and a third output terminal, wherein the third input terminal is connected to the third control pin and a fourth output terminal of the second memory unit, and the third output terminal is connected to the first control pin, the first input terminal and the second output terminal.
5. The memory circuit according to claim 4, characterized in that When the second data of the second memory unit is to be written into the third memory unit, the controller sends a read instruction and a write instruction to the second control pin and the third control pin respectively, and the second memory unit sends the second data from the fourth output end to the third input end according to the read instruction, and the third memory unit stores the second data on the third input end according to the write instruction.
6. The memory circuit according to claim 1, wherein: The memory circuit further includes: a third control pin, used to connect to the controller; and A third memory unit has a third input terminal and a third output terminal, wherein the third input terminal is connected to the third control pin and a fourth output terminal of the first memory unit, and the third output terminal is connected to the first control pin, the first input terminal and the second output terminal.
7. The memory circuit according to claim 6, wherein: When the second data of the second memory unit is to be written into the third memory unit, the controller first sends a read instruction and a write instruction to the second control pin and the first control pin respectively, the second memory unit sends the second data from the second output end to the first input end according to the read instruction, and the first memory unit stores the second data on the first input end according to the write instruction; After the second data is stored in the first memory unit, the controller then sends the read instruction and the write instruction to the first control pin and the third control pin respectively. The first memory unit sends the second data from the fourth output end to the third input end according to the read instruction, and the third memory unit stores the second data on the third input end according to the write instruction.