Electrical distance region division method, data writing method and storage device

Abstract

The invention relates to the field of integrated circuits, and discloses an electrical distance region division method, a data writing method and a storage device. The electrical distance region division method comprises the following steps: drawing a resistance change line on a bare chip; wherein the resistance change line comprises a plurality of sampling points; different sampling points have different resistances; performing an electrical test on the bare chip, and recording test values of the plurality of sampling points; wherein the test value represents the reset condition of the storage unit in the sampling point; and dividing the bare chip into a plurality of electrical distance areas based on the test values of the plurality of sampling points.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a method for dividing electrical distance regions, a method for writing data, and a storage device. Background Art

[0002] The core of phase change memory (PCM) is the phase change material based on sulfur compounds. There are at least two clearly distinguishable solid phase structures in the phase change material that can be used to store data, usually the amorphous phase (disordered) and the crystalline phase (ordered). Among them, for phase change materials, the crystalline structure is heated to melt and cooled rapidly, that is, it undergoes a rapid annealing process to condense and obtain an amorphous state. In phase change memory, a high-intensity but short-acting electric pulse can be used on the phase change material. Under the action of Joule heat, when the temperature rises above the melting point of the phase change material, after a rapid heat release process (the cooling rate exceeds 109K / s), the phase change material directly enters the amorphous state from the molten state. This process is a write 0 (reset) operation.

[0003] However, due to the influence of peripheral circuit resistance, the energy required to write 0 to storage cells in different areas of the actual storage array is different. Far-end storage cells require a higher voltage to fully reset, but for near-end storage cells, too high a voltage will cause write disturbances and reduced reliability. Therefore, storage arrays in different areas need to correspond to different reset conditions to ensure performance. At the same time, in the actual production process, there may also be differences in peripheral circuit resistance between different wafers and different dies.

[0004] Therefore, how to reasonably divide the ED (Electrical Distance) area and distinguish the memory cells with different peripheral circuit resistance has become a problem that needs to be solved. In the related art, all dies are divided into ED areas according to a relatively fixed empirical value, which cannot achieve the best performance. Summary of the invention

[0005] In view of this, the embodiments of the present application provide a method, apparatus, storage device and storage medium for dividing electrical distance areas, which can achieve accurate division and fine adjustment of electrical distance areas, thereby ensuring that the remote storage unit can be fully reset, and improving the reliability of the proximal storage unit and reducing power consumption.

[0006] The technical solution of the embodiment of the present application is implemented as follows:

[0007] An embodiment of the present application provides a method for dividing electrical distance regions, which is applied to a phase change memory, and includes: drawing a resistance change line on a bare chip; wherein the resistance change line includes a plurality of sampling points; different sampling points have different resistances; performing an electrical test on the bare chip and recording test values ​​of the plurality of sampling points; wherein the test values ​​represent the reset status of a storage unit in the sampling points; and dividing the bare chip into a plurality of electrical distance regions based on the test values ​​of the plurality of sampling points.

[0008] In some embodiments of the present application, drawing the resistance change line on the bare die includes: determining a first slope based on line resistance in a wafer acceptability test; and drawing the resistance change line on the bare die according to the first slope.

[0009] In some embodiments of the present application, the line resistance in the wafer acceptability test includes: a bit line resistance and a word line resistance; the first slope is equal to the quotient of the bit line resistance and the word line resistance.

[0010] In some embodiments of the present application, an electrical test is performed on the bare chip, and the test values ​​of the multiple sampling points on the resistance change line are recorded, including: applying an initial test voltage to the bare chip, and recording the test values ​​of the multiple sampling points under the initial test voltage; gradually adjusting the test voltage on the bare chip, and recording the test values ​​of the multiple sampling points under each test voltage.

[0011] In some embodiments of the present application, based on the test values ​​of the plurality of sampling points, the bare chip is divided into the plurality of electrical distance regions, including: determining a region division point among the plurality of sampling points; wherein the region division point is the sampling point at which the test value reaches an inflection point after each adjustment of the test voltage; based on the region division point, drawing a region division line on the bare chip to divide the bare chip into the plurality of electrical distance regions; wherein the region division line intersects with the resistance change line at the region division point.

[0012] In some embodiments of the present application, based on the area division point, drawing the area division line on the die includes: passing through the area division point and drawing the area division line on the die according to a second slope; wherein the product of the second slope and the first slope is equal to -1.

[0013] In some embodiments of the present application, under the initial test voltage, all the sampling points on the resistance change line are fully reset.

[0014] In some embodiments of the present application, the test value includes: a reset threshold voltage of a storage unit at the sampling point.

[0015] An embodiment of the present application also provides a data writing method, which is applied to a phase change memory, comprising: the method for dividing the electrical distance area described in the above scheme; and, based on the electrical distance area where the target storage unit is located, applying a corresponding electric pulse to the target storage unit to write data 0 to the target storage unit.

[0016] An embodiment of the present application also provides a storage device, including a memory and a processor, wherein the memory stores a computer program that can be executed on the processor, and is characterized in that when the processor executes the program, the steps in the method described in the above scheme are implemented.

[0017] It can be understood that in the embodiment of the present application, by drawing the resistance change line, multiple sampling points with different peripheral circuit resistances can be determined, that is, multiple sampling points with different peripheral circuit resistances are determined; then, through electrical testing, the test value of each sampling point is recorded to determine the reset status of each sampling point; then, according to the reset status of each sampling point, multiple electrical distance areas are divided. In this way, in the process of writing data 0, corresponding electrical pulses can be applied to the storage cells in each electrical distance area based on the electrical distance area in which they are located, ensuring that each storage cell can meet the appropriate reset conditions. Thereby, accurate division and fine adjustment of the electrical distance area are achieved, which not only ensures that the remote storage unit can be fully reset, but also improves the reliability of the proximal storage unit and reduces power consumption, making the reset operation of the phase change memory more flexible and controllable. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic diagram of the structure of the phase change memory in the embodiment of the present application;

[0019] Figure 2 is a schematic diagram of the distribution of resistances at different lengths from the bit line and the word line in an embodiment of the present application;

[0020] Figure 3 This is a schematic diagram of the implementation process of the method for dividing the electrical distance area provided in the embodiment of the present application. Figure 1 ;

[0021] Figure 4 is a schematic diagram of a resistance change line in an embodiment of the present application;

[0022] Figure 5A is a schematic diagram of the distribution of word line resistance in an embodiment of the present application;

[0023] Figure 5B is a schematic diagram of the distribution of the bit line resistance in the embodiment of the present application;

[0024] Figure 6 This is a schematic diagram of the implementation process of the method for dividing the electrical distance area provided in the embodiment of the present application. Figure 2 ;

[0025] Figure 7 is a schematic diagram of the area division points in an embodiment of the present application;

[0026] Figure 8 is a schematic diagram of the electrical distance region in an embodiment of the present application;

[0027] Fig. 9 A schematic diagram of the implementation flow of the data writing method provided in the embodiment of the present application;

[0028] Fig.10 A hardware entity diagram of a storage device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0030] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0031] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0032] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0033] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0034] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising" when used in this specification determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items. The units "root", "bar" or "individual" for transmission lines all represent the same meaning.

[0035] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application.

[0036] Figure 1 is an optional structural diagram of a phase change memory in an embodiment of the present application. Figure 1 In a phase change memory, each memory cell includes a phase change material, and two ends of each memory cell are connected to a corresponding word line WL and a bit line BL, respectively. The word line WL and the bit line BL extend in different directions.

[0037] When a write 1 (set) operation is performed, the phase change material in the target storage cell changes from an amorphous state to a crystalline state, thereby writing data "1" into the target storage cell. Correspondingly, when a write 0 (reset) operation is performed, the phase change material in the target storage cell changes from a crystalline state to an amorphous state, thereby writing data "0" into the target storage cell.

[0038] It should be noted that in the memory array of the phase change memory, the peripheral circuit resistance at different positions will be different, so that the reset conditions of the memory cells at different positions are different. In actual testing, the peripheral circuit resistance at a certain position can be characterized by measuring the resistance Rs at that position. Among them, the peripheral circuit resistance is in direct proportion to the resistance Rs.

[0039] Figure 2 The resistor Rs at different locations on the die is shown as an example. Figure 2 As the length of the bit line BL and the length of the word line WL increase, the value of the resistance Rs increases accordingly, which can be expressed as resistance Rs = line resistance × wiring length. In other words, the farther the distance from the peripheral circuit, the greater the resistance Rs, that is, the greater the resistance of the peripheral circuit.

[0040] Figure 3 1 is an optional flow chart of a method for dividing electrical distance regions provided in an embodiment of the present application, and the method is applied to a phase change memory. Figure 3 As shown, the method includes steps S101 to S103, which will be described in conjunction with each step.

[0041] S101, drawing a resistance change line on a bare chip; wherein the resistance change line includes a plurality of sampling points; and different sampling points have different resistances.

[0042] In the present application examples, reference Figure 4, a resistance change line can be drawn on the die. Since the resistance change line includes multiple sampling points, and different sampling points have different resistances, the resistance change line can reflect the change of the peripheral circuit resistance at various locations on the die.

[0043] In some embodiments of the present application, the first slope k1 may be determined based on the line resistance in a wafer acceptability test (Wafer Acceptance Test, WAT); and then, a resistance variation line may be drawn on the die according to the first slope k1.

[0044] In the embodiment of the present application, the line resistance in WAT includes: a bit line resistance Rs_BL and a word line resistance Rs_WL. The bit line resistance Rs_BL is equal to the resistance of the bit line per unit length divided by the cross-sectional area of ​​the bit line; the word line resistance Rs_WL is equal to the resistance of the word line per unit length divided by the cross-sectional area of ​​the word line.

[0045] refer to Figure 5A and Figure 5B During the wafer test, WAT will output the bit line resistance Rs_BL and word line resistance Rs_WL of different wafers, dies or stacks. Figure 5A and Figure 5B In the circuit, different resistance values ​​are distinguished by different fill patterns.

[0046] Furthermore, the first slope k1 can be set according to the ratio of the bit line resistance Rs_BL to the word line resistance Rs_WL. That is, the first slope k1 can be equal to the quotient of the bit line resistance Rs_BL and the word line resistance Rs_WL, k1 = Rs_BL ÷ Rs_WL.

[0047] In some embodiments of the present application, the first slope k1 may be used as the slope of the resistance change line, so as to draw a resistance change line on the die.

[0048] In other embodiments of the present application, the storage cells included in each sampling point can be determined according to the first slope k1, that is, the shape of each sampling point can be determined according to the first slope k1. For example, in each sampling point, there are a storage cells on the length of the word line WL and b storage cells on the length of the bit line BL, then a=k1*b can be satisfied; in this way, the number of storage cells on the length of the word line WL and the number of storage cells on the length of the bit line BL can be determined, thereby determining the shape of each sampling point. Furthermore, after determining the storage cells included in each sampling point, a corresponding coordinate system can be generated, and a resistance change line with a slope of 1 can be drawn in the coordinate system, that is, the coordinates of the sampling points on the resistance change line range from (0, 0) to (n, n).

[0049] S102 , performing electrical testing on the bare chip and recording test values ​​of a plurality of sampling points; wherein the test values ​​represent reset conditions of storage units at the sampling points.

[0050] In the embodiment of the present application, after the resistance change line is drawn, the bare chip can be electrically tested to record the test value of the sampling point on the resistance change line. The test value can characterize the reset status of the storage unit at the sampling point, so whether the storage unit at the sampling point can be fully reset can be determined based on the test value.

[0051] In some embodiments of the present application, the test value includes: a reset threshold voltage of a memory cell at a sampling point, wherein the reset threshold voltage refers to the voltage required for a phase change material in a memory cell to change from a crystalline state to an amorphous state during a reset operation.

[0052] In the embodiment of the present application, since each sampling point includes a certain number of memory cells, and the reset threshold voltages of the memory cells may be different, a value is selected from the reset threshold voltages of the memory cells in the sampling point to serve as the reset threshold voltage of the sampling point. If the reset threshold voltages of the memory cells in the sampling point are described according to a normal distribution, then the value at -3.5σ in the normal distribution diagram may be used as the selected value, so that the reset threshold voltages of most of the memory cells in the sampling point are guaranteed to be greater than the selected value, and the reset threshold voltages of the memory cells in the sampling point are avoided from being distributed in the measurement of the selected value, thereby ensuring that the memory cells in the same sampling point maintain consistent test results in the electrical test.

[0053] S103 . Divide the die into a plurality of electrical distance regions based on the test values ​​of the plurality of sampling points.

[0054] In the embodiment of the present application, after obtaining the test values ​​of multiple sampling points, boundary points with special test values ​​can be selected from the multiple sampling points, and then, the region division lines are drawn according to the boundary points, thereby completing the division of multiple electrical distance regions (ED regions). Furthermore, corresponding electrical pulses can be applied to the storage cells in each electrical distance region to ensure that the storage cells in each electrical distance region can meet the appropriate reset conditions.

[0055] It can be understood that in the embodiment of the present application, by drawing the resistance change line, multiple sampling points with different peripheral circuit resistances can be determined, that is, multiple sampling points with different peripheral circuit resistances are determined; then, through electrical testing, the test value of each sampling point is recorded to determine the reset status of each sampling point; then, according to the reset status of each sampling point, multiple electrical distance areas are divided. In this way, in the process of writing data 0, corresponding electrical pulses can be applied to the storage cells in each electrical distance area based on the electrical distance area in which they are located, ensuring that each storage cell can meet the appropriate reset conditions. Thereby, accurate division and fine adjustment of the electrical distance area are achieved, which not only ensures that the remote storage unit can be fully reset, but also improves the reliability of the proximal storage unit and reduces power consumption, making the reset operation of the phase change memory more flexible and controllable.

[0056] In some embodiments of the present application, Figure 6 Steps S201 to S202 are shown to achieve Figure 3 The step S102 is shown. The description will be made in combination with each step.

[0057] S201 , applying an initial test voltage to the bare chip, and recording test values ​​of a plurality of sampling points under the initial test voltage.

[0058] In the embodiment of the present application, during the electrical test, an initial test voltage Vh may be first applied to the bare chip, and the test values ​​of multiple sampling points under the initial test voltage may be recorded. Under the initial test voltage Vh, all sampling points on the resistance change line are fully reset; that is, under the initial test voltage Vh, the farthest storage unit can also be fully reset, thus ensuring that the storage units in all regions can be fully reset, avoiding omissions and affecting the reset performance of the phase change memory.

[0059] refer to Figure 7 ,Under the initial test voltage Vh, the reset threshold voltages of each sampling point are in a straight line, indicating that each sampling point can be fully reset.

[0060] In some embodiments of the present application, the initial test voltage Vh may be set to 5V.

[0061] S202 , gradually adjusting the test voltage on the bare chip, and recording the test values ​​of multiple sampling points at each test voltage.

[0062] In the embodiment of the present application, the test voltage on the die can be gradually adjusted starting from the initial test voltage Vh, for example, starting from the initial test voltage Vh of 5V, the test voltage can be gradually reduced to 4.5V, 4.2V, etc. At the same time, the test values ​​of multiple sampling points at each test voltage are recorded.

[0063] In some embodiments of the present application, Figure 6 Steps S203 to S204 are shown to achieve Figure 3 The step S103 shown will be described in combination with each step.

[0064] S203. Determine a region division point among the plurality of sampling points; wherein the region division point is a sampling point at which the test value reaches an inflection point after each adjustment of the test voltage.

[0065] In the present application examples, reference Figure 7 When the first test voltage V1 is applied to the bare chip, the reset threshold voltage curve of each sampling point is bent, and the inflection point is the sampling point D1. Therefore, the sampling point D1 can be used as the area division point.

[0066] It should be noted that, since the first test voltage V1 is lower than the initial test voltage Vh, the remote memory cell loses a large test voltage due to the large circuit resistance, so that the test voltage obtained by the remote memory cell cannot fully reset it, and therefore, the reset threshold voltage of the sampling point farther than D1 will decrease, so that the reset threshold voltage curve of the first test voltage V1 bends and decreases at the sampling point D1. Correspondingly, the near-end memory cell can still be fully reset, so a portion of the curve of the reset threshold voltage curve of the first test voltage V1 at the sampling point closer than D1 overlaps with the reset threshold voltage curve of the initial test voltage Vh.

[0067] Continue to refer Figure 7 Similarly, when the second test voltage V2 is applied to the bare chip, the reset threshold voltage curves of each sampling point are bent, and the inflection point is the sampling point D2. Therefore, the sampling point D2 can also be used as a region division point.

[0068] It should be noted that the number of area division points is not limited to 2, and multiple area division points can be determined, and the number of area division points can be adjusted and selected as needed.

[0069] S204 , based on the area division point, draw an area division line on the bare chip to divide the bare chip into a plurality of electrical distance areas; wherein the area division line intersects with the resistance change line at the area division point.

[0070] In the present application examples, reference Figure 8After determining the area division points D1 and D2, area division lines can be drawn through the area division points D1 and D2, respectively, so as to divide the die into multiple electrical distance areas. The area division line passing through the area division point D1 divides area 1 and area 2; the area division line passing through the area division point D2 divides area 2 and area 3.

[0071] In some embodiments of the present application, reference Figure 8 , a region division line can be drawn on the die according to the second slope k2 through the region division point D1 or D2, wherein the product of the second slope k2 and the first slope k1 is equal to -1, that is, k2 = -1 / k1.

[0072] It can be understood that in the embodiment of the present application, by gradually adjusting the test voltage on the die and recording the test values ​​of multiple sampling points at each test voltage, multiple area division points can be determined; then, by passing through the area division points and drawing area division lines, the die can be divided into multiple electrical distance areas. In this way, in the process of writing data 0, corresponding electric pulses can be applied to the storage cells in each electrical distance area based on the electrical distance area in which they are located, ensuring that each storage cell can meet the appropriate reset conditions. Thereby, accurate division and fine adjustment of the electrical distance area are achieved, which not only ensures that the remote storage unit can be fully reset, but also improves the reliability of the proximal storage unit and reduces power consumption, making the reset operation of the phase change memory more flexible and controllable.

[0073] Fig. 9 The following is an optional flow chart of a data writing method provided in an embodiment of the present application, wherein the method is applied to a phase change memory. Fig. 9 As shown, the method includes steps S301 to S302, which will be described in conjunction with each step.

[0074] S301, dividing electrical distance areas.

[0075] Wherein, step S301 may be implemented according to the method for dividing the electrical distance regions shown in the above embodiment.

[0076] S302 . Apply a corresponding electric pulse to the target memory cell based on the electrical distance region where the target memory cell is located, so as to write data 0 into the target memory cell.

[0077] In the embodiment of the present application, after the division of the electrical distance area is completed, if it is necessary to write data 0 to the target storage unit, a corresponding electric pulse can be applied to the target storage unit based on the electrical distance area where the target storage unit is located, thereby completing the process of writing data 0. Specifically, for the electrical distance area far from the peripheral circuit (i.e., the electrical distance area with a larger resistance Rs), a higher electric pulse can be applied; correspondingly, for the electrical distance area close to the peripheral circuit (i.e., the electrical distance area with a smaller resistance Rs), a lower electric pulse can be applied. For example, Figure 8 In the example, the resistance Rs of region 1 is greater than the resistance Rs of region 2 and greater than the resistance Rs of region 3. Therefore, the electric pulse applied to region 1 is greater than the electric pulse applied to region 2 and greater than the electric pulse applied to region 3.

[0078] It can be understood that, in the process of writing data 0, corresponding electrical pulses are applied to the storage cells in each electrical distance region based on the electrical distance region in which they are located, thereby ensuring that each storage cell can meet the appropriate reset condition.

[0079] Fig.10 A hardware entity diagram of a storage device provided in an embodiment of the present application, such as Fig.10 As shown, the hardware entity of the storage device 1100 includes: a processor 1101 and a memory 1102. The memory 1102 stores a computer program that can be run on the processor 1101, and the processor 1101 implements the steps of the method in any of the above embodiments when executing the program.

[0080] The memory 1102 stores computer programs that can be run on the processor. The memory 1102 is configured to store instructions and applications executable by the processor 1101. It can also cache data to be processed or processed by the processor 1101 and various modules in the storage device 1100 (for example, image data, audio data, voice communication data, and video communication data). This can be achieved through flash memory (FLASH) or random access memory (Random Access Memory, RAM).

[0081] When the processor 1101 executes the program, the steps of any of the above electrical distance region division methods are implemented. The processor 1101 generally controls the overall operation of the storage device 1100 .

[0082] An embodiment of the present application provides a computer storage medium, which stores one or more programs. The one or more programs can be executed by one or more processors to implement the steps in the method of any of the above embodiments.

[0083] It should be noted here that the description of the above storage medium and device embodiments is similar to the description of the above method embodiments, and has similar beneficial effects as the method embodiments. For technical details not disclosed in the storage medium and device embodiments of this application, please refer to the description of the method embodiments of this application for understanding.

[0084] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0085] The serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0086] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A method for dividing electrical distance regions, applied to phase change memory, characterized in that: include: Drawing a resistance change line on the die; wherein the resistance change line includes a plurality of sampling points; different sampling points have different resistances; Performing electrical testing on the bare chip and recording test values ​​of a plurality of the sampling points; wherein the test values ​​represent reset conditions of the storage units in the sampling points; Based on the test values ​​of the plurality of sampling points, the die is divided into a plurality of electrical distance regions.

2. The method for dividing electrical distance regions according to claim 1, characterized in that: Drawing the resistance change line on the die includes: determining a first slope based on line resistance in a wafer acceptability test; The resistance variation line is drawn on the die according to the first slope.

3. The method for dividing electrical distance regions according to claim 2, characterized in that: The line resistance in the wafer acceptability test includes: bit line resistance and word line resistance; The first slope is equal to the ratio of the bit line resistance to the word line resistance.

4. The method for dividing electrical distance regions according to claim 1, characterized in that: Performing an electrical test on the die and recording the test values ​​of the plurality of sampling points on the resistance change line includes: Applying an initial test voltage to the die, and recording the test values ​​of a plurality of the sampling points under the initial test voltage; The test voltage on the die is adjusted step by step, and the test values ​​of a plurality of the sampling points under each of the test voltages are recorded.

5. The method for dividing electrical distance regions according to claim 4, characterized in that: Based on the test values ​​of the plurality of sampling points, the die is divided into a plurality of electrical distance regions, comprising: Determine a region division point among the plurality of sampling points; wherein the region division point is the sampling point at which the test value reaches an inflection point after each adjustment of the test voltage; Based on the area division point, an area division line is drawn on the bare chip to divide the bare chip into a plurality of the electrical distance areas; wherein the area division line intersects with the resistance change line at the area division point.

6. The method for dividing electrical distance regions according to claim 5, characterized in that: Drawing the area division line on the die based on the area division point includes: The area division line is drawn on the die through the area division point according to a second slope; wherein the product of the second slope and the first slope is equal to -1.

7. The method for dividing electrical distance regions according to claim 4, characterized in that: Under the initial test voltage, all the sampling points on the resistance change line are fully reset.

8. The method for dividing electrical distance regions according to any one of claims 1 to 7, characterized in that: The test value includes: a reset threshold voltage of the storage unit at the sampling point.

9. A data writing method, applied to a phase change memory, characterized in that: include: The method for dividing electrical distance regions according to any one of claims 1 to 8; as well as, Based on the electrical distance region where the target memory cell is located, a corresponding electrical pulse is applied to the target memory cell to write data 0 into the target memory cell.

10. A storage device comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, characterized in that: When the processor executes the program, the steps in the method according to any one of claims 1 to 9 are implemented.

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