Method for dividing electrical distance region, data writing method and storage device

Abstract

The application relates to the field of integrated circuits, and discloses a method for dividing an electrical distance region, a data writing method and a storage device. The method for dividing an electrical distance region comprises the following steps: drawing a resistance variation line on a die; wherein the resistance variation line comprises a plurality of sampling points; different sampling points have different resistances; performing an electrical property test on the die, and recording test values of the plurality of sampling points; wherein the test values represent reset conditions of storage units in the sampling points; and dividing the die into a plurality of electrical distance regions based on the test values of the plurality of sampling points.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, specifically to a method for dividing an electrical distance region, a data writing method, and a storage device. Background Technology

[0002] In phase change memory (PCM), the core component is the phase change material based on chalcogenides. PCMs used for data storage contain at least two distinct solid phase structures, typically an amorphous (disordered) and a crystalline (ordered) phase. Specifically, for PCMs, the crystalline structure is heated to melting point and then rapidly cooled, undergoing a rapid annealing process to solidify into an amorphous state. In PCMs, a high-intensity but short-duration electrical pulse is applied to the PCM. Under Joule heating, when the temperature rises above the melting point of the PCM, a rapid heat release process (cooling rate exceeding 10⁹ K / s) causes the PCM to transition directly from a molten state to an amorphous state. This process is a write-0 (reset) operation.

[0003] However, due to the influence of the external circuit resistance, the energy required to write a zero to a memory cell varies in different areas of a real memory array. Far-end memory cells require higher voltages to fully reset; however, for near-end memory cells, excessively high voltages can lead to write disturbances and decreased reliability. Therefore, different areas of the memory array need different reset conditions to ensure performance. Furthermore, in actual manufacturing processes, the resistance of the external circuits may also differ between different wafers and dies.

[0004] Therefore, how to rationally divide the ED (Electrical Distance) region and distinguish memory cells with different peripheral circuit resistances has become a problem that needs to be solved. In related technologies, all dies are divided into ED regions according to a relatively fixed empirical value, which cannot achieve the best performance. Summary of the Invention

[0005] In view of this, embodiments of this application provide a method, apparatus, storage device, and storage medium for dividing an electrical distance region, which can achieve precise division and fine adjustment of the electrical distance region, ensuring that the far-end storage unit can be fully reset, and also improving the reliability of the near-end storage unit and reducing power consumption.

[0006] The technical solution of this application embodiment is implemented as follows:

[0007] This application provides a method for dividing electrical distance regions, applied to a phase-change memory, comprising: drawing a resistance change line on a die; wherein the resistance change line includes multiple sampling points; different sampling points have different resistances; performing electrical tests on the die and recording the test values ​​of the multiple sampling points; wherein the test values ​​characterize the reset status of the memory cells in the sampling points; and dividing the die into multiple electrical distance regions based on the test values ​​of the multiple sampling points.

[0008] In some embodiments of this application, drawing the resistance variation line on the die includes: determining a first slope based on the line resistance in a wafer acceptability test; and drawing the resistance variation line on the die according to the first slope.

[0009] In some embodiments of this application, the line resistance in the wafer acceptability test includes: bit line resistance and word line resistance; the first slope is equal to the quotient of the bit line resistance and the word line resistance.

[0010] In some embodiments of this application, electrical testing is performed on the die, and the test values ​​of multiple sampling points on the resistance change line are recorded, including: applying an initial test voltage to the die and recording the test values ​​of multiple sampling points under the initial test voltage; gradually adjusting the test voltage on the die and recording the test values ​​of multiple sampling points under each test voltage.

[0011] In some embodiments of this application, the die is divided into multiple electrical distance regions based on the test values ​​of multiple sampling points, including: determining a region division point among the multiple sampling points; wherein the region division point is the sampling point where the test value reaches an inflection point after each adjustment of the test voltage; drawing a region division line on the die based on the region division point to divide the die into multiple electrical distance regions; wherein the region division line intersects the resistance change line at the region division point.

[0012] In some embodiments of this application, drawing the region division line on the die based on the region division point includes: drawing the region division line on the die through the region division point and according to a second slope; wherein the product of the second slope and the first slope is equal to -1.

[0013] In some embodiments of this application, all the sampling points on the resistance change line are fully reset under the initial test voltage.

[0014] In some embodiments of this application, the test value includes the reset threshold voltage of the storage cell in the sampling point.

[0015] This application also provides a data writing method applied to a phase-change memory, including: the electrical distance region division method described in the above scheme; and, based on the electrical distance region where the target memory cell is located, applying a corresponding electrical pulse to the target memory cell to write data 0 to the target memory cell.

[0016] This application also provides a storage device, including a memory and a processor, wherein the memory stores a computer program that can run on the processor, characterized in that the processor executes the program to implement the steps in the method described above.

[0017] It is understood that in this embodiment, by drawing resistance change lines, multiple sampling points with different peripheral circuit resistances can be identified, i.e., multiple sampling points with different peripheral circuit resistances can be identified. Then, through electrical testing, the test values ​​of each sampling point are recorded to determine the reset status of each sampling point. Furthermore, based on the reset status of each sampling point, multiple electrical distance regions are divided. Thus, during the writing of data 0, corresponding electrical pulses can be applied to the memory cells in each electrical distance region based on their location, ensuring that each memory cell meets the appropriate reset conditions. This achieves precise division and fine adjustment of the electrical distance regions, ensuring that far-end memory cells can be fully reset, improving the reliability of near-end memory cells, and reducing power consumption, making the reset operation of the phase-change memory more flexible and controllable. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the phase-change memory structure in the embodiments of this application;

[0019] Figure 2 This is a schematic diagram showing the resistance distribution at different distances from the bit line and word line in an embodiment of this application;

[0020] Figure 3 This is a schematic diagram of the implementation process of the electrical distance region division method provided in the embodiments of this application. Figure 1 ;

[0021] Figure 4 This is a schematic diagram of the resistance change line in the embodiments of this application;

[0022] Figure 5A This is a schematic diagram of the distribution of word line resistance in an embodiment of this application;

[0023] Figure 5B This is a schematic diagram of the bit line resistance distribution in the embodiments of this application;

[0024] Figure 6 This is a schematic diagram of the implementation process of the electrical distance region division method provided in the embodiments of this application. Figure 2 ;

[0025] Figure 7 This is a schematic diagram of the region division points in an embodiment of this application;

[0026] Figure 8 This is a schematic diagram of the electrical distance region in the embodiments of this application;

[0027] Figure 9 A schematic diagram illustrating the implementation flow of the data writing method provided in this application embodiment;

[0028] Figure 10 A schematic diagram of the hardware entity of the storage device provided in the embodiments of this application. Detailed Implementation

[0029] Exemplary embodiments of this application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.

[0030] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0031] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0032] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0033] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items. For the unit “root,” “strip,” or “piece” of a transmission line, all have the same meaning.

[0035] In order to gain a more detailed understanding of the features and technical content of the embodiments of this application, the implementation of the embodiments of this application will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this application.

[0036] Figure 1 This is a schematic diagram of an optional structure of the phase-change memory in an embodiment of this application. (Reference) Figure 1 In a phase-change memory (PCM), each memory cell contains a phase-change material, and the two ends of each memory cell are connected to the corresponding word line WL and bit line BL, respectively. The word line WL and bit line BL extend in different directions.

[0037] When a write 1 (set) operation is performed, the phase change material in the target memory cell changes from an amorphous state to a crystalline state, thus writing the data "1" into the target memory cell. Conversely, when a write 0 (reset) operation is performed, the phase change material in the target memory cell changes from a crystalline state to an amorphous state, thus writing the data "0" into the target memory cell.

[0038] It should be noted that in a phase-change memory (PCM) array, the resistance of the peripheral circuitry varies at different locations, resulting in different reset conditions for the memory cells at different locations. In actual testing, the resistance Rs at a specific location can be measured to characterize the resistance of the peripheral circuitry at that location. The peripheral circuitry resistance is directly proportional to the resistance Rs.

[0039] Figure 2 The resistance Rs at different locations on the die is illustrated. (Reference) Figure 2 As the length of the bit line BL and the word line WL increases, the value of the resistance Rs increases accordingly, which can be expressed as resistance Rs = line resistance × wiring length. In other words, the farther away from the external circuit, the larger the resistance Rs, that is, the larger the resistance of the external circuit.

[0040] Figure 3 This is an optional flowchart illustrating a method for dividing electrical distance regions provided in an embodiment of this application, which is applied to phase-change memory. For example... Figure 3 As shown, the method includes steps S101 to S103, which will be explained in conjunction with each step.

[0041] S101. Draw a resistance change line on the die; the resistance change line includes multiple sampling points; different sampling points have different resistances.

[0042] In this embodiment of the application, reference is made to Figure 4Resistance variation lines can be plotted on the die. Since the resistance variation line includes multiple sampling points, and different sampling points have different resistances, the resistance variation line can reflect the changes in the resistance of the peripheral circuits at various locations on the die.

[0043] In some embodiments of this application, a first slope k1 can be determined based on the line resistance in the Wafer Acceptance Test (WAT); then, a resistance change line is drawn on the die according to the first slope k1.

[0044] In this embodiment, the line resistance in WAT includes: bit line resistance Rs_BL and word line resistance Rs_WL. Specifically, the bit line resistance Rs_BL is equal to the resistance per unit length of the bit line divided by the cross-sectional area of ​​the bit line; the word line resistance Rs_WL is equal to the resistance per unit length of the word line divided by the cross-sectional area of ​​the word line.

[0045] refer to Figure 5A and Figure 5B During wafer testing, WAT outputs the bit line resistance Rs_BL and word line resistance Rs_WL for different wafers, dies, or stacks. Figure 5A and Figure 5B In this system, different resistance values ​​are distinguished by different fill patterns.

[0046] Furthermore, the first slope k1 can be set based on the ratio of the bit line resistance Rs_BL to the word line resistance Rs_WL. That is, the first slope k1 can be equal to the quotient of the bit line resistance Rs_BL and the word line resistance Rs_WL, k1 = Rs_BL ÷ Rs_WL.

[0047] In some embodiments of this application, the first slope k1 can be used as the slope of the resistance change line, thereby drawing the resistance change line on the die.

[0048] In some other embodiments of this application, the number of memory cells contained in each sampling point can be determined based on the first slope k1, that is, the shape of each sampling point can be determined based on the first slope k1. For example, in each sampling point, there are 'a' memory cells on the word line WL and 'b' memory cells on the bit line BL, then a = k1 * b can be satisfied; in this way, the number of memory cells on the word line WL and the number of memory cells on the bit line BL can be determined, thereby determining the shape of each sampling point. Furthermore, after determining the number of memory cells contained in each sampling point, a corresponding coordinate system can be generated, and a resistance change line with a slope of 1 can be drawn in the coordinate system, that is, the coordinates of the sampling points on the resistance change line range from (0, 0) to (n, n).

[0049] S102. Perform electrical tests on the bare die and record the test values ​​at multiple sampling points; wherein, the test values ​​characterize the reset status of the memory cells in the sampling points.

[0050] In this embodiment, after drawing the resistance change line, electrical tests can be performed on the die, and the test values ​​of the sampling points on the resistance change line can be recorded. The test values ​​characterize the reset status of the memory cells at the sampling points; therefore, based on the test values, it can be determined whether the memory cells at the sampling points can be fully reset.

[0051] In some embodiments of this application, the test value includes the reset threshold voltage of the memory cell at the sampling point. The reset threshold voltage refers to the voltage required for the phase change material in the memory cell to change from a crystalline state to an amorphous state during a reset operation.

[0052] In this embodiment, since each sampling point includes a certain number of memory cells, and the reset threshold voltage of each memory cell may differ, a value is selected from the reset threshold voltages of each memory cell at the sampling point to serve as the reset threshold voltage of the sampling point. If the reset threshold voltage of each memory cell at the sampling point is described according to a normal distribution, then the value at -3.5σ in the normal distribution graph can be used as the selected value. This ensures that the reset threshold voltage of most memory cells at the sampling point is greater than the selected value, avoiding the distribution of the reset threshold voltage of the memory cells at the sampling point at the selected value. Therefore, it ensures that the memory cells at the same sampling point maintain consistent test results in electrical testing.

[0053] S103. Based on the test values ​​of multiple sampling points, the bare die is divided into multiple electrical distance regions.

[0054] In this embodiment, after obtaining the test values ​​of multiple sampling points, boundary points with specific test values ​​can be selected from the multiple sampling points. Then, region division lines are drawn according to the boundary points, thereby completing the division of multiple electrical distance regions (ED regions). Furthermore, corresponding electrical pulses can be applied to the memory cells in each electrical distance region to ensure that the memory cells in each electrical distance region can meet the appropriate reset conditions.

[0055] It is understood that in this embodiment, by drawing resistance change lines, multiple sampling points with different peripheral circuit resistances can be identified, i.e., multiple sampling points with different peripheral circuit resistances can be identified. Then, through electrical testing, the test values ​​of each sampling point are recorded to determine the reset status of each sampling point. Furthermore, based on the reset status of each sampling point, multiple electrical distance regions are divided. Thus, during the writing of data 0, corresponding electrical pulses can be applied to the memory cells in each electrical distance region based on their location, ensuring that each memory cell meets the appropriate reset conditions. This achieves precise division and fine adjustment of the electrical distance regions, ensuring that far-end memory cells can be fully reset, improving the reliability of near-end memory cells, and reducing power consumption, making the reset operation of the phase-change memory more flexible and controllable.

[0056] In some embodiments of this application, it can be achieved through Figure 6 The steps S201 to S202 shown are implemented to achieve this. Figure 3 Step S102 is shown. Each step will be explained in detail.

[0057] S201. Apply an initial test voltage to the die and record the test values ​​at multiple sampling points under the initial test voltage.

[0058] In this embodiment, during electrical testing, an initial test voltage Vh is first applied to the die, and the test values ​​at multiple sampling points under the initial test voltage are recorded. Under the initial test voltage Vh, all sampling points on the resistance change line are fully reset; that is, under the initial test voltage Vh, even the furthest memory cell can be fully reset. This ensures that all memory cells in all regions can be fully reset, avoiding omissions that could affect the reset performance of the phase-change memory.

[0059] refer to Figure 7 Under the initial test voltage Vh, the reset threshold voltages at each sampling point form a straight line, indicating that each sampling point can fully reset.

[0060] In some embodiments of this application, the initial test voltage Vh can be set to 5V.

[0061] S202. Gradually adjust the test voltage on the die and record the test values ​​at multiple sampling points under each test voltage.

[0062] In this embodiment, the test voltage on the die can be gradually adjusted starting from an initial test voltage Vh. For example, starting with an initial test voltage Vh of 5V, the test voltage can be gradually reduced to 4.5V, 4.2V, etc. Simultaneously, the test values ​​at multiple sampling points under each test voltage are recorded.

[0063] In some embodiments of this application, it can be achieved through Figure 6 The steps S203 to S204 shown are implemented to achieve this. Figure 3 Step S103 is shown. The explanation will be provided in conjunction with each step.

[0064] S203. Among multiple sampling points, determine the region division point; where the region division point is the sampling point where the test value reaches the inflection point after each adjustment of the test voltage.

[0065] In this embodiment of the application, reference is made to Figure 7 When the die is subjected to the first test voltage V1, the reset threshold voltage curve of each sampling point shows a bend, and the inflection point is sampling point D1. Therefore, sampling point D1 can be used as the region division point.

[0066] It should be noted that, because the first test voltage V1 is less than the initial test voltage Vh, the far-end memory cell loses a significant amount of test voltage due to its higher circuit resistance. Consequently, the test voltage obtained by the far-end memory cell is insufficient for a sufficient reset. Therefore, the reset threshold voltage at sampling points farther than D1 decreases, resulting in a bend and a decrease in the reset threshold voltage curve of the first test voltage V1 at sampling point D1. Conversely, the near-end memory cell can still reset sufficiently. Therefore, a portion of the reset threshold voltage curve of the first test voltage V1 at sampling points closer than D1 coincides with the reset threshold voltage curve of the initial test voltage Vh.

[0067] Continue to refer to Figure 7 Similarly, when the die is subjected to the second test voltage V2, the reset threshold voltage curves at each sampling point show a bend, with the inflection point being sampling point D2. Therefore, sampling point D2 can also be used as a region division point.

[0068] It should be noted that the number of area division points is not limited to two; multiple area division points can be determined, and the number of area division points can be adjusted and selected as needed.

[0069] S204. Based on the region division points, draw region division lines on the die to divide the die into multiple electrical distance regions; wherein, the region division lines intersect with the resistance change lines at the region division points.

[0070] In this embodiment of the application, reference is made to Figure 8After determining the region division points D1 and D2, region division lines can be drawn through D1 and D2 respectively, thereby dividing the die into multiple electrical distance regions. Specifically, the region division line passing through region division point D1 divides region 1 and region 2; the region division line passing through region division point D2 divides region 2 and region 3.

[0071] In some embodiments of this application, reference is made to Figure 8 The region division line can be drawn on the bare die through the region division point D1 or D2, according to the second slope k2. The product of the second slope k2 and the first slope k1 is equal to -1, that is, k2 = -1 / k1.

[0072] Understandably, in this embodiment, by gradually adjusting the test voltage on the die and recording the test values ​​at multiple sampling points under each test voltage, multiple region division points can be determined. Then, by drawing region division lines through these points, the die can be divided into multiple electrical distance regions. Thus, during the writing of data 0, corresponding electrical pulses can be applied to the memory cells in each electrical distance region based on their location, ensuring that each memory cell meets the appropriate reset conditions. This achieves precise division and fine adjustment of the electrical distance regions, ensuring that far-end memory cells can be fully reset while also improving the reliability and reducing power consumption of near-end memory cells, making the reset operation of the phase-change memory more flexible and controllable.

[0073] Figure 9 This is a schematic flowchart of an optional data writing method provided in an embodiment of this application, which is applied to a phase-change memory. Figure 9 As shown, the method includes steps S301 to S302, which will be explained in conjunction with each step.

[0074] S301, Delineate electrical distance regions.

[0075] Step S301 can be implemented according to the method for dividing the electrical distance region shown in the above embodiment.

[0076] S302. Based on the electrical distance region where the target storage cell is located, apply a corresponding electrical pulse to the target storage cell to write data 0 to the target storage cell.

[0077] In this embodiment, after dividing the electrical distance region, if it is necessary to write data 0 to the target memory cell, a corresponding electrical pulse can be applied to the target memory cell based on the electrical distance region where the target memory cell is located, thereby completing the process of writing data 0. Specifically, for electrical distance regions farther from the peripheral circuit (i.e., electrical distance regions with larger resistance Rs), a higher electrical pulse can be applied; correspondingly, for electrical distance regions closer to the peripheral circuit (i.e., electrical distance regions with smaller resistance Rs), a lower electrical pulse can be applied. For example, in Figure 8 In the given equation, the resistance Rs of region 1 > the resistance Rs of region 2 > the resistance Rs of region 3. Therefore, the electrical pulse applied to region 1 > the electrical pulse applied to region 2 > the electrical pulse applied to region 3.

[0078] It is understandable that during the writing of data 0, based on the electrical distance region, corresponding electrical pulses are applied to the storage cells in each electrical distance region, thereby ensuring that each storage cell can meet the appropriate reset conditions.

[0079] Figure 10 This is a schematic diagram of the hardware entity of a storage device provided in an embodiment of this application, such as... Figure 10 As shown, the hardware entity of the storage device 1100 includes a processor 1101 and a memory 1102. The memory 1102 stores a computer program that can run on the processor 1101, and when the processor 1101 executes the program, it implements the steps of the method in any of the above embodiments.

[0080] The memory 1102 stores computer programs that can run on the processor. The memory 1102 is configured to store instructions and applications that can be executed by the processor 1101. It can also cache data to be processed or already processed (e.g., image data, audio data, voice communication data, and video communication data) in the various modules of the processor 1101 and the storage device 1100. It can be implemented by flash memory or random access memory (RAM).

[0081] When processor 1101 executes a program, it implements the steps of the electrical distance region division method described above. Processor 1101 typically controls the overall operation of storage device 1100.

[0082] This application provides a computer storage medium that stores one or more programs, which can be executed by one or more processors to implement the steps in the methods of any of the above embodiments.

[0083] It should be noted that the descriptions of the storage medium and device embodiments above are similar to the descriptions of the method embodiments above, and have similar beneficial effects. For technical details not disclosed in the storage medium and device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0084] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0085] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this application can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined to obtain new method or device embodiments without conflict.

[0086] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A method for dividing electrical distance regions, applied to phase-change memory, characterized in that, include: Based on the line resistance in wafer acceptability testing, a resistance variation line is plotted on the die; wherein the resistance variation line includes multiple sampling points, and different sampling points have different resistances; the line resistance includes: bit line resistance and word line resistance; Electrical tests are performed on the bare die, and test values ​​at multiple sampling points are recorded; wherein, the test values ​​characterize the reset status of the memory cells in the sampling points; Based on the test values ​​from multiple sampling points, the bare die is divided into multiple electrical distance regions.

2. The method for dividing the electrical distance region according to claim 1, characterized in that, Based on the line resistance in the wafer acceptability test, the resistance variation line is plotted on the bare die, including: The first slope is determined based on the line resistance in the wafer acceptability test; The resistance change line is plotted on the die according to the first slope.

3. The method for dividing the electrical distance region according to claim 2, characterized in that, The first slope is equal to the ratio of the bit line resistance to the word line resistance.

4. The method for dividing the electrical distance region according to claim 1, characterized in that, The bare die is subjected to electrical tests, and the test values ​​of multiple sampling points on the resistance change line are recorded, including: An initial test voltage is applied to the bare die, and the test values ​​at multiple sampling points under the initial test voltage are recorded; The test voltage on the die is gradually adjusted, and the test values ​​at multiple sampling points under each test voltage are recorded.

5. The method for dividing the electrical distance region according to claim 4, characterized in that, Based on the test values ​​from multiple sampling points, the bare die is divided into multiple electrical distance regions, including: Among the multiple sampling points, a region division point is determined; wherein, the region division point is the sampling point where the test value reaches an inflection point after each adjustment of the test voltage; Based on the region division point, region division lines are drawn on the die to divide the die into multiple electrical distance regions; wherein the region division lines intersect the resistance change lines at the region division point.

6. The method for dividing the electrical distance region according to claim 5, characterized in that, Based on the region division points, the region division lines are drawn on the bare die, including: The region division line is drawn on the die through the region division point, according to the second slope; wherein the product of the second slope and the first slope is equal to -1.

7. The method for dividing the electrical distance region according to claim 4, characterized in that, Under the initial test voltage, all the sampling points on the resistance change line are fully reset.

8. The method for dividing an electrical distance region according to any one of claims 1 to 7, characterized in that, The test values ​​include the reset threshold voltage of the storage unit in the sampling point.

9. A data writing method applied to a phase-change memory, characterized in that, include: The method for dividing the electrical distance region as described in any one of claims 1 to 8; as well as, Based on the electrical distance region where the target storage cell is located, a corresponding electrical pulse is applied to the target storage cell to write data 0 to the target storage cell.

10. A storage device comprising a memory and a processor, the memory storing a computer program executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method according to any one of claims 1 to 9.

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