Semiconductor device and its packaging process method

Abstract

The present application relates to the field of semiconductor technology, and discloses a semiconductor device and its packaging process method. The packaging process method of the semiconductor device includes the steps of: pre-connecting a cathode electrode, an anode electrode, and a gate electrode to a chip through an injection molding process to form an integrated pre-assembled structure that seals and wraps the chip; encapsulating a package shell on the outer periphery of the integrated pre-assembled structure; sealing and electrically connecting the package cathode of the package shell to the cathode electrode, and sealing and electrically connecting the package anode of the package shell to the anode electrode; and covering the package shell with a package cover plate. By adding an integrated molding step before chip packaging, the present application integrally forms and connects the metal electrodes on the chip to the chip, and injects glue into the assembled structure after integrated molding through an injection molding process to wrap the chip, so as to isolate the chip from the external environment, thereby achieving the purpose of improving the test yield of the chip.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and particularly relates to a semiconductor device and its packaging process method. Background Art

[0002] As a core component of power transmission equipment, high-power semiconductor devices need to withstand high-voltage and large-current working environments in actual applications. With the development requirements of high-voltage and large-current equipment, higher voltage and larger current usage requirements are put forward for semiconductor devices. This also poses higher requirements for cleanliness and anti-discharge breakdown during the packaging and testing process of the devices.

[0003] Such as Figure 1 shown, taking the GCT device as an example, the chip needs to go through multiple testing links such as factory testing, pre-packaging testing, and post-packaging testing during the packaging process. With the continuous improvement of the chip voltage level, the failure risk of high-voltage test spark breakdown in the air environment (the breakdown strength of air ~ 2500v / mm) during the chip packaging process is also increasing continuously; therefore, optimizing the packaging structure of high-voltage chips to improve the test yield of chips is of great significance for improving the device yield. Summary of the Invention

[0004] The purpose of this application is to provide a packaging structure, a chip, and a semiconductor device of a semiconductor device to solve the technical problem that the existing packaging process of semiconductor devices has a risk of high-voltage test failure during the chip packaging process.

[0005] To achieve the above purpose, on the one hand, this application provides a packaging process method for a semiconductor device, and the packaging process method includes the steps of:

[0006] S10: Pre-connect the cathode electrode, anode electrode, and gate electrode to the chip through an injection molding process to form an integrated pre-assembled structure that seals and wraps the chip;

[0007] S20: Package the shell on the outer periphery of the integrated pre-assembled structure;

[0008] S30: Sealingly and electrically connect the shell cathode of the shell to the cathode electrode, and sealingly and electrically connect the shell anode of the shell to the anode electrode;

[0009] S40: Use a shell cover plate to cover the shell.

[0010] In some embodiments, the step S10 includes:

[0011] S111: Sealingly pre-assemble the anode side of the chip and the anode electrode through an injection molding process so that injection molding seal layers are formed on both the cathode side and the terminal side of the chip;

[0012] S121: Respectively open a first mounting hole and a second mounting hole on the injection molding sealing layer on the cathode side of the chip through an etching process, where the first mounting hole and the second mounting hole respectively correspond to the reserved positions of the cathode electrode and the gate electrode;

[0013] S131: Assemble the cathode electrode and the gate electrode respectively into the first mounting hole and the second mounting hole correspondingly, so that the cathode electrode and the gate electrode are both electrically connected to the chip.

[0014] In some embodiments, both the first mounting hole and the second mounting hole penetrate the injection molding sealing layer radially and extend to the chip, the first mounting hole is adapted to the cathode electrode, and the second mounting hole is adapted to the gate electrode.

[0015] In some embodiments, the step S111 further includes:

[0016] Metallize the relative connection surfaces of the chip and the anode electrode;

[0017] Connect the metallized chip and the anode electrode into a pre-assembled structure by using a sintering material through a low-temperature sintering device;

[0018] Seal and encapsulate the terminals of the pre-assembled structure and the cathode side of the chip with injection molding glue, and form the injection molding sealing layer.

[0019] In some embodiments, the step S10 includes:

[0020] S141: Pre-connect the cathode electrode, the anode electrode, and the gate electrode to the corresponding positions of the chip through a sintering process to form a pre-assembled structure;

[0021] S151: Form the injection molding sealing layer on the pre-assembled structure through an injection molding process, and seal and fill the terminals of the pre-assembled structure and the gaps between the cathode electrode and the gate electrode with the injection molding sealing layer.

[0022] In some embodiments, the step S141 further includes:

[0023] Metallize the relative connection surfaces of the chip, the anode electrode, the cathode electrode, and the gate electrode;

[0024] Connect the metallized anode electrode, the cathode electrode, and the gate electrode to the chip through a sintering material by using a low-temperature sintering device to form the pre-assembled structure.

[0025] In some embodiments, the maximum service temperature of the sintering material during sintering is greater than or equal to 150 °C.

[0026] In some embodiments, the thickness of the injection molding sealing layer is 1 mm to 2 mm smaller than the thickness of the cathode electrode.

[0027] In some embodiments, the cathode electrode is a monolithic structure or a multi-ring structure.

[0028] The second aspect of the present application further provides a semiconductor device, which is encapsulated and prepared by the above-mentioned packaging process method. The semiconductor device includes:

[0029] A chip integrated assembly structure, including a chip and a cathode electrode, an anode electrode, and a gate electrode electrically connected to the chip. The terminals of the chip integrated assembly structure and the gaps between the cathode electrode and the gate electrode are all sealed and encapsulated by an injection molding sealing layer to seal and wrap the chip;

[0030] A package, used to encapsulate the chip integrated assembly structure. The package is provided with a package cathode and a package anode. The package cathode is connected to the cathode electrode, and the package anode is connected to the anode electrode.

[0031] In some embodiments, the insulation strength of the material of the injection molding sealing layer is greater than or equal to 3 times the breakdown voltage of the semiconductor device.

[0032] Through the above technical solutions, the semiconductor device and its packaging process method provided by the embodiments of the present application have the following beneficial effects:

[0033] When encapsulating the semiconductor device, first add an integral molding link in the back-end process of the chip or the front-end process of packaging. Through the injection molding process, the cathode electrode, the anode electrode, and the gate electrode are pre-connected to the chip to form an integral pre-assembly structure that seals and wraps the chip; then the package is encapsulated on the outer periphery of the integral pre-assembly structure, and the package cathode of the package is hermetically electrically connected to the cathode electrode, and the package anode of the package is hermetically electrically connected to the anode electrode; finally, the package is capped with a package cover plate for the next performance test. By integrally assembling the chip and each metal electrode on the chip and performing injection molding sealing, the present application can seal and wrap the exposed part of the chip, so as to achieve physical isolation between the chip and the external environment, and further avoid the phenomenon of breakdown failure due to contamination during the chip packaging and testing process.

[0034] Other features and advantages of the embodiments of the present application will be described in detail in the subsequent specific embodiments section. Description of the Drawings

[0035] The accompanying drawings are used to provide a further understanding of the embodiments of the present application, and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the embodiments of the present application, but do not constitute a limitation to the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on the structures shown in these drawings without creative efforts. In the drawings:

[0036] Figure 1 is a schematic diagram of the packaging structure of a semiconductor device in the prior art;

[0037] Figure 2 is a schematic diagram of the packaging structure of the semiconductor device of the present application;

[0038] Figure 3 is a schematic process flow diagram of the packaging process method of the semiconductor device in the first embodiment of the present application;

[0039] Figure 4 is a schematic process flow diagram of the packaging process method of the semiconductor device in the second embodiment of the present application.

[0040] Explanation of reference numerals

[0041] 100, chip integrated assembly structure; 101, chip; 102, cathode electrode; 103, anode electrode; 104, gate electrode; 105, gate insulating seat; 200, package shell; 201, package shell cover plate; 300, injection molding sealing layer; 400, first mounting hole; 401, second mounting hole. Detailed description of the specific embodiments

[0042] The following provides a detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application.

[0043] The following describes a semiconductor device and its packaging process method according to the present application with reference to the accompanying drawings.

[0044] Regarding the existing packaging process of the press-fit type semiconductor device as in Figure 1 there is a risk of high-voltage test failure during the packaging process of the chip 101. As shown in Figure 3 and Figure 4 the present application provides a packaging process method for a semiconductor device, and the packaging process method includes the steps:

[0045] S10: Pre-connect the cathode electrode 102, the anode electrode 103, and the gate electrode 104 to the chip 101 through an injection molding process to form an integrated pre-assembly structure that seals and wraps the chip 101;

[0046] S20: Package the package shell 200 on the outer periphery of the integrated pre-assembly structure;

[0047] S30: Hermetically and electrically connect the cathode of the package 200 to the cathode electrode 102, and hermetically and electrically connect the anode of the package 200 to the anode electrode 103;

[0048] S40: Seal the package 200 with the package cover plate 201.

[0049] It should be noted that the semiconductor device of the present application is a high-power semiconductor device. The chip 101, the cathode electrode 102, and the anode electrode 103 are all in sheet structures and are electrically connected in a stacked manner. Specifically, the anode electrode 103 is disposed on one side of the chip 101, and the cathode electrode 102 is disposed on the side of the chip 101 away from the anode electrode 103. In the prior art for such a simple stacked structure, part of the chip 101 is exposed outside and directly contacts the external environment. In the present application, an integrally formed step is added in the front-end process of chip 101 packaging. The chip 101 is electrically connected to metal electrodes (the cathode electrode 102, the anode electrode 103, and the gate electrode 104) to form an integral structure. The gaps in the integral structure and the exposed part of the chip 101 are hermetically filled by an injection molding process. The chip 101 is physically isolated from the external environment, so that the chip 101 is wrapped by the metal electrodes and the sealing layer formed by injection molding, thereby isolating and protecting the chip 101, eliminating the possibility of the chip 101 being contaminated, and improving the test yield of the chip 101 in each process. Among them, the cathode electrode 102, the anode electrode 103, and the gate electrode 104 can all be molybdenum sheets.

[0050] When packaging the semiconductor device, first, the chip 101, the cathode electrode 102, the anode electrode 103, and the gate electrode 104 are connected by an injection molding process to form an integrated pre-assembled structure. Then, the entire integrated pre-assembled structure is packaged in the package 200. The cathode of the package 200 and the cathode electrode 102 are hermetically and electrically connected by a soldering process, and the anode of the package 200 and the anode electrode 103 are hermetically and electrically connected by a soldering process. Finally, the assembled package 200 is sealed with the package cover plate 201. After the packaging is completed, dynamic and static parameter performance tests are carried out on the entire semiconductor device. The packaging process of the present application forms an integrated packaging structure by the chip 101 and the metal electrodes, and then packages the entire integrated packaging structure, which solves the problem of chip 101 contamination at the source, simplifies the packaging process flow, and improves the packaging yield.

[0051] Among them, when assembling the integrated packaging structure, the following two embodiments can be adopted:

[0052] In the first embodiment, step S10 includes:

[0053] S111: The anode side of the chip 101 and the anode electrode 103 are hermetically pre-assembled by an injection molding process, so that an injection molding sealing layer 300 is formed on both the cathode side and the terminal side of the chip 101;

[0054] S121: First mounting holes 400 and second mounting holes 401 are respectively formed on the injection molding sealing layer 300 on the cathode side of the chip 101 by an etching process. The first mounting holes 400 and the second mounting holes 401 respectively correspond to the reserved positions of the cathode electrode 102 and the gate electrode 104;

[0055] S131: The cathode electrode 102 and the gate electrode 104 are respectively assembled into the first mounting holes 400 and the second mounting holes 401, so that the cathode electrode 102 and the gate electrode 104 are electrically connected to the chip 101.

[0056] In this embodiment, when the terminal process of the chip 101 is completed, the terminal injection molding process is not carried out temporarily. The anode electrode 103 and the anode side of the chip 101 are pre-assembled by a tooling or sintering / welding process; then the above pre-assembled structure is sealed together by an injection molding or potting process. Since the cathode side of the chip 101 is exposed, an injection molding sealing layer 300 can be formed on both the cathode side of the chip 101 and the exposed part of the terminal after injection molding. Then, the first mounting holes 400 and the second mounting holes 401 are formed at the positions corresponding to the cathode side of the chip 101 on the injection molding sealing layer 300 by an etching / corrosion process. The first mounting holes 400 and the second mounting holes 401 respectively correspond to the reserved positions of the cathode electrode 102 and the gate electrode 104 of the chip 101, and the opening extends to the electrode mounting position of the chip 101; finally, the cathode electrode 102 and the gate electrode 104 are correspondingly installed in the first mounting holes 400 and the second mounting holes 401. By forming the corresponding first mounting holes 400 and second mounting holes 401 on the injection molding sealing layer 300, the present application makes the integration assembly process more accurate, and the entire assembly process has no complex process, realizing the electrical connection between each metal electrode and the chip 101 while ensuring sealing.

[0057] In some embodiments, both the first mounting holes 400 and the second mounting holes 401 penetrate the injection molding sealing layer 300 along the radial direction and extend to the chip 101. The first mounting holes 400 are adapted to the cathode electrode 102, and the second mounting holes 401 are adapted to the gate electrode 104.

[0058] In this embodiment, since the first mounting hole 400 is used to mount the cathode electrode 102 and the second mounting hole 401 is used to mount the gate electrode 104, it is necessary to adapt the shape of the first mounting hole 400 to the cathode electrode 102 and the shape of the second mounting hole 401 to the gate electrode 104. In this way, there is no gap between the first mounting hole 400 and the cathode electrode 102, and no gap between the second mounting hole 401 and the gate electrode. Moreover, by radially penetrating the first mounting hole 400 and the second mounting hole 401, one end of the cathode electrode 102 in the first mounting hole 400 can contact the chip 101 to achieve electrical connection with the chip 101, and one end of the gate electrode 104 in the second mounting hole 401 can contact the chip 101 to achieve electrical connection with the chip 101, thereby ensuring the precise installation and hermetic encapsulation of the cathode electrode 102 and the gate electrode 104.

[0059] In some embodiments, step S111 further includes the following steps:

[0060] Metalize the relative connection surfaces of the chip 101 and the anode electrode 103;

[0061] Connect the metalized chip 101 and the anode electrode 103 into a pre-assembled structure by a low-temperature sintering device using a sintering material;

[0062] Seal and encapsulate the terminals of the pre-assembled structure and the cathode side of the chip 101 with injection glue to form an injection molding sealing layer 300.

[0063] In this embodiment, when assembling the chip 101 and the anode electrode 103, first metalize the relative connection surfaces of the chip 101 and the anode electrode 103. The purpose of metalization is to ensure the wettability of the sintering / welding contact surface. For example, a silver sintering process can be used for metalization, and it is required that the material of the metalized layer has wettability with silver, which can be silver, gold, copper, etc. After metalization, connect the chip 101 and the anode molybdenum sheet through a sintering material by a dedicated low-temperature sintering device. Among them, the process parameters during the sintering process are preferably: the sintering temperature range is 180°C to 300°C, the pressure range is 10 MPa to 20 MPa, the time is 60 to 120 s, and the atmosphere is a reducing atmosphere. The low-temperature sintering device can use common sintering devices in the prior art and is not limited here. Finally, form an injection molding sealing layer 300 covering the chip 101 on the pre-assembled structure through an injection molding process, thus completing the entire integrated assembly process.

[0064] Further, during the injection molding process, surface activation of the pre-assembled structure is first required: by coating a coupling agent on the surface to be treated of the pre-assembled structure to improve the contact surface activity; then assembling the pre-assembled structure to be injected with glue into a specific fixture, leaving a certain glue injection space in the fixture, and filling the injection material into the mold through an injection molding machine; during the glue injection process, multiple cycles of degassing are carried out to eliminate the gas in the glue, and finally the pre-assembled structure after glue injection is cured and formed in a vacuum oven, and finally an injection-molded sealing layer 300 is formed in a sealed package on both the terminal of the pre-assembled structure and the cathode side of the chip 101.

[0065] In the second embodiment of the present application, step S10 includes:

[0066] S141: Pre-connect the cathode electrode 102, the anode electrode 103, and the gate electrode 104 to the corresponding positions of the chip 101 through a sintering process to form a pre-assembled structure;

[0067] S151: Form an injection-molded sealing layer 300 on the pre-assembled structure through an injection molding process, and seal and fill the gap between the terminal of the pre-assembled structure and between the cathode electrode 102 and the gate electrode 104 with the injection-molded sealing layer 300.

[0068] In this embodiment, when the chip 101 completes the terminal process, the terminal glue injection process is not carried out temporarily; first, the anode electrode 103, the cathode electrode 102, and the gate molybdenum sheet are pre-connected to the chip 101 through a sintering / welding process to form a pre-assembled structure; then the above pre-assembled structure is sealed together through a glue injection or plastic encapsulation process, so that the injection-molded sealing layer 300 fills both the terminal of the pre-assembled structure and the gap between the cathode electrode 102 and the gate electrode 104, and finally the assembly is completed. The parameters of the sintering process in the second embodiment are the same as those of the sintering process in the first embodiment, and will not be elaborated here.

[0069] In some embodiments, step S141 further includes:

[0070] Metalize the relative connection surfaces of the chip 101, the anode electrode 103, the cathode electrode 102, and the gate electrode 104;

[0071] Connect the metalized anode electrode 103, cathode electrode 102, and gate electrode 104 to the chip 101 through a sintering material by a low-temperature sintering device to form a pre-assembled structure.

[0072] When assembling each metal electrode of the chip 101, first, the opposite surfaces of the chip 101 and the anode electrode 103, the opposite surfaces of the chip 101 and the cathode electrode 102, and the opposite surfaces of the chip 101 and the gate electrode 104 are metallized, so as to ensure the wettability of the sintering / welding contact surfaces. For example, the silver sintering process can be used for metallization, and it is required that the material of the metallized layer has wettability with silver, which can be silver, gold, copper, etc. After the metallization of each relative contact surface is completed, through a special low-temperature sintering device, the chip 101, the cathode electrode 102, the anode electrode 103, and the gate electrode 104 are connected through a sintering material to form a pre-assembled structure. In this embodiment, the process parameters during the sintering process are preferably: the sintering temperature range is 180°C to 300°C, the pressure range is 10 MPa to 20 MPa, the time is 60 to 120 s, and the atmosphere is a reducing atmosphere.

[0073] In some embodiments, the maximum service temperature of the sintering material during sintering is greater than or equal to 150°C. Since the actual operating temperature (junction temperature) of the internal transistor nodes of the semiconductor device chip 101 is usually 150°C, during the semiconductor packaging process, the use temperature of the sintering material needs to be not less than 150°C, so as to ensure the normal progress of the entire sintering process.

[0074] In some embodiments, since the thickness of the cathode electrode 102 is generally 2.5 mm, during injection molding, the thickness of the entire injection molding sealing layer 300 needs to be designed to be 1 mm to 2 mm smaller than the thickness of the cathode electrode 102, so that one end of the cathode electrode 102 facing away from the chip 101 can extend out of the injection molding sealing layer 300; and by setting the thickness of the injection molding sealing layer 300 to be smaller than that of the cathode electrode 102, sufficient contact space can be ensured between the cathode electrode 102 and the shell electrode.

[0075] In some embodiments, the cathode electrode 102 is a whole-piece structure or a multi-ring structure. It can be understood that the cathode electrode 102 can be a whole circular wafer structure. At this time, the diameter of the first mounting hole 400 is larger to adapt to the whole-piece cathode electrode 102, and reference can be made to the first method shown in Figure 3 and Figure 4 ; of course, the cathode electrode 102 can also be a structure in which multiple annular sheets are arranged in sequence from the inside to the outside in the radial direction. When the cathode electrode 102 is a multi-ring structure, the number of the first mounting holes 400 is the same as the number of rings of the cathode electrode 102 (such as the second method shown in Figure 3 and Figure 4 ), and each ring of the electrode is adaptively installed corresponding to a first mounting hole 400. In addition, when the cathode electrode 102 is designed as a multi-ring structure, the pressure of the cathode electrode 102 on the chip 101 can be made uniform, and the crimping uniformity of the chip 101 during the entire packaging process can be improved.

[0076] As Figure 2 shown, the second aspect of the present application further provides a semiconductor device, which is fabricated by using the packaging process method as described above. Since this semiconductor device is obtained by using the above-mentioned packaging process method, it has all the beneficial effects brought by the above-mentioned packaging process method. The semiconductor device of the present application includes a chip integrated assembly structure 100 and a package 200; the chip integrated assembly structure 100 includes a chip 101, a cathode electrode 102, an anode electrode 103, and a gate electrode 104 electrically connected to the chip 101. The terminals of the chip integrated assembly structure 100 and the gaps between the cathode electrode 102 and the gate electrode 104 are all hermetically sealed by an injection molding sealing layer 300 to hermetically wrap the chip 101, thereby preventing the chip 101 from being exposed to the external environment; the package 200 is used to package the chip integrated assembly structure 100. The package 200 is provided with a package cathode and a package anode. The package cathode is connected to the cathode electrode 102, the package anode is connected to the anode electrode 103, and one end of the gate electrode 104 facing away from the chip 101 is connected to a gate insulating seat 105.

[0077] In this embodiment, for the semiconductor device obtained by using the above-mentioned packaging process, during the packaging process, the possibility of the chip 101 being contaminated is eliminated by integrally wrapping the chip 101, which can improve the yield rate of the chip 101 in various link tests and also improve the packaging efficiency of the semiconductor device.

[0078] In some embodiments, since the injection molding sealing layer 300 wraps the chip 101 inside, in order to prevent the injection molding sealing layer 300 from generating conductivity, the material of the injection molding sealing layer 300 needs to be made into an insulating material to be insulated from the outside. Preferably, the insulation strength of the material of the injection molding sealing layer 300 is greater than or equal to 3 times the breakdown voltage of the semiconductor device to ensure the strong insulation of the entire injection molding sealing layer 300, thereby improving the use safety of the entire semiconductor device.

[0079] In the description of the present application, it should be understood that the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of these features. In the description of the present application, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined.

[0080] In this application, unless otherwise clearly specified or limited, the terms "installed", "connected", "coupled", "fixed", etc. shall be construed in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection, an electrical connection, or communicable with each other; it may be directly connected, or indirectly connected through an intermediate medium, and it may be the communication inside two components or the interaction relationship between two components, unless otherwise clearly limited. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0081] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0082] Although the embodiments of this application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting this application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. A semiconductor device packaging process method, characterized in that: The packaging process method comprises the steps of: S10: pre-connecting the cathode electrode (102), the anode electrode (103) and the gate electrode (104) to the chip (101) through an injection molding process to form an integrated pre-assembled structure that seals and wraps the chip (101); S20: Encapsulating the tube shell (200) on the periphery of the integrated pre-assembled structure; S30: sealingly and electrically connecting the tube shell cathode of the tube shell (200) to the cathode electrode (102), and sealingly and electrically connecting the tube shell anode of the tube shell (200) to the anode electrode (103); S40: using a tube shell cover plate to seal the tube shell (200); The step S10 comprises: S111: pre-sealing and assembling the anode side of the chip (101) and the anode electrode (103) by an injection molding process, so that an injection molding sealing layer (300) is formed on both the cathode side and the terminal side of the chip (101); S121: opening a first mounting hole (400) and a second mounting hole (401) on the injection molding sealing layer (300) on the cathode side of the chip (101) through an etching process, respectively, the first mounting hole (400) and the second mounting hole (401) corresponding to reserved positions of the cathode electrode (102) and the gate electrode (104), respectively; S131: Assembling the cathode electrode (102) and the gate electrode (104) into the first mounting hole (400) and the second mounting hole (401) respectively, so that the cathode electrode (102) and the gate electrode (104) are electrically connected to the chip (101).

2. The semiconductor device packaging process according to claim 1, characterized in that: The first mounting hole (400) and the second mounting hole (401) both radially penetrate the injection-molded sealing layer (300) and extend to the chip (101); the first mounting hole (400) is adapted to the cathode electrode (102), and the second mounting hole (401) is adapted to the gate electrode (104).

3. The semiconductor device packaging process according to claim 1, characterized in that: The step S111 further includes: Metallizing the relative connection surfaces of the chip (101) and the anode electrode (103); The metallized chip (101) and the anode electrode (103) are connected into a pre-assembled structure by using a low-temperature sintering device using a sintering material; The terminal of the pre-assembled structure and the cathode side of the chip (101) are sealed and wrapped with glue injection to form the injection-molded sealing layer (300).

4. The semiconductor device packaging process method according to claim 3, characterized in that: The maximum use temperature of the sintered material during sintering is greater than or equal to 150°C.

5. The semiconductor device packaging process method according to claim 1, characterized in that: The thickness of the injection-molded sealing layer (300) is 1 mm to 2 mm smaller than the thickness of the cathode electrode (102).

6. The semiconductor device packaging process method according to claim 1, characterized in that: The cathode electrode (102) is a whole piece structure or a multi-ring structure.

7. A semiconductor device, characterized in that: The semiconductor device is packaged and prepared by the packaging process method according to any one of claims 1 to 6, and the semiconductor device comprises: A chip integrated assembly structure (100), comprising a chip (101) and a cathode electrode (102), an anode electrode (103) and a gate electrode (104) electrically connected to the chip (101), wherein the terminal of the chip integrated assembly structure (100) and the gap between the cathode electrode (102) and the gate electrode (104) are sealed and packaged by an injection molding sealing layer (300) to seal and wrap the chip (101); The tube shell (200) is used to package the chip integrated assembly structure (100); the tube shell (200) is provided with a tube shell cathode and a tube shell anode; the tube shell cathode is connected to the cathode electrode (102), and the tube shell anode is connected to the anode electrode (103).

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