Explosion-proof terminal and explosion-proof control method

Abstract

The invention discloses an explosion-proof terminal and an explosion-proof control method. The explosion-proof terminal comprises a first power supply, a first fuse, a first current limiting switch, a first switch, a second switch, a central processing unit (CPU), a first resistor group and a second resistor group, the first fuse is respectively connected with the first power supply and the first current limiting switch; the first current limiting switch is connected with the CPU, the first switch and the second switch respectively; the CPU is respectively connected with the first switch and the second switch; the first switch is connected with the first resistor group, and the second switch is connected with the second resistor group; the CPU is used for controlling the second switch to be switched to a corresponding resistor channel of the second resistor group according to a target current value; and controlling the first switch to be switched to the corresponding resistor channel of the first resistor group. The current limiting value can be adjusted to be closer to the target current value. And the accuracy of explosion-proof current limiting is improved.

Description

Technical Field

[0001] The present application relates to the technical field of explosion-proof current limiting, and in particular to an explosion-proof terminal and an explosion-proof control method. Background Art

[0002] In recent years, smart terminals have developed rapidly. During the use of smart terminals, for capacitive loads with fixed capacitance, if the high voltage exceeds the requirements of GB3836.4, a short circuit fault in the capacitor will cause sparks; for inductive loads with fixed inductance, if the energy storage exceeds the requirements of GB3836.4, an open circuit fault in the inductor will cause sparks. Abnormal circuit sparks can cause explosions in explosive environments. Another mode of ignition is high-temperature ignition of small components. For example, a chip has a short circuit fault, and its own temperature rises sharply. When the heat dissipation area is fixed, the temperature is high to a certain extent, that is, it exceeds the requirements of GB3836.1, which will cause explosions in explosive environments such as coal and petrochemicals.

[0003] Whether it is for ignition or high-temperature ignition of small components, energy limitation is required to ensure that the energy does not exceed the national standard requirements. Energy limitation requires limiting voltage and current as well as the duration of high-power state. Power multiplied by time is energy. In the prior art, explosion-proof terminals generally limit current by connecting a fuse and a current limiting switch in series on the power line. The problem with the prior art is that the current limiting value of the current limiting switch is generally a current value within the range of ±10% of the target current value, and the current limiting accuracy of the current limiting switch is not accurate enough. In this way, the current limiting consistency between different terminal individuals of the same model is poor, resulting in the need for the fuse in series with the current limiting switch to cover a larger current limiting range when selecting, which is not conducive to explosion-proof performance. When selecting a current-limiting fuse, if the current limiting value is too small, the high cost of terminal maintenance due to frequent fuse blowing is faced; if the current limiting value is too large, the current limiting protection is too broad and the safety of the terminal cannot be guaranteed. Therefore, the explosion-proof current limiting accuracy of the prior art is poor. Summary of the invention

[0004] The present application provides an explosion-proof terminal and an explosion-proof control method, which are used to solve the problem of poor accuracy of explosion-proof current limiting in the prior art.

[0005] In a first aspect, the present application provides an explosion-proof terminal, the explosion-proof terminal comprising: a first power supply, a first fuse, a first current limiting switch, a first switch, a second switch, a central processing unit CPU, a first resistor group, and a second resistor group;

[0006] The first fuse is connected to the first power supply and the first current limiting switch respectively; the first current limiting switch is connected to the CPU, the first switch and the second switch respectively; the CPU is connected to the first switch and the second switch respectively; the first switch is connected to the first resistor group, and the second switch is connected to the second resistor group;

[0007] The CPU is used to control the second switch to switch to the corresponding resistance channel of the second resistance group according to the target current value; and control the first switch to switch to the corresponding resistance channel of the first resistance group.

[0008] The above technical solution has the following advantages or beneficial effects:

[0009] The present application provides an explosion-proof terminal. Compared with the explosion-proof terminal of the prior art that only connects a fuse and a current limiting switch in series, the present application adds a first switch, a second switch, a first resistor group and a second resistor group in the explosion-proof terminal. In addition, the first fuse is connected to the first power supply and the first current limiting switch respectively; the first current limiting switch is connected to the CPU, the first switch and the second switch respectively; the CPU is connected to the first switch and the second switch respectively; the first switch is connected to the first resistor group, and the second switch is connected to the second resistor group; the CPU is used to control the second switch to switch to the corresponding resistor channel of the second resistor group according to the target current value; control the first switch to switch to the corresponding resistor channel of the first resistor group. Through the explosion-proof terminal of the present application, the current limiting value can be adjusted to be closer to the target current value, and the current limiting accuracy setting of the current limiting switch is improved. This makes it easier to select fuse devices, the fuse breaking current can also be closer to the current limiting value of the current limiting switch, and the explosion-proof design scheme is more rigorous. The accuracy of explosion-proof current limiting is improved.

[0010] In an optional embodiment, the explosion-proof terminal further includes: a second fuse, a second current limiting switch and a third switch;

[0011] The power supply end of the first power supply is respectively connected to the first end of the first fuse and the first end of the second fuse; the second end of the first fuse is connected to the first end of the first current limiting switch; the second end of the second fuse is connected to the first end of the second current limiting switch; the second end of the first current limiting switch is connected to the power receiving end of the CPU, and the control end of the CPU is respectively connected to the first ends of the first switch, the second switch and the third switch; the second end of the second current limiting switch is respectively connected to the second end of the third switch and the analog-to-digital conversion ADC sampling end of the CPU; the third end of the second current limiting switch is connected to the second end of the first switch; the third end of the first switch is connected to the first resistor group; the third end of the third switch is connected to the second end of the second switch; the third end of the second switch is connected to the second resistor group.

[0012] In an optional embodiment, the explosion-proof terminal further includes: a second power supply;

[0013] The second end of the first current limiting switch is connected to the power receiving end of the second power supply, and the power supply end of the second power supply is connected to the power receiving end of the CPU.

[0014] The above technical solution has the following advantages or beneficial effects:

[0015] In the present application, by connecting a second power supply between the second end of the first current limiting switch and the power receiving end of the CPU, the second power supply supplies power to the CPU, thereby realizing power grouping of the CPU. At a certain fixed voltage, the capacitance allowed to be mounted is limited, and the grouping is performed by current limiting, so that the total capacitance allowed to be mounted on the whole machine is larger, and the functions and performance of the terminal equipment can be guaranteed on the basis of meeting the explosion-proof standards.

[0016] In an optional implementation, the explosion-proof terminal further includes: a power management unit PMU and a memory;

[0017] The power supply end of the second power supply is connected to the power receiving end of the PMU and the memory respectively.

[0018] In an optional implementation, the explosion-proof terminal further includes: a third power supply and a peripheral unit; wherein the peripheral unit includes at least one of a display screen, a sound card, a receiver, a microphone, and a camera;

[0019] The third end of the third switch is connected to the power receiving end of the third power supply, and the power supply end of the third power supply is connected to the power receiving end of the peripheral unit.

[0020] The above technical solution has the following advantages or beneficial effects:

[0021] In the present application, by connecting a third power supply between the third end of the third switch and the power receiving end of the peripheral unit, the third power supply supplies power to the peripheral unit, thereby realizing the power grouping of the peripheral unit. At a certain fixed voltage, the capacitance allowed to be mounted is limited, and the grouping is performed by current limiting, so that the total capacitance allowed to be mounted on the whole machine is larger, and the functions and performance of the terminal device can be guaranteed on the basis of meeting the explosion-proof standards.

[0022] In an optional implementation, the third switch includes: a first MOS tube;

[0023] The control end of the CPU is connected to the gate of the first MOS tube; the second end of the second current limiting switch is connected to the source of the first MOS tube; the drain of the first MOS tube is respectively connected to the power receiving end of the third power supply and the second end of the second switch.

[0024] The above technical solution has the following advantages or beneficial effects:

[0025] In the present application, the first MOS tube can be used as the third switch to realize the control switching function of the third switch. When the CPU inputs a low level to the gate of the first MOS tube, the first MOS tube is disconnected, and when the CPU inputs a high level to the gate of the first MOS tube, the first MOS tube is turned on. Thus, the accuracy of explosion-proof current limiting control is improved.

[0026] In an optional implementation, the second switch includes: at least one second MOS tube;

[0027] The control end of the CPU is connected to the gate of the at least one second MOS tube; the drain of the first MOS tube is respectively connected to the source of the at least one second MOS tube; the drain of the at least one second MOS tube is connected to the corresponding resistor in the second resistor group.

[0028] The above technical solution has the following advantages or beneficial effects:

[0029] In the present application, at least one second MOS tube can be used as the second switch. The number of the second MOS tubes is the same as the number of resistors included in the second resistor group, and each second MOS tube corresponds to a resistor in the second resistor group. The second MOS tube acts as the second switch to realize the control switching function of the second switch. When the CPU inputs a low level to the gate of the second MOS tube, the second MOS tube is disconnected, and when the CPU inputs a high level to the gate of the second MOS tube, the second MOS tube is turned on. Thereby improving the accuracy of explosion-proof current limiting control.

[0030] In an optional implementation, the second current limiting switch includes: an operational amplifier comparator and a third MOS tube;

[0031] The second end of the second fuse is respectively connected to the inverting input end of the operational amplifier comparator, the source of the third MOS tube and the first resistor group; the output end of the operational amplifier comparator is connected to the gate of the third MOS tube; the drain of the third MOS tube is respectively connected to the first end of the third switch and the ADC sampling end of the CPU; the positive input end of the operational amplifier comparator is connected to the first resistor group.

[0032] In an optional implementation, the explosion-proof terminal further includes: a first resistor and a second resistor;

[0033] The second end of the second fuse is connected to the first end of the first resistor, and the second end of the first resistor is connected to the inverting input end of the operational amplifier comparator and the source of the third MOS tube respectively;

[0034] The positive input terminal of the operational amplifier comparator is connected to the first terminal of the second resistor; and the second terminal of the second resistor is grounded.

[0035] The above technical solution has the following advantages or beneficial effects:

[0036] In the present application, an operational amplifier comparator and a third MOS tube are used to realize the function of the second current limiting switch. The CPU controls the first switch to select different set resistance values ​​in the first resistor group. Different set resistance values ​​form different current limiting values ​​together with the operational amplifier comparator. The operational amplifier comparator outputs high and low levels to control the conduction and disconnection of the third MOS tube, thereby realizing the current limiting function.

[0037] In a second aspect, the present application provides an explosion-proof control method based on an explosion-proof terminal, which is applied to a central processing unit (CPU), and the method comprises:

[0038] According to a preset resistance value, controlling the first switch to switch to a resistance channel of the first resistance group corresponding to the preset resistance value; wherein the first resistance group includes a plurality of resistors with different resistance values;

[0039] Controlling the third switch to switch to the conducting direction of the second switch; determining a target resistance value according to the voltage at the second end of the second current limiting switch and the target current value; controlling the second switch to switch to a resistance channel of the second resistor group corresponding to the target resistance value;

[0040] Delaying a preset time, and acquiring a voltage value of the second end of the third switch through an ADC sampling end;

[0041] If the voltage value is 0, control the first switch to switch to a resistance channel of the first resistor group with a larger resistance value, until the voltage value is not 0, control the first switch to switch to a resistance channel of the current resistance channel with a smaller resistance value;

[0042] If the voltage value is not 0, the first switch is controlled to switch to a resistance channel of the first resistor group with a resistance value one level smaller than that of the first resistor group until the voltage value is 0.

[0043] In a third aspect, the present application provides an explosion-proof control device based on an explosion-proof terminal, which is applied to a central processing unit (CPU), and the device comprises:

[0044] A first control module, configured to control the first switch to switch to a resistance channel of the first resistor group corresponding to the preset resistance value according to a preset resistance value; wherein the first resistor group includes a plurality of resistors with different resistance values;

[0045] a second control module, configured to control the third switch to switch to the conducting direction of the second switch; determine a target resistance value according to the voltage at the second end of the second current limiting switch and the target current value; and control the second switch to switch to a resistance channel of the second resistor group corresponding to the target resistance value;

[0046] An acquisition module, used for delaying a preset time and acquiring a voltage value of the second end of the third switch through an ADC sampling end;

[0047] A third control module, configured to control the first switch to switch to a resistance channel of the first resistor group with a larger resistance value if the voltage value is 0, and control the first switch to switch to a resistance channel of the current resistance channel with a smaller resistance value if the voltage value is not 0;

[0048] The third control module is further configured to control the first switch to switch to a resistance channel of the first resistor group with a smaller resistance value if the voltage value is not 0, until the voltage value is 0.

[0049] In a fourth aspect, the present application provides an electronic device, including a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus;

[0050] Memory, used to store computer programs;

[0051] The processor is used to implement the method when executing the program stored in the memory.

[0052] In a fifth aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and the computer program implements the described method when executed by a processor.

[0053] In a sixth aspect, the present application provides a computer program product, wherein the computer program product comprises an executable program, and the executable program is executed by a processor to implement the described method. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0055] Figure 1 A schematic diagram of the first explosion-proof terminal structure provided for this application;

[0056] Figure 2 A schematic diagram of the second explosion-proof terminal structure provided for this application;

[0057] Figure 3 A schematic diagram of the third explosion-proof terminal structure provided for this application;

[0058] Figure 4 A schematic diagram of the fourth explosion-proof terminal structure provided for this application;

[0059] Figure 5 A schematic diagram of the fifth explosion-proof terminal structure provided for this application;

[0060] Figure 6 A schematic diagram of the structure of the second switch and the third switch provided in this application;

[0061] Figure 7 A schematic diagram of the sixth explosion-proof terminal structure provided for this application;

[0062] Figure 8 Schematic diagram of the explosion-proof control process provided for this application;

[0063] Fig. 9 Detailed flow chart of explosion-proof control provided for this application;

[0064] Fig.10 A schematic diagram of the structure of an explosion-proof control device based on an explosion-proof terminal provided in this application;

[0065] Fig.11 This is a schematic diagram of the electronic device structure provided in this application. DETAILED DESCRIPTION

[0066] In order to make the purpose and implementation method of the present application clearer, the exemplary implementation method of the present application will be clearly and completely described below in conjunction with the drawings in the exemplary embodiments of the present application. Obviously, the described exemplary embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0067] It should be noted that the brief description of terms in this application is only for the convenience of understanding the embodiments described below, and is not intended to limit the embodiments of this application. Unless otherwise specified, these terms should be understood according to their common and usual meanings.

[0068] The terms "first", "second", "third", etc. in the specification and claims of this application and the above drawings are used to distinguish similar or similar objects or entities, and do not necessarily mean to limit a specific order or sequence, unless otherwise noted. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances.

[0069] The terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover but not exclude inclusion, for example, a product or device comprising a list of components is not necessarily limited to all the components expressly listed but may include other components not expressly listed or inherent to such product or device.

[0070] The term "module" refers to any known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code that is capable of performing the functions associated with that element.

[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

[0072] For the convenience of explanation, the above description has been made in conjunction with specific embodiments. However, the above exemplary discussion is not intended to be exhaustive or limit the embodiments to the specific forms disclosed above. Based on the above teachings, various modifications and variations can be obtained. The selection and description of the above embodiments are to better explain the principles and practical applications, so that those skilled in the art can better use the embodiments and various different variations of the embodiments suitable for specific use considerations.

[0073] The explosion-proof terminals in the prior art are developing rapidly, including explosion-proof mobile phones, explosion-proof tablet computers, etc. Explosion-proof terminals are used in industries with explosion risks such as coal and petrochemicals, and technical solutions have also been greatly developed in recent years. In general, explosion-proof terminals are based on energy limitation to achieve explosion-proof. Energy limitation measures include voltage limitation, current limitation, and time limitation. This application provides an explosion-proof terminal and explosion-proof control method for current-limiting explosion-proof measures. In the field of current limiting design of explosion-proof terminals, the current limiting accuracy of general current limiting switches is ±10%, which is not accurate enough. In this way, the current limiting consistency between different machines of the same model is poor, resulting in the fuse in series with the current limiting switch. The current limiting range needs to be covered when selecting a larger one, which is not conducive to explosion-proof performance. This application calibrates the current limiting through a hardware design mechanism to improve the current limiting accuracy; in addition, for the same set of motherboards compatible with peripherals of different power consumption specifications, the compatibility is better, and there is no need to change the motherboard patch parts, and adaptively switch to the best explosion-proof current limiting state.

[0074] Figure 1 This is a schematic diagram of the first explosion-proof terminal structure provided in the present application, wherein the explosion-proof terminal comprises: a first power supply U1, a first fuse F1, a first current limiting switch S1, a first switch K1, a second switch K2, a central processing unit CPU, a first resistor group RS1 and a second resistor group RS2;

[0075] The first fuse F1 is connected to the first power supply U1 and the first current limiting switch S1 respectively; the first current limiting switch S1 is connected to the CPU, the first switch K1 and the second switch K2 respectively; the CPU is connected to the first switch K1 and the second switch K2 respectively; the first switch K1 is connected to the first resistor group RS1, and the second switch K2 is connected to the second resistor group RS2;

[0076] The CPU is used for controlling the second switch K2 to switch to the corresponding resistance channel of the second resistance group RS2 according to the target current value; and controlling the first switch K1 to switch to the corresponding resistance channel of the first resistance group RS1.

[0077] In the present application, the CPU first controls the first switch to switch to the resistance channel of the first resistor group corresponding to the preset resistance value according to the preset resistance value; wherein the first resistor group includes multiple resistors with different resistance values; obtains the voltage between the first current limiting switch and the second switch, and determines the target resistance value according to the ratio of the voltage to the target current value; controls the second switch to switch to the resistance channel of the second resistor group corresponding to the target resistance value; delays the preset time, and the CPU obtains the voltage value between the first current limiting switch and the second switch.

[0078] If the voltage value is 0, the first switch is controlled to switch to a resistance channel of the first resistance group with a resistance value one level higher, and then a preset time is delayed, and the CPU obtains the voltage value between the first current limiting switch and the second switch; if the voltage value is 0, the first switch is controlled to switch to a resistance channel of the first resistance group with a resistance value one level higher, until the voltage value is not 0, at which time the first switch is controlled to switch to a resistance channel of the current resistance channel with a resistance value one level lower.

[0079] If the voltage value is not 0, the first switch is controlled to switch to the resistance channel of the first resistor group with a smaller resistance value, and then the preset time is delayed, and the CPU obtains the voltage value between the first current limiting switch and the second switch; if the voltage value is not 0, the first switch is controlled to switch to the resistance channel of the first resistor group with a smaller resistance value until the voltage value is 0.

[0080] After calibration through the mechanism of the present application, there will be an optimal current limiting resistance value. The goal of this optimal current limiting resistance setting value is to make the current limiting switch just limit the current. If the resistance value is set one level lower, the current limiting switch cannot limit the current. This improves the accuracy of explosion-proof current limiting.

[0081] The present application provides an explosion-proof terminal. Compared with the explosion-proof terminal of the prior art that only connects a fuse and a current limiting switch in series, the present application adds a first switch, a second switch, a first resistor group and a second resistor group in the explosion-proof terminal. In addition, the first fuse is connected to the first power supply and the first current limiting switch respectively; the first current limiting switch is connected to the CPU, the first switch and the second switch respectively; the CPU is connected to the first switch and the second switch respectively; the first switch is connected to the first resistor group, and the second switch is connected to the second resistor group; the CPU is used to control the second switch to switch to the corresponding resistor channel of the second resistor group according to the target current value; control the first switch to switch to the corresponding resistor channel of the first resistor group. Through the explosion-proof terminal of the present application, the current limiting value can be adjusted to be closer to the target current value, and the current limiting accuracy setting of the current limiting switch is improved. This makes it easier to select fuse devices, the fuse breaking current can also be closer to the current limiting value of the current limiting switch, and the explosion-proof design scheme is more rigorous. The accuracy of explosion-proof current limiting is improved.

[0082] Figure 2 This is a schematic diagram of the second explosion-proof terminal structure provided in the present application, wherein the explosion-proof terminal further includes: a second fuse F2, a second current limiting switch S2 and a third switch K3;

[0083] The power supply end of the first power supply U1 is respectively connected to the first end of the first fuse F1 and the first end of the second fuse F2; the second end of the first fuse F1 is connected to the first end of the first current limiting switch S1; the second end of the second fuse F2 is connected to the first end of the second current limiting switch S2; the second end of the first current limiting switch S1 is connected to the power receiving end of the CPU, and the control end of the CPU is respectively connected to the first ends of the first switch K1, the second switch K2 and the third switch K3; the second end of the second current limiting switch S2 is respectively connected to the second end of the third switch K3 and the analog-to-digital conversion ADC sampling end of the CPU; the third end of the second current limiting switch S2 is connected to the second end of the first switch K1; the third end of the first switch K1 is connected to the first resistor group RS1; the third end of the third switch K3 is connected to the second end of the second switch K2; the third end of the second switch K2 is connected to the second resistor group RS2.

[0084] In the present application, according to a preset resistance value, the first switch is controlled to switch to a resistance channel of the first resistance group corresponding to the preset resistance value; wherein the first resistance group includes a plurality of resistors with different resistance values; the third switch is controlled to switch to a conduction direction of the second switch; the target resistance value is determined according to the voltage at the second end of the second current limiting switch and the target current value; the second switch is controlled to switch to a resistance channel of the second resistance group corresponding to the target resistance value; and a preset time is delayed to obtain the voltage value of the second end of the third switch through the ADC sampling end.

[0085] If the voltage value is 0, the first switch is controlled to switch to a resistance channel of the first resistance group with a resistance value one gear larger, and then a preset time is delayed, and the CPU obtains the voltage value of the second end of the third switch; if the voltage value is 0, the first switch is controlled to switch to a resistance channel of the first resistance group with a resistance value one gear larger, until the voltage value is not 0, and the first switch is controlled to switch to a resistance channel of the current resistance channel with a resistance value one gear smaller;

[0086] If the voltage value is not 0, the first switch is controlled to switch to a resistance channel of the first resistor group with a resistance value one level smaller, and then a preset time is delayed, and the CPU obtains the voltage value of the second end of the third switch; if the voltage value is not 0, the first switch is controlled to switch to a resistance channel of the first resistor group with a resistance value one level smaller, until the voltage value is 0.

[0087] After calibration through the mechanism of the present application, there will be an optimal current limiting resistance value. The goal of this optimal current limiting resistance setting value is to make the current limiting switch just limit the current. If the resistance value is set one level lower, the current limiting switch cannot limit the current. This improves the accuracy of explosion-proof current limiting.

[0088] Figure 3 A schematic diagram of the structure of a third explosion-proof terminal provided in the present application, wherein the explosion-proof terminal further comprises: a second power supply U2;

[0089] The second end of the first current limiting switch S1 is connected to the power receiving end of the second power source U2 , and the power supply end of the second power source U2 is connected to the power receiving end of the CPU.

[0090] In the present application, by connecting a second power supply between the second end of the first current limiting switch and the power receiving end of the CPU, the second power supply supplies power to the CPU, thereby realizing power grouping of the CPU. At a certain fixed voltage, the capacitance allowed to be mounted is limited, and the grouping is performed by current limiting, so that the total capacitance allowed to be mounted on the whole machine is larger, and the functions and performance of the terminal equipment can be guaranteed on the basis of meeting the explosion-proof standards.

[0091] Figure 4 A schematic diagram of the fourth explosion-proof terminal structure provided in the present application, wherein the explosion-proof terminal further comprises: a power management unit PMU and a memory;

[0092] The power supply end of the second power supply U2 is connected to the power receiving end of the PMU and the memory respectively.

[0093] The first power supply supplies power to the second power supply, and the second power supply supplies power to the PMU and the memory.

[0094] Figure 5 The fifth explosion-proof terminal structure schematic diagram provided in the present application further includes: a third power supply U3 and a peripheral unit; wherein the peripheral unit includes at least one of a display screen, a sound card, a handset, a microphone, and a camera;

[0095] The third end of the third switch K3 is connected to the power receiving end of the third power source U3 , and the power supply end of the third power source U3 is connected to the power receiving end of the peripheral unit.

[0096] In the present application, by connecting a third power supply between the third end of the third switch and the power receiving end of the peripheral unit, the third power supply supplies power to the peripheral unit, thereby realizing the power grouping of the peripheral unit. At a certain fixed voltage, the capacitance allowed to be mounted is limited, and the grouping is performed by current limiting, so that the total capacitance allowed to be mounted on the whole machine is larger, and the functions and performance of the terminal device can be guaranteed on the basis of meeting the explosion-proof standards.

[0097] Figure 6 This is a structural schematic diagram of a second switch and a third switch provided in the present application, wherein the third switch comprises: a first MOS tube M1;

[0098] The control end of the CPU is connected to the gate of the first MOS tube M1; the second end of the second current limiting switch S2 is connected to the source of the first MOS tube M1; the drain of the first MOS tube M1 is respectively connected to the power receiving end of the third power supply U3 and the second end of the second switch K2.

[0099] In the present application, the first MOS tube can be used as the third switch to realize the control switching function of the third switch. When the CPU inputs a low level to the gate of the first MOS tube, the first MOS tube is disconnected, and when the CPU inputs a high level to the gate of the first MOS tube, the first MOS tube is turned on. Thus, the accuracy of explosion-proof current limiting control is improved.

[0100] like Figure 6 As shown, the second switch includes: at least one second MOS tube M2;

[0101] The control end of the CPU is connected to the gate of the at least one second MOS tube M2; the drain of the first MOS tube M1 is respectively connected to the source of the at least one second MOS tube M2; the drain of the at least one second MOS tube M2 is connected to the corresponding resistor in the second resistor group RS2.

[0102] In the present application, at least one second MOS tube can be used as the second switch. The number of second MOS tubes is the same as the number of resistors included in the second resistor group, and each second MOS tube corresponds to a resistor in the second resistor group. The second MOS tube acts as a second switch to realize the control switching function of the second switch. When the CPU inputs a low level to the gate of the second MOS tube, the second MOS tube is disconnected, and when the CPU inputs a high level to the gate of the second MOS tube, the second MOS tube is turned on. Thereby improving the accuracy of explosion-proof current limiting control. It should be noted that Figure 6 In the figure, the second resistor group includes three resistors and the second switch includes three second MOS tubes M2. This application does not limit the number of resistors included in the second resistor group and the number of second MOS tubes M2 included in the second switch.

[0103] Figure 7 The sixth explosion-proof terminal structure schematic diagram provided in the present application, the second current limiting switch S2 includes: an operational amplifier comparator Q and a third MOS tube M3;

[0104] The second end of the second fuse F2 is respectively connected to the inverting input end of the operational amplifier comparator Q, the source of the third MOS tube M3 and the first resistor group RS1; the output end of the operational amplifier comparator Q is connected to the gate of the third MOS tube M3; the drain of the third MOS tube M3 is respectively connected to the first end of the third switch K3 and the ADC sampling end of the CPU; the positive input end of the operational amplifier comparator Q is connected to the first resistor group RS1.

[0105] like Figure 7 As shown, the explosion-proof terminal also includes: a first resistor R1 and a second resistor R2;

[0106] The second end of the second fuse F2 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is connected to the inverting input end of the operational amplifier comparator Q and the source of the third MOS tube M3 respectively;

[0107] The positive input terminal of the operational amplifier comparator Q is connected to the first end of the second resistor R2; the second end of the second resistor R2 is grounded.

[0108] In the present application, an operational amplifier comparator and a third MOS tube are used to realize the function of the second current limiting switch. The CPU controls the first switch to select different set resistance values ​​in the first resistor group. Different set resistance values ​​form different current limiting values ​​together with the operational amplifier comparator. The operational amplifier comparator outputs high and low levels to control the conduction and disconnection of the third MOS tube, thereby realizing the current limiting function. Among them, the first resistor can be a sampling resistor, and the second resistor can be a comparison resistor.

[0109] Figure 8 The explosion-proof control process schematic diagram provided for this application is applied to the central processing unit CPU and includes the following steps:

[0110] S101: according to a preset resistance value, controlling a first switch to switch to a resistance channel of the first resistance group corresponding to the preset resistance value; wherein the first resistance group includes a plurality of resistors with different resistance values;

[0111] S102: Control the third switch to switch to the conducting direction of the second switch; determine a target resistance value according to the voltage at the second end of the second current limiting switch and the target current value; control the second switch to switch to a resistance channel of the second resistor group corresponding to the target resistance value;

[0112] S103: Delaying a preset time, and acquiring a voltage value of the second end of the third switch through an ADC sampling end;

[0113] S104: if the voltage value is 0, control the first switch to switch to a resistance channel of the first resistor group with a larger resistance value, until the voltage value is not 0, control the first switch to switch to a resistance channel of the current resistance channel with a smaller resistance value;

[0114] S105: If the voltage value is not 0, control the first switch to switch to a resistance channel of the first resistor group with a resistance value one level smaller, until the voltage value is 0.

[0115] The traditional explosion-proof solution uses a voltage regulator to limit the backlight output voltage and a fuse to limit the current on the backlight input power supply. Circuit boards using fuses are easily damaged by transient currents during factory production. Hard damage requires the entire machine to be returned to the factory for repair, which causes great losses to the manufacturer. In this application, the input power supply of the explosion-proof terminal system is divided into two parts, one part is used to power the minimum system of the explosion-proof terminal platform, and the other part is used to power the peripheral units of the explosion-proof terminal. The minimum system of the explosion-proof terminal platform includes CPU, PMU and memory, etc. The peripheral units include display screen, sound card, earpiece, microphone, camera, etc. Both power supplies are connected in series with a current limiting switch circuit outside the fuse, and these two switches can be cut off first before the fuse is damaged to protect the fuse. It should be noted that this application is not limited to dividing the explosion-proof terminal input power supply into two groups, but can be three or more groups, such as one group of speaker drive circuits and one group of intercom modules; this application is not limited to grouping the system input power supply, but can also group other sub-power supplies. The reason for grouping is: at a certain fixed voltage, the capacitance allowed to be mounted is limited. By grouping by current limiting, the total capacitance allowed to be mounted on the whole machine is larger, and the functions and performance of the mobile phone can be guaranteed while meeting the explosion-proof standards.

[0116] This application can detect and compare the current limit value of the current limit switch of the peripheral unit, and finally adjust the current limit value to be closer to the target current value I0 through the algorithm, thereby improving the current limit accuracy setting of the current limit switch. This makes it easier to select fuse components, the fuse breaking current can be closer to the current limit value of the current limit switch, and the explosion-proof design scheme is more rigorous.

[0117] In the present application, the first current limiting switch and the second current limiting switch are both commonly used in the market to set the current limit size by externally setting the resistance value, and the accuracy is generally low. The current limit value fluctuation range is generally ±10% or ±15%, which is relatively wide. For example, the current limiting switch can be SGM2593D of Shengbang Microelectronics, and its current limit range can be set from 0.1A to 3A. The current limit value is equal to 6800 divided by the current limit resistance value. The current limit value is inversely proportional to the current limit resistance, that is, the larger the current limit resistance value, the smaller the current limit value, and the smaller the current limit resistance value, the larger the current limit value.

[0118] The second power supply can convert the system power input from the first power supply into various power supplies required by the minimum system of the platform. The third switch is used to switch whether to supply power to the third power supply or to the second switch. The third switch belongs to all-in-one, and the CPU controls the switching direction through GPIO1. The third power supply converts the system power input from the first power supply into various power supplies for powering the terminal peripherals; the second switch switches the input system power supply to the paths corresponding to the various resistance values ​​in the different second resistor groups, which belongs to all-in-one, and the CPU controls the switching direction through GPIO20, GPIO21, GPIO22, etc. of the GPIO2 series. The first switch belongs to all-in-one, which is used to switch different current limiting resistor values ​​in the first resistor group. The CPU controls the switching direction through GPIO30, GPIO31, GPIO32, etc. of the GPIO3 series. The CPU samples the voltage at the output of the second current limiting switch, that is, the input of the third switch, through the ADC channel of the PMU to determine whether it is 0, that is, to determine whether the second current limiting switch is cut off. If it is 0, it is cut off, and if it is not 0, there is no current limiting cut off.

[0119] The precise current limiting calibration mechanism of the second current limiting switch is as follows:

[0120] When current limiting calibration is required, first, according to the preset resistance value Rn, the CPU switches the first switch to the corresponding resistance value channel through the GPIO3 series, so that the second current limiting switch is set with an initial current limiting value. The CPU controls the third switch to switch to the conduction direction of the second switch through GPIO1. According to the target current value I0 to be limited, the CPU switches the second switch to the discharge resistance value channel corresponding to the second resistor group through the GPIO2 series, and the corresponding resistance value is approximately equal to the system voltage divided by the current limiting target value I0. After a delay of a period of time T0, the CPU detects whether the output of the second current limiting switch is 0 through the ADC channel. This T0 covers the time from the start of the current limiting to the cut-off output of the second current limiting switch. Regardless of whether it is 0 or not, the discharge resistance value corresponding to the second switch will not be adjusted subsequently. Subsequently, the first switch is tried to switch to different setting resistances in a step-by-step manner to obtain the best setting resistance value. For different individuals of the same terminal, after calibration through the mechanism of the present application scheme, there will be an optimal current limiting resistance value in the end. The goal of this optimal current limiting resistor setting value is to make the current limiting switch just limit the current. If the resistance value is set one level smaller, the current limiting switch will not be able to limit the current.

[0121] In the present application, the second switch and the third switch can be combined, or a MOS tube can be used as a switch, that is, the third switch is a MOS tube in the direction of the third power supply, and the switch is controlled by GPIO1. The second switch is a series of MOS tubes with different bleeder resistors connected in series, and the conduction and disconnection of these MOS tubes are controlled by the GPIO2 series. When the GPIO output is a low level, the corresponding MOS tube is disconnected, and when the GPIO output is a high level, the corresponding MOS tube is turned on. The second switch can also have only one MOS tube plus a bleeder resistor, so that the bleeder resistor values ​​of the chips are different for peripheral units with different power consumption requirements.

[0122] The three electrodes of a MOS tube are the gate, drain, and source. The gate is the control electrode that controls the current flow between the drain and source by applying a gate voltage. The source is the input terminal that provides current to the MOS tube. The drain is the output terminal that is responsible for receiving or outputting current.

[0123] In the present application, the second current limiting switch can be a solution of a MOS tube plus an op amp comparator. The CPU selects different setting resistance values ​​through the GPIO3 series control. Different setting resistance values ​​together with the op amp comparator form different current limiting values. The op amp comparator outputs high and low levels to control the conduction and cutoff of the MOS tube, thereby realizing the current limiting function.

[0124] Fig. 9 The detailed flow chart of explosion-proof control provided for this application is as follows: Fig. 9 As shown, according to the preset resistance value Rn, the CPU controls the GPIO3 series to switch the first switch to the corresponding resistance setting channel; the CPU switches the third switch to the conduction direction of the second switch through GPIO1; according to the target current value I0, the CPU controls the GPIO2 series to switch the second switch to the corresponding current discharge channel; after a delay of a period of time T0, the CPU reads whether the input voltage of the third switch is 0 through the ADC channel of the PMU.

[0125] If the input voltage of the third switch is 0, the CPU controls the GPIO3 series to switch the first switch to Rn+1, which is the next higher gear next to Rn; after a delay of T0, the CPU reads whether the input voltage of the third switch is 0 through the ADC channel of the PMU; if the input voltage of the third switch is 0, the CPU controls the GPIO3 series to switch the first switch to Rn+2, which is the next higher gear next to Rn+1; after a delay of T0, the CPU reads whether the input voltage of the third switch is 0 through the ADC channel of the PMU. If so, and so on, the CPU controls the GPIO3 series to switch the first switch to Rn+m+1, which is the next higher gear next to Rn+m; after a delay of T0, the CPU reads that the input voltage of the third switch is not 0 through the ADC channel of the PMU; at this time, the CPU controls the GPIO3 series to switch the first switch to Rn+m; the process ends.

[0126] If the input voltage of the third switch is not 0, the CPU controls the GPIO3 series to switch the first switch to the smaller gear Rn-1 next to Rn; after a delay of T0, the CPU reads whether the input voltage of the third switch is 0 through the ADC channel of the PMU; if the input voltage of the third switch is not 0, the CPU controls the GPIO3 series to switch the first switch to the smaller gear Rn-2 next to Rn-1; after a delay of T0, the CPU reads whether the input voltage of the third switch is 0 through the ADC channel of the PMU. If not, and so on, the CPU controls the GPIO3 series to switch the first switch to the smaller gear Rn-x next to Rn-x+1; after a delay of T0, the CPU reads the input voltage of the third switch through the ADC channel of the PMU as 0; at this time, the CPU controls the GPIO3 series to switch the first switch to Rn-x; the process ends.

[0127] Fig.10 The schematic diagram of the explosion-proof control device structure based on the explosion-proof terminal provided in this application is applied to the central processing unit CPU, and the device includes:

[0128] The first control module 11 is used to control the first switch to switch to the resistance channel of the first resistor group corresponding to the preset resistance value according to the preset resistance value; wherein the first resistor group includes a plurality of resistors with different resistance values;

[0129] The second control module 12 is used to control the third switch to switch to the conducting direction of the second switch; determine the target resistance value according to the voltage at the second end of the second current limiting switch and the target current value; and control the second switch to switch to the resistance channel of the second resistor group corresponding to the target resistance value;

[0130] An acquisition module 13, used for delaying a preset time and acquiring a voltage value of the second end of the third switch through an ADC sampling end;

[0131] A third control module 14 is configured to control the first switch to switch to a resistance channel with a larger resistance value of the first resistor group if the voltage value is 0, and control the first switch to switch to a resistance channel with a smaller resistance value of the current resistance channel if the voltage value is not 0;

[0132] The third control module 14 is further configured to control the first switch to switch to a resistance channel of the first resistor group with a smaller resistance value if the voltage value is not 0, until the voltage value is 0.

[0133] The present application also provides an electronic device, which is, for example, a CPU. Fig.11 As shown, it includes: a processor 21, a communication interface 22, a memory 23 and a communication bus 24, wherein the processor 21, the communication interface 22, and the memory 23 communicate with each other through the communication bus 24;

[0134] The memory 23 stores a computer program, and when the program is executed by the processor 21, the processor 21 executes any one of the above method steps.

[0135] The communication bus mentioned in the above electronic device can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0136] The communication interface 22 is used for communication between the above electronic device and other devices.

[0137] The memory may include a random access memory (RAM) or a non-volatile memory (NVM), such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0138] The above-mentioned processor can be a general-purpose processor, including a central processing unit, a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, etc.

[0139] The present application also provides a computer storage readable storage medium, wherein the computer readable storage medium stores a computer program executable by an electronic device, and when the program runs on the electronic device, the electronic device implements any of the above method steps when executing.

[0140] The present application provides a computer program product, wherein the computer program product comprises an executable program, and when the executable program is executed by a processor, the method described above is implemented.

[0141] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0142] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. An explosion-proof terminal, characterized in that: The explosion-proof terminal comprises: a first power supply, a first fuse, a first current limiting switch, a first switch, a second switch, a central processing unit CPU, a first resistor group and a second resistor group; The first fuse is connected to the first power supply and the first current limiting switch respectively; the first current limiting switch is connected to the CPU, the first switch and the second switch respectively; the CPU is connected to the first switch and the second switch respectively; the first switch is connected to the first resistor group, and the second switch is connected to the second resistor group; The CPU is used to control the second switch to switch to the corresponding resistance channel of the second resistance group according to the target current value; and control the first switch to switch to the corresponding resistance channel of the first resistance group.

2. The explosion-proof terminal according to claim 1, characterized in that: The explosion-proof terminal also includes: a second fuse, a second current limiting switch and a third switch; The power supply end of the first power supply is respectively connected to the first end of the first fuse and the first end of the second fuse; the second end of the first fuse is connected to the first end of the first current limiting switch; the second end of the second fuse is connected to the first end of the second current limiting switch; the second end of the first current limiting switch is connected to the power receiving end of the CPU, and the control end of the CPU is respectively connected to the first ends of the first switch, the second switch and the third switch; the second end of the second current limiting switch is respectively connected to the second end of the third switch and the analog-to-digital conversion ADC sampling end of the CPU; the third end of the second current limiting switch is connected to the second end of the first switch; the third end of the first switch is connected to the first resistor group; the third end of the third switch is connected to the second end of the second switch; the third end of the second switch is connected to the second resistor group.

3. The explosion-proof terminal according to claim 2, characterized in that: The explosion-proof terminal also includes: a second power supply; The second end of the first current limiting switch is connected to the power receiving end of the second power supply, and the power supply end of the second power supply is connected to the power receiving end of the CPU.

4. The explosion-proof terminal according to claim 3, characterized in that: The explosion-proof terminal also includes: a power management unit PMU and a memory; The power supply end of the second power supply is connected to the power receiving end of the PMU and the memory respectively.

5. The explosion-proof terminal according to claim 2, characterized in that: The explosion-proof terminal further includes: a third power supply and a peripheral unit; wherein the peripheral unit includes at least one of a display screen, a sound card, a receiver, a microphone, and a camera; The third end of the third switch is connected to the power receiving end of the third power supply, and the power supply end of the third power supply is connected to the power receiving end of the peripheral unit.

6. The explosion-proof terminal according to claim 5, characterized in that: The third switch comprises: a first MOS tube; The control end of the CPU is connected to the gate of the first MOS tube; the second end of the second current limiting switch is connected to the source of the first MOS tube; the drain of the first MOS tube is respectively connected to the power receiving end of the third power supply and the second end of the second switch.

7. The explosion-proof terminal according to claim 6, characterized in that: The second switch includes: at least one second MOS tube; The control end of the CPU is connected to the gate of the at least one second MOS tube; the drain of the first MOS tube is respectively connected to the source of the at least one second MOS tube; the drain of the at least one second MOS tube is connected to the corresponding resistor in the second resistor group.

8. The explosion-proof terminal according to claim 1, characterized in that: The second current limiting switch includes: an operational amplifier comparator and a third MOS tube; The second end of the second fuse is respectively connected to the inverting input end of the operational amplifier comparator, the source of the third MOS tube and the first resistor group; the output end of the operational amplifier comparator is connected to the gate of the third MOS tube; the drain of the third MOS tube is respectively connected to the first end of the third switch and the ADC sampling end of the CPU; the positive input end of the operational amplifier comparator is connected to the first resistor group.

9. The explosion-proof terminal according to claim 8, characterized in that: The explosion-proof terminal further comprises: a first resistor and a second resistor; The second end of the second fuse is connected to the first end of the first resistor, and the second end of the first resistor is connected to the inverting input end of the operational amplifier comparator and the source of the third MOS tube respectively; The positive input terminal of the operational amplifier comparator is connected to the first terminal of the second resistor; and the second terminal of the second resistor is grounded.

10. An explosion-proof control method for an explosion-proof terminal according to any one of claims 2 to 9, applied to a central processing unit (CPU), characterized in that: The method comprises: According to a preset resistance value, controlling the first switch to switch to a resistance channel of the first resistance group corresponding to the preset resistance value; wherein the first resistance group includes a plurality of resistors with different resistance values; Controlling the third switch to switch to the conducting direction of the second switch; determining a target resistance value according to the voltage at the second end of the second current limiting switch and the target current value; controlling the second switch to switch to a resistance channel of the second resistor group corresponding to the target resistance value; Delaying a preset time, and acquiring a voltage value of the second end of the third switch through an ADC sampling end; If the voltage value is 0, control the first switch to switch to a resistance channel of the first resistor group with a larger resistance value, until the voltage value is not 0, control the first switch to switch to a resistance channel of the current resistance channel with a smaller resistance value; If the voltage value is not 0, the first switch is controlled to switch to a resistance channel of the first resistor group with a resistance value one level smaller than that of the first resistor group until the voltage value is 0.

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