Input Control Method

Abstract

The present invention provides an input control method. First, the maximum values ​​of the input voltage and output voltage of an energy recovery system are set. Next, an input voltage equal to the maximum value is input to the energy recovery system, and the input power is controlled to increase gradually by a fixed amount starting from 0 to calculate the first maximum duty cycle of a main control signal corresponding to the input power when the output voltage is equal to the maximum value. Thereafter, the input power is controlled to increase gradually by a fixed amount starting from 0, and the input voltage is controlled to decrease gradually by a fixed amount starting from the maximum value to calculate the second maximum duty cycle of the main control signal corresponding to the input power and input voltage when the output voltage is equal to the maximum value. Finally, multiple duty cycle and input power curves corresponding to different input voltages are generated based on the calculation results, and the energy recovery system is controlled accordingly.

Description

Technical Field

[0001] The present invention relates to a control method, and in particular to an input control method. Background Art

[0002] Traditional boost converters have a simple architecture. To recycle power back into the grid, a single-phase inverter with a 220V AC input typically outputs a DC link voltage of 380V or higher. Therefore, the preceding DC voltage converter must be able to boost the voltage to greater than 380V to enable power recovery.

[0003] Existing energy recovery systems are designed with a DC link voltage between 400 and 525 volts, regulated over an input DC voltage range of 40 to 60 volts. The first-stage full-bridge voltage conversion circuit employs open-loop control with a fixed duty cycle. To reduce input current ripple and stabilize the DC link voltage, the second-stage DC buck-boost converter employs both an outer voltage loop and an inner current loop to achieve constant current and voltage requirements. However, under these fixed current and voltage requirements, the expected output specifications cannot be achieved due to the upper limit of the input voltage. Summary of the Invention

[0004] An object of the present invention is to provide an input control method, which increases the upper limit of the input voltage to achieve the expected output specification.

[0005] An input control method according to an embodiment of the present invention is applied to an energy recovery system. The input control method includes: setting a first maximum input voltage and a second maximum output voltage of the energy recovery system, wherein when the input power of the energy recovery system is zero, the output voltage generated by the energy recovery system receiving the first maximum value, a main control signal, and a conversion control signal is less than or equal to the second maximum value; inputting an input voltage equal to the first maximum value, a main control signal, and a conversion control signal to the energy recovery system, and controlling the input power to increase gradually by a first fixed amount starting from zero to calculate a first maximum duty cycle of the main control signal corresponding to the input power when the output voltage is equal to the second maximum value; inputting an input voltage equal to the first maximum value, a main control signal, and a conversion control signal to the energy recovery system, and controlling the input power to increase gradually by a first fixed amount starting from zero and the input voltage to decrease gradually by a second fixed amount starting from the first maximum value to calculate a second maximum duty cycle of the main control signal corresponding to the input power and the input voltage when the output voltage is equal to the second maximum value; and generating a plurality of duty cycle and input power curves corresponding to different input voltages based on the input voltage, input power, the first maximum duty cycle, and the second maximum duty cycle, and controlling the energy recovery system according to the duty cycle and input power curves.

[0006] In an embodiment of the present invention, an energy recovery system includes a full-bridge isolated DC voltage conversion circuit and a boost converter. The full-bridge isolated DC voltage conversion circuit receives an input voltage, input power, and a main control signal. The boost converter is coupled to the full-bridge isolated DC voltage conversion circuit, receives a conversion control signal, and generates an output voltage.

[0007] In an embodiment of the present invention, a full-bridge isolation-stage DC voltage conversion circuit includes a first field-effect transistor, a second field-effect transistor, a third field-effect transistor, a fourth field-effect transistor, a first transformer, a fifth field-effect transistor, a sixth field-effect transistor, a seventh field-effect transistor, an eighth field-effect transistor, a second transformer, a ninth field-effect transistor, a tenth field-effect transistor, an eleventh field-effect transistor, and a twelfth field-effect transistor. The drain of the second field-effect transistor is coupled to the source of the first field-effect transistor, the drain of the third field-effect transistor is coupled to the drain of the first field-effect transistor, the drain of the fourth field-effect transistor is coupled to the source of the third field-effect transistor, and the source of the fourth field-effect transistor is coupled to the source of the second field-effect transistor. The drains of the first and third field-effect transistors and the sources of the second and fourth field-effect transistors receive an input voltage. One end of the primary side of the first transformer is coupled to the node between the first and second field-effect transistors via a first inductor, and the other end is coupled to the node between the third and fourth field-effect transistors. The drain of the sixth field-effect transistor is coupled to the source of the fifth field-effect transistor, the drain of the seventh field-effect transistor is coupled to the drain of the fifth field-effect transistor, the drain of the eighth field-effect transistor is coupled to the source of the seventh field-effect transistor, and the source of the eighth field-effect transistor is coupled to the source of the sixth field-effect transistor. The drains of the fifth and seventh field-effect transistors and the sources of the sixth and eighth field-effect transistors receive an input voltage. One end of the primary side of the second transformer is coupled to the node between the fifth and sixth field-effect transistors via a second inductor, and the other end is coupled to the node between the seventh and eighth field-effect transistors. The drain of the tenth field-effect transistor is coupled to the source of the ninth field-effect transistor, the drain of the eleventh field-effect transistor is coupled to the drain of the ninth field-effect transistor, the drain of the twelfth field-effect transistor is coupled to the source of the eleventh field-effect transistor, and the source of the twelfth field-effect transistor is coupled to the source of the tenth field-effect transistor. One end of the secondary side of the first transformer is coupled to one end of the secondary side of the second transformer. The other end of the secondary side of the first transformer is coupled to a node between the ninth field-effect transistor and the tenth field-effect transistor. The other end of the secondary side of the second transformer is coupled to a node between the eleventh field-effect transistor and the twelfth field-effect transistor. Gates of the first field-effect transistor, the second field-effect transistor, the third field-effect transistor, the fourth field-effect transistor, the fifth field-effect transistor, the sixth field-effect transistor, the seventh field-effect transistor, the eighth field-effect transistor, the ninth field-effect transistor, the tenth field-effect transistor, the eleventh field-effect transistor, and the twelfth field-effect transistor respectively receive a main control signal.

[0008] In an embodiment of the present invention, in the step of controlling the energy recovery system according to the multiple duty cycles and input power curves, the first maximum duty cycle and / or the second maximum duty cycle are adjusted to reduce the drain-source voltage of the first field-effect transistor, the second field-effect transistor, the third field-effect transistor, the fourth field-effect transistor, the fifth field-effect transistor, the sixth field-effect transistor, the seventh field-effect transistor, the eighth field-effect transistor, the ninth field-effect transistor, the tenth field-effect transistor, the eleventh field-effect transistor, and the twelfth field-effect transistor to be lower than a default drain-source withstand voltage value. This reduces the number of different slopes of the duty cycle and input power curves, and the energy recovery system is then controlled according to the multiple duty cycles and input power curves.

[0009] In an embodiment of the present invention, the first field effect transistor, the second field effect transistor, the third field effect transistor, the fourth field effect transistor, the fifth field effect transistor, the sixth field effect transistor, the seventh field effect transistor, the eighth field effect transistor, the ninth field effect transistor, the tenth field effect transistor, the eleventh field effect transistor and the twelfth field effect transistor are N-channel metal oxide semiconductor field effect transistors.

[0010] In an embodiment of the present invention, a boost converter includes a first capacitor, a thirteenth field-effect transistor, a fourteenth field-effect transistor, and a second capacitor. The first capacitor is coupled between the drain of the eleventh field-effect transistor and the source of the twelfth field-effect transistor. The source of the thirteenth field-effect transistor is coupled to a node between the first capacitor and the drain of the eleventh field-effect transistor via a third inductor. The drain of the fourteenth field-effect transistor is coupled to a node between the third inductor and the source of the thirteenth field-effect transistor. One end of the second capacitor is coupled to the source of the fourteenth field-effect transistor, and the other end is coupled to the drain of the thirteenth field-effect transistor. The second capacitor outputs the output voltage, and the gates of the thirteenth and fourteenth field-effect transistors receive a conversion control signal.

[0011] In the embodiment of the present invention, the thirteenth field effect transistor and the fourteenth field effect transistor are N-channel insulated gate bipolar transistors.

[0012] In an embodiment of the present invention, the second maximum value is less than or equal to a withstand voltage value of the second capacitor.

[0013] In the embodiment of the present invention, when the thirteenth field effect transistor is in the on state, the fourteenth field effect transistor is in the off state. When the fourteenth field effect transistor is in the on state, the thirteenth field effect transistor is in the off state.

[0014] In an embodiment of the present invention, the first field-effect transistor, the fourth field-effect transistor, the fifth field-effect transistor, the eighth field-effect transistor, the ninth field-effect transistor, and the twelfth field-effect transistor all receive the same main control signal. The second field-effect transistor, the third field-effect transistor, the sixth field-effect transistor, the seventh field-effect transistor, the tenth field-effect transistor, and the eleventh field-effect transistor all receive the same main control signal. When the first field-effect transistor, the fourth field-effect transistor, the fifth field-effect transistor, the eighth field-effect transistor, the ninth field-effect transistor, and the twelfth field-effect transistor are in the on state, the second field-effect transistor, the third field-effect transistor, the sixth field-effect transistor, the seventh field-effect transistor, the tenth field-effect transistor, and the eleventh field-effect transistor are in the off state. When the second field-effect transistor, the third field-effect transistor, the sixth field-effect transistor, the seventh field-effect transistor, the tenth field-effect transistor, and the eleventh field-effect transistor are in the on state, the first field-effect transistor, the fourth field-effect transistor, the fifth field-effect transistor, the eighth field-effect transistor, the ninth field-effect transistor, and the twelfth field-effect transistor are in the off state.

[0015] Based on the above, the input control method creates a table for the duty cycle of the main control signal according to the input power and input voltage to increase the upper limit of the input voltage to achieve the expected output specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to further understand and appreciate the structural features and effects achieved by the present invention, the embodiments of the present invention are described below with reference to the accompanying drawings:

[0017] Figure 1 FIG. 4 is a schematic diagram of an energy recovery system according to an embodiment of the present invention.

[0018] Figure 2 FIG. 4 is a flow chart of an input control method according to an embodiment of the present invention.

[0019] Figure 3 FIG. 4 is a waveform diagram of a main control signal and a conversion control signal according to an embodiment of the present invention.

[0020] Figure 4 FIG. 4 is a schematic diagram of a duty cycle and input power curve according to an embodiment of the present invention.

[0021] Reference numerals:

[0022] 1: Energy recovery system

[0023] 10: Full-bridge isolation level DC voltage conversion circuit

[0024] 11: Boost Converter

[0025] 12: Signal Controller

[0026] B: Battery

[0027] S1, S2: main control signal

[0028] S3, S4: conversion control signal

[0029] Vo: output voltage

[0030] T1: First field effect transistor

[0031] T2: Second field effect transistor

[0032] T3: The third field effect transistor

[0033] T4: The fourth field effect transistor

[0034] T5: Fifth field effect transistor

[0035] T6: Sixth field effect transistor

[0036] T7: Seventh Field Effect Transistor

[0037] T8: Eighth Field Effect Transistor

[0038] T9: Ninth Field Effect Transistor

[0039] T10: Tenth Field Effect Transistor

[0040] T11: Eleventh Field Effect Transistor

[0041] T12: twelfth field effect transistor

[0042] T13: Thirteenth Field Effect Transistor

[0043] T14: Fourteenth field effect transistor

[0044] F1: First transformer

[0045] F2: Second transformer

[0046] L1: First inductor

[0047] L2: Second inductor

[0048] C1: First capacitor

[0049] C2: Second capacitor

[0050] S10, S12, S14, S16: Steps DETAILED DESCRIPTION

[0051] The embodiments of the present invention are further explained below with reference to the accompanying drawings. Whenever possible, identical reference numerals will be used throughout the drawings and the specification to represent identical or similar components. In the drawings, shapes and thicknesses may be exaggerated for simplicity and convenience. It should be understood that components not specifically shown in the drawings or described in the specification are known to those skilled in the art. Those skilled in the art may make various changes and modifications based on the disclosure of the present invention.

[0052] Unless otherwise specified, conditional clauses or words such as "may," "might," "might," or "could" are generally intended to convey that an embodiment of the present invention has features, components, or steps, but may also be interpreted as not being required. In other embodiments, these features, components, or steps may not be required.

[0053] The following description of "one embodiment" or "an embodiment" refers to a specific component, structure, or feature associated with at least one embodiment. Therefore, multiple references to "one embodiment" or "an embodiment" in various places below do not necessarily refer to the same embodiment. Furthermore, specific components, structures, and features in one or more embodiments may be combined in any suitable manner.

[0054] Certain words are used in this application to refer to specific components. However, it should be understood by those skilled in the art that the same component may be referred to by different nouns. This application does not use the difference in name as a way to distinguish components, but uses the difference in function of the components as the basis for distinction. The "including" mentioned in this application is an open term, so it should be interpreted as "including but not limited to". In addition, "coupling" here includes any direct and indirect connection means. Therefore, if the text describes that the main component is coupled to the slave component, it means that the main component can be directly connected to the slave component through electrical connection or wireless transmission, optical transmission and other signal connection methods, or indirectly electrically or signal connected to the slave component through other components or connection means.

[0055] The present application is described below based on examples. These examples are intended to be illustrative only. Those skilled in the art will readily appreciate that various modifications and variations can be made without departing from the spirit and scope of the present invention. Therefore, the scope of the following embodiments shall be determined by the claims. Throughout this application, unless the context clearly dictates otherwise, the meanings of "a," "an," and "the" encompass such references as include "one or at least one" of the components or ingredients. Furthermore, as used in the present invention, the singular article includes references to plural components or ingredients unless the context clearly dictates otherwise. Furthermore, as used in this description and in the claims, the meaning of "wherein" includes "wherein" and "on therein" unless the context clearly dictates otherwise. Terms used in this application, unless otherwise noted, generally have their ordinary meanings as used in the art, within the context of this disclosure, and in the specific context. Certain terms used to describe the present invention are discussed below and elsewhere in this specification to provide practitioners with additional guidance regarding the description of the present invention. The use of examples anywhere throughout the specification, including examples of any term discussed herein, is for illustrative purposes only and certainly does not limit the scope and meaning of the embodiments of the present invention or any term used in the embodiments. Similarly, the embodiments of the present invention are not limited to the various embodiments set forth in this specification.

[0056] The input control method of the embodiment of the present invention creates a table for the duty cycle of the main control signal according to the input power and the input voltage, so as to increase the upper limit of the input voltage to achieve the expected output specification.

[0057] Figure 1 is a schematic diagram of an energy recovery system according to an embodiment of the present invention, Figure 2 FIG is a flow chart of an input control method according to an embodiment of the present invention. Figure 1 and Figure 2 The following describes the input control method of the present invention, which is applied to an energy recovery system 1. The energy recovery system 1 includes a full-bridge isolation-level DC voltage conversion circuit 10, a boost converter 11, and a signal controller 12. The signal controller 12 is coupled to the full-bridge isolation-level DC voltage conversion circuit 10 and the boost converter 11. The full-bridge isolation-level DC voltage conversion circuit 10 is coupled to the battery B, and the boost converter 11 is coupled to the full-bridge isolation-level DC voltage conversion circuit 10. Battery B provides the input voltage and input power of the energy recovery system 1. The signal controller 12 generates main control signals S1 and S2 and conversion control signals S3 and S4. The full-bridge isolation-level DC voltage conversion circuit 10 receives the input voltage, input power, and main control signals S1 and S2. The boost converter 11 receives the conversion control signals S3 and S4 and generates an output voltage Vo.

[0058] In certain embodiments of the present invention, a full-bridge isolated DC voltage converter circuit 10 may include a first field-effect transistor T1, a second field-effect transistor T2, a third field-effect transistor T3, a fourth field-effect transistor T4, a first transformer F1, a fifth field-effect transistor T5, a sixth field-effect transistor T6, a seventh field-effect transistor T7, an eighth field-effect transistor T8, a second transformer F2, a ninth field-effect transistor T9, a tenth field-effect transistor T10, an eleventh field-effect transistor T11, and a twelfth field-effect transistor T12. The first field-effect transistor T1, the second field-effect transistor T2, the third field-effect transistor T3, the fourth field-effect transistor T4, the fifth field-effect transistor T5, the sixth field-effect transistor T6, the seventh field-effect transistor T7, the eighth field-effect transistor T8, the ninth field-effect transistor T9, the tenth field-effect transistor T10, the eleventh field-effect transistor T11, and the twelfth field-effect transistor T12 may be, but are not limited to, N-channel metal-oxide-semiconductor field-effect transistors. The first field-effect transistor T1, the third field-effect transistor T3, the fifth field-effect transistor T5, and the seventh field-effect transistor T7 are coupled to the positive electrode of the battery B, and the second field-effect transistor T2, the fourth field-effect transistor T4, the sixth field-effect transistor T6, and the eighth field-effect transistor T8 are coupled to the negative electrode of the battery B. The gates of the first field-effect transistor T1, the second field-effect transistor T2, the third field-effect transistor T3, the fourth field-effect transistor T4, the fifth field-effect transistor T5, the sixth field-effect transistor T6, the seventh field-effect transistor T7, the eighth field-effect transistor T8, the ninth field-effect transistor T9, the tenth field-effect transistor T10, the eleventh field-effect transistor T11, and the twelfth field-effect transistor T12 are respectively coupled to the signal controller 12. The drain of the second field-effect transistor T2 is coupled to the source of the first field-effect transistor T1, the drain of the third field-effect transistor T3 is coupled to the drain of the first field-effect transistor T1, the drain of the fourth field-effect transistor T4 is coupled to the source of the third field-effect transistor T3, and the source of the fourth field-effect transistor T4 is coupled to the source of the second field-effect transistor T2. The drains of the first field-effect transistor T1 and the third field-effect transistor T3 and the sources of the second field-effect transistor T2 and the fourth field-effect transistor T4 receive the input voltage. One end of the primary side of the first transformer F1 is coupled to the node between the first field-effect transistor T1 and the second field-effect transistor T2 via the first inductor L1, and the other end is coupled to the node between the third field-effect transistor T3 and the fourth field-effect transistor T4. The drain of the sixth field-effect transistor T6 is coupled to the source of the fifth field-effect transistor T5. The drain of the seventh field-effect transistor T7 is coupled to the drain of the fifth field-effect transistor T5. The drain of the eighth field-effect transistor T8 is coupled to the source of the seventh field-effect transistor T7. The source of the eighth field-effect transistor T8 is coupled to the source of the sixth field-effect transistor T6. The drains of the fifth field-effect transistor T5 and the seventh field-effect transistor T7 and the sources of the sixth field-effect transistor T6 and the eighth field-effect transistor T8 receive an input voltage.One end of the primary side of the second transformer F2 is coupled to the node between the fifth field-effect transistor T5 and the sixth field-effect transistor T6 via a second inductor L2, and the other end is coupled to the node between the seventh field-effect transistor T7 and the eighth field-effect transistor T8. The drain of the tenth field-effect transistor T10 is coupled to the source of the ninth field-effect transistor T9, the drain of the eleventh field-effect transistor T11 is coupled to the drain of the ninth field-effect transistor T9, the drain of the twelfth field-effect transistor T12 is coupled to the source of the eleventh field-effect transistor T11, and the source of the twelfth field-effect transistor T12 is coupled to the source of the tenth field-effect transistor T10. One end of the secondary side of the first transformer F1 is coupled to one end of the secondary side of the second transformer F2, the other end of the secondary side of the first transformer F1 is coupled to the node between the ninth field-effect transistor T9 and the tenth field-effect transistor T10, and the other end of the secondary side of the second transformer F2 is coupled to the node between the eleventh field-effect transistor T11 and the twelfth field-effect transistor T12. Gates of the first field effect transistor T1, the second field effect transistor T2, the third field effect transistor T3, the fourth field effect transistor T4, the fifth field effect transistor T5, the sixth field effect transistor T6, the seventh field effect transistor T7, the eighth field effect transistor T8, the ninth field effect transistor T9, the tenth field effect transistor T10, the eleventh field effect transistor T11 and the twelfth field effect transistor T12 receive the main control signals S1 and S2, respectively.

[0059] In certain embodiments of the present invention, the boost converter 11 may include a first capacitor C1, a thirteenth field-effect transistor T13, a fourteenth field-effect transistor T14, and a second capacitor C2. The thirteenth field-effect transistor T13 and the fourteenth field-effect transistor T14 may be, but are not limited to, N-channel insulated gate bipolar transistors. The gates of the thirteenth field-effect transistor T13 and the fourteenth field-effect transistor T14 are respectively coupled to the signal controller 12. The first capacitor C1 is coupled between the drain of the eleventh field-effect transistor T11 and the source of the twelfth field-effect transistor T12. The source of the thirteenth field-effect transistor T13 is coupled to the node between the first capacitor C1 and the drain of the eleventh field-effect transistor T11 via a third inductor L3. The drain of the fourteenth field-effect transistor T14 is coupled to the node between the third inductor L3 and the source of the thirteenth field-effect transistor T13. One end of the second capacitor C2 is coupled to the source of the fourteenth field-effect transistor T14, and the other end is coupled to the drain of the thirteenth field-effect transistor T13. The second capacitor C2 outputs the output voltage Vo. The gates of the thirteenth field effect transistor T13 and the fourteenth field effect transistor T14 receive the switching control signals S3 and S4.

[0060] In the input control method, as shown in step S10, the signal controller 12 sets a first maximum input voltage and a second maximum output voltage Vo of the energy recovery system 1. When the input power of the energy recovery system 1 is zero, the output voltage Vo generated by the energy recovery system 1 receiving the first maximum value, the main control signals S1 and S2, and the conversion control signals S3 and S4 is less than or equal to the second maximum value. When the input power of the energy recovery system 1 is zero, the energy recovery system 1 is not connected to any load. In a preferred embodiment, the second maximum value is less than or equal to the withstand voltage of the second capacitor C2. As shown in step S12, the signal controller 12 and the battery B input an input voltage equal to the first maximum value, the main control signals S1 and S2, and the conversion control signals S3 and S4 to the energy recovery system 1. The signal controller 12 controls the input power to gradually increase by a first fixed amount starting from zero, thereby calculating the first maximum duty cycle of the main control signals S1 and S2 corresponding to the input power when the output voltage Vo is equal to the second maximum value. For example, the first fixed amount may be, but is not limited to, 250 watts. As shown in step S14, the signal controller 12 and the battery B input an input voltage equal to the first maximum value, the main control signals S1 and S2, and the conversion control signals S3 and S4 to the energy recovery system 1, and control the input power to gradually increase by a first fixed amount starting from 0, and the input voltage to gradually decrease by a second fixed amount starting from the first maximum value, so as to calculate the second maximum duty cycle of the main control signals S1 and S2 corresponding to the input power and input voltage when the output voltage Vo is equal to the second maximum value. The second fixed amount can be but is not limited to 1 volt. Finally, as shown in step S16, the signal controller 12 produces multiple duty cycle and input power curves corresponding to different input voltages according to the input voltage, input power, the first maximum duty cycle, and the second maximum duty cycle, and controls the energy recovery system 1 according to the multiple duty cycle and input power curves. If substantially the same result can be obtained, these steps do not have to be followed. Figure 2 To reduce the table lookup burden, in step S16, the signal controller 12 may adjust the first maximum duty cycle and / or the second maximum duty cycle to reduce the drain-source voltage of the first field effect transistor T1, the second field effect transistor T2, the third field effect transistor T3, the fourth field effect transistor T4, the fifth field effect transistor T5, the sixth field effect transistor T6, the seventh field effect transistor T7, the eighth field effect transistor T8, the ninth field effect transistor T9, the tenth field effect transistor T10, the eleventh field effect transistor T11, and the twelfth field effect transistor T12 to be lower than the default drain-source withstand voltage value, thereby reducing the number of different slopes of the duty cycle and input power curves. After each duty cycle and input power curve maintains a fixed slope as much as possible, the energy recovery system 1 is controlled according to the above multiple duty cycles and input power curves.

[0061] Figure 3FIG is a waveform diagram of a main control signal and a conversion control signal according to an embodiment of the present invention. Figure 1 and Figure 3 In order to smoothly operate the energy recovery system 1, the voltage waveforms of the main control signals S1 and S2 and the conversion control signals S3 and S4 are as follows: Figure 3 As shown, the first field-effect transistor T1, the fourth field-effect transistor T4, the fifth field-effect transistor T5, the eighth field-effect transistor T8, the ninth field-effect transistor T9, and the twelfth field-effect transistor T12 all receive the same main control signal S1. The second field-effect transistor T2, the third field-effect transistor T3, the sixth field-effect transistor T6, the seventh field-effect transistor T7, the tenth field-effect transistor T10, and the eleventh field-effect transistor T11 all receive the same main control signal S2. When the first field-effect transistor T1, the fourth field-effect transistor T4, the fifth field-effect transistor T5, the eighth field-effect transistor T8, the ninth field-effect transistor T9, and the twelfth field-effect transistor T12 are in the on state, the second field-effect transistor T2, the third field-effect transistor T3, the sixth field-effect transistor T6, the seventh field-effect transistor T7, the tenth field-effect transistor T10, and the eleventh field-effect transistor T11 are in the off state. When the second field-effect transistor T2, the third field-effect transistor T3, the sixth field-effect transistor T6, the seventh field-effect transistor T7, the tenth field-effect transistor T10, and the eleventh field-effect transistor T11 are in the on state, the first field-effect transistor T1, the fourth field-effect transistor T4, the fifth field-effect transistor T5, the eighth field-effect transistor T8, the ninth field-effect transistor T9, and the twelfth field-effect transistor T12 are in the off state. Furthermore, when the thirteenth field-effect transistor T13 is in the on state, the fourteenth field-effect transistor T14 is in the off state. When the fourteenth field-effect transistor T14 is in the on state, the thirteenth field-effect transistor T13 is in the off state.

[0062] The full-bridge isolation-level DC voltage conversion circuit 10 adopts open-loop control, and the boost converter 11 controls the input current and output voltage Vo provided by the battery B to the full-bridge isolation-level DC voltage conversion circuit 10. In practical operation, the input voltage can be a DC voltage of 60 to 66 volts, and the output voltage Vo can reach a DC voltage of 400 to 525 volts, which can be used for energy recovery by the subsequent inverter in the AC 220 volt mains system. Figure 1 The circuit and Figure 2 The data in Table 1 is obtained by following the process. In Table 1, the input voltage is designed to be 60-66 volts, the output voltage Vo is designed to be 525 volts, and the input power is 0-5000 watts. Because the total data is too large, a portion of the data is cut out in Table 1 to illustrate the data trend.

[0063] Table 1 Maximum duty cycle and drain-source voltage at different input power and input voltage

[0064]

[0065]

[0066] Figure 4 FIG is a schematic diagram of a working cycle and input power curve according to an embodiment of the present invention. Figure 4 and Figure 1 , Figure 4 It is made according to Table 1, including data when the input voltage is less than or equal to 64 volts and the input voltage is greater than 64.5 volts. Figure 4 The output voltage Vo can be guaranteed to not exceed the withstand voltage of the second capacitor C2 when the upper limit of the input voltage is increased, and the expected output specification can be achieved. In addition, the drain-source voltages of the first field-effect transistor T1, the second field-effect transistor T2, the third field-effect transistor T3, the fourth field-effect transistor T4, the fifth field-effect transistor T5, the sixth field-effect transistor T6, the seventh field-effect transistor T7, the eighth field-effect transistor T8, the ninth field-effect transistor T9, the tenth field-effect transistor T10, the eleventh field-effect transistor T11, and the twelfth field-effect transistor T12 are also lower than the default drain-source withstand voltage. The input control method of the present invention can increase the input voltage to over 60 volts. Therefore, the input voltage can be provided by 15 3.7 volt lithium polymer batteries or 17 or 18 3.2 volt lithium iron batteries connected in series, meeting a wide range of usage requirements.

[0067] According to the above embodiment, the input control method creates a table for the duty cycle of the main control signal according to the input power and the input voltage, so as to increase the upper limit of the input voltage to achieve the expected output specification.

[0068] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of implementation of the present invention. All changes and modifications in the shape, structure, characteristics and spirit described within the scope of protection of the present invention should be included in the scope of protection of the present invention.

Claims

1. An input control method, applied to an energy recovery system, characterized in that: The input control method includes: setting a first maximum value for the input voltage and a second maximum value for the output voltage of the energy recovery system, wherein when the input power of the energy recovery system is 0, the output voltage generated by the energy recovery system receiving the first maximum value, the main control signal, and the conversion control signal is less than or equal to the second maximum value; inputting the input voltage equal to the first maximum value, the main control signal, and the conversion control signal to the energy recovery system, and controlling the input power to gradually increase by a first fixed amount starting from 0, so as to calculate a first maximum duty cycle of the main control signal corresponding to the input power when the output voltage is equal to the second maximum value; inputting the input voltage equal to the first maximum value, the main control signal, and the conversion control signal into the energy recovery system, and controlling the input power to gradually increase by the first fixed amount starting from 0, and the input voltage to gradually decrease by a second fixed amount starting from the first maximum value, so as to calculate a second maximum duty cycle of the main control signal corresponding to the input power and the input voltage when the output voltage is equal to the second maximum value; and A plurality of duty cycle and input power curves corresponding to different input voltages are generated according to the input voltage, the input power, the first maximum duty cycle, and the second maximum duty cycle, and the energy recovery system is controlled according to the duty cycle and input power curves.

2. The input control method according to claim 1, wherein: The energy recovery system comprises: a full-bridge isolation-level DC voltage conversion circuit, receiving the input voltage, the input power, and the main control signal; and A boost converter is coupled to the full-bridge isolation-level DC voltage conversion circuit, receives the conversion control signal, and generates the output voltage.

3. The input control method according to claim 2, wherein: The full-bridge isolation-level DC voltage conversion circuit comprises: a first field effect transistor; a second field effect transistor, wherein a drain of the second field effect transistor is coupled to a source of the first field effect transistor; a third field effect transistor, wherein a drain of the third field effect transistor is coupled to the drain of the first field effect transistor; a fourth field-effect transistor, wherein a drain of the fourth field-effect transistor is coupled to a source of the third field-effect transistor, and a source of the fourth field-effect transistor is coupled to a source of the second field-effect transistor, wherein the drains of the first field-effect transistor and the third field-effect transistor and the sources of the second field-effect transistor and the fourth field-effect transistor receive the input voltage; a first transformer, wherein one end of a primary side of the first transformer is coupled to a node between the first field effect transistor and the second field effect transistor via a first inductor, and the other end of a primary side of the first transformer is coupled to a node between the third field effect transistor and the fourth field effect transistor; a fifth field effect transistor; a sixth field effect transistor, wherein a drain of the sixth field effect transistor is coupled to the source of the fifth field effect transistor; a seventh field effect transistor, wherein a drain of the seventh field effect transistor is coupled to the drain of the fifth field effect transistor; an eighth field-effect transistor, wherein a drain of the eighth field-effect transistor is coupled to the source of the seventh field-effect transistor, and a source of the eighth field-effect transistor is coupled to the source of the sixth field-effect transistor, wherein the drains of the fifth field-effect transistor and the seventh field-effect transistor and the sources of the sixth field-effect transistor and the eighth field-effect transistor receive the input voltage; a second transformer, wherein one end of a primary side of the second transformer is coupled to a node between the fifth field-effect transistor and the sixth field-effect transistor via a second inductor, and the other end of a primary side of the second transformer is coupled to a node between the seventh field-effect transistor and the eighth field-effect transistor; a ninth field effect transistor; a tenth field effect transistor, wherein a drain of the tenth field effect transistor is coupled to the source of the ninth field effect transistor; an eleventh field-effect transistor, a drain of the eleventh field-effect transistor being coupled to the drain of the ninth field-effect transistor; and a twelfth field-effect transistor, wherein a drain of the twelfth field-effect transistor is coupled to the source of the eleventh field-effect transistor, and a source of the twelfth field-effect transistor is coupled to the source of the tenth field-effect transistor; One end of the secondary side of the first transformer is coupled to one end of the secondary side of the second transformer, the other end of the secondary side of the first transformer is coupled to a node between the ninth field-effect transistor and the tenth field-effect transistor, and the other end of the secondary side of the second transformer is coupled to a node between the eleventh field-effect transistor and the twelfth field-effect transistor. Gates of the first field-effect transistor, the second field-effect transistor, the third field-effect transistor, the fourth field-effect transistor, the fifth field-effect transistor, the sixth field-effect transistor, the seventh field-effect transistor, the eighth field-effect transistor, the ninth field-effect transistor, the tenth field-effect transistor, the eleventh field-effect transistor, and the twelfth field-effect transistor respectively receive the main control signal.

4. The input control method according to claim 3, wherein: In the step of controlling the energy recovery system according to the multiple duty cycles and input power curves, the first maximum duty cycle and / or the second maximum duty cycle are adjusted to reduce the drain-source voltage of the first field-effect transistor, the second field-effect transistor, the third field-effect transistor, the fourth field-effect transistor, the fifth field-effect transistor, the sixth field-effect transistor, the seventh field-effect transistor, the eighth field-effect transistor, the ninth field-effect transistor, the tenth field-effect transistor, the eleventh field-effect transistor, and the twelfth field-effect transistor to be lower than a default drain-source withstand voltage value, thereby reducing the number of different slopes of the duty cycle and input power curves. After that, the energy recovery system is controlled according to the multiple duty cycles and input power curves.

5. The input control method according to claim 3, wherein: The first field effect transistor, the second field effect transistor, the third field effect transistor, the fourth field effect transistor, the fifth field effect transistor, the sixth field effect transistor, the seventh field effect transistor, the eighth field effect transistor, the ninth field effect transistor, the tenth field effect transistor, the eleventh field effect transistor and the twelfth field effect transistor are N-channel metal oxide semiconductor field effect transistors.

6. The input control method according to claim 3, wherein: The boost converter comprises: a first capacitor coupled between the drain of the eleventh field-effect transistor and the source of the twelfth field-effect transistor; a thirteenth field-effect transistor, a source of the thirteenth field-effect transistor coupled to a node between the first capacitor and the drain of the eleventh field-effect transistor through a third inductor; a fourteenth field-effect transistor, a drain of the fourteenth field-effect transistor coupled to a node between the third inductor and the source of the thirteenth field-effect transistor; and a second capacitor, one end of the second capacitor being coupled to the source of the fourteenth field-effect transistor and the other end being coupled to the drain of the thirteenth field-effect transistor, wherein the second capacitor outputs the output voltage, and the gates of the thirteenth field-effect transistor and the fourteenth field-effect transistor receive the conversion control signal.

7. The input control method according to claim 6, wherein: The thirteenth field effect transistor and the fourteenth field effect transistor are N-channel insulated gate bipolar transistors.

8. The input control method according to claim 6, wherein: The second maximum value is less than or equal to a withstand voltage value of the second capacitor.

9. The input control method according to claim 6, wherein: When the thirteenth field effect transistor is in the on state, the fourteenth field effect transistor is in the off state; when the fourteenth field effect transistor is in the on state, the thirteenth field effect transistor is in the off state.

10. The input control method according to claim 3, wherein: The main control signal received by the first field effect transistor, the fourth field effect transistor, the fifth field effect transistor, the eighth field effect transistor, the ninth field effect transistor, and the twelfth field effect transistor is the same; the main control signal received by the second field effect transistor, the third field effect transistor, the sixth field effect transistor, the seventh field effect transistor, the tenth field effect transistor, and the eleventh field effect transistor is the same; When the body transistor is in the on state, the second field-effect transistor, the third field-effect transistor, the sixth field-effect transistor, the seventh field-effect transistor, the tenth field-effect transistor, and the eleventh field-effect transistor are in the off state; when the second field-effect transistor, the third field-effect transistor, the sixth field-effect transistor, the seventh field-effect transistor, the tenth field-effect transistor, and the eleventh field-effect transistor are in the on state, the first field-effect transistor, the fourth field-effect transistor, the fifth field-effect transistor, the eighth field-effect transistor, the ninth field-effect transistor, and the twelfth field-effect transistor are in the off state.

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