Adaptive zero voltage switch for near field communication

Abstract

The invention relates to an adaptive zero voltage switch for near field communication. Systems and methods for operating a wireless power transfer device are described. The circuit may generate a first signal indicating that a voltage at a node between a first high side (HS) transistor and a first low side (LS) transistor in the switching converter falls below ground. The circuit may delay a gate-source voltage of a second LS transistor in the switching converter to generate a second signal. The circuit may combine the first signal and the second signal to generate a third signal. The controller may trigger a rising edge of the command signal using a third signal to turn on the first LS transistor at a particular time. The conduction of the first LS transistor at the specific time reduces the diode conduction time of the body diode of the first LS transistor.

Description

Technical Field

[0001] The present disclosure generally relates to apparatus and methods for wireless power transmission devices. In particular, the operating efficiency of a wireless power receiver can be improved by reducing the diode conduction time. Background Art

[0002] Wireless power transfer using a near field communication (NFC) protocol (e.g., an NFC wireless power system) can occur between two devices that include a near field communication (NFC) interface. Such an NFC wireless power system may include a poller having a transmitting coil and a listener having a receiver coil. On the one hand, the poller can be connected to a structure including a wireless charging area. In response to a device including the listener being placed close to a device including the poller, the transmitting coil and the receiver coil can be inductively coupled to each other to establish an NFC communication link between the poller and the listener, and an inductive transfer of alternating current (AC) power can occur using the established NFC communication link. The transmission of AC power from the poller to the listener can help charge the battery of the device including the listener. Summary of the invention

[0003] In one embodiment, a semiconductor device in a wireless power transmission device is generally described. The semiconductor device may include a controller, a switching converter, and a circuit. The switching converter may include a first high-side (HS) transistor, a second HS transistor, a first low-side (LS) transistor, and a second LS transistor. The circuit may be configured to generate a first signal indicating that the voltage at a node between the first HS transistor and the first LS transistor drops below ground. The circuit may be further configured to delay the gate-source voltage of the second LS transistor to generate a second signal. The circuit may be further configured to merge the first signal and the second signal to generate a third signal. The controller may be configured to use the third signal to trigger the rising edge of the instruction signal to turn on the first LS transistor at a specific time. Turning on the first LS transistor at a specific time can reduce the diode conduction time of the body diode of the first LS transistor.

[0004] In one embodiment, a semiconductor device for a semiconductor device in a wireless power transmission device is generally described. The semiconductor device may include a comparator configured to generate a first signal, the first signal indicating that the voltage at a node between a first high-side (HS) transistor and a first low-side (LS) transistor in a switching converter drops below ground. The semiconductor device may further include a delay circuit configured to delay the gate-source voltage of a second LS transistor in the switching converter to generate a second signal. The semiconductor device may further include an OR gate configured to merge the first signal and the second signal to generate a third signal. The OR gate may be further configured to send the third signal to a controller to trigger the rising edge of the instruction signal to turn on the first LS transistor at a specific time. Turning on the first LS transistor at a specific time can reduce the diode conduction time of the body diode of the first LS transistor.

[0005] In one embodiment, a method for operating a wireless power transmission device is generally described. The method may include generating a first signal indicating that a voltage at a node between a first high-side (HS) transistor and a first low-side (LS) transistor in a switching converter drops below ground. The method may further include delaying a gate-source voltage of a second LS transistor in the switching converter to generate a second signal. The method may further include merging the first signal and the second signal to generate a third signal. The method may further include using the third signal to trigger a rising edge of a command signal to turn on the first LS transistor at a specific time. Turning on the first LS transistor at a specific time can reduce the diode conduction time of the body diode of the first LS transistor.

[0006] Other features as well as the structure and operation of various embodiments will be described in detail below with reference to the accompanying drawings.In the drawings, like reference numbers indicate identical or functionally similar elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a diagram illustrating an example system in which adaptive zero voltage switching for near field communications may be implemented in one embodiment.

[0008] Figure 2 is a diagram illustrating an example circuit in which adaptive zero voltage switching for near field communications may be implemented in one embodiment.

[0009] Figure 3 is a diagram showing signal waveforms in an example implementation of adaptive zero voltage switching for near field communication, in one embodiment.

[0010] Figure 4 is a flow chart illustrating a process of implementing adaptive zero voltage switching for near field communications, in one embodiment. DETAILED DESCRIPTION

[0011] A large number of specific details, such as particular structures, components, materials, dimensions, processing steps and techniques are set forth in the following description in order to provide an understanding of the various embodiments of the present application. However, it will be appreciated by those of ordinary skill in the art that the various embodiments of the present application can be implemented without these specific details. In other instances, known structures or processing steps are not described in detail to avoid obscuring the present application.

[0012] The NFC wireless power system can provide charging in static mode or negotiation mode. The static mode can use a standard radio frequency (RF) field strength and provide a constant power level, and the negotiation mode can use a relatively high RF field to support different power transfer levels (such as 250, 500, 750 and 1000 milliwatts (mW)). In the NFC wireless power system, the poller and the listener can communicate with each other using the NFC communication protocol. On the one hand, the NFC wireless power system can use a specific base frequency (e.g., 13.56 megahertz (MHz)) and control power transfer using an NFC communication link between two devices. To perform NFC communication, one device can apply or pass a modulated signal (e.g., an amplitude shift keying (ASK) signal) to another device, and the other device can demodulate the modulated signal.

[0013] Figure 1 1 is a diagram showing an example system in which adaptive zero voltage switching for near field communication can be implemented in one embodiment. System 100 may include a power device (such as a transmitter 110 and a receiver 120) configured to wirelessly transmit power and data therebetween via inductive coupling. Although described herein as a transmitter 110 and a receiver 120, each of the transmitter 110 and the receiver 120 may be configured to transmit and receive power or data therebetween via inductive coupling. Transmitter 110 may be referred to as a wireless power transmitter, and receiver 120 may be referred to as a wireless power receiver. In an embodiment in which system 100 is configured as an NFC wireless power system, transmitter 110 may be configured as a poller and receiver 120 may be configured as a listener. Transmitter 110 and receiver 120 may include various types of components (such as an integrated circuit (IC)), which may be a semiconductor device composed of semiconductor materials.

[0014] The transmitter 110 is configured to receive power from one or more power sources and wirelessly transmit AC power to the receiver 120. For example, the transmitter 110 can be configured to be connected to a power source 116 (such as, for example, an arbitrator or a DC power source). The transmitter 110 can be a semiconductor device including a controller 112, a resonant circuit 113, and a switching converter 114. The switching converter 114 can be an integrated circuit (IC), which can be part of a power driver and is configured to convert one type of current to another type of current. By way of example, the switching converter 114 can be configured as an inverter to convert a DC signal to an AC signal.

[0015] The controller 112 may be configured to control and operate the switching converter 114 and other components of the transmitter 110. The controller 112 may include, for example, a processor, a central processing unit (CPU), a field programmable gate array (FPGA), or any other circuit device configured to control and operate the switching converter 114. Although the controller 112 is described as a CPU in the illustrated embodiments, it is not limited to the CPU in these embodiments and may include any other circuit device configured to control and operate the switching converter 114. In an example embodiment, the controller 112 may be configured to control the switching converter 114 to drive the resonant circuit 113 to generate a magnetic field. The switching converter 114 may drive the coil TX at a frequency range and configuration defined by a wireless power standard such as, for example, the NFC Forum Wireless Charging (WLC) specification. The resonant circuit 113 may include a coil TX and one or more capacitors, inductors, resistors, which may form a circuit device for outputting various signals and transmitting the AC power 130 to the receiver 120.

[0016] The receiver 120 may be configured to receive the AC power 130 transmitted from the transmitter 110 and supply power to one or more loads, such as a load 126 or other components of a destination device that includes the receiver 120. The load 126 may include, for example, a battery charger configured to charge a battery, a DC-DC converter configured to supply DC power 132 to a processor, a display or other electronic component of the destination device 140, or any other load of the destination device 140. The destination device may include the receiver 120 and may be, for example, a computing device, a smart device, a wearable device, or any other electronic device configured to wirelessly receive power. In other embodiments, the receiver 120 may be separate from the destination device and may be connected to the destination device via a wire or other component configured to provide power to the destination device 140.

[0017] Receiver 120 may be a semiconductor device including controller 122, resonant circuit 123, switching converter 124, and circuit 150. In one embodiment, circuit 150 may be an IC, such as a semiconductor device made of semiconductor material. Controller 122 may be an integrated circuit, which includes, for example, a digital controller (such as a microcontroller, a processor, a CPU, an FPGA, or any other circuit device that may be configured to control and operate switching converter 124). Resonant circuit 123 may include coil RX and one or more capacitors, inductors, resistors, which may form a circuit device for receiving AC power 130 and outputting communication packets 136. Switching converter 124 may be an IC configured to convert one type of current into another type of current. By way of example, switching converter 124 may be configured as a power rectifier to convert an AC signal into a DC signal. When configured as a power rectifier, the power switching converter 124 may include a rectifier circuit (such as a half-bridge rectifier, a full-bridge rectifier, or other type of rectifier circuit that can be configured to rectify power received via the resonant coil RX of the resonant circuit 123 to a power type as required by the load 126).

[0018] As an example, when receiver 120 is placed near transmitter 110, the magnetic field generated by coil TX of resonant circuit 113 and switching converter 114 induces a current in coil RX of resonant circuit 123. The induced current causes AC power 130 to be inductively transmitted to switching converter 124 via resonant circuit 123. Switching converter 124 receives AC power 130 and converts AC power 130 into DC power 132 for load 126.

[0019] The transmitter 110 and the receiver 120 are also configured to exchange information or data, for example, exchanging messages via the power driver 106 and the inductive coupling of the resonant circuit 113 and the resonant circuit 123. For example, before the transmitter 110 begins to transfer power to the receiver 120, a power contract may be agreed upon and created between the receiver 120 and the transmitter 110. For example, the receiver 120 may send a communication packet 136 using an ASK signal to the transmitter 110, the communication packet 136 indicating power transfer information, such as, for example, the amount of power transferred to the receiver 120, an instruction to increase, decrease, or maintain the power level of the AC power 130, an instruction to stop power transfer, or other power transfer information. In another example, in response to the receiver 120 being introduced into proximity with the transmitter 110 (e.g., close enough so that the coil TX and the coil RX can form a transformer to allow power transfer), the receiver 120 may be configured to enable communication by sending a signal to the transmitter 110 requesting power transfer. In this case, the transmitter 110 may respond to the request of the receiver 120 by establishing a power contract or starting to transfer power to the receiver 120 (e.g., if the power contract is already in effect). The transmitter 110 and the receiver 120 may transmit and receive ASK signals, data, or other information via the inductive coupling of the coil TX and the coil RX.

[0020] like Figure 1 As shown, the switching converter 124 can be formed by two half-bridge circuits including two high-side metal oxide semiconductor field effect transistors (MOSFETs) HS1, HS2 and two low-side MOSFETs LS1, LS2. MOSFETs HS1 and LS2 can be turned on and off at the same time, and MOSFETs HS2 and LS1 can be turned on and off at the same time. The HS1, LS2 pair and the HS2, LS1 pair can be switched alternately to rectify the AC power 130 into DC power 132. Alternating switching can cause current to flow from node AC1 to AC2 and alternatively, vice versa. When HS2 and LS1 are turned on, current can flow from AC1 to AC2, during which the AC1 voltage will become low and the AC2 voltage will become high. When HS1 and HS2 are turned on, current can flow from AC2 to AC1, during which the AC2 voltage will become low and the AC1 voltage will become high.

[0021] Maximizing operating efficiency is an important aspect of wireless charging. In addition to environmental impacts, operating efficiency affects the power density and charging time of portable devices. On the one hand, some receivers can use Schottky diodes to rectify the received AC power, but Schottky diodes may have a large forward voltage drop and may limit the receiver to less than 80% efficiency. Some receivers can implement active rectifiers using low RDS(on) transistors, but active rectifiers may require precise control of MOSFETs while accommodating the high frequencies of AC signals (e.g., in the 13.56MHz range).

[0022] On the one hand, when the switching converter 124 senses current flowing through one diagonal (e.g., LS1-HS2 or LS2-HS1), the corresponding MOSFET is placed in the ON state, providing a low-loss current path. However, there is a delay when turning on the corresponding MOSFET in the diagonal. During this delay, the current path can pass through the body diode of the MOSFET, causing a diode forward voltage drop. This diode forward voltage drop may cause increased losses, increased heat, and reduced operating efficiency. On the one hand, if the delay causes more than 3 nanoseconds (ns) of diode conduction time, the receiver suffers more than 0.7% efficiency loss.

[0023] To improve the efficiency of the receiver 120, the receiver 120 may include at least one circuit 150 configured to perform zero voltage switching (ZVS) control. ZVS control may include monitoring the situation when the voltage at the node AC1 and / or AC2 crosses a zero voltage (e.g., changes to below zero or below ground), and performing one or more tasks in response to the voltage crossing the zero voltage to control other aspects of the receiver 120. In one embodiment, the circuit 150 may monitor the low-side MOSFETs LS1, LS2, and reduce the diode conduction time when the MOSFETs LS1 and LS2 are turned on. A replica of the circuit 150 may be connected across LS1, and another replica of the circuit 150 may be connected across LS2. In one embodiment, the circuit 150 may measure the voltage across the MOSFET (such as LS1 or LS2), and based on the measured voltage, reduce the diode conduction time of the MOSFET by predicting the rising edge of the gate-source voltage (Vgs) of the MOSFET. The reduced diode conduction time may also induce a reduction in electromagnetic interference (EMI).

[0024] Figure 2 is a diagram showing an example circuit in which adaptive zero voltage switching for near field communications may be implemented in one embodiment. Figure 2 For a description, see Figure 1 The parts shown in . Figure 2The embodiment shown in FIG. 1 may be a method of implementing a circuit 150 for monitoring LS1 and reducing the diode conduction time of the body diode 200 of LS1 . Figure 2 The implementation method of the circuit 150 shown can also be applied to Figure 1 LS2 of the switching converter 124 in FIG. 1 . In one embodiment, the Figure 2 The components shown in embody the circuit 150. Figure 2 In the illustrated embodiment, circuit 150 may include comparator 202 , delay circuit 206 , delay circuit 208 , OR gate 210 , arbiter 212 , filter 214 , and counter 216 .

[0025] The input of comparator 202 can be across a low-side MOSFET (such as LS1 or LS2) in switching converter 124. Figure 2 LS1 in the figure) is connected. Comparator 202 can monitor the voltage at node AC1. Gate-source voltage VGS_LS1 can be applied to the gate of LS1. When VGS_LS1 is greater than the threshold voltage of LS1, LS1 can be turned on. When LS1 is turned on, current can flow through LS1 and the voltage at node AC1 can become low. The voltage output by comparator 202 is marked as comparator output 204 or on1_comp signal, which can indicate whether the voltage at node AC1 is above ground or below ground (e.g., above zero or below zero).

[0026] Circuit 150 may receive a gate-source voltage of LS1 (VSG_LS1) and a gate-source voltage of LS2 (VSG_LS2). Delay circuit 206 may apply a delay (e.g., a fine-tuning delay) on VGS_LS1. Delay circuit 206 may output a delayed VGS_LS1 (labeled as signal 207). In one embodiment, the delay applied by delay circuit 206 may be predefined and fixed, and may be equivalent to the propagation delay of comparator 202. Delay circuit 208 may apply a programmable delay on the falling edge of VGS_LS2, wherein the programmable delay may depend on delay signal 217. Delay circuit 208 may output a delayed version of the falling edge of VGS_LS2 (labeled as signal 209).

[0027] The arbiter 212 may be configured to check the arrival order of the signal VGS_LS1 and the comparator output 204 (or on1_comp) on a cycle-by-cycle basis. If on1_comp arrives at the r1 input of the arbiter 212 before VGS_LS1 arrives at the r2 input of the arbiter 212, the arbiter 212 may output the signal g1. If VGS_LS1 arrives at the r2 input of the arbiter 212 before on1_comp arrives at the r1 input of the arbiter 212, the arbiter 212 may output the signal g2.

[0028] The filter 214 may be a digital filter configured to filter noise from the output of the arbiter 212, and may also check whether the arbiter 212 outputs g1 or g2 for more than one continuous cycle. If the arbiter 212 outputs g1 for more than one cycle, the counter 216 may count down by decrementing the delay signal 217. If the arbiter 212 outputs g2 for more than one cycle, the counter 216 may count up by incrementing the delay signal 217. The delay signal 217 may be applied to the delay circuit 208 to adjust the delay applied to the falling edge of VGS_LS2. In one embodiment, the system (e.g., the receiver 120) may eventually reach a stable state and the counter 216 may stop counting, or the delay signal 217 may be alternately incremented and decremented to maintain the delay signal 217.

[0029] OR gate 210 can receive comparator output 204 and signal 209. OR gate 210 can combine or merge comparator output 204 and signal 209. Controller 122 can receive ON1 output from OR gate 210. ON1 is a high voltage (e.g., binary 1) that can trigger a rising edge of command signal 219 output by controller 122. Driver 220 can receive command 219 and turn on LS1 by applying VGS_LS1 to the gate of LS1 (e.g., VGS_LS1 goes high). When LS1 is turned on, it can rectify diode 200 and end the diode conduction time.

[0030] On the one hand, if the circuit 150 is disabled or the delay applied is too long (for example, when the system has not reached a steady state after power-on), the comparator 202 can provide the comparator output 204 directly to the controller 122 to trigger the controller 122, thereby controlling the driver 220 to turn on LS1. The propagation delays in the comparator 202, the controller 122, and the driver 220 may affect the diode conduction time of the body diode 200 of LS1. The activation circuit 150 can predict the turn-on time of LS1 and turn on LS1 earlier than the deactivation circuit 150. The earlier turn-on time can reduce the diode conduction time of the body diode 200 in LS1.

[0031] In one embodiment, the ON1 signal is generated based on the delay applied to the delay circuit 208 and output by the OR gate 210, which can replace the comparator output 204 (on1_comp) to trigger the rising edge of the command signal 219 at an earlier time than the rising edge of the command signal 219 (or disable the circuit 150) triggered by on1_comp. The rising edge of the command signal 219 is triggered earlier to turn on LS1 so that the timing of the rising edge of the on1_comp signal is aligned with the VGS_LS1 signal.

[0032] Further, using the arbiter 212 and counter 216, and optionally using the filter 214, adaptive compensation can be provided for propagation delays and the alignment of the on1_comp signal and the VGS_LS1 signal can be precisely controlled. By way of example, if the on1_comp lags behind the VGS_LS1 signal, the signal 207 can arrive at the arbiter 212 earlier than the comparator output 204. The arbiter 212 can output g2 to trigger the counter 216 to increment the delay signal 217, thereby increasing the programmable delay applied by the delay circuit 208. The increased delay applied by the delay circuit 208 can delay the VGS_LS1 signal to align VGS_LS1 with the lagging on1_comp signal. If the VGS_LS1 signal lags behind the on1_comp signal, the comparator output 204 can arrive at the arbiter 212 earlier than the signal 207. The arbiter 212 may output g1 to trigger the counter 216 to decrement the delay signal 217, thereby reducing the programmable delay imposed by the delay circuit 208. The reduced delay imposed by the delay circuit 208 may advance the rising edge of the trigger VGS_LS1 signal earlier, thereby aligning the lagging VGS_LS1 with the on1_comp signal. The adaptive alignment may maintain the reduced diode conduction time of the body diode 200 and result in an improvement in the efficiency of the receiver 120.

[0033] Figure 3 is a diagram showing waveforms of signals in an example implementation of adaptive zero voltage switching for near field communication in one embodiment. Figure 3 For a description, see Figure 1 and Figure 2 The parts shown in . Figure 3 1 shows a plurality of waveforms of various signals in an implementation of circuit 150. Figure 3 In the waveform shown, the voltage at node AC1 may begin to drop below ground at approximately time t1. The propagation delay of comparator 202 may cause comparator 202 to raise the on1_comp signal to a high voltage at approximately time t3. Figure 3 The description relates to an example implementation method of the circuit 150 for LS1, which may also be applicable to the implementation method of the circuit 150 for LS2.

[0034] Figure 3Also shown is the waveform of signal 209 output by delay circuit 208. The rising edge of signal 209 is a delayed version of the falling edge of VGS_LS2. Signal 209 remains high for a fixed period of time sufficient to be latched by controller 122. If delay signal 217 increases the delay applied by delay circuit 208, the rising edge of signal 209 will be delayed for a longer time. If delay signal 217 decreases the delay applied by delay circuit 208, signal 209 will be delayed for a shorter time.

[0035] refer to Figure 2 Since the signal 209 and on1_comp are fed into the OR gate 210, in response to one or both of the signal 209 and on1_comp being high, the output of the OR gate 210 or the ON1 signal can be high. The OR gate 210 can combine the signal 209 and on1_comp, and the rising edge of the ON1 signal can be triggered relatively early to compensate for the propagation delay in the controller 122 and the driver 220. Figure 3 As shown, when the signal 209 is high and on1_comp remains low, the command signal 219 output by the controller 122 also becomes high because the OR gate 210 outputs ON1 as a high voltage. Therefore, the signal 209 can trigger the rising edge of the command signal 219 to start turning on LS1 before the rising edge of the on1_comp signal. After the propagation delay of the driver 220, at about time t2, VGS_LS1 can start to rise to turn on LS1.

[0036] At time t3, the on1_comp signal may rise and VGS_LS1 may exceed the threshold voltage Vth of LS1, thus fully turning on LS1 and ending the diode conduction time of the body diode 200 in LS1. The diode conduction time may start at t1 and end at t3, which is the difference between the propagation time of the comparator 202 (e.g., from the voltage at AC1 going low to below ground to the rising edge of on1_comp) and the delay imposed by the circuit 206. Therefore, Figure 3 The example in illustrative embodiments shows an implementation of circuit 150 in which propagation delays in controller 122 and driver 220 are eliminated and propagation delays in comparator 202 are greatly reduced.

[0037] In one embodiment, if on1_comp rises after t3, the on1_comp signal lags behind the VGS_LS1 signal and the circuit 150 may increase the delay applied by the delay circuit 208 to increase the rising edge delay of the signal 209. In one embodiment, if the on1_comp signal rises earlier than t3, the VGS_LS1 signal lags behind the on1_comp signal and the circuit 150 may decrease the delay applied by the delay circuit 208 to decrease the rising edge delay of the signal 209. In one embodiment, a reduction of about 300 picoseconds (ps) may result in an operating efficiency improvement of more than 0.7%.

[0038] Figure 4 4 is a flow chart illustrating a process of implementing adaptive zero voltage switching for near field communication in one embodiment. The process may include one or more operations, behaviors, or functions as illustrated by one or more of blocks 402, 404, 406, and / or 408. Although illustrated as discrete blocks, various blocks may be divided into additional blocks, combined into fewer blocks, eliminated, performed in a different order, or performed in parallel, depending on the desired implementation method.

[0039] Process 400 may be implemented by a wireless power transfer device, such as a receiver, transceiver, such as receiver 120 described herein. Process 400 may begin at block 402, where a circuit may generate a first signal indicating that a voltage at a node between a first high-side (HS) transistor and a first low-side (LS) transistor in a switching converter has dropped below ground. In one embodiment, the switching converter may be in a listener of a near field (NFC) power transfer system. In one embodiment, a rising edge of a gate-source voltage of the first LS transistor is aligned with a rising edge of the first signal at a particular time.

[0040] Process 400 may continue from block 402 to block 404. At block 404, the circuit may delay the gate-source voltage of a second LS transistor in the switching converter to generate a second signal. In one embodiment, the delay of the gate-source voltage applied to the second LS transistor may be a fixed delay.

[0041] Process 400 may continue from block 404 to block 406. At block 406, the circuit may combine the first signal and the second signal to generate a third signal, and process 400 may continue from block 406 to block 408. At block 408, the controller may use the third signal to trigger a rising edge of the command signal to turn on the first LS transistor at a specific time. Turning on the first LS transistor at the specific time may reduce a diode conduction time of a body diode of the first LS transistor.

[0042] In one embodiment, the circuit may delay the gate-source voltage of the first LS transistor to generate the fourth signal. The circuit may generate the delay signal based on arbitration between the first signal and the fourth signal. The circuit may use the delay signal to adjust the delay of the gate-source voltage applied to the second LS transistor. The adjustment of the delay may adjust the specific time. In one embodiment, the delay of the gate-source voltage applied to the first LS transistor may be a programmable delay.

[0043] In one embodiment, in response to the arbitration indicating that the first signal arrives at the arbitrator before the fourth signal, the circuit may generate a delay signal to reduce the delay. In response to the arbitration indicating that the fourth signal arrives at the arbitrator before the first signal, the circuit may generate a delay signal to increase the delay.

[0044] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functions and operations of the possible implementation methods of the system, method and computer program product according to various embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, segment or code portion, which includes one or more executable instructions for implementing a specified logical function. In some alternative implementation methods, the functions marked in the box may not occur in the order marked in the accompanying drawings. For example, depending on the functions involved, the two boxes shown in succession can actually be executed substantially simultaneously, or the box can sometimes be executed in the opposite order. It should also be noted that each box illustrated in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented by a dedicated hardware-based system that performs a specified function or action or performs a combination of dedicated hardware and computer instructions.

[0045] The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the terms "comprise" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0046] The corresponding structures, materials, actions, and equivalents of all method or step plus function elements (if any) in the following claims are intended to include any structure, material, or action that is combined with other claimed elements to perform a function as specifically claimed. A description of the present invention has been given for purposes of illustration and description, but is not intended to be exhaustive or to limit the invention to the disclosed form. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the present invention. The embodiment is selected and described to best explain the principles and practical application of the present invention, and to enable other persons of ordinary skill in the art to understand the present invention for various embodiments with various modifications suitable for the intended specific use.

Claims

1. A semiconductor device comprising: Controller; a switching converter comprising a first high-side transistor, a second high-side transistor, a first low-side transistor, and a second low-side transistor; as well as The circuit is configured as: generating a first signal indicating that a voltage at a node between the first high-side transistor and the first low-side transistor has dropped below ground; delaying a gate-source voltage of the second low-side transistor to generate a second signal; as well as combining the first signal and the second signal to generate a third signal, The controller is configured to use the third signal to trigger a rising edge of a command signal to turn on the first low-side transistor at a specific time, wherein turning on the first low-side transistor at the specific time reduces a diode conduction time of a body diode of the first low-side transistor.

2. The semiconductor device of claim 1, wherein the switching converter is in a listener of a near field communication power transfer system.

3. The semiconductor device according to claim 1, wherein the circuit is configured as: delaying a gate-source voltage of the first low-side transistor to generate a fourth signal; generating a delay signal based on arbitration between the first signal and the fourth signal; and The delay of the gate-source voltage applied to the second low-side transistor is adjusted using the delay signal, wherein the adjustment of the delay adjusts the specific time. 4 . The semiconductor device according to claim 3 , wherein the delay of the gate-source voltage applied to the first low-side transistor is a fixed delay.

5. The semiconductor device according to claim 3, wherein: In response to the arbitration indication that the first signal arrives at the arbitrator before the fourth signal, generating the delay signal for reducing the delay; as well as In response to the arbitration indicating that the fourth signal arrives at the arbitrator before the first signal, the delay signal for increasing the delay is generated. 6 . The semiconductor device of claim 1 , wherein the delay of the gate-source voltage applied to the second low-side transistor is a programmable delay. 7 . The semiconductor device according to claim 1 , wherein a rising edge of a gate-source voltage of the first low-side transistor is aligned with a rising edge of the first signal at the specific time.

8. A semiconductor device comprising: a comparator configured to generate a first signal indicating that a voltage at a node between a first high-side transistor and a first low-side transistor in the switching converter has dropped below ground; a delay circuit configured to delay a gate-source voltage of a second low-side transistor in the switching converter to generate a second signal; as well as OR gate, configured as: combining the first signal and the second signal to generate a third signal; as well as The third signal is sent to the controller to trigger a rising edge of the command signal to turn on the first low-side transistor at a specific time, wherein turning on the first low-side transistor at the specific time reduces a diode conduction time of a body diode of the first low-side transistor.

9. The semiconductor device of claim 8, wherein the switching converter is in a listener of a near field communication power transfer system.

10. The semiconductor device according to claim 8, wherein the delay circuit is a first delay circuit, and the semiconductor device further comprises: a second delay circuit configured to delay a gate-source voltage of the first low-side transistor to generate a fourth signal; an arbitrator configured to arbitrate between the first signal and the fourth signal; as well as Counters, configured as: generating a delay signal based on the arbitration between the first signal and the fourth signal; as well as The delay signal is sent to the controller to adjust the delay of the gate-source voltage applied to the second low-side transistor, wherein the adjustment of the delay adjusts the specific time. 11 . The semiconductor device of claim 10 , wherein the delay of the gate-source voltage applied to the first low-side transistor is a fixed delay. 12 . The semiconductor device according to claim 11 , wherein the fixed delay is equivalent to a propagation delay of the comparator.

13. The semiconductor device according to claim 10, wherein the counter is configured to: In response to the arbitration indication that the first signal arrives at the arbitrator before the fourth signal, generating the delay signal for reducing the delay; and In response to the arbitration indicating that the fourth signal arrives at the arbitrator before the first signal, the delay signal for increasing the delay is generated. 14 . The semiconductor device of claim 8 , wherein the delay of the gate-source voltage applied to the second low-side transistor is a programmable delay. 15 . The semiconductor device according to claim 8 , wherein a rising edge of a gate-source voltage of the first low-side transistor is aligned with a rising edge of the first signal at the specific time.

16. A method for operating a wireless power transmission device, the method comprising: generating a first signal indicating that a voltage at a node between a first high-side transistor and a first low-side transistor in the switching converter has dropped below ground; delaying a gate-source voltage of a second low-side transistor in the switching converter to generate a second signal; combining the first signal and the second signal to generate a third signal; as well as The third signal is used to trigger a rising edge of a command signal to turn on the first low-side transistor at a specific time, wherein turning on the first low-side transistor at the specific time reduces a diode conduction time of a body diode of the first low-side transistor.

17. The method of claim 16, wherein the switching converter is in a listener of a near field communication power transfer system.

18. The method according to claim 16, further comprising: delaying a gate-source voltage of the first low-side transistor to generate a fourth signal; generating a delay signal based on arbitration between the first signal and the fourth signal; as well as The delay of the gate-source voltage applied to the second low-side transistor is adjusted using the delay signal, wherein the adjustment of the delay adjusts the specific time.

19. The method of claim 18, wherein: In response to the arbitration indication that the first signal arrives at the arbitrator before the fourth signal, generating the delay signal for reducing the delay; as well as In response to the arbitration indicating that the fourth signal arrives at the arbitrator before the first signal, the delay signal for increasing the delay is generated. 20 . The method of claim 18 , wherein a rising edge of a gate-source voltage of the first low-side transistor is aligned with a rising edge of the first signal at the specific time.

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