Half-bridge driving circuit and control method of half-bridge driving circuit

Abstract

The invention provides a half-bridge driving circuit and a control method of the half-bridge driving circuit. Comprising a signal input end, a delay circuit, a first switch part, a second switch part, a first signal output end and a second signal output end, an input signal input to the half-bridge driving circuit is respectively input to the delay circuit, the first switch component and the second switch component through a signal input end; the time delay circuit performs time delay processing on the input signal to obtain a time delay signal, and inputs the time delay signal to the first switch component and the second switch component respectively; the first switch component is used for performing first processing on the input signal and the delay signal to obtain a first output signal, and outputting the first output signal through the first signal output end; the second switch component performs second processing on the input signal and the delay signal to obtain a second output signal, and outputs the second output signal through a second signal output end; wherein the first output signal and the second output signal are not at high levels at the same time, so that the safety of the circuit is improved.

Description

Technical Field

[0001] The present application relates to the technical field of switching power supplies, and in particular to a half-bridge drive circuit and a control method for the half-bridge drive circuit. Background Art

[0002] Half-bridge drive circuits are widely used in analog devices and power devices, and they precisely control current and voltage by adjusting the on and off time of switching devices, thereby achieving efficient power conversion and management.

[0003] In the prior art, a half-bridge drive circuit is formed by two transistors, and a control signal is applied to the gates of the two transistors. A dead time is preset in the program to control the on and off of the two transistors, thereby preventing the first transistor and the second transistor in the half-bridge drive circuit from being turned on at the same time, forming a through current, causing a short circuit in the bridge arm or damage to the transistor.

[0004] However, this method occupies more port resources and has low reliability. Summary of the invention

[0005] The embodiments of the present application provide a half-bridge driving circuit and a control method for the half-bridge driving circuit, so as to avoid circuit shoot-through and improve circuit safety.

[0006] In a first aspect, the present application provides a half-bridge driving circuit, comprising: a signal input terminal, a delay circuit, a first switch component, a second switch component, a first signal output terminal, and a second signal output terminal;

[0007] The signal input end is respectively connected to the input end of the delay circuit, the first input end of the first switch component and the first input end of the second switch component, and is used to input the input signal input to the half-bridge drive circuit to the input end of the delay circuit, the first input end of the first switch component and the first input end of the second switch component respectively;

[0008] The first output end of the delay circuit is connected to the second input end of the first switch component, and the second output end of the delay circuit is connected to the second input end of the second switch component. The delay circuit is used to delay the input signal to obtain a delayed signal, and input the delayed signal to the second input end of the first switch component and the second input end of the second switch component respectively;

[0009] The output end of the first switch component is connected to the first signal output end, and the first switch component is used to perform a first process on the input signal and the delayed signal to obtain a first output signal, and output the first output signal through the first signal output end;

[0010] The output end of the second switch component is connected to the second signal output end, and the second switch component is used to perform a second process on the input signal and the delayed signal to obtain a second output signal, and output the second output signal through the second signal output end;

[0011] The first output signal and the second output signal are not at high level at the same time.

[0012] In a possible design, the first switch component is an AND gate, and the second switch component is a NOR gate.

[0013] In a possible design, the half-bridge driving circuit further includes an interlocking circuit;

[0014] The input end of the interlock circuit is connected to the first signal output end and the second signal output end respectively;

[0015] The interlocking circuit is used to perform signal interlocking processing on the first output signal and the second output signal to output a first target output signal and a second target output signal;

[0016] The first output signal and the second output signal are not at high level at the same time.

[0017] In one possible design, the interlock circuit includes a third switch component, a fourth switch component, a fifth switch component, and a sixth switch component;

[0018] The input end of the third switch component is connected to the first signal output end, the output end of the third switch component is connected to the first input end of the fifth switch component, and the third switch component is used to invert the first output signal to output a first inverted output signal;

[0019] The input end of the fourth switch component is connected to the second signal output end, the output end of the fourth switch component is connected to the first input end of the sixth switch component, and the fourth switch component is used to invert the second output signal to output a second inverted output signal;

[0020] The second input terminal of the fifth switch component is connected to the second signal output terminal, and the fifth switch component is used to perform a third process on the second output signal and the first inverted output signal to output a second target output signal through the output terminal of the fifth switch component;

[0021] The second input terminal of the sixth switch component is connected to the first signal output terminal, and the sixth switch component is used to perform a fourth process on the first output signal and the second inverted output signal to output a second target output signal through the output terminal of the sixth switch component.

[0022] In a possible design, the third switch component and the fourth switch component are inverters.

[0023] In a possible design, the fifth switch component and the sixth switch component are AND gates.

[0024] In one possible design, the delay circuit includes a first delay resistor and a first delay capacitor;

[0025] A first end of the first delay resistor is connected to the signal input end, and a second end of the first delay resistor is connected to a first end of the first delay capacitor;

[0026] The second terminal of the first delay capacitor is grounded.

[0027] In one possible design, the delay circuit includes a P-channel metal oxide semiconductor field effect transistor, an N-channel metal oxide semiconductor field effect transistor, a second delay resistor, a second delay capacitor, and an inverter;

[0028] A first electrode of the P-channel metal oxide semiconductor field effect transistor is connected to the signal input terminal, a second electrode of the P-channel metal oxide semiconductor field effect transistor is connected to the power supply voltage, and a third electrode of the P-channel metal oxide semiconductor field effect transistor is connected to the first end of the second delay resistor;

[0029] A first electrode of the N-channel metal oxide semiconductor field effect transistor is connected to the signal input terminal, a second electrode of the N-channel metal oxide semiconductor field effect transistor is connected to the first end of the second delay resistor; and a third electrode of the N-channel metal oxide semiconductor field effect transistor is grounded;

[0030] The second end of the second delay resistor is connected to the first end of the inverter and the first end of the second delay capacitor respectively;

[0031] The second end of the second delay capacitor is grounded;

[0032] The second end of the inverter is the output end of the delay circuit.

[0033] In a second aspect, the present application proposes a control method for a half-bridge drive circuit, which is applied to the half-bridge drive circuit. The method includes:

[0034] Inputting an input signal to the signal input terminal, so as to input the input signal to the input terminal of the delay circuit, the first input terminal of the first switch component, and the first input terminal of the second switch component respectively;

[0035] Delaying the input signal through the delay circuit to obtain a delayed signal, and inputting the delayed signal to the second input end of the first switch component and the second input end of the second switch component respectively;

[0036] Performing a first process on the input signal and the delayed signal through the first switch component to obtain a first output signal, and outputting the first output signal through the first signal output terminal;

[0037] Performing a second process on the input signal and the delayed signal through the second switch component to obtain a second output signal, and outputting the second output signal through the second signal output terminal;

[0038] The first output signal and the second output signal are not at high level at the same time.

[0039] In a possible design, the input signal is a sine wave signal, a triangle wave signal, a square wave signal, or a pulse width modulation signal.

[0040] The present application provides a half-bridge driving circuit and a control method for the half-bridge driving circuit. The half-bridge circuit includes a signal input terminal, a delay circuit, a first switch component, a second switch component, a first signal output terminal and a second signal output terminal; the signal input terminal is connected to the input terminal of the delay circuit, the first input terminal of the first switch component and the first input terminal of the second switch component, and after receiving the input signal, the input signal is transmitted to the input terminal of the delay circuit, the first input terminal of the first switch component and the first input terminal of the second switch component respectively; by receiving a single-channel input signal, the occupation of the signal input port is reduced, and the port resources are saved; the first output terminal of the delay circuit is connected to the second input terminal of the first switch component, and the second output terminal of the delay circuit is connected to the second output terminal of the second switch component. The input end is connected, the delay circuit delays the received input signal to obtain a delayed signal, and inputs the delayed signal into the second input end of the first switch component and the second input end of the second switch component respectively; the output end of the first switch component is connected to the first signal output end, the input signal and the delayed signal are first processed, and a first output signal is generated and output; the output end of the second switch component is connected to the second signal output end, the input signal and the delayed signal are second processed, and a second output signal is generated and output; it is ensured that the first output signal and the second output signal will not be high at the same time, thereby avoiding the direct-through phenomenon caused by incorrect signal setting, and improving the reliability of the half-bridge drive circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0042] Figure 1 A schematic diagram of the structure of a half-bridge drive circuit provided by the prior art;

[0043] Figure 2 A schematic diagram of an application scenario of a half-bridge drive circuit provided in this application;

[0044] Figure 3 A schematic diagram of a half-bridge drive circuit provided in this application Figure 1 ;

[0045] Figure 4 A schematic diagram of a half-bridge drive circuit provided in this application Figure 2 ;

[0046] Figure 5 A schematic diagram of a half-bridge drive circuit provided in this application Figure 3 ;

[0047] Figure 6 A flow chart of a control method for a half-bridge drive circuit provided in the present application;

[0048] Figure 7 This is a timing diagram of the delayed signal, the first output signal, and the second output signal provided in this application.

[0049] Reference numerals:

[0050] M1: Top tube;

[0051] M2: down tube;

[0052] HO: first control signal;

[0053] LO: second control signal;

[0054] Q1: first semiconductor field effect transistor;

[0055] Q2: second semiconductor field effect transistor;

[0056] Q3: the third semiconductor field effect transistor;

[0057] Q4: fourth semiconductor field effect transistor;

[0058] M: motor;

[0059] IN: signal input terminal;

[0060] U1: delay circuit;

[0061] U2: first switch component;

[0062] U3: second switch component;

[0063] Y1: first signal output terminal;

[0064] Y2: second signal output terminal;

[0065] R1: the first delay resistor;

[0066] C1: first delay capacitor;

[0067] PMOS: P-channel metal oxide semiconductor field effect transistor;

[0068] NMOS: N-channel metal oxide semiconductor field effect transistor;

[0069] R2: the second delay resistor;

[0070] C2: the second delay capacitor;

[0071] N1: inverter;

[0072] U4: third switch component;

[0073] U5: fourth switch component;

[0074] U6: fifth switch component;

[0075] U7: Sixth switch component. DETAILED DESCRIPTION

[0076] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0077] Half-bridge drive circuits are widely used in analog devices and power devices, and they precisely control current and voltage by adjusting the on and off time of switching devices, thereby achieving efficient power conversion and management.

[0078] In the prior art, the following can be used: Figure 1 The half-bridge driving circuit shown uses two semiconductor field effect transistors or insulated gate bipolar transistors as switching devices, wherein the first semiconductor field effect transistor or the first insulated gate bipolar transistor is called the upper tube M1, and the second semiconductor field effect transistor or the second insulated gate bipolar transistor is called the lower tube M2;

[0079] The drain of the upper tube M1 is connected to the power supply, the source is connected to the drain of the lower tube M2, and the source of the lower tube M2 is grounded; the half-bridge drive circuit is turned on and off by applying control signals to the gates of the upper tube M1 and the lower tube M2. Usually, two PWM (Pulse Width Modulation) signals are used as the first control signal HO and the second control signal LO input, and the dead time is preset in the program to avoid the upper tube M1 and the lower tube M2 being turned on at the same time, resulting in a shoot-through phenomenon, causing a bridge arm short circuit or transistor damage.

[0080] However, the two PWM signals occupy more port resources, and if the high and low levels set by the program are incorrect, the two control signals will be at high levels at the same time, causing the upper tube M1 and the lower tube M2 to be turned on at the same time, resulting in a shoot-through phenomenon, which reduces the reliability of the half-bridge drive circuit.

[0081] In order to solve the above problems, the core concept of the present application is: a signal input terminal, a delay circuit, a first switch component, a second switch component, a first signal output terminal and a second signal output terminal are set in a half-bridge driving circuit, the signal input terminal receives a single-channel input signal to save port resources, and transmits the input signal to the input terminal of the delay circuit, the first input terminal of the first switch component and the first input terminal of the second switch component respectively; the delay circuit delays the received input signal to obtain a delayed signal, and inputs the delayed signal to the second input terminal of the first switch component and the second input terminal of the second switch component respectively for corresponding processing to generate a corresponding output signal; it ensures that the output signal will not be high at the same time, thereby avoiding the direct-through phenomenon caused by the wrong signal setting, and improving the reliability of the half-bridge driving circuit. Based on this, the present application proposes a half-bridge driving circuit.

[0082] Figure 2 A schematic diagram of an application scenario of a half-bridge drive circuit provided in this application. Figure 2 As shown, in the field of motor drive, there is an H-bridge drive circuit that can control the motor to achieve forward and reverse rotation. To ensure the operation of the motor, a pair of semiconductor field effect transistors on the diagonal must be turned on. When the first semiconductor field effect transistor Q1 and the fourth semiconductor field effect transistor Q4 are turned on, and the second semiconductor field effect transistor Q2 and the third semiconductor field effect transistor Q3 are turned off, the current passes through the motor M from the positive pole of the power supply through the first semiconductor field effect transistor Q1 from left to right, and then returns to the negative pole of the power supply through the fourth semiconductor field effect transistor Q4. At this time, the current will drive the motor M to rotate clockwise. When the second semiconductor field effect transistor Q2 and the third semiconductor field effect transistor Q3 are turned on, and the first semiconductor field effect transistor Q1 and the fourth semiconductor field effect transistor Q4 are turned off, the current flows from the right to the left through the motor M, thereby driving the motor M to rotate in the counterclockwise direction. By controlling the conduction and disconnection of the semiconductor field effect transistor by the drive signal, the forward and reverse rotation of the motor M can be achieved.

[0083] Therefore, the half-bridge drive circuit proposed in the embodiment of the present application is introduced to prevent the first semiconductor field effect transistor Q1 and the second semiconductor field effect transistor Q2 from being turned on at the same time; or to prevent the third semiconductor field effect transistor Q3 and the fourth semiconductor field effect transistor Q4 from being turned on at the same time, causing the current to pass through the semiconductor field effect transistor from the positive pole of the power supply directly back to the negative pole of the power supply, causing a short circuit and damaging the circuit.

[0084] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0085] Figure 3 A schematic diagram of a half-bridge drive circuit provided in this application Figure 1 .like Figure 3 As shown, the half-bridge driving circuit includes: a signal input terminal IN, a delay circuit U1, a first switch component U2, a second switch component U3, a first signal output terminal Y1 and a second signal output terminal Y2;

[0086] The signal input terminal IN is respectively connected to the input terminal of the delay circuit U1, the first input terminal of the first switch component U2 and the first input terminal of the second switch component U3, and is used to input the input signal input to the half-bridge drive circuit to the input terminal of the delay circuit U1, the first input terminal of the first switch component U2 and the first input terminal of the second switch component U3.

[0087] In this embodiment, a single input signal is input to the input end of the delay circuit U1, the first input end of the first switch component U2 and the first input end of the second switch component U3 through the signal input end IN, which reduces the occupancy of the input port and saves port resources.

[0088] The first output end of the delay circuit U1 is connected to the second input end of the first switch component U2, and the second output end of the delay circuit U1 is connected to the second input end of the second switch component U3. The delay circuit U1 is used to delay the input signal to obtain a delayed signal, and input the delayed signal to the second input end of the first switch component U2 and the second input end of the second switch component U3 respectively.

[0089] In this embodiment, the delay circuit U1 generates a delay when the input signal switches between high and low levels, thereby obtaining a dead time; thereby avoiding the situation where the first switch component U2 and the second switch component U3 are turned on at the same time, thereby ensuring the reliability of the half-bridge drive circuit.

[0090] In some embodiments, the delay circuit U1 includes a first delay resistor R1 and a first delay capacitor C1; wherein the first end of the first delay resistor R1 is connected to the signal input end IN, and the second end of the first delay resistor R1 is connected to the first end of the first delay capacitor C1; the second end of the first delay capacitor C1 is grounded.

[0091] In this embodiment, a corresponding delay network is formed by the first delay resistor R1 and the first delay capacitor C1, which is used to control the delay time of the input signal, thereby obtaining the delay limit P1; wherein, the resistance value of the first delay resistor R1 is proportional to the delay time, and the capacitance value of the first delay capacitor C1 is proportional to the delay time.

[0092] In another possible implementation, Figure 4 As shown, in Figure 3 The structure of the half-bridge drive circuit shown in Figure 1 On the basis of, the delay circuit U1 includes a P-channel metal oxide semiconductor field effect transistor PMOS, an N-channel metal oxide semiconductor field effect transistor NMOS, a second delay resistor R2, a second delay capacitor C2 and an inverter N1.

[0093] In this embodiment, the P-channel metal oxide semiconductor field effect transistor PMOS refers to a field effect transistor with a P-type channel, which is turned on when the gate voltage is lower than the source voltage; the N-channel metal oxide semiconductor field effect transistor NMOS refers to a field effect transistor with an N-type channel, which is turned on when the gate voltage is higher than the source voltage.

[0094] A first electrode of the P-channel metal oxide semiconductor field effect transistor PMOS is connected to the signal input terminal IN, a second electrode of the P-channel metal oxide semiconductor field effect transistor PMOS is connected to the power supply voltage VCC, and a third electrode of the P-channel metal oxide semiconductor field effect transistor PMOS is connected to the first end of the second delay resistor R2.

[0095] In this embodiment, the first electrode of the P-channel metal oxide semiconductor field effect transistor PMOS is the gate of the P-channel metal oxide semiconductor field effect transistor PMOS; the second electrode of the P-channel metal oxide semiconductor field effect transistor PMOS is the drain of the P-channel metal oxide semiconductor field effect transistor PMOS; and the third electrode of the P-channel metal oxide semiconductor field effect transistor PMOS is the source of the P-channel metal oxide semiconductor field effect transistor PMOS.

[0096] A first electrode of the N-channel metal oxide semiconductor field effect transistor NMOS is connected to the signal input terminal IN, a second electrode of the N-channel metal oxide semiconductor field effect transistor NMOS is connected to the first end of the second delay resistor R2, and a third electrode of the N-channel metal oxide semiconductor field effect transistor NMOS is grounded.

[0097] In this embodiment, the first electrode of the N-channel metal oxide semiconductor field effect transistor NMOS is the gate of the N-channel metal oxide semiconductor field effect transistor NMOS; the second electrode of the N-channel metal oxide semiconductor field effect transistor NMOS is the drain of the N-channel metal oxide semiconductor field effect transistor NMOS; and the third electrode of the N-channel metal oxide semiconductor field effect transistor NMOS is the source of the N-channel metal oxide semiconductor field effect transistor NMOS.

[0098] The second end of the second delay resistor R2 is connected to the first end of the inverter N1 and the first end of the second delay capacitor C2 respectively;

[0099] The second end of the second delay capacitor C2 is grounded;

[0100] The second end of the inverter N1 is the output end of the delay circuit U1.

[0101] In this embodiment, for example, if the input signal inputted by the signal input terminal IN is at a high level, the P-channel metal oxide semiconductor field effect transistor PMOS is turned off, and the N-channel metal oxide semiconductor field effect transistor NMOS is turned on, so that the input signal is inverted and becomes a low level. At this time, the delay resistor R2 and the delay capacitor C2 form a discharge path, and the inverted input signal is delayed by the N-channel metal oxide semiconductor field effect transistor NMOS, and then inverted again by the inverter N1 to become a high level, thereby obtaining a delayed signal. At this time, the delayed signal is in phase with the input signal.

[0102] If a low level is input to the signal input terminal, the P-channel metal oxide semiconductor field effect transistor PMOS is turned on and the N-channel metal oxide semiconductor field effect transistor NMOS is turned off, so that the input signal is inverted and becomes a high level. At this time, the delay resistor R2 and the delay capacitor C2 form a charging path, and the inverted input signal is delayed by the P-channel metal oxide semiconductor field effect transistor PMOS, and then inverted again by the inverter N1 to become a high level, thereby obtaining a delayed signal. At this time, the delayed signal is in phase with the input signal.

[0103] Specifically, the delay time can be changed by adjusting the resistance of the delay resistor R2 and the capacitance of the delay capacitor C2 to meet different delay requirements.

[0104] The output end of the first switch component U2 is connected to the first signal output end Y1. The first switch component U2 is used to perform a first process on the input signal and the delayed signal to obtain a first output signal, and output the first output signal through the first signal output end Y1.

[0105] In some embodiments, the first switch component U2 is an AND gate.

[0106] In this embodiment, for example, when the input signal and the delayed signal include at least one low level, the first output signal output by the first signal output terminal Y1 is a low level; when the input signal and the delayed signal are both high levels, the first output signal output by the first signal output terminal Y1 is a high level.

[0107] The output end of the second switch component U3 is connected to the second signal output end Y2, and the second switch component U3 is used to perform a second process on the input signal and the delayed signal to obtain a second output signal, and output the second output signal through the second signal output end Y2;

[0108] In some embodiments, the second switch component U3 is a NOR gate.

[0109] In this embodiment, for example, when the input signal and the delayed signal include at least one high level, the second output signal output by the second signal output terminal Y2 is a low level; when the input signal and the delayed signal are both low levels, the second output signal output by the second signal output terminal Y2 is a high level.

[0110] The first output signal and the second output signal are not at high level at the same time.

[0111] In this embodiment, the input signal and the delayed signal are processed accordingly by the first switch component U2 and the second switch component U3 respectively, so that the first output signal and the second output signal are not high level at the same time, avoiding the occurrence of the direct-through phenomenon and improving the reliability of the half-bridge drive circuit.

[0112] Alternatively, if Figure 5 As shown, in Figure 3 The structure of the half-bridge drive circuit shown in Figure 1 On the basis of, the half-bridge driving circuit also includes an interlocking circuit;

[0113] The input end of the interlock circuit is connected to the first signal output end Y1 and the second signal output end Y2 respectively;

[0114] The interlocking circuit is used to perform signal interlocking processing on the first output signal and the second output signal to output a first target output signal and a second target output signal;

[0115] The first output signal and the second output signal are not at high level at the same time.

[0116] In some embodiments, the interlock circuit includes a third switch component U4, a fourth switch component U5, a fifth switch component U6, and a sixth switch component U7;

[0117] The input end of the third switch component U4 is connected to the first signal output end Y1, the output end of the third switch component U4 is connected to the first input end of the fifth switch component U6, and the third switch component U4 is used to invert the first output signal to output a first inverted output signal.

[0118] In this embodiment, the third switch component U4 is an inverter.

[0119] In this embodiment, for example, if the first output signal is at a low level, the third switch component U4 is used to invert the first output signal, and the output first inverted output signal is at a high level; if the first output signal is at a high level, the third switch component U4 is used to invert the first output signal, and the output first inverted output signal is at a low level.

[0120] The input end of the fourth switch component U5 is connected to the second signal output end Y2, the output end of the fourth switch component U5 is connected to the first input end of the sixth switch component U7, and the fourth switch component U5 is used to invert the second output signal to output a second inverted output signal.

[0121] In this embodiment, the fourth switch component U5 is an inverter.

[0122] In this embodiment, for example, if the second output signal is at a low level, the fourth switch component U5 is used to invert the second output signal, and the output second inverted output signal is at a high level; if the second output signal is at a high level, the fourth switch component U5 is used to invert the second output signal, and the output second inverted output signal is at a low level.

[0123] The second input terminal of the fifth switch component U6 is connected to the second signal output terminal Y2, and the fifth switch component U6 is used to perform a third process on the second output signal and the first inverted output signal to output a second target output signal through the output terminal of the fifth switch component U6.

[0124] In this embodiment, the fifth switch component U6 is an AND gate.

[0125] In this embodiment, for example, if the second output signal and the first inverted output signal are both high levels, the second target output signal output through the output end of the fifth switch component U6 is a high level; if the second output signal and the first inverted output signal include at least one low level, the second target output signal output through the output end of the fifth switch component U6 is a low level.

[0126] The second input terminal of the sixth switch component U7 is connected to the first signal output terminal Y1, and the sixth switch component U7 is used to perform a fourth process on the first output signal and the second inverted output signal to output a second target output signal through the output terminal of the sixth switch component U7.

[0127] In this embodiment, the sixth switch component U7 is an AND gate.

[0128] In this embodiment, for example, if the first output signal and the second inverted output signal are both high levels, the second target output signal output through the output end of the sixth switch component U7 is a high level; if the first output signal and the second inverted output signal include at least one low level, the second target output signal output through the output end of the sixth switch component U7 is a low level.

[0129] In this embodiment, if the first output signal and the second output signal include at least one low level, the second target output signal is output through the output end of the fifth switch component U6, and the second target output signal output through the output end of the sixth switch component U7 is both low level; if the first output signal and the second output signal are complementary signals, the second target output signal is output through the output end of the fifth switch component U6, and the second target output signal output through the output end of the sixth switch component U7 is a complementary signal; the interlocking circuit ensures the interlocking between the two second target output signals. When the delay circuit U1, the first switch component U2 or the second switch component U3 fails, it can also prevent the half-bridge drive circuit from outputting high-level signals at the same time, causing a through phenomenon and damaging the half-bridge drive circuit, further improving the reliability of the half-bridge drive circuit.

[0130] Figure 6 A flow chart of a control method for a half-bridge drive circuit provided in the present application is shown as follows: Figure 6 As shown, this method is applied to Figure 3 The half-bridge driving circuit shown in the figure comprises:

[0131] S601 , input an input signal to a signal input terminal, so as to input the input signal to an input terminal of a delay circuit, a first input terminal of a first switch component, and a first input terminal of a second switch component respectively.

[0132] In some embodiments, the input signal is a sine wave signal, a triangle wave signal, a square wave signal, or a pulse width modulation signal.

[0133] In this embodiment, for example, if the input signal is a sine wave signal or a triangular wave signal, since there is a threshold voltage in the delay circuit, the first switch component and the second switch component, when the voltage of the input signal is higher than the threshold voltage, the input signal is a high level; when the voltage of the input signal is lower than the threshold voltage, the input signal is a low level.

[0134] S602 , delay the input signal through a delay circuit to obtain a delayed signal, and input the delayed signal to the second input end of the first switch component and the second input end of the second switch component respectively.

[0135] In this embodiment, the delay circuit generates a delay when the input signal switches between high and low levels, thereby obtaining a dead time.

[0136] S603: Perform a first process on the input signal and the delayed signal through a first switch component to obtain a first output signal, and output the first output signal through a first signal output terminal.

[0137] In this embodiment, the first switch component performs a first processing on the input signal and the delayed signal. When the input signal and the delayed signal are both at a high level, the obtained first output signal is a high level; when the input signal and the delayed signal include at least one low level, the obtained first output signal is a low level.

[0138] S604, performing a second process on the input signal and the delayed signal through a second switch component to obtain a second output signal, and outputting the second output signal through a second signal output terminal; wherein the first output signal and the second output signal are not at high level at the same time.

[0139] In this embodiment, the second switch component performs a second processing on the input signal and the delayed signal. When the input signal and the delayed signal are both at a low level, the obtained second output signal is a high level; when the input signal and the delayed signal include at least one high level, the obtained second output signal is a low level.

[0140] For example, if the input signal is a square wave signal, the timing diagram of the delay signal, the first output signal, and the second output signal is as follows: Figure 7 As shown, from t0 to t1, the input signal remains at a low level, at this time, the delay signal is at a low level, the first output signal is at a low level, and the second output signal is at a high level; at t1, the input signal changes from a low level to a high level, the delay signal and the first output signal change to a high level after a delay time t2, and the first output signal immediately changes to a low level at t1; from t2 to t3, the input signal remains at a high level, then the delay signal is at a high level, the first output signal is at a high level, and the second output signal is at a low level; at t3, the input signal changes from a high level to a low level, the first output signal immediately changes to a low level at t3, the delay signal changes to a low level after a delay time t4, and the second output signal changes to a high level after a delay time t4.

[0141] The control method of the half-bridge drive circuit proposed in the present application saves port resources through a single-channel input signal, and delays the input signal through a delay circuit to obtain a delayed signal, and inputs the delayed signal and the input signal into the first switch component and the second switch component respectively for corresponding processing to obtain a corresponding output signal, so as to ensure that the output signal is not a high-level signal at the same time, avoid the direct-through phenomenon, cause damage to the half-bridge drive circuit, and improve the reliability of the half-bridge drive circuit.

[0142] Finally, it should be noted that those skilled in the art will readily conceive of other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses or adaptations of the present invention, which follow the general principles of the present invention and include common knowledge or customary technical means in the art not disclosed by the present invention, are not limited to the precise structure described above and shown in the drawings, and may be modified and changed in various ways without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A half-bridge driving circuit, characterized in that: It includes a signal input terminal, a delay circuit, a first switch component, a second switch component, a first signal output terminal and a second signal output terminal; The signal input end is respectively connected to the input end of the delay circuit, the first input end of the first switch component and the first input end of the second switch component, and is used to input the input signal input to the half-bridge drive circuit to the input end of the delay circuit, the first input end of the first switch component and the first input end of the second switch component respectively; The first output end of the delay circuit is connected to the second input end of the first switch component, and the second output end of the delay circuit is connected to the second input end of the second switch component. The delay circuit is used to perform delay processing on the input signal to obtain a delayed signal, and input the delayed signal to the second input end of the first switch component and the second input end of the second switch component respectively; The output end of the first switch component is connected to the first signal output end, and the first switch component is used to perform a first process on the input signal and the delayed signal to obtain a first output signal, and output the first output signal through the first signal output end; The output end of the second switch component is connected to the second signal output end, and the second switch component is used to perform a second process on the input signal and the delayed signal to obtain a second output signal, and output the second output signal through the second signal output end; The first output signal and the second output signal are not at high level at the same time.

2. The half-bridge driving circuit according to claim 1, characterized in that: The first switch component is an AND gate, and the second switch component is a NOR gate.

3. The half-bridge driving circuit according to claim 1, characterized in that: Also included is an interlock circuit; The input end of the interlock circuit is connected to the first signal output end and the second signal output end respectively; The interlock circuit is used to perform signal interlock processing on the first output signal and the second output signal to output a first target output signal and a second target output signal; The first output signal and the second output signal are not at high level at the same time.

4. The half-bridge driving circuit according to claim 3, characterized in that: The interlock circuit includes a third switch component, a fourth switch component, a fifth switch component and a sixth switch component; The input end of the third switch component is connected to the first signal output end, the output end of the third switch component is connected to the first input end of the fifth switch component, and the third switch component is used to invert the first output signal to output a first inverted output signal; The input end of the fourth switch component is connected to the second signal output end, the output end of the fourth switch component is connected to the first input end of the sixth switch component, and the fourth switch component is used to invert the second output signal to output a second inverted output signal; The second input terminal of the fifth switch component is connected to the second signal output terminal, and the fifth switch component is used to perform a third process on the second output signal and the first inverted output signal to output a second target output signal through the output terminal of the fifth switch component; The second input terminal of the sixth switch component is connected to the first signal output terminal, and the sixth switch component is used to perform a fourth process on the first output signal and the second inverted output signal to output a second target output signal through the output terminal of the sixth switch component.

5. The half-bridge driving circuit according to claim 4, characterized in that: The third switch component and the fourth switch component are inverters.

6. The half-bridge driving circuit according to claim 5, characterized in that: The fifth switch component and the sixth switch component are AND gates.

7. The half-bridge driving circuit according to any one of claims 1 to 6, characterized in that: The delay circuit includes a first delay resistor and a first delay capacitor; The first end of the first delay resistor is connected to the signal input end, and the second end of the first delay resistor is connected to the first end of the first delay capacitor; The second end of the first delay capacitor is grounded.

8. The half-bridge driving circuit according to any one of claims 1 to 6, characterized in that: The delay circuit includes a P-channel metal oxide semiconductor field effect transistor, an N-channel metal oxide semiconductor field effect transistor, a second delay resistor, a second delay capacitor and an inverter; A first electrode of the P-channel metal oxide semiconductor field effect transistor is connected to the signal input terminal, a second electrode of the P-channel metal oxide semiconductor field effect transistor is connected to a power supply voltage, and a third electrode of the P-channel metal oxide semiconductor field effect transistor is connected to a first end of the second delay resistor; The first electrode of the N-channel metal oxide semiconductor field effect transistor is connected to the signal input terminal, the second electrode of the N-channel metal oxide semiconductor field effect transistor is connected to the first end of the second delay resistor; the third electrode of the N-channel metal oxide semiconductor field effect transistor is grounded; The second end of the second delay resistor is connected to the first end of the inverter and the first end of the second delay capacitor respectively; The second end of the second delay capacitor is grounded; The second end of the inverter is the output end of the delay circuit.

9. A control method for a half-bridge drive circuit, characterized in that: Applied to the half-bridge driving circuit according to any one of claims 1 to 8, the method comprises: Inputting an input signal to the signal input terminal, so as to input the input signal to the input terminal of the delay circuit, the first input terminal of the first switch component, and the first input terminal of the second switch component respectively; Delaying the input signal through the delay circuit to obtain a delayed signal, and inputting the delayed signal to the second input end of the first switch component and the second input end of the second switch component respectively; Performing a first process on the input signal and the delayed signal through the first switch component to obtain a first output signal, and outputting the first output signal through the first signal output terminal; Performing a second process on the input signal and the delayed signal through the second switch component to obtain a second output signal, and outputting the second output signal through the second signal output terminal; The first output signal and the second output signal are not at high level at the same time.

10. The method according to claim 9, characterized in that The input signal is a sine wave signal, a triangle wave signal, a square wave signal or a pulse width modulation signal.

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