Power supply system with power factor correction and control method thereof

Abstract

The invention discloses a power supply system with power factor correction and a control method thereof. The power supply system with the power factor correction function comprises an alternating current rectifier, a power factor correction conversion circuit, an asymmetric half-bridge flyback converter and a communication protocol power supply transmission interface. When the power of the adapter output power supply is lower than a power threshold value and the conversion voltage of the conversion power supply is higher than a first voltage threshold value, the communication protocol power supply transmission interface generates a forbidding signal to forbid power factor correction conversion in the power factor correction conversion circuit; wherein when the power factor correction conversion is prohibited, the conversion circuit performs bypass coupling operation, so that the conversion voltage is equal to the rectified voltage of the rectified power supply.

Description

Technical Field

[0001] The present invention relates to a power supply system with power factor correction, and more particularly to a power supply system that can determine whether to prohibit power factor correction conversion according to the output power of an adapter. The present invention also relates to a power supply system control method for controlling the power supply system. Background Art

[0002] Please refer to Figure 1A , Figure 1A is a schematic diagram of a power supply system 100 of the prior art. Figure 1A As shown, the power supply system 100 of the prior art includes an AC rectifier 1, a power factor correction (PFC) conversion circuit 10, a flyback power converter 15, and a communication protocol (protocol) power delivery (PD) interface 40. The AC rectifier 1 rectifies the AC input voltage VAC to generate a rectified voltage VBD, and the power factor correction conversion circuit 10 is used to perform power factor correction conversion to convert the rectified voltage VBD to generate a power factor correction conversion voltage VPFC. The power factor correction conversion circuit 100 includes a boost power stage circuit to boost and convert the rectified voltage VBD into a PFC conversion voltage VPFC, wherein the power factor correction conversion circuit 100 is used to correct the power factor (PowerFactor) of the power supply system 100.

[0003] Please refer to Figure 1B , Figure 1B : is a waveform diagram of the rectified voltage VBD and the PFC conversion voltage VPFC in the power supply system of the prior art. Figure 1B As shown, after rectification by the AC rectifier 1, the waveform of the rectified voltage VBD is a full wave rectified sinewave above zero, and the power factor correction conversion circuit 10 performs PFC conversion to generate a DC PFC conversion voltage VPFC, wherein the PFC conversion voltage VPFC is usually a fixed value higher than the peak value of the rectified voltage VBD.

[0004] The flyback power converter 15 is used to convert the PFC conversion voltage VPFC in a DC-DC manner to generate an adapter output voltage VDD, and supply power to the communication protocol PD interface 40. The communication protocol PD interface 40 is used to transmit relevant information to the DC-DC power converter 15 according to the first communication protocol information PRT1 to determine the adapter output voltage VDD. The communication protocol PD interface 40 also controls the power path switch MBUS therein to transmit the adapter output voltage VDD to the power supply pin VBUS therein, and then supply the adapter output voltage VDD to the circuit coupled to the outside (not shown). The aforementioned power supply system 100 is often used in a traditional travel adapter (traveleradaptor) with relatively fixed output power and output voltage.

[0005] Travel adapters that comply with the latest universal serial bus power delivery (USBPD) specification need to provide output power from 5V / 5A (i.e. 25W) to 20V / 5A (i.e. 100W). According to the USB PD extended power range (EPR) protocol, the maximum output power can reach 48V / 5A (i.e. 240W). According to the IEC61000-3-2 standard, electrical appliances with an input power of 75W or more (Class-D devices) must comply with the maximum amplitude limit of line-frequency harmonics up to the 39th harmonic. Therefore, a USB PD travel adapter with an output power of no less than 75W should have the following features: Figure 1A The power supply system 100 including the power factor correction (PFC) conversion circuit 10 is shown to minimize line frequency harmonics. For the application of the USB PD EPR travel adapter, it is necessary to generate a PFC conversion voltage VPFC of, for example, 400V for a generally common AC input voltage VAC range, such as from 85 to 265Vrms, and the adapter output voltage VDD range is, for example, from 5V to 48V.

[0006] One of the disadvantages of implementing a USB PD EPR travel adapter with the above-mentioned prior art power supply system 100 is that, under the premise that the voltage level of the conversion voltage VPFC is fixed at 400V, in applications where the rectified voltage VBD is low (e.g., 85Vrms), and / or the output voltage VDD of the adapter (e.g., below 20V) or the output power power is low, the energy loss of the power supply system 100 is relatively high, resulting in a relatively low conversion efficiency.

[0007] In addition, when the flyback power converter 15 converts the PFC conversion voltage VPFC into the adapter output voltage VDD, the conventional flyback power converter 15 is not easy to achieve zero voltage switching (ZVS) and has higher voltage stress, thus resulting in lower conversion efficiency and higher cost.

[0008] For other related prior art, please refer to US Pat. No. 11411489 and US Pat. No. 6768655.

[0009] In view of this, the present invention aims at the above-mentioned shortcomings of the prior art and proposes a power supply system and a control method thereof that can determine whether to prohibit power factor correction conversion according to the output power of the adapter. Since the present invention can determine whether to prohibit power factor correction conversion according to the output power of the adapter, it can reduce energy loss and improve conversion efficiency. Summary of the invention

[0010] The present invention provides a power supply system with power factor correction, comprising: an AC rectifier for rectifying an AC input power supply to generate a rectified power supply; a power factor correction (PFC) conversion circuit for performing a PFC conversion on the rectified power supply to generate a converted power supply, and determining whether to disable the PFC conversion according to a prohibition signal; an asymmetric half-bridge (AHB) flyback converter for converting the converted power supply from DC to DC to generate an adapter output power supply; and a communication protocol (protocol) power delivery (PD) interface for determining the adapter output power supply according to a first communication protocol information, and controlling one of the power path switches to transmit the adapter output power supply to one of the power supply pins; wherein, when the power of the adapter output power supply is lower than a power threshold and a conversion voltage of the converted power supply is higher than a first voltage threshold, the communication protocol PD interface generates the prohibition signal to prohibit the PFC conversion in the PFC conversion circuit.

[0011] The present invention also provides a power supply system control method, comprising: rectifying an AC input power supply to generate a rectified power supply; performing a PFC conversion on the rectified power supply to generate a converted power supply, and determining whether to disable the PFC conversion according to a prohibition signal; DC-DC converting the converted power supply to generate an adapter output power supply; determining the adapter output power supply according to a first communication protocol information, and controlling a power path switch to transmit the adapter output power supply to a power supply pin; when the power of the adapter output power supply is lower than a power threshold and a conversion voltage of the converted power supply is higher than a first voltage threshold, generating the prohibition signal to prohibit the PFC conversion; and when the PFC conversion is prohibited, performing a bypass coupling operation so that the conversion voltage is equal to a rectified voltage of the rectified power supply.

[0012] In some embodiments, when the PFC conversion is disabled, the PFC conversion circuit performs a bypass coupling operation so that the conversion voltage is equal to a rectified voltage of the rectified power source.

[0013] In some embodiments, when the PFC conversion circuit disables the PFC conversion, when the conversion voltage is lower than a second voltage threshold, the disable signal stops disabling the PFC conversion, wherein the first voltage threshold is not lower than the second voltage threshold.

[0014] In some embodiments, the conversion circuit includes a boost follower.

[0015] In some embodiments, the power supply system with power factor correction further includes an opto-coupler coupled between the communication protocol PD interface and the PFC conversion circuit to transmit the disable signal from the communication protocol PD interface to the PFC conversion circuit.

[0016] In some embodiments, the communication protocol PD interface determines whether the power of the adapter output power is lower than the power threshold according to a current sensing signal of an adapter output current of the adapter output power sensed by a current sensing circuit coupled to the AHB flyback converter.

[0017] In some embodiments, the communication protocol PD interface determines whether the power of the adapter output power is lower than the power threshold based on an adapter output voltage of the adapter output power, a conduction state of the power path switch and / or a second communication protocol information of the communication protocol PD interface.

[0018] In some embodiments, the first voltage threshold is related to an adapter output voltage of the adapter output power.

[0019] In some embodiments, the communication protocol PD interface determines whether the conversion voltage is higher than the first voltage threshold based on whether a second winding voltage of the AHB flyback converter is higher than a winding voltage threshold, wherein the winding voltage threshold is related to an adapter output voltage of the adapter output power supply or a turns ratio of a primary winding to a secondary winding of a transformer of the AHB flyback converter.

[0020] In some embodiments, the communication protocol PD interface further determines whether the conversion voltage is higher than the first voltage threshold according to a maximum duty cycle of the AHB flyback converter.

[0021] In some embodiments, the communication protocol PD interface determines that the power of the adapter output power is lower than a power threshold based on an adapter output voltage of the adapter output power being lower than a first adapter output voltage threshold, wherein the first adapter output voltage threshold is related to an upper limit of an adapter output current of the adapter output power.

[0022] In some embodiments, when the PFC conversion circuit prohibits the PFC conversion, when the communication protocol PD interface determines that the power of the adapter output power is not less than the power threshold based on the adapter output voltage being higher than a second adapter output voltage threshold, the prohibition signal stops prohibiting the PFC conversion.

[0023] The following will be described in detail through specific embodiments to make it easier to understand the purpose, technical content, characteristics and effects achieved by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1A is a schematic diagram of a power supply system in the prior art.

[0025] Figure 1B It is a waveform diagram of input voltage and output voltage in a power supply system of the prior art.

[0026] Figure 2 An embodiment of a power supply system with power factor correction of the present invention is shown.

[0027] Figure 3 A more specific embodiment of the power supply system with power factor correction of the present invention is shown.

[0028] Figure 4 It is an operation waveform diagram of a relevant voltage in the power supply system of an embodiment of the present invention.

[0029] Figure 5 is a block diagram of an embodiment of a power supply system of the present invention.

[0030] Fig. 6A and Figure 6BIt is a schematic diagram of an embodiment of a power factor correction conversion circuit in a power supply system of the present invention.

[0031] Figure 7 A schematic diagram showing the hysteresis relationship between the conversion voltage VCN and the disable signal DIS in an embodiment of the present invention.

[0032] Figure 8 The schematic diagram shows the coupling relationship between the control chip 41 of the communication protocol PD interface, the optical coupler OC and the power factor correction control circuit 22 in one embodiment of the present invention.

[0033] Fig. 9 The schematic diagram shows the coupling relationship between the control chip 41 of the communication protocol PD interface, the optical coupler OC and the power factor correction control circuit 22 in one embodiment of the present invention.

[0034] Fig.10 It is a flow chart of an embodiment of a power factor correction conversion circuit in a power supply system of the present invention.

[0035] Explanation of symbols in the figure

[0036] 1: AC rectifier

[0037] 10: Power factor correction conversion circuit

[0038] 15: Flyback Power Converter

[0039] 20: PFC conversion circuit

[0040] 21: Power stage circuit

[0041] 22: Power factor correction control circuit

[0042] 30: AHB flyback converter

[0043] 31: Power stage circuit

[0044] 33: Transformer

[0045] 34: Synchronous Rectifier

[0046] 40: Communication protocol PD interface

[0047] 200: Power supply system

[0048] 401: USB PD protocol controller

[0049] 402: Multifunction Device

[0050] 403: Analog-to-digital converter

[0051] 404: Control signal generator

[0052] DIS: Disable signal

[0053] Dw: diode

[0054] D+, D-, CC1, CC2: pins

[0055] GD: switch operation signal

[0056] GND: Ground potential

[0057] HGATE: upper bridge switch signal

[0058] ILm: Inductor current

[0059] ILr: resonant inductor current

[0060] Iout: output current

[0061] Isec: sensing current

[0062] Lm: Inductance

[0063] LGATE: lower bridge switch signal

[0064] Lr: resonant inductance

[0065] M1, M2, Sw: Switch

[0066] MBUS: Power Path Switch

[0067] n: Turn ratio

[0068] Np: primary winding

[0069] Ns: Secondary winding

[0070] OC: Optocoupler

[0071] Pmax: The maximum power of the adapter output power

[0072] Pout: The power of the adapter output power

[0073] PWM: Modulation Signal

[0074] PRT1: First communication protocol information

[0075] RCS: Sense resistor

[0076] S11~S19: Steps

[0077] t1, t2, t3, t4, t5: time points

[0078] SWb: Bypass switch

[0079] VAC: AC input voltage

[0080] VBD: rectified voltage

[0081] VBUS: power supply pin

[0082] VCN: conversion voltage

[0083] VCS: Current sensing signal

[0084] VDD: adapter output voltage

[0085] Vd: synchronous rectification voltage

[0086] Vds1, Vds2: drain-source voltage

[0087] VF: Feedback voltage

[0088] Vgs1, Vgs2: gate-source voltage

[0089] VPFC: PFC conversion voltage

[0090] VRH: High level

[0091] VRL: Low Level

[0092] VTH1: First voltage threshold

[0093] VTH2: Second voltage threshold DETAILED DESCRIPTION

[0094] The drawings in the present invention are schematic, and are mainly intended to show the coupling relationship between the various circuits and the relationship between the various signal waveforms. The circuits, signal waveforms and frequencies are not drawn according to scale. For the purpose of clarity, many practical details will be described in the following description, but this is not intended to limit the scope of the patent application of the present invention.

[0095] Please refer to Figure 2 , Figure 2 An embodiment of the power supply system with power factor correction of the present invention is shown. Figure 2As shown, in one embodiment, a power supply system 200 with power factor correction includes: an AC rectifier 1, a power factor correction (PFC) conversion circuit 20, an asymmetric half-bridge (AHB) flyback converter 30, and a communication protocol (protocol) power delivery (PD) interface 40. In one embodiment, the AC rectifier 1 is used to rectify the AC input power to generate a rectified power. The AC input power includes an AC input voltage VAC, and the rectified power includes a rectified voltage VBD. The PFC conversion circuit 20 is used to perform PFC conversion on the rectified power to generate a converted power, and determine whether to disable the PFC conversion according to a disable signal DIS. The converted power includes a converted voltage VCN. The AHB flyback converter 30 is used to convert the converted power in a DC-DC manner to generate an adapter output power, wherein the adapter output power includes an adapter output voltage VDD.

[0096] like Figure 2 As shown, the communication protocol PD interface 40 is used to transmit relevant information to the AHB flyback converter 30 according to the first communication protocol information PRT1 to determine the adapter output power. The communication protocol PD interface 40 also controls the power path switch MBUS therein to transmit the adapter output power to the power supply pin VBUS therein, thereby supplying the adapter output power to the circuit coupled to the outside.

[0097] According to the present invention, when the power of the adapter output power supply is lower than the power threshold and the conversion voltage VCN of the converted power supply is higher than the first voltage threshold, the communication protocol PD interface 40 generates a disable signal DIS to disable the PFC conversion in the PFC conversion circuit 20.

[0098] In one embodiment, when the PFC conversion is disabled, the PFC conversion circuit 20 performs a bypass coupling operation so that the conversion voltage VCN is equal to the rectified voltage VBD of the rectified power supply. Figure 2 As shown, the PFC conversion circuit 20 performs a bypass coupling operation, controls the bypass switch SWb to be turned on, and electrically connects the conversion voltage VCN to the rectified voltage VBD.

[0099] Please refer to Figure 3 , Figure 3 A more specific embodiment of the power supply system with power factor correction of the present invention is shown. Figure 3As shown, the power supply system 200 with power factor correction includes an AC rectifier 1 , a PFC conversion circuit 20 , an AHB flyback converter 30 and a communication protocol power delivery (PD) interface 40 .

[0100] In this embodiment, the power factor correction conversion circuit 20 includes: a power stage circuit 21 and a power factor correction control circuit 22. In one embodiment, the power stage circuit 21 is, for example, a boost power stage circuit, including at least one switch and an inductor L. In this embodiment, at least one switch in the power stage circuit 21 includes a switch Sw and a diode Dw, the switch Sw corresponds to the lower bridge switch of the power stage circuit 21, the diode Dw corresponds to the upper bridge switch of the power stage circuit 21, the switch Sw is an N-type metal oxide semiconductor (MOS) element, and in other embodiments, the diode Dw can also be a switch. In one embodiment, the power factor correction conversion circuit 20 enables PFC conversion to correct the power factor of the rectified power supply to generate a converted power supply. The power factor correction control circuit 22 generates a switch operation signal GD according to a feedback signal FB related to the conversion voltage VCN, operates the switch Sw, and performs PFC conversion on the rectified power supply to generate a converted power supply; and determines whether to disable PFC conversion according to a disable signal DIS.

[0101] The power supply system 200, for example but not limited to, adjusts the conversion voltage VCN to a fixed level, in one embodiment, for example, 400V; corresponding to a relatively low AC input voltage VAC, such as 85Vrms. In addition, in one embodiment, the PFC conversion circuit 20 includes a boost follower, which is a circuit whose output voltage follows the input voltage. The PFC conversion circuit 20 with the boost follower adjusts the conversion voltage VCN to a fixed level higher than the peak value of the AC input voltage VAC, and can adjust the conversion voltage VCN according to the rectified voltage VBD, so that the conversion voltage VCN is positively correlated with the rectified voltage VBD; and the PFC conversion circuit 20 with the boost follower has a smaller overall circuit area, and can use a lower-priced inductor, so that the power loss can be reduced during the switching period and conduction time of the switch Sw, thereby improving the power conversion efficiency and reducing the cost.

[0102] In this embodiment, the AHB flyback converter 30 includes a power stage circuit 31 with a buck characteristic, a power stage control circuit 32, a transformer 33, and a synchronous rectifier (SR) 34. The power stage control circuit 32 generates an upper bridge switch signal HGATE and a lower bridge switch signal LGATE to control switches M1 and M2 respectively, so as to switch one end of the resonant inductor Lr in the power stage circuit 31 with a buck characteristic between the conversion voltage VCN and the ground potential GND, so as to step down the conversion voltage VCN to input the transformer 33, and then convert it into the adapter output voltage VDD. The synchronous rectifier 34 is used to synchronously rectify the adapter output voltage VDD, which includes a synchronous rectification switch and a diode to improve the rectification efficiency and reduce energy loss. The node between the synchronous rectifier 34 and the secondary winding Ns of the transformer 33 has a synchronous rectification voltage Vd, which can be used to indicate the level of the conversion voltage VCN.

[0103] The power supply system 200 uses an asymmetric half-bridge (AHB) flyback converter 30 to replace the conventional flyback converter to achieve zero voltage switching and lower voltage stress of switches M1 and M2, thereby having higher power conversion efficiency. Unlike the conventional flyback converter, which is a buck-boost power stage circuit, the AHB flyback converter 30 includes a power stage circuit 31 with buck characteristics, wherein the output end of the AHB flyback converter 30 generates an adapter output voltage VDD lower than the conversion voltage VCN at the input end. In the case of the M1 and M2 switches switching in a complementary steady state, the adapter output voltage VDD at the output end of the AHB flyback converter 30 is the conversion voltage VCN divided by n, and then multiplied by the maximum duty cycle of the upper bridge switch operation signal HGATE of the AHB flyback converter (whose value is less than 1). Where n is the turns ratio of the primary winding Np and the secondary winding Ns of the transformer 33 (n=Np / Ns). In addition, the AHB flyback converter 30 can achieve zero voltage switching (ZVS) in the power switch of the power stage circuit 31 with a step-down characteristic, thereby further reducing switching loss.

[0104] The communication protocol PD interface 40 is used to transmit relevant information to the AHB flyback converter 30 according to the first communication protocol information PRT1, so as to determine the adapter output power, and control the power path switch MBUS therein to transmit the adapter output power to the power supply pin VBUS therein, and the pin GND is electrically connected to the ground potential. The communication protocol PD interface 40 is a communication protocol related to power transmission (supply and / or receive power), which is, for example but not limited to, a universal serial bus (USB) PD. The enlarged view of the control chip 41 of the USB PD interface is shown in FIG. Figure 3 As shown in the figure below. The first communication protocol information PRT1 is, for example, in the USB PD interface, through the pins D+, D-, CC1, CC2, etc., the USB PD interface of the circuit at the other end connected to the USB PD interface (not shown, such as the battery circuit of a mobile phone or computer powered by the power supply system 200) communicates to obtain the target level of the adapter output voltage VDD of the adapter output power or other information such as the sensing voltage and sensing current, and transmits relevant instructions to the PFC conversion circuit 20 and the AHB flyback converter 30 according to the first communication protocol information PRT1, so as to adjust the adapter output power to the needs of the circuit at the other end connected to the USB PD interface.

[0105] According to the present invention, when the power of the adapter output power is lower than the power threshold, for example but not limited to when the power of the adapter output power is lower than 75W, and the conversion voltage VCN of the conversion power is higher than the first voltage threshold, the communication protocol PD interface 40 generates a disable signal DIS to disable the PFC conversion in the PFC conversion circuit 20, thereby improving the overall conversion efficiency of the power supply system 200. In one embodiment, when the PFC conversion is disabled, the PFC conversion circuit 20 performs a bypass coupling operation, so that the conversion voltage VCN is equal to the rectified voltage VBD of the rectified power supply.

[0106] Generally speaking, when the PFC converter 20 does not have a boost follower, the conversion voltage VCN is maintained at a relatively high level (e.g., 400V) to allow the AHB flyback converter 30 to operate under the conditions of a lower AC input voltage VAC and a higher conversion voltage VCN. However, when the PFC operates under the conditions of a lower AC input voltage VAC and a higher conversion voltage VCN, the PFC conversion voltage ratio is large and the PFC conversion efficiency is low.

[0107] In order to improve the PFC efficiency, a PFC conversion circuit 20 with a boost follower is used, and the conversion voltage VCN is converted proportionally with the AC input voltage VAC to improve the PFC efficiency. When the power of the adapter output power is lower than the power threshold, for example but not limited to when the power of the adapter output power is lower than 75W, when the AC input voltage VAC is low (such as 85Vrms), if the PFC conversion in the PFC conversion circuit 20 is prohibited, the PFC conversion circuit 20 performs a bypass coupling operation, and the conversion voltage VCN is equal to the rectified voltage VBD of the rectified power supply, which may not be enough for the AHB flyback converter 30 to generate the required adapter output voltage VDD (such as 48V).

[0108] In order to make the power supply system 200 including the PFC converter 20 including the boost follower and the AHB flyback converter 30 with an adjustable adapter output voltage VDD have better power conversion efficiency, when the power of the adapter output power of the AHB flyback converter 30 is lower than the power threshold, for example but not limited to less than 75W, and when the conversion voltage VCN is sufficient to enable the AHB flyback converter 30 to generate the required adapter output voltage VDD, the communication protocol PD interface 40 generates a disable signal DIS to disable the PFC conversion in the PFC conversion circuit 20. In one embodiment, a bypass coupling operation is performed, for example, the switch Sw is constantly turned off when the PFC conversion in the PFC conversion circuit 20 is disabled, or a bypass coupling path is provided, so that the conversion voltage VCN is equal to the rectified voltage VBD, so as to improve the power conversion efficiency.

[0109] In one embodiment, when the PFC conversion circuit 20 disables PFC conversion, when the conversion voltage VCN is lower than the second voltage threshold, the disable signal DIS stops disabling PFC conversion, wherein the first voltage threshold is not lower than the second voltage threshold, so that there is a hysteresis effect between disabling PFC conversion and stopping disabling PFC conversion. In one embodiment, when the disable signal DIS stops disabling PFC conversion, the PFC conversion circuit 20 performs PFC conversion on the rectified power supply to generate a converted power supply.

[0110] In one embodiment, the communication protocol PD interface 40 determines whether the power of the adapter output power is lower than the power threshold based on the current sensing signal VCS of the adapter output current of the adapter output power sensed by the current sensing circuit 42 coupled to the AHB flyback converter 30, wherein the current sensing circuit 42, for example, includes a sensing resistor RCS for sensing the sensing current Isec flowing through the sensing resistor RCS to output the current Iout, the conduction state of the switch in the synchronous rectifier 34, and the conduction state of the power path switch MBUS.

[0111] In one embodiment, the communication protocol PD interface 40 determines whether the power of the adapter output power is lower than the power threshold according to the adapter output voltage VDD of the adapter output power, the conduction state of the power path switch MBUS and / or the second communication protocol information of the communication protocol PD interface 40. The second communication protocol information is, for example, the target level of the adapter output voltage VDD of the adapter output power or other information such as the sensing voltage and sensing current obtained by the USB PD interface through the pins D+, D-, CC1, CC2, etc., and the USB PD interface of the circuit at the other end connected to the USB PD interface (not shown, such as the battery circuit of the mobile phone or computer powered by the power supply system 200). The second communication protocol information may be the first communication protocol information, or include part of the first communication protocol information, or may not include the first communication protocol information.

[0112] In one embodiment, if Figure 3 As shown, the power factor corrected power supply system 200 further includes an opto-coupler OC coupled between the communication protocol PD interface 40 and the PFC conversion circuit 20 to transmit the disable signal DIS from the communication protocol PD interface 40 to the PFC conversion circuit 20 .

[0113] In one embodiment, the first voltage threshold is related to the adapter output voltage VDD of the adapter output power. From another point of view, the level of the first voltage threshold is used to ensure that the adapter output voltage VDD is sufficient to enable the AHB flyback converter 30 to convert the conversion voltage VCN into the required adapter output voltage VDD. In detail, since the PFC conversion is prohibited, in one embodiment, the PFC conversion circuit 20 is operated with bypass coupling so that the conversion voltage VCN is equal to the rectified voltage VBD to improve the power conversion efficiency. At this time, it is necessary to confirm whether the AHB flyback converter 30 of the power stage circuit with buck characteristics can convert the conversion voltage VCN into the adapter output voltage VDD. Therefore, it is necessary to confirm that under the bypass coupling operation, the level of the conversion voltage VCN is sufficient to provide the required adapter output voltage VDD after the buck conversion of the AHB flyback converter 30. Therefore, when the power of the adapter output power supply is lower than the power threshold, before disabling PFC conversion, it is necessary to confirm whether the conversion voltage VCN is higher than the first voltage threshold, wherein the first voltage threshold is related to the adapter output voltage VDD adjusted to the desired target, so that the AHB flyback converter 30 can still generate the adapter output voltage VDD to the desired target when the conversion voltage VCN is higher than the first voltage threshold.

[0114] In one embodiment, the communication protocol PD interface 40 determines whether the conversion voltage VCN is higher than the first voltage threshold based on whether the synchronous rectification voltage Vd of the AHB flyback converter 30 is higher than the winding voltage threshold, wherein the winding voltage threshold is related to the adapter output voltage VDD or the turns ratio (n) of the primary winding Np and the secondary winding Ns of the transformer 33 of the AHB flyback converter 30.

[0115] In one embodiment, the communication protocol PD interface 40 further determines whether the conversion voltage VCN is higher than the first voltage threshold according to the maximum duty cycle of the AHB flyback converter 30 .

[0116] In one embodiment, the communication protocol PD interface 40 determines that the power of the adapter output power is lower than the power threshold based on the adapter output voltage VDD of the adapter output power being lower than the first adapter output voltage threshold, wherein the first adapter output voltage threshold is related to the upper limit of the adapter output current of the adapter output power.

[0117] In one embodiment, when the PFC conversion circuit 20 prohibits PFC conversion, when the communication protocol PD interface 40 determines that the power of the adapter output power is not less than the power threshold according to the adapter output voltage VDD being higher than the second adapter output voltage threshold, the prohibition signal stops prohibiting PFC conversion.

[0118] Please refer to Figure 4 , Figure 4 FIG. 1 is an operation waveform diagram of an embodiment of the output voltage and the rectified voltage in the power supply system of the present invention. Figure 4 As shown, during the period from time point t1 to time point t2, switch M1 is turned on, and its gate-source voltage Vgs1 is high potential; and during this period, switch M2 is turned off, and its gate-source voltage Vgs2 is low potential. And during the period from time point t1 to time point t2, the resonant inductor Lr in the power stage circuit 31 with buck characteristics and the inductor Lm of the transformer 33 are both in the excitation state, so the corresponding resonant inductor current ILr and inductor current ILm flowing through the resonant inductor Lr and the inductor Lm are both rising; and during this period, because switch M1 is turned on, its drain-source voltage Vds1 is low potential (0V), and because switch M2 is turned off, its drain-source voltage Vds2 is the conversion voltage VCN. During the period from time point t1 to time point t2, the switch in the synchronous rectifier 34 is turned off, so the synchronous rectification voltage Vd is the conversion voltage VCN divided by the turn ratio (n), that is, VCN / n. The turns ratio n is equal to the turns of the primary winding Np divided by the turns of the secondary winding Ns, and the conversion voltage VCN is proportional to the root mean square of the AC input voltage VAC. Therefore, the synchronous rectification voltage Vd is positively correlated with the AC input voltage VAC.

[0119] Please continue to refer to Figure 4, during the period from time t3 to time t4, the switch M1 is turned off, and its gate-source voltage Vgs1 is at a low potential; and during this period, the switch M2 is turned on, and its gate-source voltage Vgs2 is at a high potential. And during the period from time t1 to time t2, the resonant inductor Lr in the power stage circuit 31 with a step-down characteristic and the inductor Lm of the transformer 33 are both in a demagnetized state, so the corresponding resonant inductor current ILr and inductor current ILm flowing through the resonant inductor Lr and the inductor Lm are both reduced, wherein the inductor current ILm flowing through the inductor Lm is converted to the secondary winding Ns of the transformer 33; and during this period, the switch in the synchronous rectifier 34 is turned on, and the synchronous rectifier voltage Vd is 0V.

[0120] According to the above description of the operation of the AHB flyback converter 30, in one embodiment, in order to determine whether the conversion voltage VCN is higher than the first voltage threshold based on whether the synchronous rectification voltage Vd is higher than the winding voltage threshold, it is necessary to use the synchronous rectification voltage Vd when the switch in the synchronous rectifier 34 is turned off.

[0121] Figure 5 An embodiment of the present invention is shown. The main purpose of this embodiment is to screen out situations where PFC conversion can be safely prohibited under specific conditions, and after sensing relevant parameters for situations where PFC conversion can be prohibited, in combination with methods such as table lookup and / or circuit, when the power Pout of the adapter output power is lower than the power threshold (75W in this embodiment) and the conversion voltage VCN of the converted power is higher than the first voltage threshold, the communication protocol PD interface 40 generates a prohibition signal DIS to prohibit PFC conversion in the PFC conversion circuit 20.

[0122] exist Figure 5 In the embodiment shown, see Figure 3 and Figure 4 , considering that the turns ratio (n) is 6, and the PFC conversion circuit 20 does not include a boost follower, but still has a boost power stage circuit, and the maximum current Imax of the output current Iout is 3A; wherein, when the switch M1 is turned on, and the switch M2 and the switch in the synchronous rectifier 34 are both turned off, the synchronous rectification voltage Vd is equal to the conversion voltage VCN divided by the turns ratio (n).

[0123] exist Figure 5In the illustrated situation 1, the prerequisites are as follows: the root mean square of the AC input voltage VAC is 265Vrms, that is, the peak-to-peak voltage is 375Vpp, and the communication protocol PD interface 40 transmits the relevant information to the AHB flyback converter 30 according to the first communication protocol information PRT1, and determines that the adapter output voltage VDD of the adapter output power Pout is 48V, the duty cycle upper limit Dmax is 0.8, and when the PFC conversion is enabled, the conversion voltage VCN is 400V, and if the PFC conversion in the PFC conversion circuit 20 is disabled, the conversion voltage VCN is equal to the peak voltage of the AC input voltage VAC, which is 375Vpp.

[0124] Therefore, in Figure 5 In the illustrated case 1, if the PFC conversion in the PFC conversion circuit 20 is disabled, the adapter output voltage VDD can be 48V (because the conversion voltage VCN is divided by 6 and then multiplied by the duty cycle upper limit Dmax not higher than 0.8, the maximum can reach 50V). The synchronous rectification voltage Vd is 66.7V, and the maximum power Pmax of the adapter output power supply is 144W, which is higher than the power threshold 75W. According to the IEC61000-3-2 standard, the PFC conversion needs to be enabled. In this embodiment, the duty cycle is the adapter output voltage VDD (48) divided by the conversion voltage VCN (400V) multiplied by n (6), which is about 0.72.

[0125] exist Figure 5 In the illustrated situation 2, the prerequisites are as follows: the root mean square of the AC input voltage VAC is 265Vrms, that is, the peak-to-peak voltage is 375Vpp, and the communication protocol PD interface 40 determines the adapter output voltage VDD of the adapter output power to be 5V and the duty cycle upper limit Dmax to be 0.8 according to the first communication protocol information PRT1, and when the PFC conversion is enabled, the conversion voltage VCN is 400V, and if the PFC conversion in the PFC conversion circuit 20 is disabled, the conversion voltage VCN is equal to the peak voltage of the AC input voltage VAC, which is 375Vpp.

[0126] Therefore, in Figure 5 In the case 2 shown, the maximum power Pmax of the power output of the adapter is 15W, which is lower than the power threshold 75W. In addition, the conversion voltage VCN (375V) divided by 6 and multiplied by the duty cycle upper limit Dmax (about 50V) not higher than 0.8 is sufficient to generate the adapter output voltage VDD, and the PFC conversion in the PFC conversion circuit 20 can be disabled to improve the conversion efficiency. Therefore, in Figure 5In case 2 shown, according to the present invention, PFC conversion in the PFC conversion circuit 20 is disabled. This results in a duty cycle of the adapter output voltage VDD (5V) divided by the conversion voltage VCN (375V) times n (6), which is approximately 0.08.

[0127] exist Figure 5 In the illustrated situation 3, the prerequisites are as follows: the root mean square of the AC input voltage VAC is 85Vrms, that is, the peak-to-peak voltage is 120Vpp, and the communication protocol PD interface 40 determines that the adapter output voltage VDD of the adapter output power is 48V according to the first communication protocol information PRT1, and the duty cycle upper limit Dmax is 0.8, and when the PFC conversion is enabled, the conversion voltage VCN is 400V, and if the PFC conversion in the PFC conversion circuit 20 is disabled, the conversion voltage VCN is equal to the peak voltage of the AC input voltage VAC, which is 120Vpp.

[0128] Therefore, in Figure 5 In case 3, if the PFC conversion in the PFC conversion circuit 20 is disabled, the adapter output voltage VDD cannot be 48V (because the conversion voltage VCN is divided by 6 and then multiplied by the duty cycle upper limit Dmax not higher than 0.8, the maximum can only reach 16V). Figure 5 In the illustrated case 3, according to the present invention, the PFC conversion in the PFC conversion circuit 20 is not prohibited, that is, the PFC conversion is enabled. This makes the synchronous rectification voltage Vd 66.7V, and the maximum power Pmax of the power output power of the adapter is 144W, which is higher than the power threshold 75W. In this embodiment, the duty cycle is the value of the adapter output voltage VDD (48) divided by the conversion voltage VCN (400V) multiplied by n (6), which is about 0.72.

[0129] exist Figure 5 In the illustrated situation 4, the prerequisites are as follows: the root mean square of the AC input voltage VAC is 85Vrms, that is, the peak-to-peak voltage is 120Vpp, and the communication protocol PD interface 40 determines that the adapter output voltage VDD of the adapter output power is 5V and the duty cycle upper limit Dmax is 0.8 according to the first communication protocol information PRT1, and when the PFC conversion is enabled, the conversion voltage VCN is 400V, and if the PFC conversion in the PFC conversion circuit 20 is disabled, the conversion voltage VCN is equal to the peak voltage of the AC input voltage VAC, which is 120Vpp.

[0130] Therefore, in Figure 5In the case 4 shown, the maximum power Pmax of the power output of the adapter is 15W, which is lower than the power threshold 75W. In addition, the conversion voltage VCN (120V) divided by 6 and multiplied by the duty cycle upper limit Dmax (about 16V) not higher than 0.8 is sufficient to generate the adapter output voltage VDD, and the PFC conversion in the PFC conversion circuit 20 can be disabled to improve the conversion efficiency. Figure 5 In case 4, according to the present invention, PFC conversion in the PFC conversion circuit 20 is disabled. This results in a duty cycle of the adapter output voltage VDD (5V) divided by the conversion voltage VCN (120V) times n (6), which is approximately 0.25.

[0131] From another perspective, Figure 5 Case 5 shows that when the root mean square of the AC input voltage VAC is 85Vrms and the PFC conversion in the PFC conversion circuit 20 is disabled, the conversion voltage VCN is equal to the peak voltage of the AC input voltage VAC, which is 120Vpp. When the duty cycle upper limit Dmax is 0.8, the maximum adapter output voltage VDD that can be provided is 16V, and the maximum current Imax of the output current Iout is 3A.

[0132] Fig. 6A and Figure 6B An embodiment of the present invention is shown. Figure 5 Similarly, the purpose is to screen out situations where PFC conversion can be safely prohibited under specific conditions, and after sensing relevant parameters for situations where PFC conversion can be prohibited, in combination with methods such as table lookup and / or circuits, when the power of the adapter output power is lower than the power threshold (75W in this embodiment) and the conversion voltage VCN of the converted power is higher than the first voltage threshold, the communication protocol PD interface 40 generates a prohibition signal DIS to prohibit PFC conversion in the PFC conversion circuit 20.

[0133] exist Fig. 6A and Figure 6B In the embodiment shown, see Figure 3 and Figure 4 , consider the turn ratio (n) is 6, and Figure 5 The difference between the embodiment shown is that the PFC conversion circuit 20 includes a boost follower. The characteristic curve of the PFC conversion circuit 20 converting the AC input voltage VAC into the conversion voltage VCN is as follows: Figure 6B It should be noted that when the RMS of the AC input voltage VAC is between 240Vrms and 265Vrms, the RMS of the AC input voltage VAC is proportional to the conversion voltage VCN, and when the RMS of the AC input voltage VAC is lower than 240Vrms, the conversion voltage VCN is maintained at a fixed level of 360V. Figure 5The same as the illustrated embodiments is that the maximum current Imax of the output current Iout is 3A; wherein, when the switch M1 is turned on and the switch M2 and the switch in the synchronous rectifier 34 are turned off, the synchronous rectification voltage Vd is equal to the conversion voltage VCN divided by the turns ratio (n).

[0134] exist Fig. 6A and Figure 6B In the case 1 shown, except that the PFC conversion circuit 20 includes a boost follower, the other prerequisites are the same as those Figure 5 The situation 1 shown is the same as follows: the root mean square of the AC input voltage VAC is 265Vrms, that is, the peak-to-peak voltage is 375Vpp, and the communication protocol PD interface 40 transmits the relevant information to the AHB flyback converter 30 according to the first communication protocol information PRT1, and determines that the adapter output voltage VDD of the adapter output power is 48V, the duty cycle upper limit Dmax is 0.8, and when the PFC conversion is enabled, the conversion voltage VCN is 400V, and if the PFC conversion in the PFC conversion circuit 20 is disabled, the conversion voltage VCN is equal to the peak voltage of the AC input voltage VAC, which is 375Vpp.

[0135] Therefore, in Fig. 6A and Figure 6B In the case 1 shown, if the PFC conversion in the PFC conversion circuit 20 is disabled, the adapter output voltage VDD can be 48V (because the conversion voltage VCN is divided by 6 and then multiplied by the duty cycle upper limit Dmax not higher than 0.8, the maximum can reach 50V). Fig. 6A and Figure 6B In the illustrated case 1, according to the present invention, the synchronous rectification voltage Vd is 66.7V, and the maximum power Pmax of the power output of the adapter is 144W, which is higher than the power threshold 75W. According to the IEC61000-3-2 standard, PFC conversion needs to be enabled. In this embodiment, the duty cycle is the value of the adapter output voltage VDD (48) divided by the conversion voltage VCN (400V) multiplied by n (6), which is approximately 0.72.

[0136] exist Fig. 6A and Figure 6B In the illustrated situation 2, the prerequisites are as follows: the root mean square of the AC input voltage VAC is 265Vrms, that is, the peak-to-peak voltage is 375Vpp, and the communication protocol PD interface 40 determines that the adapter output voltage VDD of the adapter output power is 5V and the duty cycle upper limit Dmax is 0.8 according to the first communication protocol information PRT1, and when the PFC conversion is enabled, the conversion voltage VCN is 400V, and if the PFC conversion in the PFC conversion circuit 20 is disabled, the conversion voltage VCN is equal to the peak voltage of the AC input voltage VAC, which is 375Vpp.

[0137] Therefore, in Fig. 6A and Figure 6B In the case 2 shown, the maximum power Pmax of the power output of the adapter is 15W, which is lower than the power threshold 75W. In addition, the conversion voltage VCN (375V) divided by 6 and multiplied by the duty cycle upper limit Dmax (about 50V) not higher than 0.8 is sufficient to generate the adapter output voltage VDD, and the PFC conversion in the PFC conversion circuit 20 can be disabled to improve the conversion efficiency. Therefore, in Fig. 6A and Figure 6B In case 2, according to the present invention, PFC conversion in the PFC conversion circuit 20 is disabled. This makes the duty cycle equal to the adapter output voltage VDD (5V) divided by the conversion voltage VCN (375V) divided by n (6), which is approximately 0.08.

[0138] exist Fig. 6A and Figure 6B In the illustrated situation 3, the prerequisites are as follows: the root mean square of the AC input voltage VAC is 85Vrms, that is, the peak-to-peak voltage is 120Vpp, and the communication protocol PD interface 40 determines that the adapter output voltage VDD of the adapter output power is 48V according to the first communication protocol information PRT1, and the duty cycle upper limit Dmax is 0.8, and when the PFC conversion is enabled, the conversion voltage VCN is 360V as described above, and if the PFC conversion in the PFC conversion circuit 20 is disabled, the conversion voltage VCN is equal to the peak voltage of the AC input voltage VAC, which is 120Vpp.

[0139] Therefore, in Fig. 6A and Figure 6B In case 3, if the PFC conversion in the PFC conversion circuit 20 is disabled, the adapter output voltage VDD cannot be 48V (because the conversion voltage VCN is divided by 6 and then multiplied by the duty cycle upper limit Dmax not higher than 0.8, the maximum can only reach 16V). Fig. 6A and Figure 6B In the illustrated case 3, according to the present invention, the PFC conversion in the PFC conversion circuit 20 is not prohibited, that is, the PFC conversion is enabled. This makes the synchronous rectification voltage Vd 60V, and the maximum power Pmax of the power output power of the adapter is 144W, which is higher than the power threshold 75W. In this embodiment, the duty cycle is the value of the adapter output voltage VDD (48) divided by the conversion voltage VCN (360V) multiplied by n (6), which is 0.8.

[0140] exist Fig. 6A and Figure 6BIn the illustrated situation 4, the prerequisites are as follows: the root mean square of the AC input voltage VAC is 85Vrms, that is, the peak-to-peak voltage is 120Vpp, and the communication protocol PD interface 40 determines that the adapter output voltage VDD of the adapter output power is 5V and the duty cycle upper limit Dmax is 0.8 according to the first communication protocol information PRT1, and when the PFC conversion is enabled, the conversion voltage VCN is 360V, and if the PFC conversion in the PFC conversion circuit 20 is disabled, the conversion voltage VCN is equal to the peak voltage of the AC input voltage VAC, which is 120Vpp.

[0141] Therefore, in Fig. 6A and Figure 6B In the illustrated case 4, the maximum power Pmax of the power output of the adapter is 15W, which is lower than the power threshold 75W. In addition, the conversion voltage VCN (120V) divided by 6 and multiplied by the duty cycle upper limit Dmax (about 16V) not higher than 0.8 is sufficient to generate the adapter output voltage VDD (5V), and the PFC conversion in the PFC conversion circuit 20 can be disabled to improve the conversion efficiency. Therefore, in Fig. 6A and Figure 6B In case 4, according to the present invention, PFC conversion in the PFC conversion circuit 20 is disabled. This results in a duty cycle of the adapter output voltage VDD (5V) divided by the conversion voltage VCN (120V) times n (6), which is approximately 0.25.

[0142] From another perspective, Fig. 6A and Figure 6B Case 5 shows that when the root mean square of the AC input voltage VAC is 85Vrms and the PFC conversion in the PFC conversion circuit 20 is disabled, the conversion voltage VCN is equal to the peak voltage of the AC input voltage VAC, which is 120Vpp. When the duty cycle upper limit Dmax is 0.8, the maximum adapter output voltage VDD that can be provided is 16V, and the maximum current Imax of the output current Iout is 3A.

[0143] Figure 7 A schematic diagram showing the hysteresis relationship between the conversion voltage VCN and the disable signal DIS in one embodiment is shown. Figure 7 As shown, when the PFC conversion is enabled, when the conversion voltage VCN of the conversion power source is higher than the first voltage threshold VTH1, the communication protocol PD interface 40 generates a disable signal CIS, that is, the disable signal CIS is switched to a high level VRH; when the PFC conversion is disabled, when the conversion voltage VCN is lower than the second voltage threshold VTH2, the disable signal CIS stops disabling the PFC conversion, that is, the disable signal CIS is switched to a low level VRL, wherein the first voltage threshold VTH1 is not lower than the second voltage threshold VTH2.

[0144] Figure 8 A schematic diagram showing the coupling relationship between the control chip 41, the optical coupler OC and the power factor correction control circuit 22 of the communication protocol PD interface in one embodiment of the present invention. Figure 8 As shown, the control chip 41 of the communication protocol PD interface includes a USB PD protocol controller 401, a multiplexer (MUX) 402, an analog-to-digital converter (ADC) 403, and a control signal generator 404. The output current Iout related information and the adapter output voltage VDD related information can be obtained by the USB PD protocol controller 401 through the pins D+, D-, CC1, CC2, etc., through the communication protocol PD interface of the circuit at the other end connected to the communication protocol PD interface 40. The control chip 41 of the communication protocol PD interface can obtain the related information of the power of the adapter output power and the adapter output voltage VDD through the pins D+, D-, CC1, CC2, etc. of the USB PD protocol controller 401, and transmit it to the control signal generator 404; it can also obtain the related information of the synchronous rectification voltage Vd, the current sensing signal VCS and the adapter output voltage VDD through the multiplexer 402, and convert the related information through the analog-to-digital converter 403 and transmit it to the control signal generator 404. The control signal generator 404 generates a control signal based on the above information to control the switch in the control chip 41 of the communication protocol PD interface, thereby generating a disable signal DIS, and transmitting it to the power factor correction control circuit 22 via the optical coupler OC to disable or enable PFC conversion. It should be noted that the disable signal DIS is related to the control chip 41 side of the communication protocol PD interface and the power factor correction control circuit 22 side, but does not need to be the same level and form, as long as it can determine whether to disable the PFC conversion in the PFC conversion circuit 20 according to the present invention.

[0145] Fig. 9 A schematic diagram showing the coupling relationship between the control chip 41, the optical coupler OC and the power factor correction control circuit 22 of the communication protocol PD interface in one embodiment of the present invention. Fig. 9 As shown, the control chip 41 of the communication protocol PD interface includes a USB PD protocol controller 401, a control signal generator 404 and a hysteresis comparator 405. Figure 8 The control chip 41 of the communication protocol PD interface shown is different in that: Fig. 9The control chip 41 of the communication protocol PD interface shown does not include the multiplexer 402 and the analog-to-digital converter 403, but includes a hysteresis comparator 405 for comparing the synchronous rectification voltage Vd with the voltage threshold Vth_vd to determine whether to disable the PFC conversion in the PFC conversion circuit 20. In one embodiment, the voltage threshold Vth_vd includes the aforementioned first voltage threshold and the second voltage threshold.

[0146] Fig.10 An embodiment of the present invention is shown to illustrate an implementation method of a power supply system control method according to the present invention. Fig.10 As shown, the power supply system control method includes:

[0147] Step S11: receiving an AC voltage;

[0148] Step S12: rectifying the AC input power to generate a rectified power supply; turning off the power path switch MBUS; enabling PFC conversion;

[0149] Step S13: Determine whether the communication protocol PD interface is externally connected to another communication protocol PD interface.

[0150] Step S14: No, turn off the power path switch MBUS; set the output current Iout to 0, set the adapter output voltage VDD to 5V; disable PFC conversion. Return to step S13.

[0151] Step S15: Yes, turn on the power path switch MBUS; obtain VDD, Iout and Vd related signals; estimate the adapter output power according to VDD and Iout; and estimate the conversion voltage VCN according to Vd.

[0152] Step S16: Determine whether the power of the adapter output power is lower than the power threshold.

[0153] Step S17: No, enable PFC conversion and return to step S13.

[0154] Step S18: Yes, determine whether the conversion voltage VCN is higher than the first voltage threshold.

[0155] Step S17: No, enable PFC conversion and return to step S13.

[0156] Step S19: Yes, PFC conversion is prohibited. Return to step S13.

[0157] The present invention has been described above with respect to the preferred embodiment, but the above is only to make it easy for those skilled in the art to understand the content of the present invention, and is not used to limit the scope of rights of the present invention. The various embodiments described are not limited to individual applications, but can also be used in combination. For example, two or more embodiments can be used in combination, and part of the components in one embodiment can also be used to replace the corresponding components in another embodiment. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. For example, the present invention refers to "processing or calculating or generating an output result according to a certain signal", which is not limited to the signal itself, but also includes, when necessary, converting the signal to voltage and current, current and voltage, and / or ratio conversion, and then processing or calculating according to the converted signal to generate an output result. It can be seen from this that under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations, and there are many combinations, which are not listed one by one here. Therefore, the scope of the present invention should cover the above and all other equivalent changes.

Claims

1. A power supply system with power factor correction, comprising: an AC rectifier for rectifying an AC input power source to generate a rectified power source; a power factor correction (PFC) conversion circuit for performing a PFC conversion on the rectified power supply to generate a converted power supply, and determining whether to prohibit the PFC conversion according to a prohibition signal; an asymmetric half-bridge (AHB) flyback converter for DC-DC converting the converted power to generate an adapter output power; and A communication protocol power delivery (PD) interface, for determining the adapter output power according to a first communication protocol information, and controlling one of the power path switches to transmit the adapter output power to one of the power supply pins; in, When the power of the adapter output power source is lower than a power threshold and a conversion voltage of the conversion power source is higher than a first voltage threshold, the communication protocol PD interface generates the prohibition signal to prohibit the PFC conversion in the PFC conversion circuit.

2. The power supply system with power factor correction as claimed in claim 1, wherein: When the PFC conversion is disabled, the PFC conversion circuit performs a bypass coupling operation so that the conversion voltage is equal to a rectified voltage of the rectified power source.

3. The power supply system with power factor correction as claimed in claim 1, wherein: When the PFC conversion circuit prohibits the PFC conversion, when the conversion voltage is lower than a second voltage threshold, the prohibition signal stops prohibiting the PFC conversion, wherein the first voltage threshold is not lower than the second voltage threshold.

4. The power supply system with power factor correction as claimed in claim 1, wherein: The conversion circuit includes a boost follower.

5. The power supply system with power factor correction as claimed in claim 1, wherein: The invention also comprises an optical coupler coupled between the communication protocol PD interface and the PFC conversion circuit to transmit the prohibition signal from the communication protocol PD interface to the PFC conversion circuit.

6. The power supply system with power factor correction as claimed in claim 1, wherein: The communication protocol PD interface determines whether the power of the adapter output power is lower than the power threshold according to a current sensing signal of an adapter output current of the adapter output power sensed by a current sensing circuit coupled to the AHB flyback converter.

7. The power supply system with power factor correction as claimed in claim 1, wherein: The communication protocol PD interface determines whether the power of the adapter output power is lower than the power threshold according to an adapter output voltage of the adapter output power, a conduction state of the power path switch and / or a second communication protocol information of the communication protocol PD interface.

8. The power supply system with power factor correction as claimed in claim 1, wherein: The first voltage threshold is related to an adapter output voltage of the adapter output power.

9. The power supply system with power factor correction as claimed in claim 1, wherein: The communication protocol PD interface determines whether the conversion voltage is higher than the first voltage threshold based on whether a second winding voltage of the AHB flyback converter is higher than a winding voltage threshold, wherein the winding voltage threshold is related to an adapter output voltage of the adapter output power supply or the turns ratio of the primary winding to the secondary winding of a transformer of the AHB flyback converter.

10. The power supply system with power factor correction as claimed in claim 9, wherein: The communication protocol PD interface also determines whether the conversion voltage is higher than the first voltage threshold according to a maximum duty cycle of the AHB flyback converter.

11. The power supply system with power factor correction as claimed in claim 1, wherein: The communication protocol PD interface determines that the power of the adapter output power is lower than the power threshold based on an adapter output voltage of the adapter output power being lower than a first adapter output voltage threshold, wherein the first adapter output voltage threshold is related to an upper limit of an adapter output current of the adapter output power.

12. The power supply system with power factor correction as claimed in claim 11, wherein when the PFC conversion circuit prohibits the PFC conversion, when the communication protocol PD interface determines that the power of the adapter output power is not less than the power threshold according to the adapter output voltage being higher than a second adapter output voltage threshold, the prohibition signal stops prohibiting the PFC conversion.

13. A power supply system control method, comprising: Rectifying an AC input power source to generate a rectified power source; Performing a power factor correction (PFC) conversion on the rectified power supply to generate a converted power supply, and determining whether to prohibit the PFC conversion according to a prohibition signal; DC-DC converting the converted power to generate an adapter output power; Determining the adapter output power according to a first communication protocol information, and controlling a power path switch to transmit the adapter output power to a power supply pin; and When the power of the adapter output power source is lower than a power threshold and a conversion voltage of the conversion power source is higher than a first voltage threshold, the prohibition signal is generated to prohibit the PFC conversion.

14. The power supply system control method according to claim 13, wherein: The method further comprises: when the PFC conversion is disabled, performing a bypass coupling operation so that the conversion voltage is equal to a rectified voltage of the rectified power supply.

15. The power supply system control method according to claim 13, wherein: The method further comprises: when the PFC conversion is prohibited, when the conversion voltage is lower than a second voltage threshold, the prohibition signal stops prohibiting the PFC conversion, wherein the first voltage threshold is not lower than the second voltage threshold.

16. The power supply system control method according to claim 13, wherein: The method further comprises: sensing a current sensing signal of an adapter output current of the adapter output power to determine whether the power of the adapter output power is lower than the power threshold.

17. The power supply system control method according to claim 13, wherein: The method further comprises: determining whether the power of the adapter output power is lower than the power threshold according to an adapter output voltage of the adapter output power, a conduction state of the power path switch and / or a second communication protocol information.

18. The power supply system control method according to claim 13, wherein: The first voltage threshold is related to an adapter output voltage of the adapter output power.

19. The power supply system control method according to claim 13, wherein: It also includes: determining whether the conversion voltage is higher than the first voltage threshold based on whether a second winding voltage of an asymmetric half-bridge flyback converter is higher than a winding voltage threshold, wherein the winding voltage threshold is related to an adapter output voltage of the adapter output power supply or a turns ratio of a primary winding to a secondary winding of a transformer.

20. The power supply system control method according to claim 19, wherein: The method further comprises: determining that the power of the adapter output power is lower than a first adapter output voltage threshold value according to an adapter output voltage of the adapter output power being lower than the power threshold value, wherein the first adapter output voltage threshold value is related to an upper limit of an adapter output current of the adapter output power supply.

21. The power supply system control method according to claim 20, wherein: The method further comprises: when the PFC conversion is disabled, when a communication protocol power transmission interface determines that the power of the adapter output power is not lower than the power threshold according to the adapter output voltage being higher than a second adapter output voltage threshold, the disable signal stops disabling the PFC conversion.

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