GaAs PHEMT-based power amplifier

Abstract

The invention provides a GaAs PHEMT-based power amplifier. The GaAs PHEMT-based power amplifier comprises an input matching circuit, an inter-stage matching circuit and an output matching circuit which are connected in sequence, and the output matching circuit adopts a reactance compensation network matching mode. The class E power amplifier obtains excellent performance, the reactance compensation technology is used in the frequency range of 2.45-2.85 GHz, the power additional efficiency PAE is 61%, the output 1dB compression point is larger than 29 dBm, and broadband, high efficiency and high power are achieved; the invention relates to a broadband hybrid class E power amplifier combining parallel circuit load and reactance compensation technology, the bandwidth of a diode parameter amplifier is improved by using the reactance compensation technology, and the output impedance is matched by designing a matching network as a low-pass network. The class-E power amplifier has the characteristics of high gain and high efficiency, and keeps good performance in the aspects of output, power gain and PAE.

Description

Technical Field

[0001] The present invention relates to the technical field of power amplifiers, in particular to a power amplifier based on GaAs PHEMT. Background Art

[0002] GaAs PHEMT (gallium arsenide pseudomorphic high electron mobility transistor) power amplifier is a high-performance microwave power amplifier, widely used in wireless communications, radar systems, optical fiber communications and other fields. GaAs PHEMT is particularly suitable for high-frequency and high-power applications due to its high efficiency, low noise, and strong radiation resistance.

[0003] Existing power amplifiers, such as patent CN202120894680.1, disclose an ultra-wideband distributed power amplifier based on GaAs PHEMT, which includes an input port, an output port, and N-stage power amplification units cascaded in sequence between the input port and the output port, N>2; each stage of the power amplification unit includes an input matching network and a common-source and common-gate transistor module; the common-source and common-gate transistor module of each stage of the power amplification unit includes M PHEMT tubes, M≥2, the first end of the first-stage power amplification unit is connected to the input port, and the second end of the second-stage power amplification unit is connected to the output port; from input to output, the size of the PHEMT tube in the common-source and common-gate transistor module of each stage of the power amplification unit decreases step by step.

[0004] However, the power amplifier of the above patent achieves the ultra-wideband effect by cascading multiple transistors at each stage, which is not only costly but also inefficient. Summary of the invention

[0005] In view of the deficiencies of the prior art, the present invention provides a power amplifier based on GaAs PHEMT, which has the characteristics of high gain and high efficiency and maintains good performance in terms of output, power gain and PAE.

[0006] The technical solution of the present invention is: a power amplifier based on GaAs PHEMT, comprising an input matching circuit, an inter-stage matching circuit, and an output matching circuit connected in sequence; the output matching circuit adopts a matching method of a reactance compensation network.

[0007] As a preferred embodiment, the input matching circuit is connected to the signal input terminal RF through the DC blocking capacitor C1. IN connect.

[0008] Preferably, the input matching circuit includes capacitor C2, inductor L1, inductor L2, resistors R1 and R2; one end of the capacitor C2 and inductor L1 is connected to the DC blocking capacitor C1, and the other end of the capacitor C2 is grounded; the other end of the inductor L1 is connected in parallel with resistors R1 and R2; the other end of the resistor R2 is connected to the inductor L2; the other end of the resistor R1 is connected to the inter-stage matching circuit through the transistor M1.

[0009] Preferably, the other end of the resistor R1 is connected to the gate of the transistor M1; the source of the transistor M1 is grounded; and the drain of the transistor M1 is connected to the inter-stage matching circuit.

[0010] Preferably, the other end of the inductor L2 is respectively connected to the capacitor C3 and the first-stage gate feed VG1, and the other end of the capacitor C3 is grounded.

[0011] Preferably, the inter-stage matching circuit includes an inductor L3, an inductor L4, a capacitor C5, a resistor R3, and a resistor R4; the drain of the transistor M1 is connected to one end of the inductor L3 and the capacitor C5 respectively; the other end of the capacitor C5 is connected to the resistor R3 and the resistor R4 respectively; the other end of the resistor R3 is connected to the inductor L4; the other end of the resistor R4 is connected to the output matching circuit through the transistor M2.

[0012] Preferably, the other end of the inductor L3 is connected to the capacitor C4 and the input power supply VD1 respectively; the other end of the capacitor C4 is grounded.

[0013] Preferably, the other end of the inductor L4 is connected to the capacitor C6 and the second-stage gate feed VG2 respectively, and the other end of the capacitor C6 is grounded.

[0014] Preferably, the other end of the resistor R4 is connected to the gate of the transistor M2, the source of the transistor M2 is grounded; and the drain of the transistor M2 is connected to the output matching circuit.

[0015] Preferably, the output matching circuit includes an inductor compensation network, which includes an inductor L5, a capacitor C8, an inductor L6, and a capacitor C9; the drain of the transistor M2 is respectively connected to one end of the inductor L5, the capacitor C8, and the inductor L6, and the other end of the capacitor C8 is grounded; and the inductor L6 is connected to the capacitor C9.

[0016] Preferably, the output matching circuit further includes an inductor L7 and a capacitor C10; one end of the inductor L7 is connected to the capacitor C9; the other end of the inductor L7 is connected to the capacitor C10 and the signal output terminal RF out .

[0017] Preferably, the other end of the inductor L5 is connected to the input power supply VD2 and the capacitor C7 respectively, and the other end of the capacitor C7 is grounded.

[0018] Preferably, the power amplifier has a power added efficiency (PAE) of 61% and an output 1dB compression point greater than 29dBm in the frequency range of 2.45 to 2.85 GHz.

[0019] The beneficial effects of the present invention are:

[0020] 1. By using reactance compensation technology, the class E power amplifier of the present invention has excellent performance. In the frequency range of 2.45 to 2.85 GHz, the power added efficiency PAE is 61%, the output 1 dB compression point is greater than 29 dBm, and broadband, high efficiency and high power are achieved;

[0021] 2. The present invention proposes a broadband hybrid class-E power amplifier that combines parallel circuit load and reactance compensation technology, and uses reactance compensation technology to further improve the bandwidth of the diode parameter amplifier by designing the matching network as a low-pass network to match the output impedance.

[0022] 3. The driving stage and the power stage of the present invention both adopt a deep class AB mode design, and have the characteristics of high gain and high efficiency. The class E power amplifier of the present invention maintains good performance in terms of output, power gain and PAE. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a circuit diagram of a power amplifier of the present invention;

[0024] Figure 2 A circuit diagram of an output matching circuit of the present invention;

[0025] Figure 3 is an equivalent circuit diagram of the output matching circuit of the present invention;

[0026] Figure 4 A schematic diagram showing the efficiency comparison between the present invention and the traditional LCLC matching network;

[0027] Figure 5 A schematic diagram showing the output power comparison between the present invention and the traditional LCLC matching network;

[0028] Figure 6 It is a schematic diagram of the output power of the present invention under frequency sweep;

[0029] Figure 7 It is a schematic diagram of the PAE of the present invention under frequency sweep;

[0030] Figure 8 It is a schematic diagram of the gain S21 of the present invention. DETAILED DESCRIPTION

[0031] The specific implementation of the present invention will be further described below in conjunction with the accompanying drawings:

[0032] like Figure 1 As shown, this embodiment provides a power amplifier based on GaAs PHEMT, including an input matching circuit, an inter-stage matching circuit, and an output matching circuit connected in sequence; the output matching circuit adopts a matching method of a reactance compensation network. The power amplifier has a power added efficiency PAE of 61% in the frequency range of 2.45 to 2.85 GHz, and an output 1 dB compression point greater than 29 dBm.

[0033] As a preferred embodiment of the present invention, the input matching circuit is connected to the signal input terminal RF via a DC blocking capacitor C1. IN connect.

[0034] As a preferred embodiment of the present invention, the input matching circuit includes a capacitor C2, an inductor L1, a capacitor L2, resistors R1 and R2; one end of the capacitor C2 and the inductor L1 are connected to the DC blocking capacitor C1, and the other end of the capacitor C2 is grounded; the other end of the inductor L1 is connected in parallel with resistors R1 and R2; the other end of the resistor R2 is connected to the inductor L2; the other end of the resistor R1 is connected to the inter-stage matching circuit through a transistor M1.

[0035] The other end of the resistor R1 is connected to the gate of the transistor M1; the source of the transistor M1 is grounded; and the drain of the transistor M1 is connected to the inter-stage matching circuit.

[0036] The other end of the inductor L2 is respectively connected to the capacitor C3 and the first-stage gate feeder VG1, and the other end of the capacitor C3 is grounded.

[0037] As a preferred embodiment of the present invention, the inter-stage matching circuit includes an inductor L3, an inductor L4, a capacitor C5, a resistor R3, and a resistor R4; the drain of the transistor M1 is connected to one end of the inductor L3 and the capacitor C5 respectively; the other end of the capacitor C5 is connected to the resistor R3 and the resistor R4 respectively; the other end of the resistor R3 is connected to the inductor L4; the other end of the resistor R4 is connected to the output matching circuit through the transistor M2. The other end of the inductor L3 is connected to the capacitor C4 and the input power supply VD1 respectively; the other end of the capacitor C4 is grounded. The other end of the inductor L4 is connected to the capacitor C6 and the second-stage gate feed VG2 respectively, and the other end of the capacitor C6 is grounded. The other end of the resistor R4 is connected to the gate of the transistor M2, and the source of the transistor M2 is grounded; the drain of the transistor M2 is connected to the output matching circuit.

[0038] As preferred in this embodiment, Figure 2 As shown, the output matching circuit includes an inductor compensation network, and the inductor compensation network includes an inductor L5, a capacitor C8, an inductor L6, and a capacitor C9; the drain of the transistor M2 is respectively connected to one end of the inductor L5, the capacitor C8, and the inductor L6, and the other end of the capacitor C8 is grounded; the inductor L6 is connected to the capacitor C9.

[0039] The output matching circuit also includes an inductor L7 and a capacitor C10; one end of the inductor L7 is connected to the capacitor C9; the other end of the inductor L7 is connected to the capacitor C10 and the signal output terminal RF out The other end of the inductor L5 is connected to the input power supply VD2 and the capacitor C7 respectively, and the other end of the capacitor C7 is grounded. Figure 3 FIG. 4 is an equivalent circuit of the output matching circuit described in this embodiment. In the figure, RL is a load, and Co and Ron are equivalent components inside the transistor M2.

[0040] The efficiency and output power of this embodiment are compared with those of the traditional LCLC matching network. The results are as follows: Figure 4 As shown in , and 5, it can be seen from the figure that due to the use of the reactance compensation network, this embodiment can significantly improve the efficiency and power compared with the traditional matching network.

[0041] In addition, this embodiment also performs HB simulation and S parameter simulation on 0GHz-6GHz, and the saturation efficiency is 55-61% and the saturation power is 28-29dBm. Figure 6 , 7 As shown, this embodiment can maintain efficiency above 50% within a bandwidth of 2-3 GHz, and the power is stable at around 28 dBm, achieving broadband, high efficiency and high power. Figure 8 As shown, the gain S21 of this embodiment is also significantly improved.

[0042] The above embodiments and descriptions are only for illustrating the principles and best embodiments of the present invention. Without departing from the spirit and scope of the present invention, the present invention may be subject to various changes and improvements, all of which fall within the scope of the present invention to be protected.

Claims

1. A power amplifier based on GaAs PHEMT, characterized in that: It comprises an input matching circuit, an inter-stage matching circuit, and an output matching circuit which are connected in sequence; the output matching circuit adopts a matching method of a reactance compensation network.

2. A GaAs PHEMT-based power amplifier according to claim 1, characterized in that: The input matching circuit is connected to the signal input terminal RF through the DC blocking capacitor C1. IN connect.

3. A GaAs PHEMT-based power amplifier according to claim 2, characterized in that: The input matching circuit includes capacitor C2, inductor L1, inductor L2, resistors R1 and R2; one end of the capacitor C2 and inductor L1 is connected to the DC blocking capacitor C1, and the other end of the capacitor C2 is grounded; the other end of the inductor L1 is connected in parallel with resistors R1 and R2; the other end of the resistor R2 is connected to the inductor L2; the other end of the inductor L2 is respectively connected to the capacitor C3 and the first-stage gate feed VG1, and the other end of the capacitor C3 is grounded; the other end of the resistor R1 is connected to the inter-stage matching circuit through the transistor M1.

4. A GaAs PHEMT-based power amplifier according to claim 3, characterized in that: The other end of the resistor R1 is connected to the gate of the transistor M1; the source of the transistor M1 is grounded; and the drain of the transistor M1 is connected to the inter-stage matching circuit.

5. A GaAs PHEMT-based power amplifier according to claim 4, characterized in that: The inter-stage matching circuit includes an inductor L3, an inductor L4, a capacitor C5, a resistor R3, and a resistor R4; the drain of the transistor M1 is respectively connected to one end of the inductor L3 and the capacitor C5; the other end of the inductor L3 is respectively connected to the capacitor C4 and the input power supply VD1; the other end of the capacitor C4 is grounded; the other end of the capacitor C5 is respectively connected to the resistor R3 and the resistor R4; the other end of the resistor R3 is connected to the inductor L4; the other end of the inductor L4 is respectively connected to the capacitor C6 and the second-stage gate feed VG2, and the other end of the capacitor C6 is grounded; the other end of the resistor R4 is connected to the output matching circuit through the transistor M2.

6. A GaAs PHEMT-based power amplifier according to claim 5, characterized in that: The other end of the resistor R4 is connected to the gate of the transistor M2, the source of the transistor M2 is grounded; and the drain of the transistor M2 is connected to the output matching circuit.

7. A GaAs PHEMT-based power amplifier according to claim 6, characterized in that: The output matching circuit includes an inductor compensation network, which includes an inductor L5, a capacitor C8, an inductor L6, and a capacitor C9; the drain of the transistor M2 is respectively connected to one end of the inductor L5, the capacitor C8, and the inductor L6, and the other end of the capacitor C8 is grounded; the inductor L6 is connected to the capacitor C9.

8. The GaAs PHEMT-based power amplifier according to claim 7, characterized in that: The output matching circuit also includes an inductor L7 and a capacitor C10; one end of the inductor L7 is connected to the capacitor C9; the other end of the inductor L7 is connected to the capacitor C10 and the signal output terminal RF OUT .

9. A GaAs PHEMT-based power amplifier according to claim 8, characterized in that: The other end of the inductor L5 is connected to the input power source VD2 and the capacitor C7 respectively, and the other end of the capacitor C7 is grounded.

10. A GaAs PHEMT-based power amplifier according to claim 9, characterized in that: The power amplifier has a power added efficiency PAE of 61% within a frequency range of 2.45 to 2.85 GHz, and an output 1 dB compression point greater than 29 dBm.

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