Method and system for injection locked frequency divider with frequency calibration

Abstract

The invention relates to a method and system for an injection locked frequency divider with frequency calibration. In some embodiments, a circuit system may include a series of symmetric stages, where an initial stage in the series is coupled to an input signal having a first plurality of phases and an output stage in the series couples an output signal including a second plurality of phases to a calibration engine, wherein a number of the phases in the output signal increases based at least on a number of the symmetric stages and a number of the first plurality of phases in the input signal. Additionally, the circuitry may include embodiments in which the calibration engine calibrates a frequency of the circuitry within a range based at least on a target frequency. The circuitry may include embodiments in which the calibration engine outputs a current provided to the series, where the output current may be based at least on a calibration frequency.

Description

Technical Field

[0001] The present disclosure relates generally to the field of injection locked frequency dividers, and more particularly to an injection locked frequency divider with frequency calibration. Background Art

[0002] Multiphase clocking generates several different clock signals with different phases. Multiphase clocking can provide improved data sampling, reduce clock-to-data skew, enable parallel operation, and reduce errors. Multiphase clock generation using injection-locked ring oscillators (ILROs) can be used in serializers and deserializers for phase alignment, low jitter, power efficiency, scalability, tunability, and reduced component count.

[0003] If there is asymmetric injection, the ILRO produces an inherent static skew between the injection and non-injection nodes. The inherent static skew in ILRO refers to the phase difference between the multiple clock phases generated by the ILRO. An orthogonal locked loop can be used to compensate for the inherent static skew. Due to the inherent mismatch, the orthogonal loop can shift the self-oscillation frequency of the ILRO further away from the desired operating frequency. This shift can degrade other performance characteristics related to the ILRO, such as locking range and jitter filtering. Summary of the invention

[0004] Symmetrical injection locked dividers can provide skew correction from superharmonics. For example, an injection locked divider (IL-DIV or IL divider) can be used as a divider that divides the number of phases by the number N and reduces the in-phase and quadrature (I / Q) mismatch caused by the injected clock. Due to the symmetrical injection architecture, a quadrature locked loop (QLL) may not be required and only frequency calibration may be added. In order to reduce input skew and optimize the jitter performance for process, voltage and temperature (PVT) factors at different clock frequencies, the IL divider can be designed to have a narrow lock range, and a frequency calibration engine can be used for this narrow lock range. A buffer can be used to provide a fixed swing and duty cycle control for the injected clock. The buffer reduces the IL divider lock range and bandwidth sensitivity.

[0005] In one general aspect, a circuit system may include a series of symmetrical stages, wherein an initial stage in the series is coupled to an input signal. In some embodiments, the input signal may have a first plurality of phases. In some embodiments, the series may have an output stage that couples an output signal comprising a second plurality of phases to a calibration engine. In some embodiments, the number of phases in the output signal comprising the second plurality of phases increases based at least on the number of symmetrical stages and the number of the first plurality of phases in the input signal. The calibration engine may calibrate the frequency of the circuit system within a range based at least on a target frequency. In some embodiments, the calibration engine outputs a current provided to the series. In some embodiments, the output current is based at least on a calibration frequency. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each of which is configured to perform the actions of a method.

[0006] Embodiments may include one or more of the following features. Each stage in the symmetric stage series may include a pair of first inverters coupled in series to a pair of cross-coupled inverters or coupled in parallel to a pair of feed-forward resistors. In embodiments, when each stage in the symmetric stage series includes the pair of first inverters coupled in series to the pair of cross-coupled inverters, each stage in the symmetric stage series may further include a switch coupled in parallel to the cross-coupled inverters, wherein the switch may control the injection intensity of the output voltage. In some embodiments, the switch may reduce the capacitive load of the previous stage in the symmetric stage series on the next stage in the symmetric stage series. In some embodiments, each stage in the symmetric stage series may further include a capacitor coupled in parallel to the cross-coupled inverters, wherein the capacitor may tune the frequency of each stage in the symmetric stage series. In some embodiments, the capacitor reduces the jitter of each stage in the symmetric stage series.

[0007] In some embodiments, the calibration engine further includes a frequency calibrator. In some embodiments, a current source is coupled to the frequency calibrator, wherein the frequency calibrator sends instructions to the circuit system of the current source. In some embodiments, the instructions are based at least on the calibration frequency. In some embodiments, the current source transmits the current to the circuit system, wherein the current is based at least on the calibration frequency. The circuit system may include a series of loops, each loop having a series of inverters coupled in parallel to an amplifier, wherein each loop can control the duty cycle of a phase in the first plurality of phases of the input signal. The circuit system may include a series of buffers coupled between the series of loops and the series of symmetric stages, wherein the series of buffers can provide a fixed swing of the output signal including the second plurality of phases. The circuit system may include a series of buffers coupled between the series of loops and the series of symmetric stages, wherein the series of buffers can reduce at least one of the frequency range of the output signal or the bandwidth sensitivity of the frequency range of the output signal, wherein the output signal includes the second plurality of phases. Implementations of the described technology may include hardware, methods or processes, or computer tangible media.

[0008] In one general aspect, a system may include a series of symmetric stages, wherein the series is configured to receive an input signal having a first plurality of phases. The system may also include a calibration engine coupled to an output stage of the series and configured to receive an output signal from the series. In some embodiments, the output signal may include a second plurality of phases. The calibration engine may be configured to calibrate the frequency of the series of symmetric stages to operate at a target frequency. The system may further include an implementation, wherein the output stage of the series of symmetric stages is configured to provide the output signal. In some embodiments, the output signal may represent an increase in the number of the first plurality of phases of the input signal based at least on the number of the symmetric stages. In some embodiments, the calibration engine may be configured to provide a current to the series of symmetric stages based at least on the frequency calibrated by the calibration engine. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each of which is configured to perform the actions of a method.

[0009] The implementation may include one or more of the following features. The system has an implementation, wherein each of the symmetric stages includes a pair of first inverters coupled in series to a pair of cross-coupled inverters or coupled in parallel to a pair of feed-forward resistors. In an implementation, when each stage in the symmetric stage series includes the pair of first inverters coupled in series to the pair of cross-coupled inverters, each stage in the symmetric stage series may further include a switch coupled in parallel to the cross-coupled inverters, wherein the switch can control the injection intensity of the output voltage. In some embodiments, the switch reduces the capacitive load of the previous stage in the symmetric stage series on the next stage in the symmetric stage. In some embodiments, each stage in the symmetric stage series further includes a capacitor coupled in parallel to the cross-coupled inverters, wherein the capacitor can tune the frequency of each stage in the symmetric stage series. In some embodiments, the capacitor reduces the jitter of each stage in the symmetric stage series. In some embodiments, the calibration engine further includes a frequency calibrator, a current source coupled to the frequency calibrator, wherein the frequency calibrator sends instructions to the circuit system of the current source. In some embodiments, the instruction may be based at least on the calibration frequency. In some embodiments, the current source transmits the current to the circuitry, wherein the current may be based at least on the calibration frequency. The system may include an implementation, wherein the circuitry further includes a series of loops, wherein each loop may have a series of inverters coupled in parallel to an amplifier. In some embodiments, each loop may control a duty cycle of a phase in the first plurality of phases of the input signal. Implementations of the described techniques may include hardware, a method or process, or a computer tangible medium.

[0010] In one general aspect, a method may include increasing the number of phases in an output signal, wherein the output signal includes a first plurality of phases. Increasing the number of phases in the output signal may be based at least on (i) the number of symmetry stages in a series of symmetry stages and (ii) the number of a second plurality of phases in an input signal. In some embodiments, the series of symmetry stages may have an initial stage in the series, wherein the initial stage is coupled to the input signal having the second plurality of phases. In some embodiments, the series of symmetry stages may have an output stage in the series, wherein the output stage couples the output signal to a calibration engine. The method may also include calibrating, by the calibration engine, a frequency of a circuit system within a range based at least on a target frequency. The method may further include outputting, by the calibration engine, a current coupled to the series, wherein the output current may be based at least on a calibration frequency. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each of which is configured to perform the actions of the method.

[0011] Implementations may include one or more of the following features. The method may include sending, by a frequency calibrator of the calibration engine, instructions to circuitry of a current source. In some embodiments, the instructions may be based at least on the calibration frequency. The method may include transmitting, by the current source of the frequency calibrator, the current to the circuitry, wherein the current may be based at least on the calibration frequency. Implementations of the described techniques may include hardware, methods or processes, or computer tangible media. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 An injection locked divider (IL-DIV or IL divider) system 100 is illustrated having an IL divider 102 in a receive clock path in accordance with some embodiments.

[0013] Figure 2 A block diagram illustrating core components of an IL divider core according to some embodiments.

[0014] Figure 3 An IL divider with frequency calibration according to some embodiments is described.

[0015] Figure 4 In-phase and quadrature (I / Q) skew reduction ratios implemented in an IL divider system according to some embodiments are described.

[0016] Figure 5 The output signal frequency of the IL divider system after frequency calibration according to some embodiments is illustrated.

[0017] Figure 6 Jitter performance in an IL divider system according to some embodiments is described.

[0018] Figure 7 An IL divider system having one or more input duty cycle control loops according to some embodiments is described.

[0019] Figure 8 The bandwidth and jitter performance of an IL divider with different duty cycles of an input signal according to some embodiments is described.

[0020] Fig. 9 A flow chart illustrating a calibration method according to some embodiments.

[0021] Fig.10 Flowchart illustrating an example process of a calibration method according to some embodiments.

[0022] Fig.11A and 11B A block diagram of a computing device for practicing embodiments of a client device or network device is depicted in accordance with some embodiments.

[0023] Fig. 11C An embodiment of a computing device is depicted in which a processor communicates directly with a main memory via a memory port in accordance with some embodiments. DETAILED DESCRIPTION

[0024] Injection refers to the process of introducing an external signal (referred to as the "injection signal") into the circuitry of an injection-locked frequency divider. An injection-locked frequency divider is a frequency divider circuit that is designed to synchronize with an external signal and produce a frequency output that may be, for example, a fraction of the input frequency. When the injection signal is introduced, the injection signal causes the circuit to lock onto the frequency of the external signal, resulting in a relatively stable frequency output.

[0025] The injection process may rely at least in part on a phase detector that compares the phase of the injected signal to the output signal and generates a control signal that adjusts the frequency of the divider circuit. By adjusting the frequency, the circuit may lock onto the frequency of the injected signal and generate a relatively stable output signal.

[0026] The injection clock swing can affect the ILRO frequency locking range and bandwidth. Bandwidth refers to the amount of data that can be transmitted over a network or communication channel in a given amount of time. For example, bandwidth can be measured in bits per second or bytes per second. The wider the locking range, the larger the injection swing is required. The injection stage can be designed to tune the properties of the ILRO, such as the self-oscillation frequency, bandwidth, and locking range.

[0027] The self-oscillation frequency (SOF) of an ILRO may vary when process, voltage, and temperature (PVT) factors vary, and a frequency lock range needs to be considered in the ILRO. A wider lock range provides robustness across optical PVT at the expense of input clock jitter requirements and phase correction capabilities. Calibrating the SOF of an ILRO to the clock operating frequency can at least partially alleviate the constraints associated with the lock range.

[0028] Various methods can be used to tune the frequency range. For example, a power supply voltage VDD can be provided to an asymmetric ILRO, which can receive a 2-bit input signal CKi[1:0] and output a 4-bit output signal CKo[3:0]. The 2-bit input signal CKi[1:0] represents bit signals CKi[1] and CKi[0]. The 4-bit output signal CKo[3:0] represents bit signals CKo[3], CKo[2], CKo[1], and CKo[0].

[0029] An asymmetric ILRO may include a series of stages (eg, two stages) where each stage includes a pair of main inverters with a pair of parallel cross-coupled inverters coupled in series between the main inverters. A capacitor may be coupled in series between the main inverters and in parallel with the pair of cross-coupled inverters.

[0030] A cross-coupled inverter may be a digital logic circuit used to implement a memory element in a digital circuit. A pair of cross-coupled inverters may be connected in a feedback loop, where the output of one inverter is coupled to the input of the other inverter and vice versa. The feedback loop creates a bistable state, where the circuit may remain in one of two relatively stable states for a long time until a signal is applied to change the signal state.

[0031] The first input bit signal CKo[0] may be supplied to the initial stage between the first main inverter of the initial stage and the cross-coupled inverter pair of the initial stage. The second input bit signal CKo[1] may be supplied to the initial stage between the second main inverter of the initial stage and the cross-coupled inverter pair of the initial stage. The first output bit signal CKo[0] may be output at the initial stage between the first main inverter of the initial stage and the cross-coupled inverter pair of the initial stage. The second output bit signal CKo[1] may be output at the second stage between the second main inverter of the second stage and the pair of cross-coupled inverters of the second stage. The third output bit signal CKo[2] may be output at the initial stage between the second main inverter of the initial stage and the cross-coupled inverter pair of the initial stage. The fourth output bit signal CKo[3] may be output at the second stage between the first main inverter of the second stage and the cross-coupled inverter pair of the second stage.

[0032] To tune the frequency range, the following method can be used. The capacitors at the initial stage or the second stage can be adjusted to cover a wide frequency range. This adjustment contributes to the additional loading of high frequency clock operation.

[0033] Another tuning method may be performed via controlling at least one of the cross-coupled inverters of the initial stage or the second stage to achieve a wide frequency range. This tuning method may result in a weakened start-up condition for the oscillator and may cause additional loading at critical nodes.

[0034] In addition, the size of the primary inverters of the initial or second stage may be adjusted to support different frequency applications. This adjustment may be achieved by adding a P-channel metal oxide semiconductor (PMOS) or N-channel metal oxide semiconductor (NMOS) current source to each primary inverter. This adjustment of the size of the primary inverter may result in additional noise from the current source, which may degrade the output jitter performance.

[0035] Jitter refers to the timing variations of signal transitions. Jitter can damage the accuracy and reliability of data transmission. Jitter can cause errors in digital systems and can lead to data loss, interference or corruption. Jitter can be caused by various factors, such as electromagnetic interference, signal reflections, crosstalk and thermal noise. One type of jitter is deterministic jitter, which can be caused by system factors, such as signal distortion, clock jitter or interference.

[0036] Sizing the main inverter may result in inherent mismatches in each stage due to the presence of individual current source mismatches. Sizing the main inverter may result in the output common mode voltage being more sensitive to the PMOS or NMOS skew angle, and the next stage duty cycle may be distorted.

[0037] Duty cycle refers to the ratio of the time a device or system remains active to the total time the device or system is available for operation. Duty cycle can be expressed as a percentage. Duty cycle can refer to the ratio of the amount of time a signal or current is on to the total time the signal or current is available for on or off. Duty cycle can be the ratio of the time a signal is active to the total period of the signal.

[0038] Sensitivity refers to the ability of an electronic circuit to detect relatively small changes in an input signal or parameter. Sensitivity refers to how well a circuit can respond to weak or low amplitude signals. Sensitivity can be measured in volts per unit of input signal or as a ratio of the output signal to the input signal. A highly sensitive circuit can detect very small signals and produce a correspondingly large output signal.

[0039] The injection strength is used by the ILRO to determine the locking range or bandwidth. Various methods can be used to control the programmable injection strength. For example, the injection buffer drive capability can be used to control the injection strength. This control can be implemented in a current mode logic device via a differential pair of buffers with current source tuning.

[0040] In general, intensity describes the strength or magnitude of a particular characteristic, property, or force. In terms of electric current, intensity refers to the amount of charge flowing through a conductor per unit time. The strength of an electric current is measured in amperes (amps). The strength of a voltage is measured in volts.

[0041] A buffer is a device or circuit used to separate or isolate two or more connected circuits with different characteristics. The buffer amplifies the input signal and maintains the relative integrity of the input signal while preventing or substantially reducing signal loss caused by impedance mismatch between the two circuits. The buffer can act as a bridge between two circuits, thereby facilitating accurate and efficient transmission of signals. For example, a buffer can be used to prevent signal distortion and reduce the load on other components of the circuit system.

[0042] In ILRO, a first buffer may be coupled between a first input bit signal CKi[0] and a first node, which may be between a first main inverter of an initial stage and a cross-coupled inverter pair of the initial stage. A second buffer may be coupled between a second input bit signal CKi[1] and a second node, which may be between a second main inverter of the initial stage and a cross-coupled inverter pair of the initial stage. This configuration provides a wider swing variation across PVT.

[0043] Another control method that exploits the injection buffer drive capability can be implemented in a complementary metal oxide semiconductor (CMOS) logic device. This control method can be implemented via an inverter with resistor derating or PMOS and NMOS current source tuning. This configuration increases the device size and can be parasitic at the injection node.

[0044] Another method of controlling the swing of the input signal CKi[1:0] may be implemented with an amplitude control loop. A loop refers to a closed path that a current follows. A loop may be formed when a circuit connects two or more components or elements in a circuit to allow current to flow between them. The direction and magnitude of the current in the loop are determined by the voltage and resistance of the components in the loop. The control method with an amplitude control loop uses an analog rectifier and may have low sensitivity to accurately convert the input signal to a direct current (DC) output. This configuration may be sensitive to PVT and increase the load on the input signal CKi[1:0].

[0045] Figure 1 An injection locked divider (IL-DIV or IL divider) system 100 having an IL divider 102 in a receive clock path is illustrated according to some embodiments. The injection locked divider 102 may include a plurality of buffers 104a to 104d corresponding to the number of input phases of an input signal CKi. For example, the input signal CKi may have four input phases: clock in-phase (CKI), clock inverted (CKIB), quadrature clock in-phase (CKQ), and quadrature clock inverted (CKQB).

[0046] In some embodiments, the IL divider 102 may be symmetrical, for example, the IL divider 102 may have identical or similar stages coupled in series. A "stage" may refer to a specific component or section within the IL divider 102. Each "stage" in the IL divider 102 represents a discrete portion or building block of the entire IL divider 102. The stages operate together to achieve frequency synchronization, clock generation, frequency synthesis, etc. Symmetrical stages are stages within various systems or circuits that are configured to maintain balance and relatively equal characteristics (e.g., amplitude, delay, load, impedance, and the like) to enable the system to operate predictably and with reduced distortion or error. Each stage in the symmetrical stages may have identical or similar components as the other stages.

[0047] Symmetrical IL divider 102 can provide skew correction from superharmonic distortion using symmetrical injection. IL divider 102 can be used as a divider that divides the input phase by a number N (e.g., divides the number of input phases by 2). IL divider 102 can reduce mismatch between in-phase and quadrature (I / Q) from four injected clocks.

[0048] Improved I / Q skew reduction can be achieved without the need for a quadrature locked loop (QLL) to compensate for the I / Q skew. In some embodiments, due to the symmetrical injection architecture of the IL divider 102, the IL divider system 100 can operate without a quadrature locked loop (QLL). The QLL generates in-phase (I) and quadrature (Q) signals. The I and Q signals generated by the QLL can be injected as reference signals into an injection locked divider (ILRO). Due to injection locking, the ILRO can divide these reference signals to maintain relatively accurate phase and frequency synchronization.

[0049] In some embodiments, the IL divider system 100 may include a frequency calibration engine 108. A calibration engine is a hardware, firmware, or software program or combination thereof that can be used to adjust and fine-tune settings of a device, system, or the like. The calibration engine may be configured to be able to generate accurate and reliable values ​​output by devices and systems. In some embodiments, the calibration engine may utilize a set of algorithms and mathematical models to evaluate the values ​​output by the devices. The calibration engine compares the actual values ​​generated by these devices to provided reference values ​​and adjusts the settings accordingly.

[0050] Frequency calibration refers to the process of adjusting the frequency output of the IL divider system 100 to match a known desired frequency. This desired frequency may be provided by an external source. The purpose of calibration is to ensure that the output frequency of the IL divider system 100 is accurate and reliable within a specified range. Frequency calibration may be achieved by various methods, such as using a frequency counter or spectrum analyzer to compare the output frequency of the IL divider system 100 to the desired frequency. The calibration process involves adjusting the frequency of the IL divider system 100 using a feedback loop until the output frequency matches the desired frequency.

[0051] In some embodiments, the IL divider 102 can be designed to operate within a narrow lock range, and the frequency calibration engine 108 can achieve input skew reduction and jitter performance optimization over PVT at different clock frequencies. The duty cycle control engine 106 can include a plurality of duty cycle control loops 201 ( Figure 7 ).

[0052] Buffers 104a to 104d and duty cycle control engine 106 may provide fixed swing and duty cycle for the injected clock. Fixed swing refers to a type of signal amplification used to produce an output signal of relatively constant peak amplitude. Fixed swing may be achieved by setting the amplifier gain and bias so that the output signal is limited to a fixed voltage range (regardless of the amplitude of the input signal). Circuits for fixed swing amplification limit the amplitude of the output signal by clipping the portion of the signal that exceeds a preset threshold. The threshold may be adjusted manually or automatically to ensure that the output signal remains within the desired range.

[0053] Buffers 104a to 104d or duty cycle control engine 106 can reduce the IL divider lock range and bandwidth sensitivity. To minimize the IL divider 102 jitter induced by power supply noise, current source 186 ( Figure 3 ) can be added to the IL divider system 100. This current source 186 can isolate or reduce noise from the power supply.

[0054] The above architecture may be implemented with different numbers of input and output phases depending on the requirements of the IL divider system 100. For example, the IL divider 102 may divide the input phase by 4, 8, 16, etc.

[0055] Figure 2 A block diagram illustrating a core component 110 (IL divider core) of an IL divider 102 according to some embodiments. In some embodiments, the IL divider core 110 may include four stages: 112, 114, 116, and 118. The IL divider core 110 may include a main inverter (e.g., inverters 128, 130, 144, and 146) and a cross-coupled inverter (e.g., inverters 152 and 154). In some embodiments, the IL divider core 110 may include a feed-forward resistor (e.g., resistors 164 and 166) and an injection switch (e.g., switch 168 of the first stage 112). In some embodiments, the IL divider core 110 may include a differential capacitor (e.g., capacitor 170 of the first stage 112).

[0056] The IL divider core 110 may receive a 4-phase input signal CK1T[3:0] which is symmetrically injected into the IL divider core 110. For example, the 4-phase input signal CK1T[3:0] may include CK1T[0], CK1T[1], CK1T[2], and CK1T[3] phase input signals having first, second, third, and fourth phases, respectively. The IL divider core 110 may generate an 8-phase CK2T[7:0] output signal which may include CK2T[0], CK2T[1], ..., CK2T[7] phase input signals having first, second, ..., eighth phases, respectively.

[0057] Each stage may include a first node and a second node such that an input signal is input between the first node and the second node. For example, the first stage (initial stage) 112 may include a first node 120 and a second node 122. The first stage 112 may receive a first input signal CK1T[0] having a first phase of the input signal CK1T[3:0]. In some embodiments, the first input signal CK1T[0] is received between the first node 120 of the first stage 112 and the second node 122 of the first stage 112.

[0058] In some embodiments, the second stage 114 may include a first node 124 and a second node 126. The second stage 114 may receive a second input signal CK1T[1] having a second phase of the input signal CK1T[3:0]. In some embodiments, the second input signal CK1T[1] may be received between the first node 124 of the second stage 114 and the second node 126 of the second stage 114. In some embodiments, the third input signal CK1T[2] may be received between the first node 180 of the third stage 116 and the second node 182 of the third stage 116. In some embodiments, the fourth input signal CK1T[3] may be received between the first node 148 of the fourth stage 118 and the second node 150 of the fourth stage 118.

[0059] In some embodiments, the first output signal CK2T[0] may be output at the first node 120 of the first stage 112. In some embodiments, the second output signal CK2T[1] may be output at the second node 126 of the second stage 114. In some embodiments, the third output signal CK2T[2] may be output at the first node 180 of the third stage 116. In some embodiments, the fourth output signal CK2T[3] may be output at the second node 150 of the fourth stage 118. In some embodiments, the fifth output signal CK2T[4] may be output at the second node 122 of the first stage 112. In some embodiments, the sixth output signal CK2T[5] may be output at the first node 124 of the second stage 114. In some embodiments, the seventh output signal CK2T[6] may be output at the second node 182 of the third stage 116. In some embodiments, the eighth output signal CK2T[7] may be output at the first node 148 of the fourth stage 118.

[0060] Each stage 112 to 118 may include a first inverter and a second inverter (main inverter), each having a first end and a second end. For example, the first stage 112 may include a first inverter 128 having a first end 132 and a second end 134. In some embodiments, the first stage 112 may include a second inverter 130 having a first end 136 and a second end 138.

[0061] In some embodiments, the last stage (e.g., fourth stage) 118 may include a first node 148 and a second node 150. In some embodiments, the second end 134 of the first inverter 128 of the first stage 112 is coupled to the second node 150 of the last stage 118. In some embodiments, the first node 148 of the last stage 118 is coupled to the second end 138 of the second inverter 130 of the first stage 112.

[0062] In some embodiments, the second stage 114 may include a first inverter 144 having a first end and a second end 140. In some embodiments, the second stage 114 may include a second inverter 146 having a first end and a second end 142. In some embodiments, the first end 132 of the first inverter 128 of the first stage 112 is coupled to the first node 120 of the first stage 112. In some embodiments, the first node 120 of the first stage 112 is coupled to the second end 140 of the first inverter 144 of the second stage 114.

[0063] In some embodiments, each stage 112, 114, 116, and 118 of the IL divider core 110 may include a pair of cross-coupled inverters. For example, the first stage 112 may include a pair of cross-coupled inverters, such as a third inverter 152 having a first end 156 and a second end 158 and a fourth inverter 154 including a first end 160 and a second end 162.

[0064] In some embodiments, the third inverter 152 and the fourth inverter 154 of the first stage 112 are cross-coupled such that a first end 156 of the third inverter 152 and a second end 162 of the fourth inverter 154 of the first stage 112 are coupled to the first node 120 of the first stage 112 .

[0065] In some embodiments, the third inverter 152 of the first stage 112 and the fourth inverter 154 of the first stage 112 are cross-coupled such that a second end 158 of the third inverter 152 of the first stage 112 and a first end 160 of the fourth inverter 154 of the first stage 112 are coupled to the second node 122 of the first stage 112 .

[0066] In some embodiments, the IL divider core 110 includes a first resistor 164 and a second resistor 166. In some embodiments, the first resistor 164 is coupled between the second end 138 of the second inverter 130 and the first node 120 of the first stage 112. In some embodiments, the second resistor 166 is coupled between the second end 134 of the first inverter 128 and the second node 122 of the first stage 112.

[0067] In some embodiments, capacitor 170 of first stage 112 may be coupled between first node 120 and second node 122 of first stage 112. In some embodiments, first stage 112 may have switches 172 and 174 between capacitor 170 and respective first and second nodes 120 and 122 of first stage 112.

[0068] In some embodiments, the size of the main inverters (e.g., inverters 128, 130, 144, 146) may be determined by the target frequency and jitter requirements. Cross-coupled inverters (e.g., inverters 152 and 154) may be used to reduce or avoid latched states and satisfy differential clock relationships at PMOS / NMOS (PN) skew angles. Latch-up refers to a condition where a device becomes locked in an undesired state to cause failure or damage. By using complementary clock signals from inverters 152 and 154, the setup and hold times of sequential elements in the circuit may be balanced to cause the data input to be relatively stable during both the rising and falling edges of the clock.

[0069] Feed-forward resistors, such as resistors 164 and 166 (also referred to as series input resistors), are passive electronic components used to improve the linearity and stability of amplifier circuits. Feed-forward resistors can attenuate input signals and reduce the amount of distortion caused by the nonlinearity of the amplifier gain. By reducing the input signal level, feed-forward resistors can prevent the amplifier from becoming saturated or clipping, which can cause distortion and signal loss.

[0070] Feed-forward resistors, such as resistors 164 and 166, can be used to reduce or avoid latch-up conditions, increase operating frequencies, and balance I / Q phase mismatches. For example, in an amplifier, the input signal passes through the main amplification path, which is used to provide most of the amplification. Due to the characteristics of active components in the path, such as transistors or operational amplifiers, this path may have limitations in bandwidth. The feed-forward resistor introduces an auxiliary path for the input signal. The auxiliary path shunts a small portion of the input signal and processes this small portion of the input signal separately. The shunt signal is processed in a manner that causes the shunt signal to carry the distortion and nonlinearity present in the main path. By processing the shunt signal to be out of phase with the distortion introduced in the main path and equal in magnitude, the shunt signal is effectively canceled when combined with the main signal at the output. This cancellation process allows for the reduction of distortion and nonlinearity, thereby effectively extending the available bandwidth of the amplifier or circuit. The auxiliary path "cleans up" the signal, enabling the system to accurately amplify a wider range of frequencies.

[0071] It is desirable to include in-phase (I) and quadrature (Q) components with equal amplitude and 90 degree phase difference (quadrature). I / Q mismatch may occur when there is a difference between the amplitude and phase of the I and Q components. I / Q mismatch may occur due to imperfections in components of, for example, a modulator or demodulator, such as amplitude and phase imbalances in a mixer, amplifier, or coupler. In some embodiments, feed-forward differential mode compensation using feed-forward resistors may reduce I / Q mismatch. For example, using feed-forward resistors instead of active current sources may reduce input capacitance, which in turn reduces I / Q mismatch.

[0072] The injection switches, such as switch 168, may include NMOS switches to reduce the load of the previous stage and use the load of each stage to determine the injection strength. The term "load" refers to the process of transferring data, settings, or configurations from one stage to another. For example, switch 168 can reduce the effective load time because the data transfer and processing occurs simultaneously with the switch to another stage. In some embodiments, the timing of the switch operation can ensure that the load process of the next stage begins as soon as the current stage completes the operation of the current stage.

[0073] In some embodiments, implementing feedback control during the switching and loading process can help monitor and adjust timing and synchronization. This feedback control can affect the loading time of the previous stage by ensuring that the switching occurs when the next stage is ready to receive data. In some embodiments, preloading the next stage with data can help reduce the time required for data transfer. If the switching begins as soon as the data is ready, then this timing can reduce the loading time.

[0074] Differential capacitors, such as capacitor 170, may be used for coarse frequency tuning. For example, by varying the capacitance of differential capacitor 170, IL divider system 100 may be tuned to achieve a desired frequency with a wider range of target frequencies without implementing fine tuning methods that require more precise frequency synchronization mechanisms or fine tuning timing.

[0075] In some embodiments, the differential capacitor (or varactor) may be a semiconductor device having a capacitance that depends on voltage. For example, the capacitance of a varactor may be controlled by changing the voltage applied to it. For example, increasing the voltage across the varactor may cause its capacitance to decrease, and conversely, decreasing the voltage causes the capacitance to increase. In an injection locked oscillator (ILO), a varactor may be integrated into a resonant circuit along with an inductor and a fixed capacitor. In some embodiments, a varactor may provide coarse frequency tuning. By adjusting the voltage applied to the varactor, the capacitance within the resonant circuit changes, which in turn affects the oscillator resonant frequency. The resonant frequency of the oscillator is inversely proportional to the square root of the product of the inductance and the capacitance. Therefore, in the injection locking process, the varactor may perform an initial coarse adjustment before performing a subsequent more precise frequency adjustment to synchronize with the injected signal.

[0076] Differential capacitor 170 can improve clock swing and jitter. Clock swing refers to the magnitude of the voltage change of the clock signal. Differential capacitor 170 can be adjusted to tune the delay of the ring oscillator in IL divider system 100. Therefore, the output frequency can be controlled and the adjustment of differential capacitor 170 can affect the clock swing. In order to meet the target frequency, the capacitance can be adjusted so that a smaller differential capacitance can result in a reduced swing with less current consumption, while a larger capacitance can result in an increased swing and increased current consumption. Jitter refers to the timing variation of the clock edge. When the output frequency is controlled using differential capacitor 170, this control can reduce jitter. Jitter is associated with phase noise, and by stabilizing the oscillator frequency, IL divider system 100 can reduce the variation of the clock edge timing, resulting in lower jitter.

[0077] In some embodiments, there may be a different number of stages, a different number of phases of the input and output signals, etc.

[0078] Figure 3 1. An IL divider with frequency calibration according to some embodiments is described. In some embodiments, a calibration engine 180 may perform frequency calibration. The frequency calibration engine 180 may include a calibration divider 182, a frequency calibrator 184, and a digitally controlled current source (DCCS) 186. The calibration divider 182 may divide the phase of the output signal CK2T[7:0] by a number N (e.g., divide the number of output phases by 2). The DCCS 186 may include a reference current source 192 that supplies a reference current (Iref), a pair of transistors 190a, 190b, one or more capacitors 194, and one or more resistors 196.

[0079] In some embodiments, calibration divider 182 may output a calibration divider clock signal (cal_ck) that may be used as an input to frequency calibrator 184. Frequency calibrator 184 may receive a reference clock signal (ref_ck) having a target frequency.

[0080] A frequency calibrator is a device used to measure and adjust the frequency of a signal. The frequency calibrator is configured to generate a stable test signal with a known frequency and amplitude, which is then applied to the device under test. The device's response to the test signal is then measured and compared to the expected response. Any differences can be corrected by adjusting the device frequency or other settings until the device produces the desired results. This frequency calibration process ensures the accuracy and precision of the device frequency measurement and calibration, allowing the device to operate efficiently.

[0081] Short reference Fig. 9A code (e.g., "cal_en") provided by the frequency calibrator 184 may indicate when to begin frequency calibration, for example, before analog biasing is ready. Analog biasing refers to the introduction of a small controlled voltage or current to set the operating point or quiescent point of an analog circuit. This biasing technique is used to enable circuit components to operate within their linear operating range and reduce signal distortion.

[0082] When calibration is complete, another code (eg, "cal_done") may be activated and begin injecting the clock input signal CK1T[3:0] into the IL divider system 100. Fig. 9 As described, the frequency calibrator 184 performs calibration of the signal cal_ck to adjust the signal cal_ck so that the signal cal_ck falls within a range corresponding to a target frequency of the signal ref_ck received by the frequency calibrator 184 .

[0083] In some embodiments, the frequency calibrator 184 applies a code “Iband[9:0]” having, for example, 10 bits corresponding to DCCS settings configured for individual system applications to overcome variations in process and supply voltages (eg, PVT parameters).

[0084] In some embodiments, temperature variations may be compensated by adjusting the reference current (Iref) or configuring the DCCS 186 based on temperature sensor information.

[0085] In some embodiments, the IL divider core 110 with the current source 186 can prevent or reduce the noise caused by the power supply VDD. In some embodiments, VDDR represents the voltage supplied to the IL divider core 110. The current source 186 coupled between VDD and VDDR can provide a constant current (regardless of the change in load resistance) and provide a stable current between VDD and VDDR. The use of the current source 186 can keep the voltage division between VDD and VDDR consistent. The current source 186 can have a high input impedance, for example, the current source 186 can draw a relatively small current from the circuit between VDD and VDDR in which the current source 186 is coupled. This can help maintain the accuracy of the voltage divider because it does not significantly affect the circuit to which it is connected. By controlling the current source 186, the current flowing through the divider network between VDD and VDDR can be determined. This control of the current source 186 can control the voltage level at different points in the cascade structure with relatively high accuracy. The use of the current source 186 can provide isolation between different stages in the cascade, for example, at the node where VDD is coupled and at the node where VDDR is coupled. This isolation can reduce interference between the stages (where VDD and VDDR are coupled) and maintain signal integrity.

[0086] Figure 4The I / Q skew reduction ratio implemented in the IL divider system 100 according to some embodiments is illustrated. The I / Q skew at the input signal (e.g., CK1T[3:0]) is a major part of the phase interpolator (PI) nonlinearity. The I / Q correction using the IL divider system 100 improves the I / Q skew at the IL divider output signal (e.g., CK2T[7:0]).

[0087] For example, the I / Q skew after the IL divider system 100 is reduced by more than a factor of 10 (using the absolute value of the CK2T output I / Q phase error). The symmetric injection of the IL divider system 100 provides improved cancellation of I / Q skew over PVT variations.

[0088] Figure 5 The output signal CK2T frequency of the IL divider system 100 after frequency calibration according to some embodiments is illustrated. In some embodiments, the IL divider system 100 with frequency calibration using DCCS 186 can extend the operating range from 4 to 18 GHz. Without frequency calibration, the typical lock range of the target frequency can be between -2 GHz and +2 GHz.

[0089] Figure 6 Jitter performance (e.g., performance of root mean square (RMS) jitter) measured in, for example, femtoseconds (fs) at a frequency of 14 GHz is illustrated. After frequency calibration, the IL divider system 100 may set the Iband code to balance jitter and power. For example, the Iband[9:0] code may be set to 10'd550 at a typical process corner at nominal voltage and nominal temperature (TTNVNT). In some embodiments, the Iband[9:0] code may be set to 10'd650 at a slow process corner at low voltage and high temperature (SSL VHT). In some embodiments, the Iband[9:0] code may be set to 10'd500 at a fast process corner at low voltage and high temperature (FFL VHT).

[0090] Figure 7 An IL divider system 200 is illustrated having one or more input duty cycle control loops 201. In some embodiments, the IL divider system 200 may include a frequency calibration engine 108. In some embodiments, the IL divider 102 may be symmetrical, for example, the IL divider 102 may have identical stages coupled in series.

[0091] Duty cycle control engine 106 ( Figure 1 ) may include a plurality of duty cycle control loops 201a to 201d corresponding to the number of input phases of the input signal CKIN. For example, the input signal CKIN may have four input phases. The duty cycle control engine 106 may have four duty cycle control loops 201a to 201d (e.g., Figure 7In some embodiments, the signal CK1T[3:0] may be output from the duty cycle control engine 106 and received by the IL divider 102.

[0092] Each input duty cycle control loop 201 may include an amplifier 202 (e.g., an operational amplifier), a pair of resistors 212, 216, a pair of capacitors 214, 218, and a pair of switches 208, 210. A feedback loop may be configured by a loop corresponding to nodes 220, 222, 224, 226, 228, and 230 of the duty cycle control loop 201. In some embodiments, a pair of inverters 204, 206 may be included in each buffer 104a-104d.

[0093] An amplifier, such as an operational amplifier, abbreviated as op-amp, is a high-gain, voltage differential amplifier that has two inputs, referred to as inverting (-) and non-inverting (+) inputs, and a single output. The operational amplifier can amplify the voltage difference between the two inputs. For example, the output voltage Vout of the operational amplifier can be equal to the open-loop gain A of the amplifier multiplied by the difference between V+ and V-, where V+ is the voltage at the non-inverting input and V- is the voltage at the inverting input.

[0094] The inverting input of amplifier 202 may be coupled in series with resistor 216 and inverters 204, 206, which are coupled in series with each other and with resistor 216. The non-inverting input of amplifier 202 may be coupled to a reference voltage source V REF The output of amplifier 202 may be coupled to a bias voltage source Vbias. The bias voltage source Vbias may be coupled in parallel to a VSS voltage source (which may be, for example, grounded).

[0095] In some embodiments, the signal CK1T[3:0] can be designed as a CMOS rail-to-rail clock output using the duty cycle control engine 106. The switches 208 and 210 can be activated by the instructions "cal_done" and "cal_doneB", respectively, which are activated by the switches 208 and 210 from the frequency calibration engine 108 ( Figure 1 and 3 ) is received. In the operating state of the duty cycle control loop 201, after "cal_done" is activated, the signal with the corresponding phase of the signal CK1T[3:0] will be valid. Otherwise, the signal CK1T[3:0] remains in the low position until the frequency calibration is completed.

[0096] For example, during frequency calibration, the duty cycle control loop 201 is in a non-operational state and “cal_doneB” is activated and switch 210 is turned on, while switch 208 is turned off, and the signal CK1T[3:0] will be invalid, e.g., not sent from the plurality of duty cycle control loops 201. During this non-operational state, the feedback loops (loops corresponding to nodes 220, 222, 224, 226, 228, and 230) are invalid because node 230 is coupled to the VSS voltage source, which may correspond to the ground voltage. When the frequency calibration is completed, “cal_done” is activated and the feedback loops of the duty cycle control loop 201 (loops corresponding to nodes 220, 222, 224, 226, 228, and 230) are valid (in an operational state) and the CK1T[3:0] signal is sent by the plurality of duty cycle control loops 201 and the signal CK1T[3:0] is received by the IL divider 102.

[0097] Amplitude to phase modulation (AM to PM) effects occur when the phase of a signal is modulated by amplitude variations of the signal. AM to PM effects can be caused by nonlinear components in the signal path or imperfections in the modulation process. When these amplitude variations occur, they introduce phase distortion into the signal. Fixed swing input refers to a relatively constant, unchanging amplitude level of the input signal. During a fixed swing input, the amplitude of the modulated signal remains relatively constant over time. The fixed swing input of the IL divider 102 can reduce the AM to PM effect and reduce the lock range variation of the IL divider 102. When the input signal has a fixed swing or constant amplitude, the AM to PM effect is typically minimal because there are no input signal amplitude variations that induce phase variations.

[0098] In some embodiments, the duty cycle control loop 201 of the input signal CK1T[3:0] can be programmed to adjust the lock range (eg Figure 8 In some embodiments, the duty cycle control loop 201 can be programmed to adjust the switch 168 ( Figure 1 ) injection intensity.

[0099] The duty cycle control loop 201 can suppress PN device mismatch and aging effects to maintain the quality of the CK1T[3:0] signal. For example, by adjusting the voltage V REF , the duty cycle of the output clock can be determined. The duty cycle is the ratio of the time the signal is in the valid state (high) to the total period of the signal. By adjusting V REF , can change the reference voltage level for components involved in generating the clock signal. This voltage change of the component can affect the timing of the signal transitioning between the high and low states of the clock signal, thus affecting the duty cycle.

[0100] Figure 8The bandwidth and jitter performance of the IL divider 102 with different duty cycles of the input signal CK1T are illustrated. In some embodiments, different duty cycles of the input signal CK1T may provide different results for the IL divider bandwidth and jitter results, such as Figure 8 In some embodiments, duty cycle adjustability provides the benefit of fine-tuning ILRO performance.

[0101] In some embodiments, for a second order harmonic injection architecture, a larger duty cycle degrades the IL divider jitter and bandwidth. The IL divider systems 100, 200 provide various circuit advantages.

[0102] The IL divider system 100, 200 based on the DCCS186 provides power supply rejection (power supply rejection ratio, PSRR) and a wide frequency range. PSRR quantifies the ability of a circuit to reject or attenuate variations in the power supply voltage. PSRR measures the ability of a device to maintain the performance or output of the device in the presence of variations or noise in the power supply voltage.

[0103] The IL divider systems 100, 200 can provide robust jitter and skew reduction across PVT and PN mismatches. Because the adjustment is done via digital control, the adjustment result is less sensitive to mismatches.

[0104] The IL divider system 100, 200 can provide less drive capability requirements for the IL divider input clock to save power. The term "drive capability" refers to the ability of an electronic circuit or component to provide a signal with the required characteristics to effectively operate another component or subsystem. For example, in the context of an injection-locked divider input clock, the drive capability is related to the strength and quality of the clock signal delivered to the IL divider. The drive capability includes factors such as the signal voltage level, the ability of the signal to maintain a stable and accurate frequency, and the ability of the signal to overcome impedance mismatches and signal degradation on the transmission line. The drive capability covers the signal ability to "drive" or properly operate the input of the injection-locked divider to facilitate the injection-locked divider to receive a relatively clean, synchronous and reliable clock signal. The IL divider system 100, 200 can reduce this drive capability requirement while reducing the power requirements to perform this drive capability.

[0105] In some embodiments, the drive capability (or drive strength) of an oscillator may refer to the ability of the oscillator to counteract the effects of capacitive loading (or capacitance loading) and other external factors that may otherwise disrupt the stable oscillation of the oscillator (e.g., IL divider 100, 200). When the oscillator is subjected to capacitive loading, the oscillator experiences changes in the electrical characteristics of the oscillator. The capacitor adds additional load to the oscillator circuit, thereby affecting the resonant frequency and overall performance of the oscillator. The drive strength of the oscillator enables the oscillator to maintain oscillation when experiencing changes in capacitance (or capacitive) loading.

[0106] In some embodiments, the adjustment of the IL divider bandwidth and jitter can be performed by changing the duty cycle of the IL divider system 100, 200. The IL divider system 100, 200 provides various advantages for the system implementing the IL divider system 100, 200. For example, the IL divider system 100, 200 can improve the jitter tolerance, effective number of bits (ENOB) and signal to noise and distortion ratio (SNDR) of the receiver system. ENOB is a measure of the number of bits of resolution that can be achieved in analog / digital conversion. Reducing jitter leads to more accurate and stable timing of the analog / digital converter (ADC). SNDR quantifies the quality of the output signal compared to noise and distortion. Lower jitter can lead to better SNDR through several mechanisms, such as reducing aperture jitter and reducing the noise floor. Aperture jitter refers to the uncertainty of the sampling instant. Reducing the jitter of the sampling clock can reduce aperture jitter, thereby improving the accuracy of the analog / digital conversion. Jitter-induced noise can be considered as an additional noise floor in the system. By reducing jitter, the additive noise floor is lowered, resulting in a cleaner signal and improved SNDR.

[0107] The IL divider system 100, 200 provides various advantages for products implementing the IL divider system 100, 200. In some embodiments, the IL divider system 100, 200 can be extended to a wide frequency range covering various communication standards. For example, the IL divider system 100, 200 can increase data rates and speeds. The system described herein can extend channels to longer distances by reducing clock jitter compared to other systems that do not implement the features of the IL divider system 100, 200. In some embodiments, the IL divider system 100, 200 can provide lower power and area consumption.

[0108] In some embodiments, multi-phase clock generation or clock skew compensation methods may be implemented by the IL divider system 100, 200, for example, in a time-interleaved analog-to-digital converter (ADC) application. The IL divider system 100, 200 may at least partially alleviate challenges of multi-phase clock distribution, such as amplitude and phase mismatch, which may be sensitive to process, temperature, and voltage. The IL divider system 100, 200 may at least partially compensate for or reduce phase mismatch between multi-phase clocks. The IL divider system 100, 200 may at least partially improve clock jitter performance after long channel distribution or multi-stage cascading.

[0109] The IL divider system 100, 200 can be implemented using an injection locked circuit (e.g., an oscillator or divider); such a circuit can be relatively straightforward to calibrate. To improve the locking range and phase correction of the injection locked circuit, frequency calibration can be utilized. For example, multiple phase interpolators (PIs) and injection locked circuit calibration can be implemented by the IL divider system 100, 200.

[0110] In some embodiments, the IL divider systems 100 , 200 may have different chip measurements at the receiver ADC output compared to other ILRO systems that do not implement the IL divider systems 100 , 200 .

[0111] Typically, I / Q path (even and odd paths) mismatch information may be available.The architecture of the IL divider systems 100, 200 provides instant or near instant recovery of I / Q skew, while other ILRO systems (eg, asymmetric ILRO systems) fail to provide consistent performance under different external conditions.

[0112] In some embodiments, when a chip with the IL divider system 100, 200 operates at different operating rates (or VCO frequencies), I / Q path mismatch may occur from even or odd ADC outputs. The architecture with the IL divider system 100, 200 provides consistent I / Q path matching. Some frequency tuning methods that do not implement the IL divider system 100, 200 may have significant I / Q path matching degradation for wideband operation.

[0113] In the IL divider system 100, 200, the noise floor of the ADC spectrum may be different at different process corners of the semiconductor chip. The slow-slow (SS) corner may provide a higher noise floor than the typical (TT) corner. The architecture of the IL divider system 100, 200 may set calibration codes for the IL divider system 100, 200 to provide an improved noise floor in each corner. In some embodiments, there is substantially no noise floor difference at the SS and TT corners over process variations.

[0114] In some embodiments, the inductors from the VCO and distributed clock routing can be traced to each channel of the semiconductor chip. The architecture of the IL divider system 100, 200 can utilize a symmetric injection locked divider, and symmetric placement of input and output clock routing can exist in each channel. In some embodiments, the digital controlled current source (DCCS) can have a relatively large active device area and passive low pass filter compared to other clock buffers.

[0115] High performance multi-phase clock paths are used in high speed transceiver applications. When the clock runs at high speed, the system is more sensitive to jitter in the clock path. The higher the clock speed, the worse the skew mismatch of the multi-phase clock can be. Injection locked oscillators or dividers can be an efficient and low cost solution to improve jitter and power.

[0116] The IL divider systems 100, 200 can be used in high-performance multi-phase clock generation. The IL divider systems 100, 200 and the method 1000 described herein can be implemented in network switches, computer systems in data centers, high-speed physical layers, coherent optical transceivers, and systems that perform 5G, 6G, next-generation, or microwave broadband data capture.

[0117] For example, in network applications such as data centers and telecommunications, high bandwidth and high data rates can be utilized. High-speed communications can be performed between network devices such as switches, routers, and servers. High-speed serializers and deserializers enable faster and more efficient data exchange, resulting in a relatively seamless flow of information across the network.

[0118] In artificial intelligence (AI) applications such as deep learning and neural networks, large amounts of data can be processed quickly and efficiently. Compared to other devices that do not implement the IL divider system 100, 200, the serializer and deserializer of the IL divider system 100, 200 that can operate at 200Gbps, 400Gbps, and 800Gbps transmission rates can effectively operate a high-performance computing system, thereby enabling relatively fast data exchange between GPUs, accelerators, and storage devices. This enables fast training and reasoning of complex AI models, thereby improving the overall performance and efficiency of the AI ​​system.

[0119] Fig. 9 is a flow diagram of an example process 900. In some embodiments, Fig. 9 One or more process blocks of may be performed by the IL divider system 100, 200. The IL divider system 100, 200 may have a series of symmetrical stages, as described above.

[0120] like Fig. 9 As shown in FIG. 9 , process 900 may include a method for calibrating signals of IL divider systems 100, 200. In some embodiments, code cal_en is generated by frequency calibrator 184 ( Figure 3 ) is provided to start frequency calibration of the frequency calibration engine 180 (block 902). In some embodiments, the method 900 checks whether the calibration is complete, for example, whether the code cal_done is activated (block 904). If the code cal_done is activated, the frequency calibration is stopped (block 906).

[0121] In some embodiments, if the code cal_done is not active, the frequency calibrator 184 initiates calibration of the signal cal_ck signal received from the calibration divider 182 (block 908). In some embodiments, the frequency calibrator 184 applies the code Iband[9:0] equal to one (1) and i equals nine (9) (blocks 908, 910).

[0122] In some embodiments, the signal cal_ck is adjusted so that the signal cal_ck falls within the target frequency f corresponding to the ref_ck signal received by the frequency calibrator 184. target If the frequency F of the cal_ck signal cal_ck Greater than the target frequency ftarget , then index i is decremented by one (1), e.g., index i is equal to eight (8) and the Iband[9:0] code is set to one (1) (block 910). cal_ck Less than the target frequency f target , then index i is decremented by one, for example, index i is equal to eight (8) and the Iband[9:0] code is set to zero (0) (block 910).

[0123] If after executing step 910, the frequency F of the signal cal_ck cal_ck Greater than the target frequency f target , then the index i is decremented by one (1), for example, the index i is equal to seven (7) and the Iband[9:0] code is set to zero (0) (block 912a). If the frequency F of the signal cal_ck cal_ck Less than the target frequency f target , then index i is decremented by one (1), eg, index i is equal to seven (7) and the Iband[9:0] code is set to one (1) (block 912b).

[0124] The process of decrementing index i and setting Iband[9:0] to different values ​​continues until index i reaches zero (0), e.g., further decrementing index i by one (1) results in index i being less than zero (0) (blocks 914a to b). If this condition is not met (e.g., decrementing index i by one (1) does not result in index i being less than zero (0)), then the iterative process of decrementing index i by one (1) and setting Iband[9:0] to different values ​​continues (arrow 916). Otherwise, if decrementing index i by one (1) results in index i being less than zero (0), then calibration is complete (blocks 918a to b). When calibration is complete, code cal_done may be activated to stop calibration within the frequency calibration engine 180.

[0125] although Fig. 9 An example block diagram of process 900 is shown, but in some embodiments, process 900 may be comparable to Fig. 9 The process 900 may include additional blocks, fewer blocks, different blocks, or differently arranged blocks rather than the blocks depicted in the process 900. In some embodiments, two or more blocks of the process 900 may be performed in parallel.

[0126] Fig.10 is a flow diagram of an example process 1000. In some embodiments, Fig.10 One or more process blocks of may be performed by the IL divider system 100, 200. The IL divider system 100, 200 may have a series of symmetrical stages, as described above.

[0127] like Fig.10As shown in FIG. 1 , process 1000 may include a method of increasing the number of phases in an output signal including a first plurality of phases (block 1010). Fig.10 As shown in FIG. 1 , process 1000 may include a method in which increasing the number of phases in the output signal is based on a second plurality of phases in the input signal (block 1012). Fig.10 , process 1000 may include a method where increasing the number of phases in an output signal is based on the number of symmetry stages in a series of symmetry stages (block 1014). In some embodiments, the series of symmetry stages enables an initial stage in the series to be coupled to an input signal (block 1016). In some embodiments, the series of symmetry stages may be coupled to an output stage in the series of symmetry stages to couple the output signal to a calibration engine, where the output signal includes a first plurality of phases (block 1018).

[0128] like Fig.10 As shown in FIG. 1 , process 1000 may include a method of calibrating a frequency of a circuit system within a range (block 1020). In some embodiments, calibrating the frequency of the circuit system may be performed by a calibration engine (block 1022). The frequency range may be based at least on a target frequency (block 1024).

[0129] like Fig.10 As shown in FIG. 1 , process 1000 may include a method of outputting a current coupled to a series (block 1030). In some embodiments, outputting the current may be performed by a calibration engine (block 1032). In some embodiments, the output current may be based on at least a calibration frequency (block 1034).

[0130] Process 1000 may include additional embodiments, such as any single embodiment or any combination of embodiments described below or in combination with one or more other processes described elsewhere herein. In a first embodiment, process 1000 further includes sending instructions to the circuitry of the current source by the frequency calibrator of the calibration engine. In some embodiments, the instructions may be based at least on the calibration frequency. In some embodiments, the method may include transmitting a current to the circuitry by the current source of the frequency calibrator, wherein the current may be based at least on the calibration frequency.

[0131] although Fig.10 An example block diagram of process 1000 is shown, but in some embodiments, process 1000 may be comparable to Fig.10 The process 1000 may include additional blocks, fewer blocks, different blocks, or differently arranged blocks rather than the blocks depicted in the process 1000. In some embodiments, two or more blocks of the process 1000 may be executed in parallel.

[0132] The following IEEE standards (including any draft versions of such standards) are hereby incorporated by reference herein in their entirety and become part of the present disclosure for all purposes: IEEE 802.3, IEEE 802.11x, IEEE 802.11ad, IEEE 802.11ah, IEEE 802.11aj, IEEE 802.16 and 802.16a, and IEEE 802.11ac. In addition, although the present disclosure may refer to aspects of these standards, the present disclosure is in no way limited by these standards.

[0133] After discussing specific embodiments of the present solution, it may be helpful to describe aspects of the operating environment and associated system components (eg, hardware elements) in conjunction with the methods and systems described herein. Fig.11A , depicting an embodiment of a network environment. The network may include or communicate with one or more storage area networks (SANs), security adapters, or Ethernet converged network adapters (CNAs). In short, the network environment includes a communication system that includes one or more network devices 1106, one or more client devices 1102, and network hardware components 1192. In some embodiments, the network device 1106 may be an access point (AP). In some embodiments, the client device 1102 may be a wireless communication device. For example, the client device 1102 may include a laptop computer 1102, a tablet computer 1102, a personal computer 1102, a wearable device 1102, a vehicle 1102 (such as a car, a drone, an intelligent vehicle, a robotic unit, and the like), an electronic game console 1102, a cellular telephone device 1102, a smart television 1102, an Internet of Things (IoT) device 1102, and any other electronic device 1102 capable of wireless communication. Reference Fig. 11B and 11C Details of embodiments of client device 1102 and network device 1106 are described in more detail. In one embodiment, the network environment may be an ad hoc network environment, an infrastructure wireless network environment, a wired network coupled to a wireless network, a subnet environment, or a combination of the foregoing.

[0134] The term "coupled" and its variations include two components being joined directly or indirectly to each other. The term "electrically coupled" and its variations include two components being joined directly or indirectly to each other through a conductive material (e.g., a metal or copper trace). This joining may be fixed (e.g., permanent or fixed) or movable (e.g., removable or releasable). This joining may be achieved by: two components being directly coupled to each other; two components being coupled to each other using a separate intermediary component and any additional intermediate components that are coupled to each other; or two components being coupled to each other using an intermediary component that is integrally formed as a single entity with one of the two components. If "coupled" or its variations are modified by additional terms (e.g., directly coupled), the general definition of "coupled" provided above is modified by the plain language meaning of the additional terms (e.g., "directly coupled" means that the two components are joined without any separate intermediary components), resulting in a narrower definition than the general definition of "coupled" provided above. This coupling may be mechanical, electrical, or fluidic.

[0135] The network devices 1106 may be operably coupled to the network hardware 1192 via a local area network connection. The network hardware 1192, which may include one or more routers, gateways, switches, bridges, modems, system controllers, appliances, and the like, may provide a local area network connection for the communication system. Each network device 1106 may have an associated antenna or antenna array to communicate with client devices in its area. Client devices may register with a particular network device 1106 to receive services from the communication system (e.g., via SU-MIMO or MU-MIMO configurations). For direct connections (i.e., point-to-point communications), some client devices may communicate directly via an assigned channel and communication protocol. Some client devices 1102 may be mobile or relatively stationary relative to the network devices 1106.

[0136] In some embodiments, the network device 1106 includes a device or module (including a combination of hardware and software) capable of connecting the client device 1102 to a wired or wireless network. The network device 1106 is oriented toward a wired connection and is also designed to support wireless connections. The configuration and design of the network device 1106 enable communication between the network device 1106 and the controller and storage device established by a wired link. In some embodiments, the network device 1106 can be connected to a router (e.g., via a wired network) as a standalone device. In other embodiments, the network device 1106 can be a component of a router. The network device 1106 can provide network access to multiple devices. The network device 1106 can, for example, be connected to a wired Ethernet connection and use a radio frequency link to provide a wireless connection for other devices 1102 to utilize the wired connection. The network device 1106 can be constructed and configured to support standards for sending and receiving data using one or more radio frequencies. These standards and the frequencies they use can be defined by IEEE (e.g., IEEE 802.11 standards). The network device 1106 may be configured and used to support public Internet hotspots and extend the Wi-Fi signal range of the network on an internal network.

[0137] In some embodiments, the network devices 1106 may be used for an indoor or in-building wireless network (e.g., IEEE 802.11, Bluetooth, ZigBee, any other type of radio frequency based network protocol or variants thereof). Each client device 1102 may include a built-in radio or be coupled to a radio. Such client devices 1102 and network devices 1106 may operate in accordance with various aspects of the present disclosure presented herein to enhance performance, reduce cost or size, and enhance broadband applications. Each client device 1102 may be capable of acting as a client node to seek access to resources (e.g., data and connections to networked nodes such as servers) via one or more network devices.

[0138] The network connection may include any type or form of network and may include any of the following: a point-to-point network, a broadcast network, a telecommunications network, a data communications network, or a computer network. The network topology may be a bus, star, or ring network topology. The network may have any such network topology known to those of ordinary skill in the art and may be capable of supporting the operations described herein. In some embodiments, different types of data may be transmitted via different protocols. In other embodiments, the same type of data may be transmitted via different protocols.

[0139] The client device 1102 and the network device 1106 may be deployed as or executed on any type and form of computing device, such as a computer, network device, or appliance capable of communicating over any type and form of network and performing the operations described herein. Fig. 11B and 11CA block diagram of a computing device 1100 is depicted for practicing an embodiment of a client device 1102 or a network device 1106. Fig. 11B and 11C As shown in FIG. 1 , each computing device 1100 includes a central processing unit 1121 and a main memory or main memory unit 1122. Fig. 11B As shown in FIG. 1 , computing device 1100 may include storage device 1128, installation device 1116, network interface 1118, I / O controller 1123, display devices 1124a to 1124n, keyboard 1126, and pointing device 1127, such as a mouse. Storage device 1128 may include, but is not limited to, an operating system or software. Fig. 11C As shown in , each computing device 1100 may also include additional optional elements, such as a memory port 1103 that communicates with a central processing unit 1121, a bridge 1170, one or more input / output (I / O) devices 1130a to 1130n (collectively referred to using reference numeral 1130), and a cache memory 1140.

[0140] "Circuitry" may refer to an interconnected arrangement of electronic components and paths that allow electrical signals to flow in a device, system, or application. In some embodiments, a single-component circuit system may be an electronic component that performs a specific function within an electronic system, such as a resistor, capacitor, or transistor. In some embodiments, multiple components working together in a circuit system may include coordination of various electronic components. In some embodiments, a circuit system may include hardware components, such as integrated circuits, transistors, resistors, capacitors, and connectors, and a combination of hardware and software or firmware elements that can operate together to perform various functions. Multiple components may include separate components, such as sensors, microcontrollers, memory modules, communication interfaces, or power management circuits, which are interconnected to form a functional system. For example, a circuit system may include a microcontroller or processor that executes software instructions to control the behavior of hardware components. For example, a circuit system processor may run a program to enable a device or system to perform various tasks, such as data processing and communication. Components may not be physically contained within the same device, for example, components may be distributed across different devices connected by wired or wireless interfaces.

[0141] The central processing unit (CPU) 1121 is any logic circuitry that responds to and processes instructions fetched from the main memory unit 1122. In many embodiments, the central processing unit 1121 is provided by a microprocessor unit, such as those manufactured by Intel Corporation of Mountain View, California, by International Business Machines of White Plains, New York, or by Advanced Micro Devices of Sunnyvale, California. The computing device 1100 may be based on any of these processors or any other processor capable of operating as described herein. The CPU may be a programmable parallel processor.

[0142] Other programmable parallel processors may include graphics processing units (GPUs) and neural processors. GPUs are programmable parallel processors that can perform complex calculations for graphics rendering and general computing tasks. GPUs consist of processing cores interconnected by high-bandwidth memory interfaces and bus systems to achieve efficient parallel processing. The processing cores of GPUs may be equipped with dedicated arithmetic logic units and memory caches, allowing multiple computing threads to be executed simultaneously. In order to optimize the graphics rendering pipeline, GPUs may incorporate the following hardware components: texture units and rasterizers. GPUs may use optimized algorithms and data parallel techniques to accelerate calculations, resulting in better performance than conventional CPUs. GPUs can be programmed using graphics APIs and parallel computing frameworks to achieve scientific simulations, machine learning, and data analysis.

[0143] The main memory unit 1122 may be one or more memory chips capable of storing data and allowing the microprocessor 1121 to access any storage location, such as any type or variation of static random access memory (SRAM), dynamic random access memory (DRAM), ferroelectric RAM (FRAM), NAND flash, NOR flash, and solid-state drive (SSD). The main memory 1122 may be based on any of the above memory chips or any other available memory chip capable of operating as described herein. Fig. 11B In the embodiment shown in , processor 1121 communicates with main memory 1122 via system bus 1150 (described in more detail below). Fig. 11C An embodiment of a computing device 1100 is depicted in which the processor communicates directly with the main memory 1122 via the memory port 1103. For example, in Fig. 11C In the embodiment, the main memory 1122 may be a DRAM.

[0144] Fig. 11CAn embodiment is depicted in which the main processor 1121 communicates directly with the cache memory 1140 via a secondary bus (sometimes referred to as a backside bus). In other embodiments, the main processor 1121 communicates with the cache memory 1140 using the system bus 1150. The cache memory 1140 has a faster response time than the main memory 1122 and is provided by, for example, SRAM, BSRAM, or EDRAM. Fig. 11C , the processor 1121 communicates with various I / O devices 1130 via a local system bus 1150. Various buses may be used to connect the central processing unit 1121 to any I / O device 1130, such as a VESA VL bus, an ISA bus, an EISA bus, a Micro Channel Architecture (MCA) bus, a PCI bus, a PCI-X bus, a PCI Express bus, or a NuBus. For embodiments in which the I / O device is a video display 1124, the processor 1121 may communicate with the display 1124 using an Advanced Graphics Port (AGP). Fig. 11C An embodiment of a computer or computer system 1100 is depicted in which the main processor 1121 can communicate directly with the I / O device 1130b, such as via HYPERTRANSPORT, RAPIDIO, or INFINIBAND communication technology. Fig. 11C Also depicted is an embodiment in which local busses and direct communications are mixed: processor 1121 communicates with I / O device 1130a using a local interconnect bus while communicating directly with I / O device 1130b.

[0145] Various I / O devices 1130a to 1130n may be present in computing device 1100. Input devices include keyboards, mice, track pads, trackballs, microphones, dials, touch pads, touch screens, and drawing tablets. Output devices include video displays, speakers, inkjet printers, laser printers, projectors, and dye sublimation printers. I / O devices may be controlled by I / O controller 1123, such as Fig. 11B 1100. The I / O controller may control one or more I / O devices, such as a keyboard 1126 and a pointing device 1127, such as a mouse or light pen. In addition, the I / O devices may also provide storage and installation media 1116 for the computing device 1100. In other embodiments, the computing device 1100 may provide a USB connection (not shown) to receive a handheld USB storage device, such as the USB flash drive series of devices manufactured by s Industry, Inc. of Los Alamos, California.

[0146] Reference again Fig. 11B, the computing device 1100 may support any suitable installation device 1116, such as a disk drive, a CD-ROM drive, a CD-R / RW drive, a DVD-ROM drive, a flash memory drive, a tape drive of various formats, a USB device, a hard drive, a network interface, or any other device suitable for installing software and programs. The computing device 1100 may further include a storage device (such as one or more hard drives or redundant arrays of independent disks (storage devices)) for storing an operating system and other related software and for storing application software programs, such as any program or software 1120 for implementing the systems and methods described herein (such as software 1120 configured or designed for the systems and methods described herein). In some embodiments, any installation device 1116 may be used as a storage device. In some embodiments, the operating system and software may be run from a bootable medium.

[0147] In addition, computing device 1100 may include a network interface 1118 that interfaces with network 1104 through various connections, including but not limited to a standard telephone line, a LAN or WAN link (e.g., 802.11, T1, T3, 56 kb, X.25, SNA, DECNET), a broadband connection (e.g., ISDN, Frame Relay, ATM, Gigabit Ethernet, Ethernet over SONET), a wireless connection, or some combination of any or all of the above. The connection may be established using various communication protocols (e.g., TCP / IP, IPX, SPX, NetBIOS, Ethernet, ARCNET, SONET, SDH, Fiber Distributed Data Interface (FDDI), RS232, IEEE 802.11, IEEE 802.11a, IEEE 802.11b, IEEE802.11g, IEEE 802.11n, IEEE 802.11ac, IEEE 802.11ad, CDMA, GSM, WiMax, and direct asynchronous connection). In one embodiment, the computing device 1100 communicates with other computing devices 1100 via any type and form of gateway or tunneling protocol, such as Secure Sockets Layer (SSL) or Transport Layer Security (TLS). The network interface 1118 may include a built-in network adapter, a network interface card, a PCMCIA network card, a card bus network adapter, a wireless network adapter, a USB network adapter, a modem, or any other device capable of communicating and performing the operations described herein suitable for interfacing the computing device 1100 to any type of network.

[0148] In some embodiments, the computing device 1100 may include or be connected to one or more display devices 1124a to 1124n. Thus, any I / O device 1130a to 1130n and the I / O controller 1123 may include any type or form of suitable hardware, software, or a combination of hardware and software to support, enable, or provide for the computing device 1100 to connect and use the display devices 1124a to 1124n. For example, the computing device 1100 may include any type or form of video adapter, graphics card, driver, and library to interface, communicate, connect, or otherwise use the display devices 1124a to 1124n. In one embodiment, the video adapter may include multiple connectors to interface to the display devices 1124a to 1124n. In other embodiments, the computing device 1100 may include multiple video adapters, each of which is connected to the display devices 1124a to 1124n. In some embodiments, any portion of the operating system of the computing device 1100 may be configured to use multiple displays 1124a to 1124n. One of ordinary skill in the art will recognize and appreciate the various ways and embodiments in which the computing device 1100 may be configured to have one or more display devices 1124a - 1124n .

[0149] In a further embodiment, the I / O device 1130 may be a bridge between the system bus 1150 and an external communication bus (such as a USB bus, an Apple Desktop bus, an RS-232 serial connection, a SCSI bus, a FireWire bus, a FireWire 1100 bus, an Ethernet bus, an AppleTalk bus, a Gigabit Ethernet bus, an Asynchronous Transfer Mode bus, a Fibre Channel bus, a Serial Attached Small Computer System Interface bus, a USB connection, or an HDMI bus).

[0150] Fig. 11B and 11CA computing device or system 1100 of the type depicted in the drawings may operate under the control of an operating system, which controls task scheduling and system resource access. The computing device 1100 may run any operating system, such as any version of the Microsoft Windows operating system, different versions of the Unix and Linux operating systems, any version of the MAC OS for Apple Computer, any embedded operating system, any real-time operating system, any open source operating system, any proprietary operating system, any operating system for mobile computing devices, or any other operating system capable of running on a computing device and performing the operations described herein. Typical operating systems include, but are not limited to, Android produced by Google Inc., WINDOWS 7 and 8 produced by Microsoft Corporation of Redmond, Washington, MAC OS produced by Apple Computer of Cupertino, California, WebOS produced by Research InMotion (RIM), OS / 2 and Linux produced by International Business Machines of Armonk, New York, a freely available operating system distributed by Caldera Corporation of Salt Lake City, Utah, or any type and form of Unix operating system, etc.

[0151] The computer system 1100 may be any network device, storage device, workstation, phone, desktop computer, laptop or notebook computer, server, handheld computer, mobile phone or other portable telecommunication device, media playback device, gaming system, mobile computing device, or any other type or form of computing, telecommunication or media device capable of communication. The computer system 1100 has sufficient processor power and memory capacity to perform the operations described herein.

[0152] In some embodiments, the computing device 1100 may have a different processor, operating system, and input device consistent with the device. For example, in one embodiment, the computing device 1100 is a smart phone, mobile device, tablet computer, or personal digital assistant. In other embodiments, the computing device 1100 is an Android-based mobile device, an iPhone smart phone manufactured by Apple Computer of Cupertino, California, or a Blackberry or WebOS-based handheld device or smart phone, such as a device manufactured by Research In Motion Limited. In addition, the computing device 1100 can be any workstation, desktop computer, laptop or notebook computer, server, handheld computer, mobile phone, any other computer or other form of computing or telecommunications device that is capable of communication and has sufficient processor power and memory capacity to perform the operations described herein. The aspects of the above operating environment and components will be understood in the context of the systems and methods disclosed herein.

[0153] It should be noted that certain paragraphs of the present disclosure may refer to terms (e.g., "first" and "second") associated with device signals, data, inputs, channels, and the like for identifying or distinguishing one from another or from others. These terms are not intended to relate entities (e.g., first input and second input) only in time or according to a sequence, although in some cases, these entities may include such a relationship, nor do these terms limit the number of possible entities (e.g., devices) that may operate within a system or environment.

[0154] It should be understood that the above-described systems may provide multiples of any or each of these components. In addition, the above-described systems and methods may be provided as one or more computer-readable programs or executable instructions, programmable circuits, or digital logic embodied on or in one or more articles of manufacture. The article of manufacture may be a floppy disk, hard disk, CD-ROM, flash memory card, PROM, RAM, ROM, ASIC, or magnetic tape. In general, the computer-readable program may be implemented in any programming language (e.g., LISP, PERL, C, C++, C#, PROLOG) or in any bytecode language (e.g., JAVA). The software program or executable instructions may be stored as object code on or in one or more articles of manufacture.

[0155] Although the above written description of the methods and systems enables a person of ordinary skill in the art to make and use various embodiments of these methods and systems, a person of ordinary skill in the art should understand and appreciate that there are variations, combinations, and equivalents of the specific embodiments, methods, and examples herein. Therefore, the methods and systems of the present invention should not be limited by the above-described embodiments, methods, and examples, but by all embodiments and methods within the scope and spirit of the present disclosure.

Claims

1. A circuit system, comprising: a series of symmetrical stages, wherein an initial stage in the series is coupled to an input signal comprising a first plurality of phases and an output stage in the series couples an output signal comprising a second plurality of phases to a calibration engine, wherein the number of phases in the output signal comprising the second plurality of phases is increased based at least on the number of the symmetrical stages and the number of the first plurality of phases in the input signal; wherein the calibration engine calibrates the frequency of the circuit system within a range based at least on a target frequency; and Wherein the calibration engine outputs a current provided to the series, the output current being based at least on a calibration frequency.

2. The circuit system according to claim 1, Each stage in the series of symmetrical stages comprises: A pair of first inverters are coupled in series to the pair of cross-coupled inverters or in parallel to the pair of feed-forward resistors.

3. The circuit system according to claim 2, wherein each stage in the series of symmetrical stages comprises the pair of first inverters coupled in series to the pair of cross-coupled inverters, and Each stage in the series of symmetrical stages further comprises a switch coupled in parallel to the cross-coupled inverters, the switch being used to control the injection strength of the output voltage.

4. The circuit system of claim 3, wherein the switch reduces a capacitive load of a preceding stage in the series of symmetrical stages on a succeeding stage in the series of symmetrical stages.

5. The circuit system of claim 2 , wherein each stage in the series of symmetrical stages further comprises: A capacitor is coupled in parallel to the cross-coupled inverters, the capacitor being used to tune the frequency of each stage in the series of symmetrical stages.

6. The circuit system of claim 5, wherein the capacitor reduces jitter of each stage in the series of symmetrical stages.

7. The circuit system of claim 1 , wherein the calibration engine further comprises: Frequency calibrator; and a current source, which is coupled to the frequency calibrator, wherein the frequency calibrator sends instructions to the circuitry of the current source, the instructions being based at least on the calibration frequency, and The current source transmits the current to the circuit system, the current being based at least on the calibration frequency.

8. The circuit system according to claim 1, further comprising: A series of loops, each loop comprising a series of inverters coupled in parallel to an amplifier, each loop for controlling a duty cycle of a phase of the first plurality of phases of the input signal.

9. The circuit system according to claim 1, further comprising: A series of buffers is coupled between the series of rings and the series of symmetric stages, the series of buffers being configured to provide a fixed swing of the output signal comprising the second plurality of phases.

10. The circuit system of claim 8, further comprising: a series of buffers coupled between the series of rings and the series of symmetric stages, the series of buffers for reducing at least one of a frequency range of the output signal or a bandwidth sensitivity of the frequency range of the output signal, Wherein the output signal comprises the second plurality of phases.

11. A system comprising: a series of symmetrical stages, the series configured to receive an input signal comprising a first plurality of phases; and a calibration engine coupled to the series of output stages and configured to receive output signals from the series, wherein the output signal comprises a second plurality of phases and the calibration engine is configured to calibrate the frequency of the series of symmetric stages to operate at a target frequency, wherein the output stages of the series of symmetric stages are configured to provide the output signal comprising an increased number of the first plurality of phases of the input signal based at least on the number of the symmetric stages, and Wherein the calibration engine is configured to provide current to the series of symmetrical stages based at least on the frequency calibrated by the calibration engine.

12. The system of claim 11, wherein each of the symmetry stages comprises: A pair of first inverters are coupled in series to the pair of cross-coupled inverters or in parallel to the pair of feed-forward resistors.

13. The system according to claim 12, wherein each stage in the series of symmetrical stages comprises the pair of first inverters coupled in series to the pair of cross-coupled inverters, and Each stage in the series of symmetrical stages further comprises a switch coupled in parallel to the cross-coupled inverters, the switch being used to control the injection strength of the output voltage.

14. The system of claim 13, wherein the switch reduces a capacitive load of a preceding stage in the series of symmetrical stages on a succeeding stage in the symmetrical stages.

15. The system of claim 12, wherein each stage in the series of symmetrical stages further comprises: A capacitor is coupled in parallel to the cross-coupled inverters, the capacitor being used to tune the frequency of each stage in the series of symmetrical stages.

16. The system of claim 15, wherein the capacitor reduces jitter of each stage in the series of symmetrical stages.

17. The system of claim 11, wherein the calibration engine further comprises: Frequency calibrator; and a current source, which is coupled to the frequency calibrator, wherein the frequency calibrator sends instructions to the circuitry of the current source, the instructions being based at least on the calibration frequency, and The current source transmits the current to the circuit system, the current being based at least on the calibration frequency.

18. The system of claim 11, wherein the circuit system further comprises: A series of loops, each loop comprising a series of inverters coupled in parallel to an amplifier, each loop for controlling a duty cycle of a phase of the first plurality of phases of the input signal.

19. A method comprising: increasing the number of phases in an output signal comprising a first plurality of phases, the output signal being based at least on a number of symmetric stages in a series of symmetric stages and a number of a second plurality of phases in an input signal, wherein the series of symmetric stages couples an initial stage in the series to the input signal comprising the second plurality of phases and an output stage in the series couples the output signal to a calibration engine; calibrating, by the calibration engine, a frequency of the circuit system within a range based at least on a target frequency; and A current is output coupled to the series by the calibration engine, the output current being based on at least a calibration frequency.

20. The method of claim 19, further comprising: sending, by a frequency calibrator of the calibration engine, instructions to circuitry of a current source, the instructions being based at least on the calibration frequency, and The current is transmitted to the circuit system by the current source of the frequency calibrator, the current being based at least on the calibration frequency.

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