System and method for performing adaptive voltage scaling (AVS) of analog-to-digital converter (ADC)

Abstract

The disclosure relates to systems and methods for performing adaptive voltage scaling, AVS, of analog-to-digital converters, ADCs. A system may include one or more receivers, circuitry, and a controller. Each of the one or more receivers may include a plurality of ADCs. Each ADC may measure a time related to analog-to-digital conversion by the ADC, compare the time to a threshold, and generate a first signal based on a result of the comparison. The circuitry may be coupled to the one or more receivers. The circuitry may receive the first signal from each ADC, determine a performance characteristic of each receiver based at least on the first signal, and output a plurality of second signals. Each of the plurality of second signals may indicate the performance characteristic of a corresponding receiver. The controller may be coupled to the circuitry and adjust a voltage provided to the one or more receivers based at least on the plurality of second signals received from the circuitry.

Description

Technical Field

[0001] The present disclosure relates generally to systems and methods for improving power efficiency of analog-to-digital converters (ADCs), and more particularly to performing adaptive voltage scaling (AVS) of the ADC in an integrated circuit. Background Art

[0002] High-speed and / or high-resolution ADCs are used in a variety of applications in modern data communication systems, processing systems, instrumentation / control systems, including but not limited to network switches, serializer / deserializer (SerDes) physical layers (PHYs), optical receivers, wireless base station receivers, data acquisition systems, sensors, etc. For example, next-generation network switches may be implemented based on time-interleaved successive approximation register (SAR) ADCs. However, high-speed and / or high-resolution ADCs in integrated circuits (e.g., time-interleaved SAR ADCs used in high-speed data receivers in switch chips) sometimes consume a significant portion of the total power of the integrated circuit. Summary of the invention

[0003] On the one hand, the present disclosure provides a system comprising: one or more receivers, each of which includes a plurality of analog-to-digital converters (ADCs), each ADC being configured to: measure a time associated with an analog-to-digital conversion performed by the ADC; compare the time with a threshold; and generate a first signal based on a result of the comparison; a circuit system coupled to the one or more receivers and configured to: receive the first signal from each ADC; determine a performance characteristic of each receiver based at least on the first signal; and output a plurality of second signals each indicating the performance characteristic of the corresponding receiver; and a controller coupled to the circuit system and configured to: adjust a voltage provided to the one or more receivers based at least on the plurality of second signals received from the circuit system.

[0004] On the other hand, the present disclosure provides a method, comprising: receiving, by a controller that provides voltage to a plurality of analog-to-digital converters (ADCs), a plurality of signals each indicating a performance characteristic of a corresponding ADC among the plurality of ADCs; determining, by the controller at least based on the plurality of signals, a metric indicating performance of the plurality of ADCs; comparing, by the controller, the metric with a threshold; and reducing, by the controller, the voltage by a certain factor in response to determining that the metric is greater than the threshold.

[0005] On the other hand, the present disclosure provides a circuit system comprising: a first circuit coupled to a plurality of analog-to-digital converters (ADCs) and configured to: measure a time associated with an analog-to-digital conversion performed by each of the plurality of ADCs; compare the measured time with a threshold; and generate a plurality of first signals corresponding to the plurality of ADCs based at least on a result of the comparison; determine performance characteristics of the plurality of ADCs based at least on the plurality of first signals; and output a second signal indicating the performance characteristics of the plurality of ADCs; and a second circuit coupled to the first circuit and configured to: adjust a voltage provided to the plurality of ADCs based at least on the second signal received from the first circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various objects, aspects, features and advantages of the present disclosure will become more apparent and better understood by reference to the detailed description in conjunction with the accompanying drawings, wherein the same reference symbols identify corresponding elements throughout. In the drawings, the same reference numerals generally indicate the same, functionally similar and / or structurally similar elements.

[0007] Figure 1A to Figure 1C is a schematic block diagram of an adaptive voltage scaling (AVS) system of an analog-to-digital converter (ADC) according to an embodiment.

[0008] Figure 2A is a diagram of an example conversion monitor for measuring the speed of an ADC, according to an embodiment.

[0009] Figure 2B is a timing diagram for measuring the speed of an ADC according to an embodiment.

[0010] Figure 3 is a diagram of an example ring oscillator frequency monitor for measuring a standard cell delay of a ring oscillator in accordance with an embodiment.

[0011] Figure 4 is a flow chart showing an example process of performing AVS operations of an ADC according to an embodiment.

[0012] Figure 5 is a flow chart showing another example process of performing AVS operation of an ADC according to an embodiment.

[0013] The details of various embodiments of the method and system are set forth in the accompanying drawings and the description below. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include embodiments in which first and second features in direct contact are formed, and may also include embodiments in which additional features may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, in various examples, the present disclosure may repeat reference symbols and / or letters. This repetition is for simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Various embodiments disclosed herein relate to a system including one or more receivers, a circuit system, and a controller. In some embodiments, the circuit system may include: (1) hardware, one or more processors (e.g., microprocessors), or a combination of hardware and / or one or more processors with software and / or firmware; or (2) a single component or a combination of multiple components. In some embodiments, the controller may be any circuit, hardware, processor (e.g., microprocessor), or a combination of hardware and / or one or more processors with software and / or firmware. Each of the one or more receivers may include multiple analog-to-digital converters (ADCs). Each ADC may measure a time associated with an analog-to-digital conversion performed by the ADC, compare the time with a threshold, and generate a first signal based on the result of the comparison. The circuit system may be coupled to the one or more receivers. The circuit system may receive a first signal from each ADC, determine a performance characteristic of each receiver based at least on the first signal, and output multiple second signals. Each of the multiple second signals may indicate a performance characteristic of the corresponding receiver. The controller may be coupled to the circuit system and adjust a voltage provided to the one or more receivers based at least on the multiple second signals received from the circuit system.

[0016] In some embodiments, each receiver may be a serializer / deserializer (SerDes) receiver. In some embodiments, the SerDes receiver may include one or more SerDes or one or more SerDes channels that convert parallel data into serial data and vice versa for high-speed data communication (e.g., high-speed chip-to-chip communication). In some embodiments, the multiple ADCs in each receiver include time-interleaved successive approximation register (SAR) ADCs. The threshold may be a clock interval between two SAR ADCs. In some embodiments, the performance characteristics of each receiver include at least one of the conversion timing, signal-to-noise ratio (SNR), or bit error rate (BER; for example, the number of received bits divided by the total number of transmitted bits in the same time period) of the ADC in the receiver. In some embodiments, the conversion timing of the ADC may be the amount of time or time margin spent between the conversion completion time of a sample of the analog signal and the next sample of the analog signal. In some embodiments, the conversion timing of the ADC may be the amount of time it takes for the ADC to perform an analog / digital conversion (e.g., the average amount of time across all ADCs or the amount of time it takes for each ADC to perform an analog / digital conversion).

[0017] In some embodiments, the voltage may be provided to one or more circuits. The system may further include a second circuit system coupled to the one or more circuits. The second circuit system may be configured to measure at least one of a standard cell delay, a leakage current, or a resistance and capacitance of a metal pattern from the one or more circuits. In some embodiments, the standard cell delay of a circuit or one or more elements thereof may be a delay measured by a circuit system (e.g., a ring oscillator), and the circuit system is implemented with one or more standard cells selected or chosen to match the delay of the circuit or one or more elements of the circuit. In some embodiments, the leakage current of a circuit or one or more elements thereof may be any current flowing from the circuit or one or more elements thereof when the ideal current is 0. In some embodiments, the resistance and capacitance of a metal pattern of a circuit may be the resistance and / or capacitance of one or more metal patterns (e.g., metal, wiring, via, etc.) within the circuit. The second circuit system may be configured to output one or more third signals corresponding to the one or more circuits based on the results of the measurement. The controller may be further configured to adjust the voltage provided to the one or more receivers based at least on a plurality of second signals and one or more third signals.

[0018] Various embodiments disclosed herein are directed to a method. The method includes receiving, by a controller that provides a voltage to a plurality of analog-to-digital converters (ADCs), a plurality of signals each indicating a performance characteristic of a corresponding ADC in the plurality of ADCs. The method may include determining, by the controller, a metric indicating performance of the plurality of ADCs based at least on the plurality of signals. The method may include comparing, by the controller, the metric to a threshold. The method may include reducing, by the controller, a voltage by a certain factor in response to determining that the metric is greater than the threshold.

[0019] In some embodiments, in response to determining that the metric is less than or equal to the threshold, the controller may increase the voltage by an offset. In some embodiments, before receiving the plurality of signals, the controller may set the voltage to a first voltage, and the voltage regulator may provide the first voltage to the plurality of ADCs. After reducing the voltage by the multiple, the voltage regulator may provide the reduced voltage to the plurality of ADCs.

[0020] In some embodiments, a time associated with an analog-to-digital conversion performed by each of the plurality of ADCs may be measured. The measured time may be compared to a second threshold. A plurality of signals may be generated based at least on a result of the comparison.

[0021] In some embodiments, a voltage regulator may provide a voltage to one or more circuits. At least one of a standard cell delay, a leakage current, or a resistance and a capacitance of a metal pattern may be measured by the one or more circuits. One or more signals corresponding to the one or more circuits may be generated based on the results of the measurements. The metric may be determined based on multiple signals and the one or more signals.

[0022] In some embodiments, after reducing the voltage by the factor, a second metric indicative of the performance of the plurality of ADCs may be adjusted based on the reduced voltage. The second metric may be different from the metric. In some embodiments, after reducing the voltage by the factor, a second plurality of signals each indicative of a performance characteristic of a corresponding ADC in the plurality of ADCs may be received.

[0023] Various embodiments disclosed herein relate to a circuit system including a first circuit and a second circuit. The first circuit may be coupled to a plurality of analog-to-digital converters (ADCs). The first circuit may be configured to measure a time associated with an analog-to-digital conversion performed by each of the plurality of ADCs. The first circuit may be configured to compare the measured time with a threshold. The first circuit may be configured to generate a plurality of first signals corresponding to the plurality of ADCs based at least on a result of the comparison. The first circuit may be configured to determine performance characteristics of the plurality of ADCs based at least on the plurality of first signals. The first circuit may be configured to output a second signal indicating the performance characteristics of the plurality of ADCs. The second circuit may be coupled to the first circuit. The second circuit may be configured to adjust a voltage provided to the plurality of ADCs based at least on a second signal received from the first circuit.

[0024] In some embodiments, the plurality of ADCs may include time-interleaved successive approximation register (SAR) ADCs. The threshold may be a clock interval between two SAR ADCs.

[0025] In some embodiments, multiple ADCs may form a receiver.The performance characteristics may include at least one of conversion timing of multiple ADCs in the receiver, a signal-to-noise ratio (SNR) of the receiver, or a bit error rate (BER) of the receiver.

[0026] In some embodiments, the voltage may be provided to one or more circuits. The circuit system may further include a third circuit coupled to the one or more circuits. The third circuit may be configured to measure at least one of a standard cell delay, a leakage current, or a resistance and a capacitance of a metal pattern by the one or more circuits. The third circuit may be configured to output one or more third signals corresponding to the one or more circuits based on the results of the measurement. The second circuit may be further configured to adjust the voltage provided to the plurality of ADCs based at least on the second signal and the one or more third signals.

[0027] On the one hand, high-speed and / or high-resolution ADCs in integrated circuits (e.g., time-interleaved SAR ADCs used in complementary metal oxide semiconductor (CMOS) digital circuits or switch chips) consume a significant portion of the total power of the integrated circuit. Adaptive voltage scaling (AVS) technology has been applied in the latest network switch chips to optimize the power and thermal performance of complementary metal oxide semiconductor (CMOS) digital circuits. AVS is a closed-loop dynamic power minimization technology that adjusts the voltage supplied to a computer chip to match the voltage required by the chip during operation. AVS can be used to minimize the power dissipation of CMOS-based digital circuits and DVDD. 2 AVS is a key technology for achieving power reduction of CMOS digital circuits due to the fact that the power consumption of the switch chip is proportional to the power consumption of the CMOS digital circuit, where DVDD (digital drain supply voltage) refers to the digital power supply voltage. In addition to the CMOS digital circuits, the switch chip may also integrate a large number of SerDes cores that consume a large portion of the total power of the switch chip. Therefore, the AVS technology may be suitable for the SerDes core to further improve the power efficiency. However, compared with the AVS for the trade-off between speed and power used for CMOS digital circuits, the AVS of the SerDes core may be more complex because the SerDes core may include various analog signal blocks and / or mixed signal blocks, whose design goals and complexity are different from those of digital circuits. Therefore, it is necessary to design or implement a comprehensive timing and / or performance evaluation scheme specific to the system (such as a SerDes system) for the AVS system.

[0028] In addition, the SAR ADC may be a major building block in the SerDes core. The SAR ADC in the SerDes core consumes 1 / 3 of the total power of the SerDes core. The SAR ADC in the SerDes core may be a suitable block for applying AVS technology because the SAR ADC is similar to a digital circuit in terms of delay sensitivity and / or power sensitivity to supply voltage and process variations. A digital circuit may use a process monitor (PM), which may contain multiple ring oscillators based on standard cells to monitor circuit delays under process variations. Unlike digital circuits, the SAR ADC may contain both analog components (such as comparators and capacitive digital / analog converters (CDACs)) and digital components (such as SAR logic circuits), both of which determine the conversion delay of the SAR ADC. Specifically, the delay of the analog components may be a function not only of the process and power supply, but also of many other design parameters, including bias conditions, signal amplitude, common-mode voltage, etc. Therefore, a PM based on standard cells cannot characterize or measure the performance of the SAR ADC.

[0029] Furthermore, as a mixed signal circuit, a SAR ADC may have many design specifications (or goals) in addition to speed and power, including noise, distortion, leakage, etc. Power supply adaptation (e.g., VDD adaptation, AVS) may affect not only speed and power, but also other metrics (e.g., performance metrics), which may directly affect system performance, including signal-to-noise ratio (SNR) or bit error rate (BER), etc. An AVS scheme is needed that can be performed without significantly affecting system performance.

[0030] To address these issues, according to certain aspects, embodiments of the present disclosure relate to a technique for providing an AVS system for a high-speed and / or high-resolution ADC (e.g., a SAR ADC) in an integrated circuit (e.g., a network switch chip). In some embodiments, the AVS system can closely monitor system performance (e.g., timing, BER, SNR, etc.) so as to perform AVS without significantly affecting system performance. In some embodiments, after adapting the supply power or voltage, the relevant analog design parameters can be tuned, adjusted, or adjusted again to meet the design goals (e.g., speed and power, including noise, distortion, and leakage, etc.).

[0031] In some embodiments, an AVS system may include: (1) multiple receivers (or receiver (RX) channels), each of which includes multiple ADCs; (2) multiple timing and performance (TP) monitors corresponding to multiple RX channels; (3) multiple process monitors (PMs); (4) an AVS controller; and / or (5) a voltage regulator (VR; or a voltage regulator circuit or a voltage regulator module (VRM)). Each of the TP monitors may include a conversion monitoring (CM) processor (or a CM processing circuit), a BER detector (or a BER detection circuit), and / or an SNR calculator (or an SNR calculation circuit). The AVS controller may include a regulator controller and / or an analog performance tuner (or an analog performance tuning circuit). In some embodiments, at least multiple RX channels and multiple process monitors may be included in an integrated circuit (e.g., a network switch chip).

[0032] In some embodiments, the multiple RX channels may be any circuit or hardware configured to receive multiple analog signals, respectively. In some embodiments, the multiple RX channels may be SerDes channels that share the same supply voltage, such as an analog supply voltage (AVDD). Each RX channel (or SerDes channel) may contain a time-interleaved SAR ADC including multiple SAR ADCs. Voltage regulation may be controlled by an AVS controller to generate an AVDD voltage and deliver the voltage to each RX channel (or SerDes channel) through a distributed power grid.

[0033] In some embodiments, the AVS system can provide two categories of performance detection solutions from various monitors or monitor circuits (e.g., on-chip monitors). The first solution can be to use embedded monitors (e.g., conversion timing monitors) in each RX channel. The second solution can be to use dedicated process monitors placed at several points of the integrated circuit (e.g., switch chip) that provide process information (e.g., process variation information) under AVDD.

[0034] Multiple ADCs in each RX channel can measure or monitor the conversion timing of multiple ADCs, generate the measurement or monitoring results as a combined ADC conversion monitoring (CM) signal corresponding to the RX channel, and provide the combined ADC CM signal to the corresponding TP monitor (e.g., a CM processor of the corresponding TP monitor). In some embodiments, the combined ADC CM signal can be a digital signal with multiple bits. Each RX channel can combine the output signals of its multiple ADCs into a combined ADC output signal and provide the combined ADC output signal to the corresponding TP monitor.

[0035] In some embodiments, the multiple ADCs in each RX channel may be time-interleaved SAR ADCs. For example, each of the multiple ADCs in each RX channel may be a time-interleaved SAR ADC. Each of the multiple ADCs may include a conversion (timing) monitor (or conversion monitoring circuit) configured to monitor the conversion timing (e.g., conversion timing margin) of the ADC and generate a conversion monitoring (CM) signal of the ADC. In some embodiments, the CM signal of the ADC may be a 1-bit digital signal. The multiple CM signals in each RX channel may be combined into a combined CM signal corresponding to the RX channel and provided to a CM processor of a corresponding TP monitor. In some embodiments, the combined CM signal may include multiple CM bits received from multiple ADCs. Each of the multiple ADCs may be configured to generate an ADC output signal of the ADC. The multiple ADC output signals in each RX channel may be combined into a combined ADC output signal corresponding to the RX channel and provided to a corresponding TP monitor. In some embodiments, the combined ADC output signal may include multiple ADC output signals in each RX channel.

[0036] In some embodiments, the plurality of TP monitors may be any circuit or hardware or one or more microprocessors configured to measure or monitor the timing and performance of the corresponding RX channel. The CM processor of each TP monitor may generate one or more timing bits (corresponding to the RX channel) based on the combined conversion monitoring (CM) signal. In some embodiments, the one or more timing bits may include a plurality of CM bits contained in the combined CM signal. In some embodiments, the one or more timing bits may indicate the number of 1s in the plurality of CM bits contained in the combined CM signal. In some embodiments, the one or more timing bits may be set so that the greater the value indicated by the timing bit, the more power the corresponding RX channel has consumed and / or the more noise the corresponding RX channel has generated.

[0037] In some embodiments, a BER detector for each TP monitor may generate one or more BER bits (corresponding to the RX channel) based on the combined ADC output signal. In some embodiments, the BER detector may calculate the BER (corresponding to the RX channel) using the combined ADC output signal and an input signal of a pseudo-random bit sequence (PRBS) and set one or more BER bits based on the calculated BER. In some embodiments, the one or more BER bits may indicate the calculated BER (corresponding to the RX channel). In some embodiments, the one or more BER bits may be set such that the larger the value indicated by the BER bit, the more noise has been generated by the corresponding RX channel.

[0038] In some embodiments, the SNR calculator of each TP monitor may generate one or more SNR bits (corresponding to the RX channel) based on the combined ADC output signal. In some embodiments, the SNR detector may calculate the SNR (corresponding to the RX channel) after performing equalization of the combined ADC output signal and set one or more SNR bits based on the calculated SNR. In some embodiments, the one or more SNR bits may indicate the calculated SNR (corresponding to the RX channel). In some embodiments, the one or more SNR bits may be set so that the larger the value indicated by the SNR bit, the more noise has been generated by the corresponding RX channel. Each TP monitor may combine one or more timing bits, one or more BER bits, and / or one or more SNR bits to provide a set of TP bits (corresponding to the RX channel) to the AVS controller.

[0039] In some embodiments, the plurality of process monitors may be any circuit or hardware or one or more microprocessors configured to measure or monitor process changes of one or more circuits. For example, each process monitor may measure or monitor at least one of a delay (e.g., a delay measured by an oscillation frequency of a standard cell-based ring oscillator), a leakage current, a resistance, or a capacitance of one or more circuits under the same power domain (e.g., under the same AVDD power domain). Each process monitor may combine the results of the measurements or monitoring to provide a set of PM bits to the AVS controller.

[0040] In some embodiments, each process monitor may include a frequency monitor (or frequency monitoring circuit), a leakage monitor (or leakage monitoring circuit), and / or a metal resistance and capacitance (RC) monitor (or metal RC monitoring circuit). In some embodiments, a frequency monitor may measure various types of standard cell delays. In some embodiments, a leakage monitor may measure the leakage current of one or more transistors (e.g., NMOS, PMOS). In some embodiments, a metal RC monitor may monitor or measure the resistance and / or capacitance of a design metal pattern (e.g., metal, wiring, via, etc.).

[0041] In some embodiments, each process monitor may generate a combined process monitoring (PM) signal based on the output of the frequency monitor, the leakage monitor, and / or the metal RC monitor and provide the combined PM signal to the AVS controller. In some embodiments, the combined PM signal may be a digital signal having a plurality of bits. The combined PM signal may include one or more frequency monitoring (FM) bits, one or more leakage monitoring (LM) bits, and / or one or more metal resistance and capacitance monitoring (MRC) bits.

[0042] In some embodiments, one or more FM bits (in the PM bit group) may indicate a delay of one or more circuits. In some embodiments, one or more FM bits may be set so that the larger the value indicated by the FM bit, the more power one or more circuits have consumed and / or the more noise one or more circuits have generated. In some embodiments, one or more LM bits (in the PM bit group) may indicate an amount of leakage current of one or more circuits. In some embodiments, one or more LM bits may be set so that the larger the value indicated by the LM bit, the more power one or more circuits have consumed and / or the more noise one or more circuits have generated. In some embodiments, one or more MRC bits (in the PM bit group) may indicate a resistance / capacitance (RC) value of one or more metal patterns. In some embodiments, one or more MRC bits may be set so that the larger the value indicated by the MRC bit, the more power one or more circuits have consumed and / or the more noise one or more circuits have generated.

[0043] In some embodiments, the AVS controller may be any circuit or hardware or one or more microprocessors configured to control and / or perform AVS operations. The regulator controller of the AVS controller may generate one or more voltage regulator (VR) control bits based on multiple sets of TP bits and / or multiple sets of PM bits and provide the generated one or more VR control bits to the voltage regulator. In some embodiments, the voltage regulator may control the supply voltage (e.g., AVDD) based on one or more VR control bits. The analog performance tuner of the AVS controller may generate one or more analog control bits based on multiple sets of TP bits and / or multiple sets of PM bits and provide the generated one or more analog control bits to multiple RX channels (and the ADCs therein). In some embodiments, the ADCs in multiple RX channels may tune or adjust analog design parameters based on one or more analog control bits. The analog design parameters may include, but are not limited to, comparator bias current, input common mode voltage, programmable delay, etc.

[0044] In some embodiments, the voltage regulator may be any circuit or hardware configured to generate and / or regulate a supply voltage, such as AVDD (analog drain supply voltage), such that the supply voltage is maintained constant and the regulated supply voltage is provided to a plurality of circuits including a plurality of process monitors and a plurality of RX channels. The voltage regulator may generate AVDD based on a VR control bit and provide the generated AVDD to a plurality of circuits.

[0045] In some embodiments, the conversion (timing) monitor of each ADC in the plurality of ADCs (e.g., each SAR ADC) may include a DAC, a SAR logic circuit, a comparator (or a comparator circuit), a plurality of shift registers connected in series, conversion completion logic (or a conversion completion logic circuit), a multiplexer, and an output register configured to output a signal representing a CM bit. The DAC may be a capacitive DAC (CDAC) or any DAC that can convert a digital signal into an analog signal in response to a data input signal. The comparator may be a differential amplifier, such as an operational amplifier. The comparator may receive an analog signal output from the DAC and an input analog signal, compare the two signals, and output a signal indicating a comparison result. The SAR logic circuit may be configured to receive a sampling clock, sequentially determine the value of each digital bit of a digital signal (e.g., a 6-bit digital signal) based on the output signal of the comparator, and provide a clock (e.g., an asynchronous clock) to the comparator. The plurality of shift registers may count the number of conversion steps. The conversion completion logic may receive a sampling clock and an output from the last shift register and output a conversion completion signal indicating whether the conversion of the input analog signal is completed.

[0046] In some embodiments, the SAR logic circuit may be an asynchronous SAR logic circuit that does not use an internal clock while still using a sample clock for uniform sampling of the analog signal. Using asynchronous SAR logic, the execution time of each of the conversion steps of the conversion may not be fixed and / or uniform. Instead, after each of the conversion steps is completed, the next step in the conversion can begin without a large delay in between.

[0047] In some embodiments, the multiplexer may receive multiple sampling clocks of other ADC units and output a threshold signal indicating a threshold interval according to a selection signal. In some embodiments, the threshold interval may be defined as a clock interval between two unit ADCs. The threshold interval may be programmed by selecting from different clock phases. If the selection signal indicates two sampling clocks among the multiple sampling clocks, the multiplexer may output a threshold signal indicating a threshold interval as a clock interval between the two sampling clocks. The output register may receive a conversion completion signal from the conversion completion logic and a threshold signal from the multiplexer and output a signal representing a CM bit. The time margin between the conversion completion time of a sample of an analog signal and the acquisition (e.g., tracking and holding) time of the next sample of the analog signal may be referred to as a "conversion time margin," "conversion timing margin," or "conversion margin." The conversion margin may be a performance measure of a SAR ADC (e.g., an asynchronous SAR ADC) in terms of speed. For example, the SAR conversion margin may be a good indicator of the SAR ADC conversion speed compared to a design specification (or target). In general, the presence or long period of conversion margin indicates that the asynchronous SAR ADC is overperforming in terms of conversion speed and is therefore consuming more power and / or generating more noise than necessary. In some embodiments, the conversion margin may be determined based on the conversion completion signal and the next sampling clock. In some embodiments, the output register may set the CM bit to "1" when the conversion margin is greater than a threshold interval (thus consuming more power and / or generating more noise) and set the CM bit to "0" when the conversion margin is less than or equal to the threshold interval.

[0048] For example, in a timing diagram showing a sampling clock and a conversion completion signal, after sampling an analog signal in a sampling phase, a process of a conversion step may be performed asynchronously (in an asynchronous conversion phase). In response to the completion of the conversion process, a conversion completion signal may be “turned on” (e.g., switched to a high level), which defines a conversion margin (or conversion time margin) between the time when the conversion completion signal becomes “on” and the start of the next sampling phase. If the conversion margin is less than a threshold interval, the multiplexer may output a threshold signal before the conversion completion signal turns on, and the output register may set the CM bit to “0”. On the other hand, if the conversion margin is greater than the threshold interval, the multiplexer may output a threshold signal after the conversion completion signal turns on, and the output register may set the CM bit to “1”. In order to optimally characterize the ADC speed of an integrated circuit (e.g., the speed of a SAR ADC in an entire switch chip), the CM bit may be collected by obtaining multiple samples from each unit ADC (e.g., a unit SAR ADC) across all RX channels. In this way, the AVS system may capture (1) data-dependent delay variations and / or (2) delay variations induced by local or global process variability.

[0049] In some embodiments, the frequency monitor (or frequency monitoring circuit) may include a NAND gate-based ring oscillator, a frequency divider (or frequency divider circuit), and / or a counter (or counter circuit). The ring oscillator may include a plurality of NAND gates (e.g., an odd number of NAND gates). The frequency monitor may measure the delay of one or more selected standard cells under an analog power supply (e.g., AVDD). In some embodiments, the ring oscillator may be implemented with one or more standard cells selected or chosen to match the delay of a critical path in an ADC (e.g., a critical path including digital elements within a SAR ADC). The frequency divider may divide the clock output from the ring oscillator to relax the timing requirements on the counter. The counter may receive the divided clock output from the frequency divider, calculate (or count) the oscillation frequency based on the divided clock according to a reference clock, and store the oscillation frequency value in a register. For example, the frequency divider may divide the ring oscillator output clock into a low frequency clock. The counter may be driven by a reference clock and sample the incoming divided clock. The frequency of the reference clock is higher than the frequency of the divided clock. The lower frequency of the divided clock helps to reduce the frequency of the reference clock so that the timing requirements on the sequential logic paths are relaxed at the lower frequency clock.

[0050] In one method, the AVS system may perform an AVS operation process on multiple channels of an ADC in an integrated circuit (e.g., multiple SerDes channels of a SAR ADC in a switch chip). In some embodiments, the AVS system may run an AVS operation (e.g., calibration) process in the foreground and / or background. For example, a foreground calibration is a one-time calibration with a specific input training sequence. In background calibration, it is difficult to process normal data flow. Background calibration is a continuous calibration that runs with normal data flow. In some embodiments, monitors (e.g., TP monitors, process monitors, conversion monitors, frequency monitors, leakage monitors, metal RC monitors, etc.) may run in both background mode and foreground mode.

[0051] In some embodiments, at a first step, the AVS system (e.g., AVS controller, voltage regulator) may start AVS operation. At a second step, the voltage regulator may set or initialize the supply voltage (e.g., AVDD) to a default voltage without voltage scaling. In some embodiments, a regulator controller of the AVS controller may set one or more VR control bits to "0" or any default value and provide the VR control bits to the voltage regulator so that the voltage regulator may set AVDD to the default voltage.

[0052] At the third step, the AVS controller may collect process information (e.g., multiple sets of PM bits). In some embodiments, the AVS controller may read, obtain, collect, or receive a set of PM bits from each process monitor. At the fourth step, the AVS controller may collect timing and performance (TP) information (e.g., multiple sets of TP bits). In some embodiments, the AVS controller may read, obtain, collect, or receive a set of TP bits from each TP monitor or each RX channel.

[0053] At a fifth step, the AVS controller may calculate a performance metric P (e.g., a SAR ADC performance metric) based on process information (e.g., multiple sets of PM bits) and / or TP information (e.g., multiple sets of TP bits). In some embodiments, the performance metric may be calculated based on one or more values ​​indicated in the multiple sets of PM bits and / or one or more values ​​indicated in the multiple sets of TP bits. In some embodiments, the performance metric may be calculated based on: (1) a value indicated by a timing bit of the multiple sets of TP bits; (2) a value indicated by a BER bit of the multiple sets of TP bits; (3) a value indicated by an SNR bit of the multiple sets of TP bits; (4) a value indicated by an FM bit of the multiple sets of PM bits; (5) a value indicated by an LM bit of the multiple sets of PM bits; and / or (6) a value indicated by an MRC bit of the multiple sets of PM bits. In some embodiments, the performance metric may be calculated based on a sum (e.g., a weighted sum) of: (1) a value indicated by a timing bit of the plurality of sets of TP bits; (2) a value indicated by a BER bit of the plurality of sets of TP bits; (3) a value indicated by an SNR bit of the plurality of sets of TP bits; (4) a value indicated by an FM bit of the plurality of sets of PM bits; (5) a value indicated by an LM bit of the plurality of sets of PM bits; and / or (6) a value indicated by an MRC bit of the plurality of sets of PM bits. The performance metric may be calculated such that the larger the calculated performance metric, the more power the plurality of RX channels or integrated circuits have consumed and / or the more noise the plurality of RX channels or integrated circuits have generated.

[0054] At the sixth step, the AVS controller may compare the calculated performance metric P with the target performance metric P target In some embodiments, the target performance metric P target It may be determined experimentally (or by simulation) to indicate that the power and / or noise consumed and / or generated by the plurality of RX channels or integrated circuits meets a predetermined design specification (or target).

[0055] At the seventh step, in response to determining that the calculated performance metric P is greater than the target performance metric P target , the AVS controller can reduce or scale down AVDD by reducing the value of one or more VR control bits and providing the reduced value to the voltage regulator. In some embodiments, the AVS controller can reduce or decrease the value of one or more VR control bits by a predetermined step value (e.g., 1).

[0056] At the eighth step, the AVS controller (e.g., an analog performance tuner) may determine, tune, or adjust one or more analog control bits based on the one or more VR control bits (or AVDD corresponding to the VR control bits) calculated at the seventh step. In some embodiments, the AVS controller may apply pre-trained or predetermined analog control bits to the ADCs in multiple RX channels based on the one or more VR control bits calculated at the seventh step. For example, the AVS controller may refer to a lookup table (LUT) stored in a memory and look up the value of the analog control bit corresponding to the value of the one or more VR control bits (or AVDD corresponding to the VR control bits) in the LUT. Then, iteration may continue by returning to the third step.

[0057] At a ninth step, in response to determining that the computed performance metric P is less than or equal to the target performance metric P target (or calculate the performance metric P to reach the target performance metric P target ), the AVS controller may increase or scale up AVDD by increasing the value of one or more VR control bits and providing the increased value to the voltage regulator. In some embodiments, the AVS controller may increase (or back off) the value of one or more VR control bits by a predetermined value (or offset) to reserve margin for temperature drift and / or device aging.

[0058] The embodiments of the present disclosure have at least the following advantages and benefits. First, the embodiments of the present disclosure may provide useful techniques for providing timing and performance monitoring circuits embedded in multiple SerDes channels or multiple ADCs therein. Compared with traditional AVS schemes for digital circuits, embedded timing and performance monitors (or monitoring circuits) can provide accurate and comprehensive information about the performance of key blocks of an integrated circuit (e.g., SAR ADCs, SerDes systems in a switch chip) with minimal power and area overhead. Compared with traditional centralized process monitor architectures, per-channel timing and performance monitors can capture local and global process variations across the entire integrated circuit (e.g., the entire switch chip).

[0059] Secondly, embodiments in the present disclosure may provide useful techniques to significantly reduce the power consumed by an ADC (e.g., a SAR ADC) compared to an ADC-based system without AVS. For example, in a CMOS 3nm112G 7-bit SAR ADC system according to some embodiments, the total SAR ADC power may be reduced by up to 50%. For a SerDes core in a switch chip, the SARADC array may account for 1 / 3 of the total power. The total SerDes core power may be reduced by 15% to 20% using an AVS scheme based on an embedded timing and performance monitor according to some embodiments.

[0060] Third, embodiments in the present disclosure may provide useful techniques to achieve significant power reductions while maintaining high performance for a wide range of products involving time-interleaved ADCs, such as switch chips, optical links, SERDES PHY chips, etc. In other words, a wide range of products involving power-efficient and high-speed ADCs may be implemented using AVS techniques according to some embodiments.

[0061] Figure 1A to Figure 1C 1 is a schematic block diagram of an adaptive voltage scaling (AVS) system 1000 for an analog-to-digital converter (ADC) according to an embodiment. The AVS 1000 system may include: (1) a plurality of receivers (or receiver (RX) channels 100-0, 100-1, ..., 100-m; m is an integer greater than 0), each of which includes a plurality of ADCs (e.g., (n+1) ADCs); (2) a plurality of timing and performance (TP) monitors 120-0, 120-1, ..., 120-m, corresponding to the plurality of RX channels 100-0, 100-1, ..., 100-m; (3) a plurality of process monitors (PMs) 160-0, 160-1, ..., 160-k (k is an integer greater than 0); (4) an AVS controller 140; and / or (5) a voltage regulator 150 (VR; or voltage regulator circuit or voltage regulator module (VRM)). Each of the TP monitors (e.g., TP monitor 120-m) may include a conversion monitoring (CM) processor (or CM processing circuit) 122-m, a BER detector (or BER detection circuit) 124-m, and / or an SNR calculator (or SNR calculation circuit) 126-m. The AVS controller 140 may include a regulator controller 142 and / or an analog performance tuner (or analog performance tuning circuit) 144. At least a plurality of RX channels 100-0, ..., 100-m and a plurality of process monitors 160-0, ..., 160-k may be included in an integrated circuit 1001 (e.g., a network switch chip).

[0062] refer to Figure 1A , multiple RX channels 100-0, 100-1, ..., 100-m may be any circuit or hardware configured to receive multiple analog signals respectively. Multiple RX channels may be SerDes channels that share the same supply voltage (e.g., analog supply voltage (AVDD)). Each RX channel (or SerDes channel) may contain a time-interleaved SAR ADC including multiple SAR ADCs. Voltage regulation 150 may be controlled by AVS controller 140 to generate AVDD voltage 152 and deliver voltage 152 to each RX channel (or SerDes channel) 100-0, 100-1, ..., 100-m through a distributed power grid (not shown).

[0063] refer to Figure 1AThe AVS system 1000 can provide two types of performance detection solutions from various monitors or monitor circuits (such as on-chip monitors). The first solution can be to use an embedded monitor (such as an on-chip monitor) in each RX channel 100-0, 100-1, ..., 100-m. Figure 1B A second approach may be to use dedicated process monitors 160-0, 160-1, ..., 160-k placed at several points of the integrated circuit 1001 (eg, a switch chip) that provide process information (eg, process variation information) under AVDD 152.

[0064] refer to Figure 1A and Figure 1B , multiple ADCs in each RX channel (e.g., (n+1) ADCs 102-m-0, 102-m-1, ..., 102-mn in the RX channel 100-m) can measure or monitor the conversion timing of multiple ADCs, generate the measurement or monitoring results as a combined ADC conversion monitoring (CM) signal 121-m corresponding to the RX channel 100-m, and provide the combined ADC CM signal 121-m to the corresponding TP monitor (e.g., the CM processor 122-m of the corresponding TP monitor 120-m). The combined ADC CM signal 121-m can be a digital signal having multiple bits (e.g., (n+1) bits <0:n>). Each RX channel (e.g., the RX channel 100-m) can output the output signals of its multiple ADCs (e.g., ADC out <0> 105-m-0, …, ADC Out <n>105-mn) into a combined ADC output signal 125-m and provide the combined ADC output signal 125-m to the corresponding TP monitor 120-m.

[0065] refer to Figure 1B , the plurality of ADCs 102-m-0, 102-m-1, ..., 102-mn in each RX channel (e.g., RX channel 100-m) may be time-interleaved SAR ADCs. Each ADC in the plurality of ADCs 102-m-0, 102-m-1, ..., 102-mn may include a signal configured to monitor the conversion timing (e.g., conversion timing margin) of the ADC and generate a conversion monitoring (CM) signal (e.g., CM) of the ADC. <0> 104-m-0, CM <1> 104-m-1, ..., CM <n>The ADC CM signal may be a 1-bit digital signal (referred to as a "CM bit"). The multiple CM signals CM in each RX channel (e.g., RX channel 100-m) may be a 1-bit digital signal (referred to as a "CM bit"). <0> 104-m-0, CM <1> 104-m-1, ..., CM <n>The CM signals 104-mn may be combined into a combined CM signal 121-m corresponding to an RX channel (eg, RX channel 100-m) and provided to a CM processor 122-m of a corresponding TP monitor 120-m. The combined CM signal 121-m may include a plurality of CM bits CM received from a plurality of ADCs. <0> 104-m-0, CM <1> 104-m-1, ..., CM <n>Each ADC in the plurality of ADCs may be configured to generate an ADC output signal of the ADC. The plurality of ADC output signals ADC out in each RX channel (eg, RX channel 100 - m) may be configured to generate an ADC output signal of the ADC. <0> 105-m-0, …, ADC Out <n>105-mn may be combined into a combined ADC output signal 125-m corresponding to the RX channel 100-m and provided to the corresponding TP monitor 120-m. The combined ADC output signal 125-m may include multiple ADC output signals 105-m-0, ..., 105-mn in each RX channel (eg, RX channel 100-m).

[0066] refer to Figure 1A and Figure 1B , the plurality of TP monitors may be any circuit or hardware or one or more microprocessors configured to measure or monitor the timing and performance of the corresponding RX channels 100-0, ..., 100-m. The CM processor 122-m of each TP monitor (e.g., TP monitor 120-m) may generate one or more timing bits 132-m (corresponding to RX channel 100-m) based on the combined transition monitor (CM) signal 121-m. In some embodiments, the one or more timing bits 132-m may include a plurality of CM bits (e.g., CM bits) contained in the combined CM signal 121-m. <0> 104-m-0, CM <1> 104-m-1, ..., CM <n>104-mn). In some embodiments, the one or more timing bits 132-m may indicate the number of ones in the plurality of CM bits contained in the combined CM signal. In some embodiments, the one or more timing bits 132-m may be set such that the larger the value indicated by the timing bit 132-m, the more power the corresponding RX channel 100-m has consumed and / or the more noise the corresponding RX channel 100-m has generated.

[0067] refer to Figure 1B , the BER detector 124-m of each TP monitor (e.g., TP monitor 120-m) may generate one or more BER bits 134-m (corresponding to RX channel 100-m) based on the combined ADC output signal 125-m. The BER detector 124-m may calculate the BER (corresponding to RX channel 100-m) using the combined ADC output signal 125-m and the input signal of the pseudo-random bit sequence (PRBS) and set the one or more BER bits 134-m based on the calculated BER. In some embodiments, the one or more BER bits 134-m may indicate the calculated BER (corresponding to RX channel 100-m). In some embodiments, the one or more BER bits 134-m may be set so that the larger the value indicated by the BER bit 134-m, the more noise has been generated by the corresponding RX channel 100-m.

[0068] refer to Figure 1B , the SNR calculator 126-m of each TP monitor (e.g., TP monitor 120-m) may generate one or more SNR bits 136-m (corresponding to RX channel 100-m) based on the combined ADC output signal 125-m. The SNR detector 126-m may calculate the SNR (corresponding to RX channel 100-m) after performing equalization of the combined ADC output signal 100-m and set the one or more SNR bits 136-m based on the calculated SNR. In some embodiments, the one or more SNR bits 136-m may indicate the calculated SNR (corresponding to RX channel 100-m). In some embodiments, the one or more SNR bits 136-m may be set so that the larger the value indicated by the SNR bit 136-m, the more noise the corresponding RX channel 100-m has generated. Each TP monitor (eg, TP monitor 120 - m ) may combine one or more timing bits 132 - m , one or more BER bits 134 - m , and / or one or more SNR bits 136 - m to provide a set of TP bits 141 - m (corresponding to RX lane 100 - m ) to the AVS controller 140 .

[0069] refer to Figure 1A and Figure 1C , the plurality of process monitors 160-0, ..., 160-k may be any circuit or hardware or one or more microprocessors configured to measure or monitor process changes of one or more circuits. For example, each process monitor (e.g., process monitor 160-k) may measure or monitor at least one of a delay (e.g., a delay measured by an oscillation frequency of a ring oscillator based on a standard cell), a leakage current, a resistance, or a capacitance of one or more circuits under the same power domain (e.g., under the same AVDD power domain). Each process monitor (e.g., process monitor 160-k) may combine the results of the measurements or monitoring to provide a set of PM bits 145-k to the AVS controller 140.

[0070] refer to Figure 1C , each process monitor (e.g., process monitor 160-k) may include a frequency monitor 161-k (or frequency monitoring circuit), a leakage monitor 162-k (or leakage monitoring circuit), and / or a metal resistance and capacitance (RC) monitor 163-k (or metal RC monitoring circuit). The frequency monitor 161-k may measure various types of standard cell delays. The leakage monitor 162-k may measure the leakage current of one or more transistors (e.g., NMOS, PMOS). The metal RC monitor 163-k may monitor or measure the resistance and / or capacitance of a designed metal pattern (e.g., metal, wiring, via, etc.). Each process monitor (e.g., process monitor 160-k) may generate a combined process monitoring (PM) signal 145-k based on the output of the frequency monitor 161-k, the leakage monitor 162-k, and / or the metal RC monitor 163-k and provide the combined PM signal 145-k to the AVS controller 140. The combined PM signal may be a digital signal having a plurality of bits (e.g., (N+1) bits, where N is a non-negative integer). The combined PM signal 145-k may include one or more frequency monitoring (FM) bits 172-k, one or more leakage monitoring (LM) bits 174-k, and / or one or more metal resistance and capacitance monitoring (MRC) bits 176-k.

[0071] refer to Figure 1C , one or more FM bits 172-k (in the PM bit group 145-k) may indicate a delay of one or more circuits. In some embodiments, one or more FM bits 172-k may be set so that the larger the value indicated by the FM bit 172-k, the more power one or more circuits have consumed and / or the more noise one or more circuits have generated. In some embodiments, one or more LM bits 174-k (in the PM bit group 145-k) may indicate an amount of leakage current of one or more circuits. In some embodiments, one or more LM bits 174-k may be set so that the larger the value indicated by the LM bit 174-k, the more power one or more circuits have consumed and / or the more noise one or more circuits have generated. In some embodiments, one or more MRC bits 176-k (in the PM bit group 145-k) may indicate a resistance / capacitance (RC) value of one or more metal patterns. In some embodiments, one or more MRC bits 176 - k may be set such that the greater the value indicated by the MRC bits 176 - k, the more power one or more circuits have consumed and / or the more noise one or more circuits have generated.

[0072] Return to reference Figure 1A , the AVS controller 140 may be any circuit or hardware or one or more microprocessors configured to control and / or perform AVS operations. The regulator controller 142 of the AVS controller 140 may generate one or more voltage regulator (VR) control bits 151 based on multiple sets of TP bits 141-0, 141-1, ..., 141-m and / or multiple sets of PM bits 145-0, 145-1, ..., 145-k and provide the generated one or more VR control bits 151 to the voltage regulator 150. The voltage regulator 150 may control the supply voltage (e.g., AVDD 152) based on the one or more VR control bits 151. The analog performance tuner 144 of the AVS controller 140 may generate one or more analog control bits 147 based on the multiple sets of TP bits 141-0, 141-1, ..., 141-m and / or the multiple sets of PM bits 145-0, 145-1, ..., 145-k and provide the generated one or more analog control bits 147 to the multiple RX channels 100-0, 100-1, ..., 100-m (and the ADCs therein). The ADCs in the multiple RX channels 100-0, 100-1, ..., 100-m may tune or adjust analog design parameters based on the one or more analog control bits 147. The analog design parameters may include, but are not limited to, comparator bias current, input common mode voltage, programmable delay, etc.

[0073] refer to Figure 1A , the voltage regulator 150 may be any circuit or hardware configured to generate and / or regulate a supply voltage (e.g., AVDD 152) such that the supply voltage 152 is maintained constant and provides the regulated supply voltage 152 to a plurality of circuits including a plurality of process monitors 160-0, 160-1, ..., 160-k and a plurality of RX channels 100-0, 100-1, ..., 100-m. The voltage regulator 150 may generate AVDD 152 based on the VR control bit 151 and provide the generated AVDD 152 to a plurality of circuits.

[0074] Figure 2A 2 is a diagram of an example conversion monitor 2000 for measuring the speed of an ADC according to an embodiment. In some embodiments, each of the conversion monitors (e.g., conversion monitors 103-m-0, ..., 103-mn) in each RX channel (e.g., 100-m) may have a configuration similar to that of the conversion monitor 2000. The conversion (timing) monitor 2000 of the SAR ADC may include a DAC 220, a SAR logic circuit 210, a comparator 230 (or a comparator circuit), a plurality of shift registers 240-0, ..., 240-6 connected in series, a conversion completion logic 250 (or a conversion completion logic circuit), a multiplexer 260, and an output register 270 configured to output a signal 280 representing a CM bit. The DAC 220 may be a capacitive DAC (CDAC) or any DAC that can convert a digital signal (Dfb<6:1> 222) into an analog signal in response to a data input signal Din 221. The comparator 230 may be a differential amplifier, such as an operational amplifier. The comparator 230 may receive the analog signal output from the DAC and the input analog signal Vcm 231, compare the two signals, and output a signal 211 indicating the comparison result. The SAR logic circuit 210 may be configured to receive the nth unit SAR ADC (eg Figure 1B ADC in <n>102-mn) sampling clock (SARclk <n>201-n), sequentially determine the value of each digital bit of the digital signal (e.g., 6-bit digital signal 222) based on the output signal 221 of the comparator 230 and provide a clock 232 (e.g., an asynchronous clock) to the comparator 230. A plurality of shift registers 240-0, ..., 240-6 can count the number of conversion steps (e.g., 7 steps). The conversion completion logic 250 can receive the sampling clocks 201-n and the output from the last shift register 240-0 and output a conversion completion signal 272 indicating whether the conversion of the input analog signal 231 is completed.

[0075] refer to Figure 2A SAR logic circuit 210 may be an asynchronous SAR logic circuit that does not use an internal clock while still using a sample clock (e.g., sampling clocks 201-n) for uniform sampling of analog signal 231. Using asynchronous SAR logic, the execution time of each of the conversion steps of the conversion may not be fixed and / or uniform. Instead, after each of the conversion steps is completed, the next step in the conversion may begin without a significant delay in between.

[0076] refer to Figure 2A The multiplexer 260 can receive multiple sampling clocks (eg, SARclk ) of other ADC units (eg, the (n-1)th ADC unit, the (n-2)th ADC unit, and the (n-3)th ADC unit). <n-1>201-(n-1)、SARclk <n-2>201-(n-2)、SARclk <n-3>The multiplexer 260 may output a threshold signal 271 indicating a threshold interval as a clock interval between two (selected) unit ADCs, if the select signal indicates two sampling clocks (e.g., sampling clocks 201-(n-1) and 201-(n-2)) among a plurality of sampling clocks. The multiplexer 260 may output a threshold signal 271 indicating a threshold interval as a clock interval between the two sampling clocks 201-(n-1) and 201-(n-2). The output register 270 may receive a conversion completion signal 272 from the conversion completion logic 250 and a threshold signal 271 from the multiplexer 260 and output a signal 280 indicating a CM bit.

[0077] The time margin between the time when a conversion of a sample of an analog signal is completed and the time when the next sample of the analog signal is acquired (e.g., track and hold) may be referred to as a "conversion time margin" or "conversion margin". The conversion margin may be a performance measure of a SAR ADC (e.g., an asynchronous SAR ADC) in terms of speed. For example, the SAR conversion margin may be a good indicator of the SAR ADC conversion speed compared to a design specification (or target). In general, the presence or long period of the conversion margin indicates that the asynchronous SAR ADC is overperforming in terms of conversion speed and is therefore consuming more power and / or generating more noise than necessary.

[0078] Figure 2B FIG. 25 is a timing diagram 2500 for measuring the speed of an ADC according to an embodiment. Figure 2A and Figure 2B , the conversion margin 207 may be determined based on the conversion completion signal 272 and the next sampling clock 209. In some embodiments, the output register 270 may set the CM bit 280 to "1" when the conversion margin 207 is greater than a threshold interval (e.g., T_threshold_2 212) and set the CM bit 280 to "0" when the conversion margin is less than or equal to the threshold interval (e.g., T_threshold_1 211). For example, in the timing diagram 2500, after the analog signal is sampled in the sampling phase 203-1, the process of converting steps 205-1, 205-2, 205-3, ... may be performed asynchronously (in the asynchronous conversion phase 204-1). In response to the conversion process being completed, the conversion completion signal 272 may be "turned on" (e.g., switched to a high level) at time t2, which defines the conversion margin 272 (or conversion time margin) between the time t2 when the conversion completion signal becomes "on" and the start of the next sampling phase 203-1 at t4. If the conversion margin 207 is less than the threshold interval (e.g., threshold interval 211), the multiplexer 260 may output the threshold signal at time t1 before the conversion completion signal 272 is turned on, and the output register 270 may set the CM bit 280 to "0". On the other hand, if the conversion margin 207 is greater than the threshold interval (e.g., threshold interval 212), the multiplexer may output the threshold signal at t3 after the conversion completion signal is turned on, and the output register 270 may set the CM bit 280 to "1". In order to optimally characterize the ADC speed of the integrated circuit (e.g., the speed of the SAR ADC in the entire switch chip), the CM bit (calculated by the corresponding conversion monitor) may be collected by obtaining multiple samples from each unit ADC (e.g., unit SAR ADC) across all RX channels 100-0, ..., 100-m. In this way, the AVS system can capture (1) data-dependent delay variations and / or (2) delay variations induced by local or global process variability.

[0079] Figure 3 30 is a diagram of an example ring oscillator frequency monitor 3000 for measuring standard cell delays of a ring oscillator 320, according to an embodiment. In some embodiments, the frequency monitor (e.g., frequency monitor 161-k) in each process monitor (e.g., process monitors 160-0, 160-1, ..., 160-k) may have a configuration similar to that of frequency monitor 3000. Frequency monitor 3000 (or frequency monitoring circuit) may include a NAND gate-based ring oscillator 320, a divider 340 (or divider circuit), and / or a counter 360 (or counter circuit). Ring oscillator 320 may include a plurality of NAND gates 322-1, 322-2, ... (e.g., an odd number of NAND gates). Frequency monitor 3000 may measure the delay of one or more selected standard cells on an analog power supply (e.g., Figure 1A The ring oscillator 320 may be implemented with one or more standard cells selected or chosen to match the delay of a critical path in the ADC, such as a critical path including digital elements within a SAR ADC. The divider 340 may divide the clock output from the ring oscillator to relax the timing requirements on the counter 360. The counter 360 may receive the divided clock output from the divider 340, calculate (or count) an oscillation frequency value 370 based on the divided clock according to the reference clock 361, and store the oscillation frequency value 370 in a register (not shown). For example, the divider 340 may divide the ring oscillator output clock into a low frequency clock. The counter 360 may be driven by a reference clock and sample the incoming divided clock. The frequency of the reference clock 361 is higher than the frequency of the divided clock. The lower frequency of the divided clock helps to reduce the frequency of the reference clock 361, so that the timing requirements for the sequential logic path are relaxed at a lower frequency clock.

[0080] Figure 4 4 is a flow chart showing an example process 4000 for performing AVS operations of an ADC according to an embodiment. An AVS system (e.g., AVS system 1000 in FIG. 1 ) may be configured to perform AVS operations on multiple channels (e.g., Figure 1A In some embodiments, the AVS system may execute the AVS operation process 4000 in the foreground and / or the background. For example, the foreground calibration is a one-time calibration with a specific input training sequence. In the background calibration, it is difficult to process the normal data flow. The background calibration is a continuous calibration that runs with the normal data flow. In some embodiments, the monitors (e.g., TP monitor 120, process monitor 160, conversion monitor 103, frequency monitor 161, leakage monitor 162, metal RC monitor 163, etc.) may run in both the background mode and the foreground mode.

[0081] At step 401, the AVS system (e.g., AVS system 1000, AVS controller 140, voltage regulator 150) may start AVS operation. At step 402, the voltage regulator 150 may set or initialize the supply voltage (e.g., AVDD 152) to a default voltage without voltage scaling. The regulator controller 142 of the AVS controller 140 may set one or more VR control bits 151 to "0" or any default value and provide the VR control bits 151 to the voltage regulator 150 so that the voltage regulator 150 may set the AVDD 152 to the default voltage.

[0082] At step 403, the AVS controller 140 may collect process information (e.g., multiple sets of PM bits 145). The AVS controller may read, obtain, collect, or receive a set of PM bits (e.g., PM bits 145-k) from each process monitor (e.g., process monitor 160-k). At step 404, the AVS controller 140 may collect timing and performance (TP) information (e.g., multiple sets of TP bits 141). The AVS controller 140 may read, obtain, collect, or receive a set of TP bits (e.g., TP bits 141-m) from each TP monitor (e.g., TP monitor 120-m) or each RX channel (e.g., RX channel 100-m).

[0083] At step 405, the AVS controller 140 may calculate a performance metric P (e.g., a SAR ADC performance metric) based on process information (e.g., multiple sets of PM bits 145) and / or TP information (e.g., multiple sets of TP bits 141). The performance metric P may be calculated based on one or more values ​​indicated in the multiple sets of PM bits 145 and / or one or more values ​​indicated in the multiple sets of TP bits 141. In some embodiments, the performance metric may be calculated based on: (1) a value indicated by timing bits of multiple groups of TP bits (e.g., timing bits 132-m in TP bits 141-m); (2) a value indicated by BER bits of multiple groups of TP bits (e.g., BER bits 134-m in TP bits 141-m); (3) a value indicated by SNR bits of multiple groups of TP bits (e.g., SNR bits 136-m in TP bits 141-m); (4) a value indicated by FM bits of multiple groups of PM bits (e.g., FM bits 172-k in PM bits 145-k); (5) a value indicated by LM bits of multiple groups of PM bits (e.g., LM bits 174-k in PM bits 145-k); and / or (6) a value indicated by MRC bits of multiple groups of PM bits (e.g., MRC bits 176-k in PM bits 145-k). In some embodiments, the performance metric P may be calculated based on a sum (e.g., a weighted sum) of: (1) a value indicated by timing bits of multiple groups of TP bits (e.g., timing bits 132-m in TP bits 141-m); (2) a value indicated by BER bits of multiple groups of TP bits (e.g., BER bits 134-m in TP bits 141-m); (3) a value indicated by SNR bits of multiple groups of TP bits (e.g., SNR bits 136-m in TP bits 141-m); (4) a value indicated by FM bits of multiple groups of PM bits (e.g., FM bits 172-k in PM bits 145-k); (5) a value indicated by LM bits of multiple groups of PM bits (e.g., LM bits 174-k in PM bits 145-k); and / or (6) a value indicated by MRC bits of multiple groups of PM bits (e.g., MRC bits 176-k in PM bits 145-k). The performance metric P may be calculated such that the larger the calculated performance metric P is, the more power the plurality of RX channels 100 or integrated circuit 1001 has consumed and / or the more noise the plurality of RX channels 100 or integrated circuit 1001 has generated.

[0084] At step 406, the AVS controller 140 may compare the calculated performance metric P with the target performance metric P target . Target performance metric P target It may be determined experimentally (or by simulation) to indicate that the power and / or noise consumed and / or generated by the plurality of RX channels 100 or the integrated circuit 1001 meets a predetermined design specification (or target).

[0085] At step 407, in response to determining that the calculated performance metric P is greater than the target performance metric P target , the AVS controller 140 may reduce or scale down the AVDD 152 by reducing the value of one or more VR control bits 151 and providing the reduced value to the voltage regulator 150. In some embodiments, the AVS controller 140 may reduce or decrease the value of one or more VR control bits 151 by a predetermined step value (e.g., 1).

[0086] At step 408, the AVS controller 140 (e.g., the analog performance tuner 144) may determine, tune, or adjust one or more analog control bits 147 based on the one or more VR control bits 151 (or the AVDD 152 corresponding to the VR control bits 151) calculated at step 407. In some embodiments, the AVS controller 140 may apply pre-trained or predetermined analog control bits to the ADCs in the plurality of RX channels based on the one or more VR control bits 151 calculated at step 407. For example, the AVS controller 140 may refer to a lookup table (LUT) (not shown) stored in a memory (not shown) and look up the value of the analog control bit corresponding to the value of the one or more VR control bits 151 (or the AVDD 152 corresponding to the VR control bits 151) in the LUT. Then, iteration may continue by returning to step 403.

[0087] At step 409, in response to determining that the computed performance metric P is less than or equal to the target performance metric P target (or calculate the performance metric P to reach the target performance metric P target ), the AVS controller 140 may increase or scale up the AVDD 152 by increasing the value of one or more VR control bits 151 and providing the increased value to the voltage regulator 150. In some embodiments, the AVS controller 140 may increase (or back off) the value of one or more VR control bits 151 by a predetermined value (or offset; e.g., a predetermined voltage value Vos) to reserve margin for temperature drift and / or device aging.

[0088] Figure 5 1 is a flow chart showing another example process 5000 of performing AVS operations of an ADC according to an embodiment. In some embodiments, the process 5000 is performed by a system (e.g., RX channel 100, ADC 102-1, ..., 102-m) or a controller (e.g., AVS controller 140) or a circuit system (e.g., multiple process monitors 160, timing and performance monitor 120). The controller may provide voltage to multiple ADCs (e.g., ADC 102-1, ..., 102-m). In other embodiments, the process 5000 is performed by other entities. In some embodiments, the process 5000 includes Figure 5 More, fewer, or different steps than those shown in .

[0089] At step 502, a controller (e.g., TP monitors 120-0, ..., 120-m and / or AVS controller 140) may receive a plurality of signals (e.g., CM bits 105-m-0, ..., 105-mn or a plurality of sets of TP bits 141-1, ..., 141-m) each indicating a performance characteristic of a corresponding ADC in a plurality of ADCs (e.g., ADCs 102-m-0, ..., 102-mn in RX channel 100-m). In some embodiments, before receiving the plurality of signals, the controller (e.g., AVS controller 140) may set a voltage (e.g., AVDD 152) to a first voltage (e.g., a default value), and a voltage regulator (e.g., voltage regulator 150) may provide the first voltage to the plurality of ADCs (e.g., ADCs 102-m-0, ..., 102-mn in RX channel 100-m).

[0090] In some embodiments, a time associated with an analog-to-digital conversion performed by each of the plurality of ADCs may be measured (e.g., conversion margin 207). The measured time (e.g., conversion margin 207) may be compared to a second threshold (e.g., threshold interval 211 or threshold interval 212). A plurality of signals (e.g., CM bits 105-m-0, ..., 105-mn) may be generated based at least on a result of the comparison.

[0091] At step 504, a controller (e.g., AVS controller 140) determines a metric (e.g., performance metric P) indicating performance of the plurality of ADCs based at least on the plurality of signals (e.g., CM bits 105-m-0, ..., 105-mn). At step 506, the controller may compare the metric to a threshold (e.g., target performance metric P). target ).

[0092] At step 508, in response to determining that a metric (eg, a performance metric P) is greater than a threshold (eg, a target performance metric P target ), the controller (e.g., the AVS controller 140) may reduce the voltage by a certain multiple (e.g., a predetermined multiple, a predetermined portion, a predetermined percentage, a predetermined step value, or a predetermined voltage value). For example, the AVS controller 140 may reduce the value of one or more VR control bits 151 and provide the reduced value to the voltage regulator 150. The AVS controller 140 may reduce or decrease the value of one or more VR control bits 151 by a predetermined step value (e.g., 1) so that the voltage regulator 150 may reduce AVDD by a predetermined voltage value. After reducing the voltage by the multiple, the voltage regulator 150 may provide the reduced voltage (e.g., AVDD) to multiple ADCs (e.g., multiple ADCs in each RX channel 100-0, ..., 100-m). In some embodiments, in response to determining that the metric is less than or equal to the threshold, the controller (e.g., the AVS controller 140) may increase the voltage by an offset (e.g., a predetermined voltage value Vos).

[0093] In some embodiments, after reducing the voltage by the factor at step 508, a second metric indicative of the performance of the plurality of ADCs (e.g., comparator bias current, input common mode voltage, programmable delay, etc.) may be adjusted based on reducing the voltage (e.g., based on reducing AVDD or based on one or more VR control bits 151). The second metric may be different from the metric (e.g., performance metric P). In some embodiments, after reducing the voltage by the factor, a second plurality of signals (e.g., one or more analog control bits 147) may be received, each indicating a performance characteristic of a corresponding ADC in the plurality of ADCs.

[0094] In some embodiments, the voltage regulator 150 may provide the voltage AVDD to one or more circuits. At least one of the standard cell delay, the leakage current, or the resistance and capacitance of the metal pattern may be measured by the one or more circuits. One or more signals corresponding to the one or more circuits (e.g., the PM bit group 145-k including the FM bit 172-k, the LM bit 174-k, the MRC bit 176-k) may be generated based on the results of the measurement (e.g., the measurement performed by the process monitor 160-k including the frequency monitor 161-k, the leakage monitor 162-k, the metal RC monitor 163-k). The metric (e.g., the performance metric P) may be determined based on multiple signals (e.g., multiple sets of TP bits 141-0, ..., 141-m) and one or more signals (e.g., multiple sets of PM bits 145-0, ..., 145-k).

[0095] The term "coupled" and its variations include making two components directly or indirectly join to each other. The term "electrically coupled" and its variations include making two components directly or indirectly join to each other through a conductive material (such as a metal or copper trace). This joining (for both the terms "coupled" and "electrically coupled") can be static (e.g., permanent or fixed) or movable (e.g., removable or releasable). This joining (for both the terms "coupled" and "electrically coupled") can be achieved by: the two components are directly coupled to each other; the two components are coupled to each other using a separate intermediary component and any additional intermediate components that are coupled to each other; or the two components are coupled to each other using an intermediary component that is integrally formed as a single entity with one of the two components. If "coupled" or its variations are modified by additional terms (e.g., directly coupled), the general definition of "coupled" provided above is modified by the plain meaning of the additional terms (e.g., "directly coupled" means that the two components are joined without any separate intermediary components), resulting in a narrower definition than the general definition of "coupled" provided above. This coupling can be mechanical, electrical, or fluid.

[0096] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions should not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications to this document without departing from the spirit and scope of the present disclosure.

[0097] It should be noted that certain paragraphs of the present disclosure may reference terms such as "first" and "second" in relation to transmit spatial streams, sounding frames, responses, and subsets of devices for identification or distinction from one another or from others. These terms are not intended to relate entities (e.g., first device and second device) only in time or according to sequence, although in some cases, these entities may include such a relationship. These terms also do not limit the number of possible entities that may operate within a system or environment. It should be understood that the above-described systems may provide any or multiple of each of those components and that these components may be provided on a stand-alone machine or, in some embodiments, on multiple machines in a distributed system. In addition, the above-described systems and methods may be provided as one or more computer-readable programs or executable instructions embodied on or in one or more articles of manufacture (e.g., floppy disk, hard disk, CD-ROM, flash memory card, PROM, RAM, ROM, or tape). The programs may be implemented in any programming language (e.g., LISP, PERL, C, C++, C#) or in any byte code language (e.g., JAVA). The software programs or executable instructions may be stored as object code on or in one or more articles of manufacture. In some embodiments, the ADC is used as an integrated circuit in a transmitter for wireless communication. The ADC is provided on an integrated circuit that includes a calibration engine. In some embodiments, the ADC and the calibration engine are provided in a single chip or a multi-chip integrated package.

[0098] Although the foregoing written description of the methods and systems enables a person of ordinary skill to make and use embodiments thereof, the person of ordinary skill should understand and appreciate that variations, combinations, and equivalents of the specific embodiments, methods, and examples herein exist. The methods and systems of the present invention should therefore not be limited by the above-described embodiments, methods, and examples, but rather by all embodiments and methods within the scope and spirit of the present disclosure. < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A system comprising: One or more receivers, each comprising a plurality of analog-to-digital converters ADC, each ADC being configured to: measuring a time associated with an analog-to-digital conversion performed by the ADC; comparing the time to a threshold; and generating a first signal based on a result of the comparing; A circuit system coupled to the one or more receivers and configured to: receiving the first signal from each ADC; determining a performance characteristic of each receiver based at least on the first signal; and outputting a plurality of second signals each indicative of the performance characteristic of a corresponding receiver; and a controller coupled to the circuit system and configured to: A voltage provided to the one or more receivers is adjusted based at least on the plurality of second signals received from the circuitry.

2. The system of claim 1, wherein each transceiver is a serializer / deserializer (SerDes) receiver.

3. The system of claim 1, wherein the plurality of ADCs in each receiver comprises time-interleaved successive approximation register (SAR) ADCs. 4 . The system of claim 3 , wherein the threshold is a clock interval between two SAR ADCs. 5 . The system of claim 1 , wherein the performance characteristics of each receiver include at least one of conversion timing, a signal-to-noise ratio (SNR), or a bit error rate (BER) of an ADC in the receiver.

6. The system of claim 1, wherein The voltage is provided to one or more circuits, and The system further includes a second circuit system coupled to the one or more circuits and configured to: measuring, by the one or more circuits, at least one of a standard cell delay, a leakage current, or a resistance and a capacitance of a metal pattern; and One or more third signals corresponding to the one or more circuits are output based on a result of the measuring.

7. The system of claim 6, wherein the controller is further configured to adjust the voltage provided to the one or more receivers based at least on the plurality of second signals and the one or more third signals.

8. A method comprising: receiving, by a controller that provides voltages to a plurality of analog-to-digital converters ADC, a plurality of signals each indicative of a performance characteristic of a corresponding ADC of the plurality of ADCs; determining, by the controller, a metric indicative of performance of the plurality of ADCs based at least on the plurality of signals; comparing, by the controller, the metric to a threshold; and In response to determining that the metric is greater than the threshold, the voltage is reduced by a certain factor by the controller.

9. The method according to claim 8, further comprising: In response to determining that the metric is less than or equal to the threshold, the voltage is increased by the controller by an offset.

10. The method according to claim 8, further comprising: Before receiving the plurality of signals, the voltage is set to a first voltage and the first voltage is provided to the plurality of ADCs by a voltage regulator; and After reducing the voltage by the multiple, the reduced voltage is provided to the plurality of ADCs by the voltage regulator.

11. The method according to claim 8, further comprising: measuring a time associated with an analog-to-digital conversion performed by each of the plurality of ADCs; comparing the measured time with a second threshold; and The plurality of signals are generated based at least on a result of the comparing.

12. The method according to claim 8, further comprising: providing the voltage to one or more circuits; measuring, by the one or more circuits, at least one of a standard cell delay, a leakage current, or a resistance and a capacitance of a metal pattern; and generating one or more signals corresponding to the one or more circuits based on the results of the measuring; and The metric is determined based on the plurality of signals and the one or more signals.

13. The method according to claim 8, further comprising: After reducing the voltage by the factor, a second metric indicative of performance of the plurality of ADCs is adjusted based on the reduced voltage, the second metric being different from the metric.

14. The method according to claim 8, further comprising: After reducing the voltage by the factor, a second plurality of signals are received that are each indicative of a performance characteristic of a corresponding ADC in the plurality of ADCs.

15. A circuit system comprising: A first circuit is coupled to a plurality of analog-to-digital converters ADC and is configured to: measuring a time associated with an analog-to-digital conversion performed by each of the plurality of ADCs; comparing the measured time with a threshold; and generating a plurality of first signals corresponding to the plurality of ADCs based at least on a result of the comparing; determining performance characteristics of the plurality of ADCs based at least on the plurality of first signals; and outputting a second signal indicative of the performance characteristic of the plurality of ADCs; and a second circuit coupled to the first circuit and configured to: Voltages provided to the plurality of ADCs are adjusted based on at least the second signal received from the first circuit.

16. The circuit system of claim 15, wherein the plurality of ADCs comprises time-interleaved successive approximation register (SAR) ADCs.

17. The circuit system of claim 16, wherein the threshold is a clock interval between two SAR ADCs.

18. The circuit system of claim 15, wherein The plurality of ADCs form a receiver, and The performance characteristic includes at least one of conversion timing of the plurality of ADCs in the receiver, a signal-to-noise ratio (SNR) of the receiver, or a bit error rate (BER) of the receiver.

19. The circuit system of claim 15, wherein The voltage is provided to one or more circuits, and The circuit system further includes a third circuit coupled to the one or more circuits and configured to: measuring, by the one or more circuits, at least one of a standard cell delay, a leakage current, or a resistance and a capacitance of a metal pattern; and One or more third signals corresponding to the one or more circuits are output based on a result of the measuring.

20. The circuit system of claim 19, wherein the second circuit is further configured to adjust the voltage provided to the plurality of ADCs based at least on the second signal and the one or more third signals.

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